Merge changes from topic "dynamic-toolchain" into integration
* changes:
build: allow multiple toolchain defaults
build: determine toolchain tools dynamically
diff --git a/Makefile b/Makefile
index b3f103f..c2ed9ee 100644
--- a/Makefile
+++ b/Makefile
@@ -1485,7 +1485,7 @@
# Build targets
################################################################################
-.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip sp fwu_fip certtool dtbs memmap doc enctool
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip sp tl fwu_fip certtool dtbs memmap doc enctool
.SUFFIXES:
all: msg_start
@@ -1657,11 +1657,10 @@
for commit in `git rev-list --no-merges $$COMMON_COMMIT..HEAD`; \
do \
printf "\n[*] Checking style of '$$commit'\n\n"; \
- git log --format=email "$$commit~..$$commit" \
- -- ${CHECK_PATHS} | \
- ${CHECKPATCH} ${CHECKPATCH_OPTS} - || true; \
- git diff --format=email "$$commit~..$$commit" \
- -- ${CHECK_PATHS} | \
+ ( git log --format=email "$$commit~..$$commit" \
+ -- ${CHECK_PATHS} ; \
+ git diff --format=email "$$commit~..$$commit" \
+ -- ${CHECK_PATHS}; ) | \
${CHECKPATCH} ${CHECKPATCH_OPTS} - || true; \
done
@@ -1732,6 +1731,11 @@
${PYTHON} -m memory.memmap -sr ${BUILD_PLAT}
endif
+tl: ${BUILD_PLAT}/tl.bin
+${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
+ $(q)poetry -q install
+ $(q)poetry run tlc create --fdt $< -s ${FW_HANDOFF_SIZE} $@
+
doc:
$(s)echo " BUILD DOCUMENTATION"
$(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 7fafe03..7fe58f8 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -70,6 +70,8 @@
+-----------------+---------------------------+------------------------------+
| v2.11 | 4th week of May '24 | 2nd week of May '24 |
+-----------------+---------------------------+------------------------------+
+| v2.12 | 4th week of Nov '24 | 2nd week of Nov '24 |
++-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
--------------------------------
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
index 29b89b2..2b6382b 100644
--- a/docs/components/ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst
@@ -122,7 +122,7 @@
- managed-exit-virq
- value type: <empty>
- Indicates if the partition needs managed exit, if supported, to be signaled
- through vFIQ signal.
+ through vIRQ signal.
- ns-interrupts-action [mandatory]
- value type: <u32>
@@ -143,12 +143,6 @@
- 0x0: Other-Secure interrupt is queued
- 0x1: Other-Secure interrupt is signaled
-- runtime-model
- - value type: <u32>
- - Indicates whether the SP execution can be preempted.
- - This field is deprecated in favor of other-s-interrupts-action and
- ns-interrupts-action fields in the FF-A v1.1 spec.
-
- has-primary-scheduler
- value type: <empty>
- Presence of this field indicates that the partition implements the primary
@@ -228,6 +222,14 @@
then communicate the region properties (including the base address chosen
by the partition manager) to the partition.
+- load-address-relative-offset
+ - value type: <u64>
+ - Offset relative to the load address of the partition.
+ When this is provided in the partition manifest, it should be added to the
+ load address to get the base address of the region. The secure partition
+ manifest can have either "base-address" or "load-address-relative-offset".
+ It cannot have both.
+
- stream-ids
- value type: <prop-encoded-array>
- List of IDs belonging to a DMA capable peripheral device that has access to
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 5fbd7fd..03703bc 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -52,7 +52,7 @@
- ``RES0``: Bit 31 of the version number is reserved 0 as to maintain
consistency with the versioning schemes used in other parts of RMM.
-This document specifies the 0.2 version of Boot Interface ABI and RMM-EL3
+This document specifies the 0.3 version of Boot Interface ABI and RMM-EL3
services specification and the 0.3 version of the Boot Manifest.
.. _rmm_el3_boot_interface:
@@ -238,6 +238,7 @@
``E_RMM_BAD_PAS``,Incorrect PAS,-3
``E_RMM_NOMEM``,Not enough memory to perform an operation,-4
``E_RMM_INVAL``,The value of an argument was invalid,-5
+ ``E_RMM_AGAIN``,The resource is busy. Try again.,-6
If multiple failure conditions are detected in an RMM to EL3 command, then EL3
is allowed to return an error code corresponding to any of the failure
@@ -442,7 +443,21 @@
RMM_ATTEST_GET_PLAT_TOKEN command
=================================
-Retrieve the Platform Token from EL3.
+Retrieve the Platform Token from EL3. If the entire token does not fit in the
+buffer, EL3 returns a hunk of the token (via ``tokenHunkSize`` parameter) and
+indicates the remaining bytes that are pending retrieval (via ``remainingSize``
+parameter). The challenge object for the platform token must be populated in
+the buffer for the first call of this command and the size of the object is
+indicated by ``c_size`` parameter. Subsequent calls to retrieve remaining hunks of
+the token must be made with ``c_size`` as 0.
+
+If ``c_size`` is not 0, this command could cause regeneration of platform token
+and will return token hunk corresponding to beginning of the token.
+
+It is valid for the calls of this command to return ``E_RMM_AGAIN`` error,
+which is an indication to the caller to retry this command again. Depending on the
+platform, this mechanism can be used to implement queuing to HES, if HES is
+involved in platform token generation.
FID
---
@@ -457,9 +472,9 @@
:widths: 1 1 1 1 5
fid,x0,[63:0],UInt64,Command FID
- buf_pa,x1,[63:0],Address,PA of the platform attestation token. The challenge object is passed in this buffer. The PA must belong to the shared buffer
+ buf_pa,x1,[63:0],Address,"PA of the platform attestation token. The challenge object must be passed in this buffer for the first call of this command. Any subsequent calls, if required to retrieve the full token, should not have this object. The PA must belong to the shared buffer."
buf_size,x2,[63:0],Size,Size in bytes of the platform attestation token buffer. ``bufPa + bufSize`` must lie within the shared buffer
- c_size,x3,[63:0],Size,Size in bytes of the challenge object. It corresponds to the size of one of the defined SHA algorithms
+ c_size,x3,[63:0],Size,"Size in bytes of the challenge object. It corresponds to the size of one of the defined SHA algorithms. Any subsequent calls, if required to retrieve the full token, should set this size to 0."
Output values
-------------
@@ -469,7 +484,8 @@
:widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
- tokenSize,x1,[63:0],Size,Size of the platform token
+ tokenHunkSize,x1,[63:0],Size,Size of the platform token hunk retrieved
+ remainingSize,x2,[63:0],Size,Remaining bytes of the token that are pending retrieval
Failure conditions
------------------
@@ -481,9 +497,11 @@
:header: "ID", "Condition"
:widths: 1 5
+ ``E_RMM_AGAIN``,Resource for Platform token retrieval is busy. Try again.
``E_RMM_BAD_ADDR``,``PA`` is outside the shared buffer
``E_RMM_INVAL``,``PA + BSize`` is outside the shared buffer
- ``E_RMM_INVAL``,``CSize`` does not represent the size of a supported SHA algorithm
+ ``E_RMM_INVAL``,``CSize`` does not represent the size of a supported SHA algorithm for the first call to this command
+ ``E_RMM_INVAL``,``CSize`` is not 0 for subsequent calls to retrieve remaining hunks of the token
``E_RMM_UNK``,An unknown error occurred whilst processing the command
``E_RMM_OK``,No errors detected
diff --git a/docs/design_documents/rse.rst b/docs/design_documents/rse.rst
index e0e0fb3..57467f3 100644
--- a/docs/design_documents/rse.rst
+++ b/docs/design_documents/rse.rst
@@ -482,101 +482,101 @@
INFO: Get platform token start
INFO: Get platform token succeeds, len: 1086
INFO: Platform attestation token:
- INFO: d2 84 44 a1 01 38 22 a0 59 05 7a a9 19 01 09 78
- INFO: 1c 68 74 74 70 3a 2f 2f 61 72 6d 2e 63 6f 6d 2f
- INFO: 43 43 41 2d 53 53 44 2f 31 2e 30 2e 30 0a 58 20
- INFO: b5 97 3c b6 8b aa 9f c5 55 58 78 6b 7e c6 7f 69
- INFO: e4 0d f5 ba 5a a9 21 cd 0c 27 f4 05 87 a0 11 ea
- INFO: 19 09 5c 58 20 7f 45 4c 46 02 01 01 00 00 00 00
- INFO: 00 00 00 00 00 03 00 3e 00 01 00 00 00 50 58 00
- INFO: 00 00 00 00 00 19 01 00 58 21 01 07 06 05 04 03
- INFO: 02 01 00 0f 0e 0d 0c 0b 0a 09 08 17 16 15 14 13
- INFO: 12 11 10 1f 1e 1d 1c 1b 1a 19 18 19 09 61 44 cf
- INFO: cf cf cf 19 09 5b 19 30 03 19 09 62 67 73 68 61
- INFO: 2d 32 35 36 19 09 60 78 3a 68 74 74 70 73 3a 2f
- INFO: 2f 76 65 72 61 69 73 6f 6e 2e 65 78 61 6d 70 6c
- INFO: 65 2f 2e 77 65 6c 6c 2d 6b 6e 6f 77 6e 2f 76 65
- INFO: 72 61 69 73 6f 6e 2f 76 65 72 69 66 69 63 61 74
- INFO: 69 6f 6e 19 09 5f 8d a4 01 69 52 53 45 5f 42 4c
- INFO: 31 5f 32 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
- INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 9a 27 1f 2a 91 6b 0b
- INFO: 6e e6 ce cb 24 26 f0 b3 20 6e f0 74 57 8b e5 5d
- INFO: 9b c9 4f 6f 3f e3 ab 86 aa 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 67 52 53 45 5f 42 4c 32 05 58 20 53
- INFO: 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41
- INFO: 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02
- INFO: 58 20 53 c2 34 e5 e8 47 2b 6a c5 1c 1a e1 ca b3
- INFO: fe 06 fa d0 53 be b8 eb fd 89 77 b0 10 65 5b fd
- INFO: d3 c3 06 67 73 68 61 2d 32 35 36 a4 01 65 52 53
- INFO: 45 5f 53 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
- INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 11 21 cf cc d5 91 3f
- INFO: 0a 63 fe c4 0a 6f fd 44 ea 64 f9 dc 13 5c 66 63
- INFO: 4b a0 01 d1 0b cf 43 02 a2 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 66 41 50 5f 42 4c 31 05 58 20 53 78
- INFO: 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41
- INFO: 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58
- INFO: 20 15 71 b5 ec 78 bd 68 51 2b f7 83 0b b6 a2 a4
- INFO: 4b 20 47 c7 df 57 bc e7 9e b8 a1 c0 e5 be a0 a5
- INFO: 01 06 67 73 68 61 2d 32 35 36 a4 01 66 41 50 5f
+ INFO: d2 84 44 a1 01 38 22 a0 59 05 81 a9 19 01 09 78
+ INFO: 23 74 61 67 3a 61 72 6d 2e 63 6f 6d 2c 32 30 32
+ INFO: 33 3a 63 63 61 5f 70 6c 61 74 66 6f 72 6d 23 31
+ INFO: 2e 30 2e 30 0a 58 20 0d 22 e0 8a 98 46 90 58 48
+ INFO: 63 18 28 34 89 bd b3 6f 09 db ef eb 18 64 df 43
+ INFO: 3f a6 e5 4e a2 d7 11 19 09 5c 58 20 7f 45 4c 46
+ INFO: 02 01 01 00 00 00 00 00 00 00 00 00 03 00 3e 00
+ INFO: 01 00 00 00 50 58 00 00 00 00 00 00 19 01 00 58
+ INFO: 21 01 07 06 05 04 03 02 01 00 0f 0e 0d 0c 0b 0a
+ INFO: 09 08 17 16 15 14 13 12 11 10 1f 1e 1d 1c 1b 1a
+ INFO: 19 18 19 09 61 44 cf cf cf cf 19 09 5b 19 30 03
+ INFO: 19 09 62 67 73 68 61 2d 32 35 36 19 09 60 78 3a
+ INFO: 68 74 74 70 73 3a 2f 2f 76 65 72 61 69 73 6f 6e
+ INFO: 2e 65 78 61 6d 70 6c 65 2f 2e 77 65 6c 6c 2d 6b
+ INFO: 6e 6f 77 6e 2f 76 65 72 61 69 73 6f 6e 2f 76 65
+ INFO: 72 69 66 69 63 61 74 69 6f 6e 19 09 5f 8d a4 01
+ INFO: 69 52 53 45 5f 42 4c 31 5f 32 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: 9a 27 1f 2a 91 6b 0b 6e e6 ce cb 24 26 f0 b3 20
+ INFO: 6e f0 74 57 8b e5 5d 9b c9 4f 6f 3f e3 ab 86 aa
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 67 52 53 45 5f
INFO: 42 4c 32 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 10 15 9b af 26 2b 43
- INFO: a9 2d 95 db 59 da e1 f7 2c 64 51 27 30 16 61 e0
- INFO: a3 ce 4e 38 b2 95 a9 7c 58 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 67 53 43 50 5f 42 4c 31 05 58 20 53
- INFO: 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41
- INFO: 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02
- INFO: 58 20 10 12 2e 85 6b 3f cd 49 f0 63 63 63 17 47
- INFO: 61 49 cb 73 0a 1a a1 cf aa d8 18 55 2b 72 f5 6d
- INFO: 6f 68 06 67 73 68 61 2d 32 35 36 a4 01 67 53 43
- INFO: 50 5f 42 4c 32 05 58 20 f1 4b 49 87 90 4b cb 58
- INFO: 14 e4 45 9a 05 7e d4 d2 0f 58 a6 33 15 22 88 a7
- INFO: 61 21 4d cd 28 78 0b 56 02 58 20 aa 67 a1 69 b0
- INFO: bb a2 17 aa 0a a8 8a 65 34 69 20 c8 4c 42 44 7c
- INFO: 36 ba 5f 7e a6 5f 42 2c 1f e5 d8 06 67 73 68 61
- INFO: 2d 32 35 36 a4 01 67 41 50 5f 42 4c 33 31 05 58
- INFO: 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc
- INFO: 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a
- INFO: a3 02 58 20 2e 6d 31 a5 98 3a 91 25 1b fa e5 ae
- INFO: fa 1c 0a 19 d8 ba 3c f6 01 d0 e8 a7 06 b4 cf a9
- INFO: 66 1a 6b 8a 06 67 73 68 61 2d 32 35 36 a4 01 63
- INFO: 52 4d 4d 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
+ INFO: c0 fa 97 3f 7a a3 02 58 20 53 c2 34 e5 e8 47 2b
+ INFO: 6a c5 1c 1a e1 ca b3 fe 06 fa d0 53 be b8 eb fd
+ INFO: 89 77 b0 10 65 5b fd d3 c3 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 65 52 53 45 5f 53 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: 11 21 cf cc d5 91 3f 0a 63 fe c4 0a 6f fd 44 ea
+ INFO: 64 f9 dc 13 5c 66 63 4b a0 01 d1 0b cf 43 02 a2
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 66 41 50 5f 42
+ INFO: 4c 31 05 58 20 53 78 79 63 07 53 5d f3 ec 8d 8b
+ INFO: 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38 c0
+ INFO: fa 97 3f 7a a3 02 58 20 15 71 b5 ec 78 bd 68 51
+ INFO: 2b f7 83 0b b6 a2 a4 4b 20 47 c7 df 57 bc e7 9e
+ INFO: b8 a1 c0 e5 be a0 a5 01 06 67 73 68 61 2d 32 35
+ INFO: 36 a4 01 66 41 50 5f 42 4c 32 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: 10 15 9b af 26 2b 43 a9 2d 95 db 59 da e1 f7 2c
+ INFO: 64 51 27 30 16 61 e0 a3 ce 4e 38 b2 95 a9 7c 58
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 67 53 43 50 5f
+ INFO: 42 4c 31 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
- INFO: c0 fa 97 3f 7a a3 02 58 20 a1 fb 50 e6 c8 6f ae
- INFO: 16 79 ef 33 51 29 6f d6 71 34 11 a0 8c f8 dd 17
- INFO: 90 a4 fd 05 fa e8 68 81 64 06 67 73 68 61 2d 32
- INFO: 35 36 a4 01 69 48 57 5f 43 4f 4e 46 49 47 05 58
+ INFO: c0 fa 97 3f 7a a3 02 58 20 10 12 2e 85 6b 3f cd
+ INFO: 49 f0 63 63 63 17 47 61 49 cb 73 0a 1a a1 cf aa
+ INFO: d8 18 55 2b 72 f5 6d 6f 68 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 67 53 43 50 5f 42 4c 32 05 58 20 f1
+ INFO: 4b 49 87 90 4b cb 58 14 e4 45 9a 05 7e d4 d2 0f
+ INFO: 58 a6 33 15 22 88 a7 61 21 4d cd 28 78 0b 56 02
+ INFO: 58 20 aa 67 a1 69 b0 bb a2 17 aa 0a a8 8a 65 34
+ INFO: 69 20 c8 4c 42 44 7c 36 ba 5f 7e a6 5f 42 2c 1f
+ INFO: e5 d8 06 67 73 68 61 2d 32 35 36 a4 01 67 41 50
+ INFO: 5f 42 4c 33 31 05 58 20 53 78 79 63 07 53 5d f3
+ INFO: ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3
+ INFO: 22 38 c0 fa 97 3f 7a a3 02 58 20 2e 6d 31 a5 98
+ INFO: 3a 91 25 1b fa e5 ae fa 1c 0a 19 d8 ba 3c f6 01
+ INFO: d0 e8 a7 06 b4 cf a9 66 1a 6b 8a 06 67 73 68 61
+ INFO: 2d 32 35 36 a4 01 63 52 4d 4d 05 58 20 53 78 79
+ INFO: 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c
+ INFO: 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20
+ INFO: a1 fb 50 e6 c8 6f ae 16 79 ef 33 51 29 6f d6 71
+ INFO: 34 11 a0 8c f8 dd 17 90 a4 fd 05 fa e8 68 81 64
+ INFO: 06 67 73 68 61 2d 32 35 36 a4 01 69 48 57 5f 43
+ INFO: 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53 5d f3
+ INFO: ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3
+ INFO: 22 38 c0 fa 97 3f 7a a3 02 58 20 1a 25 24 02 97
+ INFO: 2f 60 57 fa 53 cc 17 2b 52 b9 ff ca 69 8e 18 31
+ INFO: 1f ac d0 f3 b0 6e ca ae f7 9e 17 06 67 73 68 61
+ INFO: 2d 32 35 36 a4 01 69 46 57 5f 43 4f 4e 46 49 47
+ INFO: 05 58 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2
+ INFO: e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97
+ INFO: 3f 7a a3 02 58 20 9a 92 ad bc 0c ee 38 ef 65 8c
+ INFO: 71 ce 1b 1b f8 c6 56 68 f1 66 bf b2 13 64 4c 89
+ INFO: 5c cb 1a d0 7a 25 06 67 73 68 61 2d 32 35 36 a4
+ INFO: 01 6c 54 42 5f 46 57 5f 43 4f 4e 46 49 47 05 58
INFO: 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc
INFO: 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a
- INFO: a3 02 58 20 1a 25 24 02 97 2f 60 57 fa 53 cc 17
- INFO: 2b 52 b9 ff ca 69 8e 18 31 1f ac d0 f3 b0 6e ca
- INFO: ae f7 9e 17 06 67 73 68 61 2d 32 35 36 a4 01 69
- INFO: 46 57 5f 43 4f 4e 46 49 47 05 58 20 53 78 79 63
- INFO: 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d
- INFO: 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20 9a
- INFO: 92 ad bc 0c ee 38 ef 65 8c 71 ce 1b 1b f8 c6 56
- INFO: 68 f1 66 bf b2 13 64 4c 89 5c cb 1a d0 7a 25 06
- INFO: 67 73 68 61 2d 32 35 36 a4 01 6c 54 42 5f 46 57
- INFO: 5f 43 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53
- INFO: 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60
- INFO: cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20 23 89 03
- INFO: 18 0c c1 04 ec 2c 5d 8b 3f 20 c5 bc 61 b3 89 ec
- INFO: 0a 96 7d f8 cc 20 8c dc 7c d4 54 17 4f 06 67 73
- INFO: 68 61 2d 32 35 36 a4 01 6d 53 4f 43 5f 46 57 5f
- INFO: 43 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53 5d
- INFO: f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf
- INFO: e3 22 38 c0 fa 97 3f 7a a3 02 58 20 e6 c2 1e 8d
- INFO: 26 0f e7 18 82 de bd b3 39 d2 40 2a 2c a7 64 85
- INFO: 29 bc 23 03 f4 86 49 bc e0 38 00 17 06 67 73 68
- INFO: 61 2d 32 35 36 58 60 21 51 20 92 d6 d0 2a e6 be
- INFO: 2f e3 93 0e a5 1f d6 98 96 32 24 56 e9 df c7 32
- INFO: 5e 0b 78 68 b6 90 73 2a 0c 0f 07 77 c1 15 40 4b
- INFO: e1 fc 83 9b 7d 30 4f 4f e6 fa 46 ae 12 a3 08 3a
- INFO: cf 24 06 67 91 06 bf ae 50 31 79 dd 50 33 49 12
- INFO: bf c6 da 33 6d d6 18 25 43 54 4d b5 88 d6 ae 67
- INFO: 35 7a fd b0 5f 95 b7
+ INFO: a3 02 58 20 23 89 03 18 0c c1 04 ec 2c 5d 8b 3f
+ INFO: 20 c5 bc 61 b3 89 ec 0a 96 7d f8 cc 20 8c dc 7c
+ INFO: d4 54 17 4f 06 67 73 68 61 2d 32 35 36 a4 01 6d
+ INFO: 53 4f 43 5f 46 57 5f 43 4f 4e 46 49 47 05 58 20
+ INFO: 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56
+ INFO: 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3
+ INFO: 02 58 20 e6 c2 1e 8d 26 0f e7 18 82 de bd b3 39
+ INFO: d2 40 2a 2c a7 64 85 29 bc 23 03 f4 86 49 bc e0
+ INFO: 38 00 17 06 67 73 68 61 2d 32 35 36 58 60 31 d0
+ INFO: 4d 52 cc de 95 2c 1e 32 cb a1 81 88 5a 40 b8 cc
+ INFO: 38 e0 52 8c 1e 89 58 98 07 64 2a a5 e3 f2 bc 37
+ INFO: f9 53 74 50 6b ff 4d 2e 4b e7 06 3c 4d 72 41 92
+ INFO: 70 c7 22 e8 d4 d9 3e e8 b6 c9 fa ce 3b 43 c9 76
+ INFO: 1a 49 94 1a b6 f3 8f fd ff 49 6a d4 63 b4 cb fa
+ INFO: 11 d8 3e 23 e3 1f 7f 62 32 9d e3 0c 1c c8
INFO: DELEGATED ATTEST TEST END
JSON format:
@@ -584,8 +584,8 @@
.. code-block:: JSON
{
- "CCA_ATTESTATION_PROFILE": "http://arm.com/CCA-SSD/1.0.0",
- "CCA_PLATFORM_CHALLENGE": "b'B5973CB68BAA9FC55558786B7EC67F69E40DF5BA5AA921CD0C27F40587A011EA'",
+ "CCA_ATTESTATION_PROFILE": "tag:arm.com,2023:cca_platform#1.0.0",
+ "CCA_PLATFORM_CHALLENGE": "b'0D22E08A98469058486318283489BDB36F09DBEFEB1864DF433FA6E54EA2D711'",
"CCA_PLATFORM_IMPLEMENTATION_ID": "b'7F454C4602010100000000000000000003003E00010000005058000000000000'",
"CCA_PLATFORM_INSTANCE_ID": "b'0107060504030201000F0E0D0C0B0A090817161514131211101F1E1D1C1B1A1918'",
"CCA_PLATFORM_CONFIG": "b'CFCFCFCF'",
@@ -738,5 +738,5 @@
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
*Copyright (c) 2024, Linaro Limited. All rights reserved.*
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 6a0241f..42b1ec4 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -31,7 +31,7 @@
Clang/LLVM 11.0.0
Device Tree Compiler 1.4.7
GNU make 3.81
-mbed TLS\ [#f1]_ 3.6.0
+mbed TLS\ [#f1]_ 3.6.1
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry [#f2]_ 1.3.2
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 5d4ab4e..87bb6a5 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -85,7 +85,8 @@
Boot with FIP
~~~~~~~~~~~~~
-You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary.
+You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) and retrieve
+DDR PHY firmware before building FIP binary.
U-Boot
______
@@ -106,9 +107,24 @@
ARCH=arm PLATFORM=stm32mp2 \
CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts
-TF-A BL2 & BL31
-_______________
-To build TF-A BL2 with its STM32 header and BL31 for SD-card boot:
+DDR PHY firmware
+________________
+DDR PHY firmware files may not be delivered inside TF-A repository, especially
+if you build directly from trustedfirmware.org repository. It then needs to be
+retrieved from `STMicroelectronics DDR PHY github`_.
+
+You can either clone the repository to the default directory:
+
+.. code:: bash
+
+ git clone https://github.com/STMicroelectronics/stm32-ddr-phy-binary.git drivers/st/ddr/phy/firmware/bin
+
+Or clone it somewhere else, and add ``STM32MP_DDR_FW_PATH=`` in your make command
+line when building FIP.
+
+TF-A BL2
+________
+To build TF-A BL2 with its STM32 header for SD-card boot:
.. code:: bash
@@ -136,5 +152,6 @@
.. _STM32MP2 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
+.. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 5643ea1..e672ad7 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -2248,26 +2248,35 @@
::
- Argument : uintptr_t, size_t *, uintptr_t, size_t
+ Argument : uintptr_t, size_t *, uintptr_t, size_t, size_t *
Return : int
-This function returns the Platform attestation token.
+This function returns the Platform attestation token. If the full token does
+not fit in the buffer, the function will return a hunk of the token and
+indicate how many bytes were copied and how many are pending. Multiple calls
+to this function may be needed to retrieve the entire token.
The parameters of the function are:
arg0 - A pointer to the buffer where the Platform token should be copied by
- this function. The buffer must be big enough to hold the Platform
- token.
+ this function. If the platform token does not completely fit in the
+ buffer, the function may return a piece of the token only.
- arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
- function returns the platform token length in this parameter.
+ arg1 - Contains the size (in bytes) of the buffer passed in arg0. In
+ addition, this parameter is used by the function to return the size
+ of the platform token length hunk copied to the buffer.
arg2 - A pointer to the buffer where the challenge object is stored.
arg3 - The length of the challenge object in bytes. Possible values are 32,
- 48 and 64.
+ 48 and 64. This argument must be zero for subsequent calls to
+ retrieve the remaining hunks of the token.
-The function returns 0 on success, -EINVAL on failure.
+ arg4 - Returns the remaining length of the token (in bytes) that is yet to
+ be returned in further calls.
+
+The function returns 0 on success, -EINVAL on failure and -EAGAIN if the
+resource associated with the platform token retrieval is busy.
Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index e925e14..765491e 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -66,7 +66,6 @@
)
ifeq (${PSA_CRYPTO},1)
-LIBMBEDTLS_CFLAGS += -Wno-error=unused-but-set-variable
LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \
psa_crypto.c \
psa_crypto_client.c \
@@ -74,6 +73,8 @@
psa_crypto_rsa.c \
psa_crypto_ecp.c \
psa_crypto_slot_management.c \
+ psa_crypto_aead.c \
+ psa_crypto_cipher.c \
psa_util.c \
)
endif
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 53f8adf..f2ccf15 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -9,13 +9,11 @@
#include <string.h>
/* mbed TLS headers */
-#include <mbedtls/gcm.h>
#include <mbedtls/md.h>
#include <mbedtls/memory_buffer_alloc.h>
#include <mbedtls/oid.h>
#include <mbedtls/platform.h>
#include <mbedtls/psa_util.h>
-#include <mbedtls/version.h>
#include <mbedtls/x509.h>
#include <psa/crypto.h>
#include <psa/crypto_platform.h>
@@ -433,78 +431,61 @@
unsigned int iv_len, const void *tag,
unsigned int tag_len)
{
- mbedtls_gcm_context ctx;
- mbedtls_cipher_id_t cipher = MBEDTLS_CIPHER_ID_AES;
+ mbedtls_svc_key_id_t key_id = MBEDTLS_SVC_KEY_ID_INIT;
+ psa_aead_operation_t operation = PSA_AEAD_OPERATION_INIT;
+ psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT;
+ psa_status_t psa_status = PSA_ERROR_GENERIC_ERROR;
unsigned char buf[DEC_OP_BUF_SIZE];
- unsigned char tag_buf[CRYPTO_MAX_TAG_SIZE];
unsigned char *pt = data_ptr;
size_t dec_len;
- int diff, i, rc;
- size_t output_length __unused;
+ size_t output_length;
- mbedtls_gcm_init(&ctx);
+ /* Load the key into the PSA key store. */
+ psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT);
+ psa_set_key_algorithm(&attributes, PSA_ALG_GCM);
+ psa_set_key_type(&attributes, PSA_KEY_TYPE_AES);
- rc = mbedtls_gcm_setkey(&ctx, cipher, key, key_len * 8);
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ psa_status = psa_import_key(&attributes, key, key_len, &key_id);
+ if (psa_status != PSA_SUCCESS) {
+ return CRYPTO_ERR_DECRYPTION;
}
-#if (MBEDTLS_VERSION_MAJOR < 3)
- rc = mbedtls_gcm_starts(&ctx, MBEDTLS_GCM_DECRYPT, iv, iv_len, NULL, 0);
-#else
- rc = mbedtls_gcm_starts(&ctx, MBEDTLS_GCM_DECRYPT, iv, iv_len);
-#endif
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ /* Perform the decryption. */
+ psa_status = psa_aead_decrypt_setup(&operation, key_id, PSA_ALG_GCM);
+ if (psa_status != PSA_SUCCESS) {
+ goto err;
+ }
+
+ psa_status = psa_aead_set_nonce(&operation, iv, iv_len);
+ if (psa_status != PSA_SUCCESS) {
+ goto err;
}
while (len > 0) {
dec_len = MIN(sizeof(buf), len);
-#if (MBEDTLS_VERSION_MAJOR < 3)
- rc = mbedtls_gcm_update(&ctx, dec_len, pt, buf);
-#else
- rc = mbedtls_gcm_update(&ctx, pt, dec_len, buf, sizeof(buf), &output_length);
-#endif
-
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ psa_status = psa_aead_update(&operation, pt, dec_len, buf,
+ sizeof(buf), &output_length);
+ if (psa_status != PSA_SUCCESS) {
+ goto err;
}
- memcpy(pt, buf, dec_len);
- pt += dec_len;
+ memcpy(pt, buf, output_length);
+ pt += output_length;
len -= dec_len;
}
-#if (MBEDTLS_VERSION_MAJOR < 3)
- rc = mbedtls_gcm_finish(&ctx, tag_buf, sizeof(tag_buf));
-#else
- rc = mbedtls_gcm_finish(&ctx, NULL, 0, &output_length, tag_buf, sizeof(tag_buf));
-#endif
-
- if (rc != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
+ /* Verify the tag. */
+ psa_status = psa_aead_verify(&operation, NULL, 0, &output_length, tag, tag_len);
+ if (psa_status == PSA_SUCCESS) {
+ psa_destroy_key(key_id);
+ return CRYPTO_SUCCESS;
}
- /* Check tag in "constant-time" */
- for (diff = 0, i = 0; i < tag_len; i++)
- diff |= ((const unsigned char *)tag)[i] ^ tag_buf[i];
-
- if (diff != 0) {
- rc = CRYPTO_ERR_DECRYPTION;
- goto exit_gcm;
- }
-
- /* GCM decryption success */
- rc = CRYPTO_SUCCESS;
-
-exit_gcm:
- mbedtls_gcm_free(&ctx);
- return rc;
+err:
+ psa_aead_abort(&operation);
+ psa_destroy_key(key_id);
+ return CRYPTO_ERR_DECRYPTION;
}
/*
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index fed16a7..14b03d9 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -14,7 +14,7 @@
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
-#define MAX_STACK_DEPTH (15U)
+#define MAX_STACK_DEPTH (40U)
/* This is used for floating-point precision calculations. */
#define FP_PRECISION (100000000UL)
@@ -52,33 +52,23 @@
return &driver;
}
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth);
+static int enable_module(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
-static int enable_clk_module(const struct s32cc_clk_obj *module,
- const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module)
{
const struct s32cc_clk *clk = s32cc_obj2clk(module);
- int ret;
-
- ret = update_stack_depth(depth);
- if (ret != 0) {
- return ret;
- }
-
- if (clk == NULL) {
- return -EINVAL;
- }
if (clk->module != NULL) {
- return enable_module(clk->module, depth);
+ return clk->module;
}
if (clk->pclock != NULL) {
- return enable_clk_module(&clk->pclock->desc, drv, depth);
+ return &clk->pclock->desc;
}
- return -EINVAL;
+ return NULL;
}
static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
@@ -145,14 +135,14 @@
}
}
-static int enable_osc(const struct s32cc_clk_obj *module,
+static int enable_osc(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_osc *osc = s32cc_obj2osc(module);
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -175,6 +165,17 @@
return ret;
}
+static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_pll *pll = s32cc_obj2pll(module);
+
+ if (pll->source == NULL) {
+ ERROR("Failed to identify PLL's parent\n");
+ }
+
+ return pll->source;
+}
+
static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq,
uint32_t *mfi, uint32_t *mfn)
@@ -313,9 +314,9 @@
return ret;
}
-static int enable_pll(const struct s32cc_clk_obj *module,
+static int enable_pll(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_pll *pll = s32cc_obj2pll(module);
const struct s32cc_clkmux *mux;
@@ -324,7 +325,7 @@
uint32_t sclk_id;
int ret;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -403,9 +404,20 @@
enable_odiv(pll_addr, div_index);
}
-static int enable_pll_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+
+ if (pdiv->parent == NULL) {
+ ERROR("Failed to identify PLL DIV's parent\n");
+ }
+
+ return pdiv->parent;
+}
+
+static int enable_pll_div(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
uintptr_t pll_addr = 0x0ULL;
@@ -413,7 +425,7 @@
uint32_t dc;
int ret;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -526,15 +538,34 @@
mux_hw_clk, false);
}
-static int enable_mux(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ struct s32cc_clk *clk;
+
+ if (mux == NULL) {
+ return NULL;
+ }
+
+ clk = s32cc_get_arch_clk(mux->source_id);
+ if (clk == NULL) {
+ ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n",
+ mux->source_id, mux->index);
+ return NULL;
+ }
+
+ return &clk->desc;
+}
+
+static int enable_mux(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
const struct s32cc_clk *clk;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -553,6 +584,7 @@
switch (mux->module) {
/* PLL mux will be enabled by PLL setup */
case S32CC_ARM_PLL:
+ case S32CC_PERIPH_PLL:
break;
case S32CC_CGM1:
ret = enable_cgm_mux(mux, drv);
@@ -569,13 +601,24 @@
return ret;
}
-static int enable_dfs(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_dfs *dfs = s32cc_obj2dfs(module);
+
+ if (dfs->parent == NULL) {
+ ERROR("Failed to identify DFS's parent\n");
+ }
+
+ return dfs->parent;
+}
+
+static int enable_dfs(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -722,9 +765,21 @@
return 0;
}
-static int enable_dfs_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *
+get_dfs_div_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+
+ if (dfs_div->parent == NULL) {
+ ERROR("Failed to identify DFS divider's parent\n");
+ }
+
+ return dfs_div->parent;
+}
+
+static int enable_dfs_div(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
const struct s32cc_pll *pll;
@@ -733,7 +788,7 @@
uint32_t mfi, mfn;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -762,12 +817,69 @@
return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
}
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
+typedef int (*enable_clk_t)(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
+
+static int no_enable(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
{
- const struct s32cc_clk_drv *drv = get_drv();
+ return 0;
+}
+
+static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod,
+ const struct s32cc_clk_drv *drv, bool leaf_node,
+ unsigned int depth)
+{
int ret = 0;
- ret = update_stack_depth(depth);
+ if (mod == NULL) {
+ return 0;
+ }
+
+ ret = update_stack_depth(&depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Refcount will be updated as part of the recursivity */
+ if (leaf_node) {
+ return en_cb(mod, drv, depth);
+ }
+
+ if (mod->refcount == 0U) {
+ ret = en_cb(mod, drv, depth);
+ }
+
+ if (ret == 0) {
+ mod->refcount++;
+ }
+
+ return ret;
+}
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module);
+
+static int enable_module(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ struct s32cc_clk_obj *parent = get_module_parent(module);
+ static const enable_clk_t enable_clbs[8] = {
+ [s32cc_clk_t] = no_enable,
+ [s32cc_osc_t] = enable_osc,
+ [s32cc_pll_t] = enable_pll,
+ [s32cc_pll_out_div_t] = enable_pll_div,
+ [s32cc_clkmux_t] = enable_mux,
+ [s32cc_shared_clkmux_t] = enable_mux,
+ [s32cc_dfs_t] = enable_dfs,
+ [s32cc_dfs_div_t] = enable_dfs_div,
+ };
+ uint32_t index;
+ int ret = 0;
+
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -776,53 +888,55 @@
return -EINVAL;
}
- switch (module->type) {
- case s32cc_osc_t:
- ret = enable_osc(module, drv, depth);
- break;
- case s32cc_clk_t:
- ret = enable_clk_module(module, drv, depth);
- break;
- case s32cc_pll_t:
- ret = enable_pll(module, drv, depth);
- break;
- case s32cc_pll_out_div_t:
- ret = enable_pll_div(module, drv, depth);
- break;
- case s32cc_clkmux_t:
- ret = enable_mux(module, drv, depth);
- break;
- case s32cc_shared_clkmux_t:
- ret = enable_mux(module, drv, depth);
- break;
- case s32cc_fixed_div_t:
- ret = -ENOTSUP;
- break;
- case s32cc_dfs_t:
- ret = enable_dfs(module, drv, depth);
- break;
- case s32cc_dfs_div_t:
- ret = enable_dfs_div(module, drv, depth);
- break;
- default:
- ret = -EINVAL;
- break;
+ index = (uint32_t)module->type;
+
+ if (index >= ARRAY_SIZE(enable_clbs)) {
+ ERROR("Undefined module type: %d\n", module->type);
+ return -EINVAL;
+ }
+
+ if (enable_clbs[index] == NULL) {
+ ERROR("Undefined callback for the clock type: %d\n",
+ module->type);
+ return -EINVAL;
+ }
+
+ parent = get_module_parent(module);
+
+ ret = exec_cb_with_refcount(enable_module, parent, drv,
+ false, depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = exec_cb_with_refcount(enable_clbs[index], module, drv,
+ true, depth);
+ if (ret != 0) {
+ return ret;
}
return ret;
}
+static int enable_module_with_refcount(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ return exec_cb_with_refcount(enable_module, module, drv, false, depth);
+}
+
static int s32cc_clk_enable(unsigned long id)
{
+ const struct s32cc_clk_drv *drv = get_drv();
unsigned int depth = MAX_STACK_DEPTH;
- const struct s32cc_clk *clk;
+ struct s32cc_clk *clk;
clk = s32cc_get_arch_clk(id);
if (clk == NULL) {
return -EINVAL;
}
- return enable_module(&clk->desc, &depth);
+ return enable_module_with_refcount(&clk->desc, drv, depth);
}
static void s32cc_clk_disable(unsigned long id)
@@ -1115,9 +1229,79 @@
return ret;
}
+static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module)
+{
+ return NULL;
+}
+
+typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj);
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
+{
+ static const get_parent_clb_t parents_clbs[8] = {
+ [s32cc_clk_t] = get_clk_parent,
+ [s32cc_osc_t] = get_no_parent,
+ [s32cc_pll_t] = get_pll_parent,
+ [s32cc_pll_out_div_t] = get_pll_div_parent,
+ [s32cc_clkmux_t] = get_mux_parent,
+ [s32cc_shared_clkmux_t] = get_mux_parent,
+ [s32cc_dfs_t] = get_dfs_parent,
+ [s32cc_dfs_div_t] = get_dfs_div_parent,
+ };
+ uint32_t index;
+
+ if (module == NULL) {
+ return NULL;
+ }
+
+ index = (uint32_t)module->type;
+
+ if (index >= ARRAY_SIZE(parents_clbs)) {
+ ERROR("Undefined module type: %d\n", module->type);
+ return NULL;
+ }
+
+ if (parents_clbs[index] == NULL) {
+ ERROR("Undefined parent getter for type: %d\n", module->type);
+ return NULL;
+ }
+
+ return parents_clbs[index](module);
+}
+
static int s32cc_clk_get_parent(unsigned long id)
{
- return -ENOTSUP;
+ struct s32cc_clk *parent_clk;
+ const struct s32cc_clk_obj *parent;
+ const struct s32cc_clk *clk;
+ unsigned long parent_id;
+ int ret;
+
+ clk = s32cc_get_arch_clk(id);
+ if (clk == NULL) {
+ return -EINVAL;
+ }
+
+ parent = get_module_parent(clk->module);
+ if (parent == NULL) {
+ return -EINVAL;
+ }
+
+ parent_clk = s32cc_obj2clk(parent);
+ if (parent_clk == NULL) {
+ return -EINVAL;
+ }
+
+ ret = s32cc_get_clk_id(parent_clk, &parent_id);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (parent_id > (unsigned long)INT_MAX) {
+ return -E2BIG;
+ }
+
+ return (int)parent_id;
}
static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index 45e2070..17ded0e 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -192,12 +192,21 @@
.n_clks = ARRAY_SIZE(s32cc_arch_clk_list),
};
+static const struct s32cc_clk_array *s32cc_clk_table[2] = {
+ &s32cc_hw_clocks,
+ &s32cc_arch_clocks,
+};
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id)
{
- static const struct s32cc_clk_array *clk_table[2] = {
- &s32cc_hw_clocks,
- &s32cc_arch_clocks,
- };
+ return s32cc_get_clk_from_table(s32cc_clk_table,
+ ARRAY_SIZE(s32cc_clk_table),
+ id);
+}
- return s32cc_get_clk_from_table(clk_table, ARRAY_SIZE(clk_table), id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id)
+{
+ return s32cc_get_id_from_table(s32cc_clk_table,
+ ARRAY_SIZE(s32cc_clk_table),
+ clk, id);
}
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_utils.c b/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
index 14ab674..0e75054 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
@@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-utils.h>
@@ -42,3 +43,23 @@
return NULL;
}
+
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+ size_t size, const struct s32cc_clk *clk,
+ unsigned long *clk_index)
+{
+ size_t i, j;
+
+ for (i = 0; i < size; i++) {
+ for (j = 0; j < clk_arr[i]->n_clks; j++) {
+ if (clk_arr[i]->clks[j] != clk) {
+ continue;
+ }
+
+ *clk_index = S32CC_CLK(clk_arr[i]->type_mask, j);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 8c4a9e8..3f6d3d7 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -17,7 +17,7 @@
#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
-static int enable_fxosc_clk(void)
+static int setup_fxosc(void)
{
int ret;
@@ -26,15 +26,10 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_FXOSC);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
-static int enable_arm_pll(void)
+static int setup_arm_pll(void)
{
int ret;
@@ -53,20 +48,10 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
- if (ret != 0) {
- return ret;
- }
-
- ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
-static int enable_periph_pll(void)
+static int setup_periph_pll(void)
{
int ret;
@@ -85,16 +70,6 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
- if (ret != 0) {
- return ret;
- }
-
- ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
@@ -170,17 +145,12 @@
s32cc_clk_register_drv();
- ret = enable_fxosc_clk();
+ ret = setup_fxosc();
if (ret != 0) {
return ret;
}
- ret = enable_arm_pll();
- if (ret != 0) {
- return ret;
- }
-
- ret = enable_periph_pll();
+ ret = setup_arm_pll();
if (ret != 0) {
return ret;
}
@@ -195,6 +165,11 @@
return ret;
}
+ ret = setup_periph_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
ret = enable_uart_clk();
if (ret != 0) {
return ret;
diff --git a/drivers/st/pmic/stm32mp_pmic2.c b/drivers/st/pmic/stm32mp_pmic2.c
new file mode 100644
index 0000000..c19d36a
--- /dev/null
+++ b/drivers/st/pmic/stm32mp_pmic2.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/regulator.h>
+#include <drivers/st/stm32_i2c.h>
+#include <drivers/st/stm32mp_pmic2.h>
+#include <drivers/st/stpmic2.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+#include <lib/utils_def.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#define PMIC_NODE_NOT_FOUND 1
+
+struct regul_handle_s {
+ const uint32_t id;
+ uint16_t bypass_mv;
+};
+
+static struct pmic_handle_s pmic2_handle;
+static struct i2c_handle_s i2c_handle;
+
+/* This driver is monoinstance */
+static struct pmic_handle_s *pmic2;
+
+static int dt_get_pmic_node(void *fdt)
+{
+ static int node = -FDT_ERR_BADOFFSET;
+
+ if (node == -FDT_ERR_BADOFFSET) {
+ node = fdt_node_offset_by_compatible(fdt, -1, "st,stpmic2");
+ }
+
+ return node;
+}
+
+int dt_pmic_status(void)
+{
+ static int status = -FDT_ERR_BADVALUE;
+ int node;
+ void *fdt;
+
+ if (status != -FDT_ERR_BADVALUE) {
+ return status;
+ }
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = dt_get_pmic_node(fdt);
+ if (node <= 0) {
+ status = -FDT_ERR_NOTFOUND;
+
+ return status;
+ }
+
+ status = DT_SECURE;
+
+ return status;
+}
+
+/*
+ * Get PMIC and its I2C bus configuration from the device tree.
+ * Return 0 on success, negative on error, 1 if no PMIC node is defined.
+ */
+static int dt_pmic2_i2c_config(struct dt_node_info *i2c_info,
+ struct stm32_i2c_init_s *init,
+ uint32_t *i2c_addr)
+{
+ static int i2c_node = -FDT_ERR_NOTFOUND;
+ void *fdt;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ if (i2c_node == -FDT_ERR_NOTFOUND) {
+ int pmic_node;
+ const fdt32_t *cuint;
+
+ pmic_node = dt_get_pmic_node(fdt);
+ if (pmic_node < 0) {
+ return PMIC_NODE_NOT_FOUND;
+ }
+
+ cuint = fdt_getprop(fdt, pmic_node, "reg", NULL);
+ if (cuint == NULL) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ *i2c_addr = fdt32_to_cpu(*cuint) << 1;
+ if (*i2c_addr > UINT16_MAX) {
+ return -FDT_ERR_BADVALUE;
+ }
+
+ i2c_node = fdt_parent_offset(fdt, pmic_node);
+ if (i2c_node < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+ }
+
+ dt_fill_device_info(i2c_info, i2c_node);
+ if (i2c_info->base == 0U) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ i2c_info->status = DT_SECURE;
+
+ return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init);
+}
+
+bool initialize_pmic_i2c(void)
+{
+ int ret;
+ struct dt_node_info i2c_info;
+ struct i2c_handle_s *i2c = &i2c_handle;
+ uint32_t i2c_addr = 0U;
+ struct stm32_i2c_init_s i2c_init;
+
+ ret = dt_pmic2_i2c_config(&i2c_info, &i2c_init, &i2c_addr);
+ if (ret < 0) {
+ ERROR("I2C configuration failed %d\n", ret);
+ panic();
+ }
+
+ if (ret != 0) {
+ return false;
+ }
+
+ /* Initialize PMIC I2C */
+ i2c->i2c_base_addr = i2c_info.base;
+ i2c->dt_status = i2c_info.status;
+ i2c->clock = i2c_info.clock;
+ i2c->i2c_state = I2C_STATE_RESET;
+ i2c_init.own_address1 = i2c_addr;
+ i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
+ i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
+ i2c_init.own_address2 = 0;
+ i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK;
+ i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE;
+ i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE;
+ i2c_init.analog_filter = 1;
+ i2c_init.digital_filter_coef = 0;
+
+ ret = stm32_i2c_init(i2c, &i2c_init);
+ if (ret != 0) {
+ ERROR("Cannot initialize I2C %x (%d)\n",
+ i2c->i2c_base_addr, ret);
+ panic();
+ }
+
+ if (!stm32_i2c_is_device_ready(i2c, i2c_addr, 1,
+ I2C_TIMEOUT_BUSY_MS)) {
+ ERROR("I2C device not ready\n");
+ panic();
+ }
+
+ pmic2 = &pmic2_handle;
+ pmic2->i2c_handle = &i2c_handle;
+ pmic2->i2c_addr = i2c_addr;
+
+ return true;
+}
+
+static int pmic2_set_state(const struct regul_description *desc, bool enable)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: set state to %d\n", desc->node_name, enable);
+
+ return stpmic2_regulator_set_state(pmic2, regul->id, enable);
+}
+
+static int pmic2_get_state(const struct regul_description *desc)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ bool enabled;
+
+ VERBOSE("%s: get state\n", desc->node_name);
+
+ if (stpmic2_regulator_get_state(pmic2, regul->id, &enabled) < 0) {
+ panic();
+ }
+
+ return enabled;
+}
+
+static int pmic2_get_voltage(const struct regul_description *desc)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ uint16_t mv;
+
+ VERBOSE("%s: get volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ /* If the regul is in bypass mode, return bypass value */
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (ret == 1) {
+ return regul->bypass_mv;
+ }
+ };
+
+ if (stpmic2_regulator_get_voltage(pmic2, regul->id, &mv) < 0) {
+ panic();
+ }
+
+ return mv;
+}
+
+static int pmic2_set_voltage(const struct regul_description *desc, uint16_t mv)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: set volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ /* If the regul is in bypass mode, authorize bypass mV */
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if ((ret == 1) && (mv != regul->bypass_mv)) {
+ return -EPERM;
+ }
+ };
+
+ return stpmic2_regulator_set_voltage(pmic2, regul->id, mv);
+}
+
+static int pmic2_list_voltages(const struct regul_description *desc,
+ const uint16_t **levels, size_t *count)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: list volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* bypass is enabled, return a list with only bypass mV */
+ if (ret == 1) {
+ if (count != NULL) {
+ *count = 1U;
+ }
+ if (levels != NULL) {
+ *levels = ®ul->bypass_mv;
+ }
+ return 0;
+ }
+ };
+
+ return stpmic2_regulator_levels_mv(pmic2, regul->id, levels, count);
+}
+
+static int pmic2_set_flag(const struct regul_description *desc, uint16_t flag)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ uint32_t id = regul->id;
+ int ret = -EPERM;
+
+ VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag);
+
+ switch (flag) {
+ case REGUL_PULL_DOWN:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_PULL_DOWN, 1U);
+ break;
+ case REGUL_OCP:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_OCP, 1U);
+ break;
+ case REGUL_SINK_SOURCE:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_SINK_SOURCE, 1U);
+ break;
+ case REGUL_ENABLE_BYPASS:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_BYPASS, 1U);
+ break;
+ case REGUL_MASK_RESET:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_MASK_RESET, 1U);
+ break;
+ default:
+ ERROR("Invalid flag %u", flag);
+ panic();
+ }
+
+ if (ret != 0) {
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+int stpmic2_set_prop(const struct regul_description *desc, uint16_t prop, uint32_t value)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ int ret;
+
+ VERBOSE("%s: set_prop 0x%x val=%u\n", desc->node_name, prop, value);
+
+ ret = stpmic2_regulator_set_prop(pmic2, regul->id, prop, value);
+ if (ret != 0)
+ return -EPERM;
+
+ return 0;
+}
+
+static struct regul_ops pmic2_ops = {
+ .set_state = pmic2_set_state,
+ .get_state = pmic2_get_state,
+ .set_voltage = pmic2_set_voltage,
+ .get_voltage = pmic2_get_voltage,
+ .list_voltages = pmic2_list_voltages,
+ .set_flag = pmic2_set_flag,
+};
+
+#define DEFINE_PMIC_REGUL_HANDLE(rid) \
+[(rid)] = { \
+ .id = (rid), \
+}
+
+static struct regul_handle_s pmic2_regul_handles[STPMIC2_NB_REG] = {
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK1),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK2),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK3),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK4),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK5),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK6),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK7),
+
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO1),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO2),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO3),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO4),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO5),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO6),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO7),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO8),
+
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_REFDDR),
+};
+
+#define DEFINE_REGUL(rid, name) \
+[rid] = { \
+ .node_name = name, \
+ .ops = &pmic2_ops, \
+ .driver_data = &pmic2_regul_handles[rid], \
+}
+
+static const struct regul_description pmic2_descs[STPMIC2_NB_REG] = {
+ DEFINE_REGUL(STPMIC2_BUCK1, "buck1"),
+ DEFINE_REGUL(STPMIC2_BUCK2, "buck2"),
+ DEFINE_REGUL(STPMIC2_BUCK3, "buck3"),
+ DEFINE_REGUL(STPMIC2_BUCK4, "buck4"),
+ DEFINE_REGUL(STPMIC2_BUCK5, "buck5"),
+ DEFINE_REGUL(STPMIC2_BUCK6, "buck6"),
+ DEFINE_REGUL(STPMIC2_BUCK7, "buck7"),
+
+ DEFINE_REGUL(STPMIC2_LDO1, "ldo1"),
+ DEFINE_REGUL(STPMIC2_LDO2, "ldo2"),
+ DEFINE_REGUL(STPMIC2_LDO3, "ldo3"),
+ DEFINE_REGUL(STPMIC2_LDO4, "ldo4"),
+ DEFINE_REGUL(STPMIC2_LDO5, "ldo5"),
+ DEFINE_REGUL(STPMIC2_LDO6, "ldo6"),
+ DEFINE_REGUL(STPMIC2_LDO7, "ldo7"),
+ DEFINE_REGUL(STPMIC2_LDO8, "ldo8"),
+
+ DEFINE_REGUL(STPMIC2_REFDDR, "refddr"),
+};
+
+static int register_pmic2(void)
+{
+ void *fdt;
+ int pmic_node, regulators_node, subnode;
+
+ VERBOSE("Register pmic2\n");
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ pmic_node = dt_get_pmic_node(fdt);
+ if (pmic_node < 0) {
+ return pmic_node;
+ }
+
+ regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators");
+ if (regulators_node < 0) {
+ return -ENOENT;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, regulators_node) {
+ const char *reg_name = fdt_get_name(fdt, subnode, NULL);
+ const struct regul_description *desc;
+ unsigned int i;
+ int ret;
+ const fdt32_t *cuint;
+
+ for (i = 0; i < STPMIC2_NB_REG; i++) {
+ desc = &pmic2_descs[i];
+ if (strcmp(desc->node_name, reg_name) == 0) {
+ break;
+ }
+ }
+ assert(i < STPMIC2_NB_REG);
+
+ ret = regulator_register(desc, subnode);
+ if (ret != 0) {
+ WARN("%s:%d failed to register %s\n", __func__,
+ __LINE__, reg_name);
+ return ret;
+ }
+
+ cuint = fdt_getprop(fdt, subnode, "st,regulator-bypass-microvolt", NULL);
+ if (cuint != NULL) {
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ regul->bypass_mv = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U);
+ VERBOSE("%s: bypass voltage=%umV\n", desc->node_name,
+ regul->bypass_mv);
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,mask-reset", NULL) != NULL) {
+ VERBOSE("%s: set mask-reset\n", desc->node_name);
+ ret = pmic2_set_flag(desc, REGUL_MASK_RESET);
+ if (ret != 0) {
+ ERROR("set mask-reset failed\n");
+ return ret;
+ }
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,regulator-sink-source", NULL) != NULL) {
+ VERBOSE("%s: set regulator-sink-source\n", desc->node_name);
+ ret = pmic2_set_flag(desc, REGUL_SINK_SOURCE);
+ if (ret != 0) {
+ ERROR("set regulator-sink-source failed\n");
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+void initialize_pmic(void)
+{
+ int ret;
+ uint8_t val;
+
+ ret = initialize_pmic_i2c();
+ if (!ret) {
+ VERBOSE("No PMIC2\n");
+ return;
+ }
+
+ if (stpmic2_get_version(pmic2, &val) != 0) {
+ ERROR("Failed to access PMIC\n");
+ panic();
+ }
+ INFO("PMIC2 version = 0x%02x\n", val);
+
+ if (stpmic2_get_product_id(pmic2, &val) != 0) {
+ ERROR("Failed to access PMIC\n");
+ panic();
+ }
+ INFO("PMIC2 product ID = 0x%02x\n", val);
+
+ ret = register_pmic2();
+ if (ret < 0) {
+ ERROR("Register pmic2 failed\n");
+ panic();
+ }
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+ stpmic2_dump_regulators(pmic2);
+#endif
+}
diff --git a/drivers/st/pmic/stpmic2.c b/drivers/st/pmic/stpmic2.c
new file mode 100644
index 0000000..05a80ec
--- /dev/null
+++ b/drivers/st/pmic/stpmic2.c
@@ -0,0 +1,474 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/st/stpmic2.h>
+
+#define RET_SUCCESS 0
+#define RET_ERROR_NOT_SUPPORTED -1
+#define RET_ERROR_GENERIC -2
+#define RET_ERROR_BAD_PARAMETERS -3
+
+#define I2C_TIMEOUT_MS 25
+
+#define VOLTAGE_INDEX_INVALID ((size_t)~0U)
+
+struct regul_struct {
+ const char *name;
+ const uint16_t *volt_table;
+ uint8_t volt_table_size;
+ uint8_t volt_cr;
+ uint8_t volt_shift;
+ uint8_t en_cr;
+ uint8_t alt_en_cr;
+ uint8_t msrt_reg;
+ uint8_t msrt_mask;
+ uint8_t pd_reg;
+ uint8_t pd_val;
+ uint8_t ocp_reg;
+ uint8_t ocp_mask;
+};
+
+/* Voltage tables in mV */
+static const uint16_t buck1236_volt_table[] = {
+ 500U, 510U, 520U, 530U, 540U, 550U, 560U, 570U, 580U, 590U,
+ 600U, 610U, 620U, 630U, 640U, 650U, 660U, 670U, 680U, 690U,
+ 700U, 710U, 720U, 730U, 740U, 750U, 760U, 770U, 780U, 790U,
+ 800U, 810U, 820U, 830U, 840U, 850U, 860U, 870U, 880U, 890U,
+ 900U, 910U, 920U, 930U, 940U, 950U, 960U, 970U, 980U, 990U,
+ 1000U, 1010U, 1020U, 1030U, 1040U, 1050U, 1060U, 1070U, 1080U, 1090U,
+ 1100U, 1110U, 1120U, 1130U, 1140U, 1150U, 1160U, 1170U, 1180U, 1190U,
+ 1200U, 1210U, 1220U, 1230U, 1240U, 1250U, 1260U, 1270U, 1280U, 1290U,
+ 1300U, 1310U, 1320U, 1330U, 1340U, 1350U, 1360U, 1370U, 1380U, 1390U,
+ 1400U, 1410U, 1420U, 1430U, 1440U, 1450U, 1460U, 1470U, 1480U, 1490U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U
+};
+
+static const uint16_t buck457_volt_table[] = {
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1600U, 1700U, 1800U, 1900U, 2000U, 2100U, 2200U, 2300U, 2400U,
+ 2500U, 2600U, 2700U, 2800U, 2900U, 3000U, 3100U, 3200U, 3300U, 3400U,
+ 3500U, 3600U, 3700U, 3800U, 3900U, 4000U, 4100U, 4200U
+};
+
+static const uint16_t ldo235678_volt_table[] = {
+ 900U, 1000U, 1100U, 1200U, 1300U, 1400U, 1500U, 1600U, 1700U, 1800U,
+ 1900U, 2000U, 2100U, 2200U, 2300U, 2400U, 2500U, 2600U, 2700U, 2800U,
+ 2900U, 3000U, 3100U, 3200U, 3300U, 3400U, 3500U, 3600U, 3700U, 3800U,
+ 3900U, 4000U
+};
+
+static const uint16_t ldo1_volt_table[] = {
+ 1800U,
+};
+
+static const uint16_t ldo4_volt_table[] = {
+ 3300U,
+};
+
+static const uint16_t refddr_volt_table[] = {
+ 0,
+};
+
+#define DEFINE_BUCK(regu_name, ID, pd, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .en_cr = ID ## _MAIN_CR2, \
+ .volt_cr = ID ## _MAIN_CR1, \
+ .alt_en_cr = ID ## _ALT_CR2, \
+ .msrt_reg = BUCKS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = pd, \
+ .pd_val = ID ## _PD_FAST, \
+ .ocp_reg = FS_OCP_CR1, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+#define DEFINE_LDOx(regu_name, ID, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .volt_shift = LDO_VOLT_SHIFT, \
+ .en_cr = ID ## _MAIN_CR, \
+ .volt_cr = ID ## _MAIN_CR, \
+ .alt_en_cr = ID ## _ALT_CR, \
+ .msrt_reg = LDOS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = LDOS_PD_CR1, \
+ .pd_val = ID ## _PD, \
+ .ocp_reg = FS_OCP_CR2, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+#define DEFINE_REFDDR(regu_name, ID, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .en_cr = ID ## _MAIN_CR, \
+ .volt_cr = ID ## _MAIN_CR, \
+ .alt_en_cr = ID ## _ALT_CR, \
+ .msrt_reg = BUCKS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = LDOS_PD_CR2, \
+ .pd_val = ID ## _PD, \
+ .ocp_reg = FS_OCP_CR1, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+/* Table of Regulators in PMIC SoC */
+static const struct regul_struct regul_table[STPMIC2_NB_REG] = {
+ [STPMIC2_BUCK1] = DEFINE_BUCK("buck1", BUCK1, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK2] = DEFINE_BUCK("buck2", BUCK2, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK3] = DEFINE_BUCK("buck3", BUCK3, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK4] = DEFINE_BUCK("buck4", BUCK4, BUCKS_PD_CR1,
+ buck457_volt_table),
+ [STPMIC2_BUCK5] = DEFINE_BUCK("buck5", BUCK5, BUCKS_PD_CR2,
+ buck457_volt_table),
+ [STPMIC2_BUCK6] = DEFINE_BUCK("buck6", BUCK6, BUCKS_PD_CR2,
+ buck1236_volt_table),
+ [STPMIC2_BUCK7] = DEFINE_BUCK("buck7", BUCK7, BUCKS_PD_CR2,
+ buck457_volt_table),
+
+ [STPMIC2_REFDDR] = DEFINE_REFDDR("refddr", REFDDR, refddr_volt_table),
+
+ [STPMIC2_LDO1] = DEFINE_LDOx("ldo1", LDO1, ldo1_volt_table),
+ [STPMIC2_LDO2] = DEFINE_LDOx("ldo2", LDO2, ldo235678_volt_table),
+ [STPMIC2_LDO3] = DEFINE_LDOx("ldo3", LDO3, ldo235678_volt_table),
+ [STPMIC2_LDO4] = DEFINE_LDOx("ldo4", LDO4, ldo4_volt_table),
+ [STPMIC2_LDO5] = DEFINE_LDOx("ldo5", LDO5, ldo235678_volt_table),
+ [STPMIC2_LDO6] = DEFINE_LDOx("ldo6", LDO6, ldo235678_volt_table),
+ [STPMIC2_LDO7] = DEFINE_LDOx("ldo7", LDO7, ldo235678_volt_table),
+ [STPMIC2_LDO8] = DEFINE_LDOx("ldo8", LDO8, ldo235678_volt_table),
+
+};
+
+int stpmic2_register_read(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t *value)
+{
+ int ret = stm32_i2c_mem_read(pmic->i2c_handle,
+ pmic->i2c_addr,
+ (uint16_t)register_id,
+ I2C_MEMADD_SIZE_8BIT, value,
+ 1, I2C_TIMEOUT_MS);
+ if (ret != 0) {
+ ERROR("Failed to read reg:0x%x\n", register_id);
+ }
+
+ return ret;
+}
+
+int stpmic2_register_write(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value)
+{
+ uint8_t val = value;
+ int ret = stm32_i2c_mem_write(pmic->i2c_handle,
+ pmic->i2c_addr,
+ (uint16_t)register_id,
+ I2C_MEMADD_SIZE_8BIT, &val,
+ 1, I2C_TIMEOUT_MS);
+ if (ret != 0) {
+ ERROR("Failed to write reg:0x%x\n", register_id);
+ }
+
+ return ret;
+}
+
+int stpmic2_register_update(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value, uint8_t mask)
+{
+ int status;
+ uint8_t val = 0U;
+
+ status = stpmic2_register_read(pmic, register_id, &val);
+ if (status != 0) {
+ return status;
+ }
+
+ val = (val & ((uint8_t)~mask)) | (value & mask);
+
+ VERBOSE("REG:0x%x v=0x%x mask=0x%x -> 0x%x\n",
+ register_id, value, mask, val);
+
+ return stpmic2_register_write(pmic, register_id, val);
+}
+
+int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool enable)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (enable) {
+ return stpmic2_register_update(pmic, regul->en_cr, 1U, 1U);
+ } else {
+ return stpmic2_register_update(pmic, regul->en_cr, 0, 1U);
+ }
+}
+
+int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool *enabled)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t val;
+
+ if (stpmic2_register_read(pmic, regul->en_cr, &val) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ *enabled = (val & 1U) == 1U;
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
+ uint8_t id, const uint16_t **levels,
+ size_t *levels_count)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (regul == NULL) {
+ return RET_ERROR_BAD_PARAMETERS;
+ }
+
+ if (levels_count != NULL) {
+ *levels_count = regul->volt_table_size;
+ }
+ if (levels != NULL) {
+ *levels = regul->volt_table;
+ }
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t *val)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t value = 0U;
+ uint8_t mask;
+
+ if (regul->volt_table_size == 0U) {
+ return RET_ERROR_GENERIC;
+ }
+
+ mask = regul->volt_table_size - 1U;
+ if (mask != 0U) {
+ if (stpmic2_register_read(pmic, regul->volt_cr, &value) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ value = (value >> regul->volt_shift) & mask;
+ }
+
+ if (value > regul->volt_table_size) {
+ return RET_ERROR_GENERIC;
+ }
+
+ *val = regul->volt_table[value];
+
+ return RET_SUCCESS;
+}
+
+static size_t voltage_to_index(const struct regul_struct *regul,
+ uint16_t millivolts)
+{
+ unsigned int i;
+
+ assert(regul->volt_table);
+ for (i = 0U; i < regul->volt_table_size; i++) {
+ if (regul->volt_table[i] == millivolts) {
+ return i;
+ }
+ }
+
+ return VOLTAGE_INDEX_INVALID;
+}
+
+int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t millivolts)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ size_t index;
+ uint8_t mask;
+
+ if (!regul->volt_table_size) {
+ return RET_SUCCESS;
+ }
+
+ mask = regul->volt_table_size - 1U;
+
+ index = voltage_to_index(regul, millivolts);
+ if (index == VOLTAGE_INDEX_INVALID) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return stpmic2_register_update(pmic, regul->volt_cr,
+ index << regul->volt_shift,
+ mask << regul->volt_shift);
+}
+
+/* update both normal and alternate register */
+static int stpmic2_update_en_crs(struct pmic_handle_s *pmic, uint8_t id,
+ uint8_t value, uint8_t mask)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (stpmic2_register_update(pmic, regul->en_cr, value, mask) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ if (stpmic2_register_update(pmic, regul->alt_en_cr, value, mask) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t val;
+
+ VERBOSE("%s: get prop 0x%x\n", regul->name, prop);
+
+ switch (prop) {
+ case STPMIC2_BYPASS:
+ if ((id <= STPMIC2_BUCK7) || (id == STPMIC2_LDO1) ||
+ (id == STPMIC2_LDO4) || (id == STPMIC2_REFDDR)) {
+ return 0;
+ }
+
+ if (stpmic2_register_read(pmic, regul->en_cr, &val) != 0) {
+ return -EIO;
+ }
+
+ if ((val & LDO_BYPASS) != 0) {
+ return 1;
+ }
+
+ break;
+ default:
+ ERROR("Invalid prop %u\n", prop);
+ panic();
+ }
+
+ return 0;
+}
+
+int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop, uint32_t arg)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ VERBOSE("%s: set prop 0x%x arg=%u\n", regul->name, prop, arg);
+
+ switch (prop) {
+ case STPMIC2_PULL_DOWN:
+ return stpmic2_register_update(pmic, regul->pd_reg,
+ regul->pd_val,
+ regul->pd_val);
+ case STPMIC2_MASK_RESET:
+ if (!regul->msrt_mask) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+ /* enable mask reset */
+ return stpmic2_register_update(pmic, regul->msrt_reg,
+ regul->msrt_mask,
+ regul->msrt_mask);
+ case STPMIC2_BYPASS:
+ if ((id <= STPMIC2_BUCK7) || (id == STPMIC2_LDO1) ||
+ (id == STPMIC2_LDO4) || (id == STPMIC2_REFDDR)) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+
+ /* clear sink source mode */
+ if ((id == STPMIC2_LDO3) && (arg != 0U)) {
+ if (stpmic2_update_en_crs(pmic, id, 0, LDO3_SNK_SRC) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+ }
+
+ /* enable bypass mode */
+ return stpmic2_update_en_crs(pmic, id,
+ (arg != 0U) ? LDO_BYPASS : 0,
+ LDO_BYPASS);
+ case STPMIC2_SINK_SOURCE:
+ if (id != STPMIC2_LDO3) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+
+ /* clear bypass mode */
+ if (stpmic2_update_en_crs(pmic, id, 0, LDO_BYPASS) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return stpmic2_update_en_crs(pmic, id, LDO3_SNK_SRC,
+ LDO3_SNK_SRC);
+ case STPMIC2_OCP:
+ return stpmic2_register_update(pmic, regul->ocp_reg,
+ regul->ocp_mask,
+ regul->ocp_mask);
+ default:
+ ERROR("Invalid prop %u\n", prop);
+ panic();
+ }
+
+ return -EPERM;
+}
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+void stpmic2_dump_regulators(struct pmic_handle_s *pmic)
+{
+ size_t i;
+ char const *name;
+
+ for (i = 0U; i < ARRAY_SIZE(regul_table); i++) {
+ uint16_t val;
+ bool state;
+
+ if (!regul_table[i].volt_cr) {
+ continue;
+ }
+
+ stpmic2_regulator_get_voltage(pmic, i, &val);
+ stpmic2_regulator_get_state(pmic, i, &state);
+
+ name = regul_table[i].name;
+
+ VERBOSE("PMIC regul %s: %s, %dmV\n",
+ name, state ? "EN" : "DIS", val);
+ }
+}
+#endif
+
+int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val)
+{
+ return stpmic2_register_read(pmic, VERSION_SR, val);
+}
+
+int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val)
+{
+ return stpmic2_register_read(pmic, PRODUCT_ID, val);
+}
diff --git a/drivers/st/regulator/regulator_core.c b/drivers/st/regulator/regulator_core.c
index 2a5d0f7..b369acd 100644
--- a/drivers/st/regulator/regulator_core.c
+++ b/drivers/st/regulator/regulator_core.c
@@ -215,14 +215,18 @@
VERBOSE("%s: set mvolt\n", rdev->desc->node_name);
- if (rdev->desc->ops->set_voltage == NULL) {
- return -ENODEV;
- }
-
if ((mvolt < rdev->min_mv) || (mvolt > rdev->max_mv)) {
return -EPERM;
}
+ if (regulator_get_voltage(rdev) == mvolt) {
+ return 0U;
+ }
+
+ if (rdev->desc->ops->set_voltage == NULL) {
+ return -ENODEV;
+ }
+
lock_driver(rdev);
ret = rdev->desc->ops->set_voltage(rdev->desc, mvolt);
@@ -420,6 +424,7 @@
static int parse_properties(const void *fdt, struct rdev *rdev, int node)
{
+ const fdt32_t *cuint;
int ret;
if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) {
@@ -430,6 +435,13 @@
}
}
+ cuint = fdt_getprop(fdt, node, "regulator-enable-ramp-delay", NULL);
+ if (cuint != NULL) {
+ rdev->enable_ramp_delay = fdt32_to_cpu(*cuint);
+ VERBOSE("%s: enable_ramp_delay=%u\n", rdev->desc->node_name,
+ rdev->enable_ramp_delay);
+ }
+
return 0;
}
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi
index 769aab2..e250e3f 100644
--- a/fdts/stm32mp25-bl2.dtsi
+++ b/fdts/stm32mp25-bl2.dtsi
@@ -21,6 +21,9 @@
st-io_policies {
fip-handles {
compatible = "st,io-fip-handle";
+#if STM32MP_DDR_FIP_IO_STORAGE
+ ddr_fw_uuid = "b11249be-92dd-4b10-867c-2c6a4b47a7fb";
+#endif
fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e";
bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
diff --git a/fdts/stm32mp25-fw-config.dtsi b/fdts/stm32mp25-fw-config.dtsi
index b187ad2..102980d 100644
--- a/fdts/stm32mp25-fw-config.dtsi
+++ b/fdts/stm32mp25-fw-config.dtsi
@@ -25,6 +25,12 @@
id = <BL33_IMAGE_ID>;
};
+ soc_fw {
+ load-address = <0x0 STM32MP_SYSRAM_BASE>;
+ max-size = <STM32MP_BL31_SIZE>;
+ id = <BL31_IMAGE_ID>;
+ };
+
tos_fw {
id = <BL32_IMAGE_ID>;
};
diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi
index fb12808..a22c823 100644
--- a/fdts/stm32mp25-pinctrl.dtsi
+++ b/fdts/stm32mp25-pinctrl.dtsi
@@ -7,6 +7,17 @@
&pinctrl {
/omit-if-no-ref/
+ i2c7_pins_a: i2c7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 15, AF10)>, /* I2C7_SCL */
+ <STM32_PINMUX('D', 14, AF10)>; /* I2C7_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
diff --git a/fdts/stm32mp251.dtsi b/fdts/stm32mp251.dtsi
index 6f39b5a..9e89813 100644
--- a/fdts/stm32mp251.dtsi
+++ b/fdts/stm32mp251.dtsi
@@ -98,6 +98,134 @@
status = "disabled";
};
+ usart3: serial@400f0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400f0000 0x400>;
+ clocks = <&rcc CK_KER_USART3>;
+ resets = <&rcc USART3_R>;
+ status = "disabled";
+ };
+
+ uart4: serial@40100000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40100000 0x400>;
+ clocks = <&rcc CK_KER_UART4>;
+ resets = <&rcc UART4_R>;
+ status = "disabled";
+ };
+
+ uart5: serial@40110000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40110000 0x400>;
+ clocks = <&rcc CK_KER_UART5>;
+ resets = <&rcc UART5_R>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@40120000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40120000 0x400>;
+ clocks = <&rcc CK_KER_I2C1>;
+ resets = <&rcc I2C1_R>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40130000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40130000 0x400>;
+ clocks = <&rcc CK_KER_I2C2>;
+ resets = <&rcc I2C2_R>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@40140000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40140000 0x400>;
+ clocks = <&rcc CK_KER_I2C3>;
+ resets = <&rcc I2C3_R>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@40150000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40150000 0x400>;
+ clocks = <&rcc CK_KER_I2C4>;
+ resets = <&rcc I2C4_R>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@40160000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40160000 0x400>;
+ clocks = <&rcc CK_KER_I2C5>;
+ resets = <&rcc I2C5_R>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@40170000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40170000 0x400>;
+ clocks = <&rcc CK_KER_I2C6>;
+ resets = <&rcc I2C6_R>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@40180000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40180000 0x400>;
+ clocks = <&rcc CK_KER_I2C7>;
+ resets = <&rcc I2C7_R>;
+ status = "disabled";
+ };
+
+ usart6: serial@40220000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40220000 0x400>;
+ clocks = <&rcc CK_KER_USART6>;
+ resets = <&rcc USART6_R>;
+ status = "disabled";
+ };
+
+ uart9: serial@402c0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x402c0000 0x400>;
+ clocks = <&rcc CK_KER_UART9>;
+ resets = <&rcc UART9_R>;
+ status = "disabled";
+ };
+
+ usart1: serial@40330000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40330000 0x400>;
+ clocks = <&rcc CK_KER_USART1>;
+ resets = <&rcc USART1_R>;
+ status = "disabled";
+ };
+
+ uart7: serial@40370000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40370000 0x400>;
+ clocks = <&rcc CK_KER_UART7>;
+ resets = <&rcc UART7_R>;
+ status = "disabled";
+ };
+
+ uart8: serial@40380000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40380000 0x400>;
+ clocks = <&rcc CK_KER_UART8>;
+ resets = <&rcc UART8_R>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@46040000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x46040000 0x400>;
+ clocks = <&rcc CK_KER_I2C8>;
+ resets = <&rcc I2C8_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@48220000 {
compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
diff --git a/fdts/stm32mp257f-ev1.dts b/fdts/stm32mp257f-ev1.dts
index 6df1b30..d2b5e55 100644
--- a/fdts/stm32mp257f-ev1.dts
+++ b/fdts/stm32mp257f-ev1.dts
@@ -37,6 +37,131 @@
};
};
+&i2c7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic2: stpmic@33 {
+ compatible = "st,stpmic2";
+ reg = <0x33>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic2-regulators";
+
+ vddcpu: buck1 {
+ regulator-name = "vddcpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <910000>;
+ regulator-always-on;
+ };
+ vddcore: buck2 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <820000>;
+ regulator-max-microvolt = <820000>;
+ regulator-always-on;
+ };
+ vddgpu: buck3 {
+ regulator-name = "vddgpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ };
+ vddio_pmic: buck4 {
+ regulator-name = "vddio_pmic";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ v1v8: buck5 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vdd_ddr: buck6 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ v3v3: buck7 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vdda1v8_aon: ldo1 {
+ regulator-name = "vdda1v8_aon";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vdd_emmc: ldo2 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ st,regulator-sink-source;
+ };
+ vdd3v3_usb: ldo4 {
+ regulator-name = "vdd3v3_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vpp_ddr: ldo5 {
+ regulator-name = "vpp_ddr";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-enable-ramp-delay = <1000>;
+ };
+ vdd_sdcard: ldo7 {
+ regulator-name = "vdd_sdcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vddio_sdcard: ldo8 {
+ regulator-name = "vddio_sdcard";
+ st,regulator-bypass-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vref_ddr: refddr {
+ regulator-name = "vref_ddr";
+ };
+ };
+ };
+};
+
+&pwr {
+ vddio1: vddio1 {
+ vddio1-supply = <&vddio_sdcard>;
+ };
+ vddio2: vddio2 {
+ vddio2-supply = <&v1v8>;
+ };
+ vddio3: vddio3 {
+ vddio3-supply = <&vddio_pmic>;
+ };
+ vddio4: vddio4 {
+ vddio4-supply = <&vddio_pmic>;
+ };
+ vddio: vddio {
+ vdd-supply = <&vddio_pmic>;
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index ca46eb1..0e6137d 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -341,7 +341,7 @@
/* GITS_CTLR bit definitions */
#define GITS_CTLR_ENABLED_BIT BIT_32(0)
-#define GITS_CTLR_QUIESCENT_BIT BIT_32(1)
+#define GITS_CTLR_QUIESCENT_BIT BIT_32(31)
#define GITS_TYPER_VSGI BIT_64(39)
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
index 6a90406..e6adecc 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
@@ -11,7 +11,12 @@
size_t size,
unsigned long clk_id);
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+ size_t size, const struct s32cc_clk *clk,
+ unsigned long *clk_index);
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id);
void s32cc_clk_register_drv(void);
diff --git a/include/drivers/st/stm32mp_pmic2.h b/include/drivers/st/stm32mp_pmic2.h
new file mode 100644
index 0000000..51eba38
--- /dev/null
+++ b/include/drivers/st/stm32mp_pmic2.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_PMIC2_H
+#define STM32MP_PMIC2_H
+
+#include <stdbool.h>
+#include <drivers/st/regulator.h>
+
+#include <platform_def.h>
+
+/*
+ * dt_pmic_status - Check PMIC status from device tree
+ *
+ * Returns the status of the PMIC (secure, non-secure), or a negative value on
+ * error
+ */
+int dt_pmic_status(void);
+
+/*
+ * initialize_pmic_i2c - Initialize I2C for the PMIC control
+ *
+ * Returns true if PMIC is available, false if not found, panics on errors
+ */
+bool initialize_pmic_i2c(void);
+
+/*
+ * initialize_pmic - Main PMIC initialization function, called at platform init
+ *
+ * Panics on errors
+ */
+void initialize_pmic(void);
+
+/*
+ * stpmic2_set_prop - Set PMIC2 proprietary property
+ *
+ * Returns non zero on errors
+ */
+int stpmic2_set_prop(const struct regul_description *desc, uint16_t prop, uint32_t value);
+
+/*
+ * pmic_switch_off - switch off the platform with PMIC
+ *
+ * Panics on errors
+ */
+void pmic_switch_off(void);
+
+#endif /* STM32MP_PMIC2_H */
diff --git a/include/drivers/st/stm32mp_risab_regs.h b/include/drivers/st/stm32mp_risab_regs.h
new file mode 100644
index 0000000..1f49bf6
--- /dev/null
+++ b/include/drivers/st/stm32mp_risab_regs.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_RISAB_REGS_H
+#define STM32MP_RISAB_REGS_H
+
+#define RISAB_CR U(0x00)
+#define RISAB_IASR U(0x08)
+#define RISAB_IACR U(0x0C)
+#define RISAB_RIFLOCKR U(0x10)
+#define RISAB_IAESR U(0x20)
+#define RISAB_IADDR U(0x24)
+#define RISAB_PG0_SECCFGR U(0x100)
+#define RISAB_PG1_SECCFGR U(0x104)
+#define RISAB_PG2_SECCFGR U(0x108)
+#define RISAB_PG3_SECCFGR U(0x10C)
+#define RISAB_PG4_SECCFGR U(0x110)
+#define RISAB_PG5_SECCFGR U(0x114)
+#define RISAB_PG6_SECCFGR U(0x118)
+#define RISAB_PG7_SECCFGR U(0x11C)
+#define RISAB_PG8_SECCFGR U(0x120)
+#define RISAB_PG9_SECCFGR U(0x124)
+#define RISAB_PG10_SECCFGR U(0x128)
+#define RISAB_PG11_SECCFGR U(0x12C)
+#define RISAB_PG12_SECCFGR U(0x130)
+#define RISAB_PG13_SECCFGR U(0x134)
+#define RISAB_PG14_SECCFGR U(0x138)
+#define RISAB_PG15_SECCFGR U(0x13C)
+#define RISAB_PG16_SECCFGR U(0x140)
+#define RISAB_PG17_SECCFGR U(0x144)
+#define RISAB_PG18_SECCFGR U(0x148)
+#define RISAB_PG19_SECCFGR U(0x14C)
+#define RISAB_PG20_SECCFGR U(0x150)
+#define RISAB_PG21_SECCFGR U(0x154)
+#define RISAB_PG22_SECCFGR U(0x158)
+#define RISAB_PG23_SECCFGR U(0x15C)
+#define RISAB_PG24_SECCFGR U(0x160)
+#define RISAB_PG25_SECCFGR U(0x164)
+#define RISAB_PG26_SECCFGR U(0x168)
+#define RISAB_PG27_SECCFGR U(0x16C)
+#define RISAB_PG28_SECCFGR U(0x170)
+#define RISAB_PG29_SECCFGR U(0x174)
+#define RISAB_PG30_SECCFGR U(0x178)
+#define RISAB_PG31_SECCFGR U(0x17C)
+#define RISAB_PG0_PRIVCFGR U(0x200)
+#define RISAB_PG1_PRIVCFGR U(0x204)
+#define RISAB_PG2_PRIVCFGR U(0x208)
+#define RISAB_PG3_PRIVCFGR U(0x20C)
+#define RISAB_PG4_PRIVCFGR U(0x210)
+#define RISAB_PG5_PRIVCFGR U(0x214)
+#define RISAB_PG6_PRIVCFGR U(0x218)
+#define RISAB_PG7_PRIVCFGR U(0x21C)
+#define RISAB_PG8_PRIVCFGR U(0x220)
+#define RISAB_PG9_PRIVCFGR U(0x224)
+#define RISAB_PG10_PRIVCFGR U(0x228)
+#define RISAB_PG11_PRIVCFGR U(0x22C)
+#define RISAB_PG12_PRIVCFGR U(0x230)
+#define RISAB_PG13_PRIVCFGR U(0x234)
+#define RISAB_PG14_PRIVCFGR U(0x238)
+#define RISAB_PG15_PRIVCFGR U(0x23C)
+#define RISAB_PG16_PRIVCFGR U(0x240)
+#define RISAB_PG17_PRIVCFGR U(0x244)
+#define RISAB_PG18_PRIVCFGR U(0x248)
+#define RISAB_PG19_PRIVCFGR U(0x24C)
+#define RISAB_PG20_PRIVCFGR U(0x250)
+#define RISAB_PG21_PRIVCFGR U(0x254)
+#define RISAB_PG22_PRIVCFGR U(0x258)
+#define RISAB_PG23_PRIVCFGR U(0x25C)
+#define RISAB_PG24_PRIVCFGR U(0x260)
+#define RISAB_PG25_PRIVCFGR U(0x264)
+#define RISAB_PG26_PRIVCFGR U(0x268)
+#define RISAB_PG27_PRIVCFGR U(0x26C)
+#define RISAB_PG28_PRIVCFGR U(0x270)
+#define RISAB_PG29_PRIVCFGR U(0x274)
+#define RISAB_PG30_PRIVCFGR U(0x278)
+#define RISAB_PG31_PRIVCFGR U(0x27C)
+#define RISAB_PG0_C2PRIVCFGR U(0x600)
+#define RISAB_PG1_C2PRIVCFGR U(0x604)
+#define RISAB_PG2_C2PRIVCFGR U(0x608)
+#define RISAB_PG3_C2PRIVCFGR U(0x60C)
+#define RISAB_PG4_C2PRIVCFGR U(0x610)
+#define RISAB_PG5_C2PRIVCFGR U(0x614)
+#define RISAB_PG6_C2PRIVCFGR U(0x618)
+#define RISAB_PG7_C2PRIVCFGR U(0x61C)
+#define RISAB_PG8_C2PRIVCFGR U(0x620)
+#define RISAB_PG9_C2PRIVCFGR U(0x624)
+#define RISAB_PG10_C2PRIVCFGR U(0x628)
+#define RISAB_PG11_C2PRIVCFGR U(0x62C)
+#define RISAB_PG12_C2PRIVCFGR U(0x630)
+#define RISAB_PG13_C2PRIVCFGR U(0x634)
+#define RISAB_PG14_C2PRIVCFGR U(0x638)
+#define RISAB_PG15_C2PRIVCFGR U(0x63C)
+#define RISAB_PG16_C2PRIVCFGR U(0x640)
+#define RISAB_PG17_C2PRIVCFGR U(0x644)
+#define RISAB_PG18_C2PRIVCFGR U(0x648)
+#define RISAB_PG19_C2PRIVCFGR U(0x64C)
+#define RISAB_PG20_C2PRIVCFGR U(0x650)
+#define RISAB_PG21_C2PRIVCFGR U(0x654)
+#define RISAB_PG22_C2PRIVCFGR U(0x658)
+#define RISAB_PG23_C2PRIVCFGR U(0x65C)
+#define RISAB_PG24_C2PRIVCFGR U(0x660)
+#define RISAB_PG25_C2PRIVCFGR U(0x664)
+#define RISAB_PG26_C2PRIVCFGR U(0x668)
+#define RISAB_PG27_C2PRIVCFGR U(0x66C)
+#define RISAB_PG28_C2PRIVCFGR U(0x670)
+#define RISAB_PG29_C2PRIVCFGR U(0x674)
+#define RISAB_PG30_C2PRIVCFGR U(0x678)
+#define RISAB_PG31_C2PRIVCFGR U(0x67C)
+#define RISAB_CID0PRIVCFGR U(0x800)
+#define RISAB_CID0RDCFGR U(0x808)
+#define RISAB_CID0WRCFGR U(0x810)
+#define RISAB_CID1PRIVCFGR U(0x820)
+#define RISAB_CID1RDCFGR U(0x828)
+#define RISAB_CID1WRCFGR U(0x830)
+#define RISAB_CID2PRIVCFGR U(0x840)
+#define RISAB_CID2RDCFGR U(0x848)
+#define RISAB_CID2WRCFGR U(0x850)
+#define RISAB_CID3PRIVCFGR U(0x860)
+#define RISAB_CID3RDCFGR U(0x868)
+#define RISAB_CID3WRCFGR U(0x870)
+#define RISAB_CID4PRIVCFGR U(0x880)
+#define RISAB_CID4RDCFGR U(0x888)
+#define RISAB_CID4WRCFGR U(0x890)
+#define RISAB_CID5PRIVCFGR U(0x8A0)
+#define RISAB_CID5RDCFGR U(0x8A8)
+#define RISAB_CID5WRCFGR U(0x8B0)
+#define RISAB_CID6PRIVCFGR U(0x8C0)
+#define RISAB_CID6RDCFGR U(0x8C8)
+#define RISAB_CID6WRCFGR U(0x8D0)
+#define RISAB_PG0_CIDCFGR U(0xA00)
+#define RISAB_PG1_CIDCFGR U(0xA04)
+#define RISAB_PG2_CIDCFGR U(0xA08)
+#define RISAB_PG3_CIDCFGR U(0xA0C)
+#define RISAB_PG4_CIDCFGR U(0xA10)
+#define RISAB_PG5_CIDCFGR U(0xA14)
+#define RISAB_PG6_CIDCFGR U(0xA18)
+#define RISAB_PG7_CIDCFGR U(0xA1C)
+#define RISAB_PG8_CIDCFGR U(0xA20)
+#define RISAB_PG9_CIDCFGR U(0xA24)
+#define RISAB_PG10_CIDCFGR U(0xA28)
+#define RISAB_PG11_CIDCFGR U(0xA2C)
+#define RISAB_PG12_CIDCFGR U(0xA30)
+#define RISAB_PG13_CIDCFGR U(0xA34)
+#define RISAB_PG14_CIDCFGR U(0xA38)
+#define RISAB_PG15_CIDCFGR U(0xA3C)
+#define RISAB_PG16_CIDCFGR U(0xA40)
+#define RISAB_PG17_CIDCFGR U(0xA44)
+#define RISAB_PG18_CIDCFGR U(0xA48)
+#define RISAB_PG19_CIDCFGR U(0xA4C)
+#define RISAB_PG20_CIDCFGR U(0xA50)
+#define RISAB_PG21_CIDCFGR U(0xA54)
+#define RISAB_PG22_CIDCFGR U(0xA58)
+#define RISAB_PG23_CIDCFGR U(0xA5C)
+#define RISAB_PG24_CIDCFGR U(0xA60)
+#define RISAB_PG25_CIDCFGR U(0xA64)
+#define RISAB_PG26_CIDCFGR U(0xA68)
+#define RISAB_PG27_CIDCFGR U(0xA6C)
+#define RISAB_PG28_CIDCFGR U(0xA70)
+#define RISAB_PG29_CIDCFGR U(0xA74)
+#define RISAB_PG30_CIDCFGR U(0xA78)
+#define RISAB_PG31_CIDCFGR U(0xA7C)
+#define RISAB_HWCFGR3 U(0xFE8)
+#define RISAB_HWCFGR2 U(0xFEC)
+#define RISAB_HWCFGR1 U(0xFF0)
+#define RISAB_VERR U(0xFF4)
+#define RISAB_IPIDR U(0xFF8)
+#define RISAB_SIDR U(0xFFC)
+
+/* RISAB_CR register fields */
+#define RISAB_CR_GLOCK BIT(0)
+#define RISAB_CR_SRWIAD BIT(31)
+
+/* RISAB_IASR register fields */
+#define RISAB_IASR_CAEF BIT(0)
+#define RISAB_IASR_IAEF BIT(1)
+
+/* RISAB_IACR register fields */
+#define RISAB_IACR_CAEF BIT(0)
+#define RISAB_IACR_IAEF BIT(1)
+
+/* RISAB_RIFLOCKR register fields */
+#define RISAB_RIFLOCKR_RLOCK0 BIT(0)
+#define RISAB_RIFLOCKR_RLOCK1 BIT(1)
+#define RISAB_RIFLOCKR_RLOCK2 BIT(2)
+#define RISAB_RIFLOCKR_RLOCK3 BIT(3)
+#define RISAB_RIFLOCKR_RLOCK4 BIT(4)
+#define RISAB_RIFLOCKR_RLOCK5 BIT(5)
+#define RISAB_RIFLOCKR_RLOCK6 BIT(6)
+#define RISAB_RIFLOCKR_RLOCK7 BIT(7)
+#define RISAB_RIFLOCKR_RLOCK8 BIT(8)
+#define RISAB_RIFLOCKR_RLOCK9 BIT(9)
+#define RISAB_RIFLOCKR_RLOCK10 BIT(10)
+#define RISAB_RIFLOCKR_RLOCK11 BIT(11)
+#define RISAB_RIFLOCKR_RLOCK12 BIT(12)
+#define RISAB_RIFLOCKR_RLOCK13 BIT(13)
+#define RISAB_RIFLOCKR_RLOCK14 BIT(14)
+#define RISAB_RIFLOCKR_RLOCK15 BIT(15)
+#define RISAB_RIFLOCKR_RLOCK16 BIT(16)
+#define RISAB_RIFLOCKR_RLOCK17 BIT(17)
+#define RISAB_RIFLOCKR_RLOCK18 BIT(18)
+#define RISAB_RIFLOCKR_RLOCK19 BIT(19)
+#define RISAB_RIFLOCKR_RLOCK20 BIT(20)
+#define RISAB_RIFLOCKR_RLOCK21 BIT(21)
+#define RISAB_RIFLOCKR_RLOCK22 BIT(22)
+#define RISAB_RIFLOCKR_RLOCK23 BIT(23)
+#define RISAB_RIFLOCKR_RLOCK24 BIT(24)
+#define RISAB_RIFLOCKR_RLOCK25 BIT(25)
+#define RISAB_RIFLOCKR_RLOCK26 BIT(26)
+#define RISAB_RIFLOCKR_RLOCK27 BIT(27)
+#define RISAB_RIFLOCKR_RLOCK28 BIT(28)
+#define RISAB_RIFLOCKR_RLOCK29 BIT(29)
+#define RISAB_RIFLOCKR_RLOCK30 BIT(30)
+#define RISAB_RIFLOCKR_RLOCK31 BIT(31)
+
+/* RISAB_IAESR register fields */
+#define RISAB_IAESR_IACID_MASK GENMASK(2, 0)
+#define RISAB_IAESR_IACID_SHIFT 0
+#define RISAB_IAESR_IAPRIV BIT(4)
+#define RISAB_IAESR_IASEC BIT(5)
+#define RISAB_IAESR_IANRW BIT(7)
+
+/* RISAB_PGx_SECCFGR register fields */
+#define RISAB_PGx_SECCFGR_SEC(_y) BIT(_y)
+
+/* RISAB_PGx_PRIVCFGR register fields */
+#define RISAB_PGx_PRIVCFGR_PRIV(_y) BIT(_y)
+
+/* RISAB_PGx_CmPRIVCFGR register fields */
+#define RISAB_PGx_CmPRIVCFGR_PRIV(_y) BIT(_y)
+
+/* RISAB_CIDxPRIVCFGR register fields */
+#define RISAB_CIDxPRIVCFGR_PPRIV(_y) BIT(_y)
+
+/* RISAB_CIDxRDCFGR register fields */
+#define RISAB_CIDxRDCFGR_PRDEN(_y) BIT(_y)
+
+/* RISAB_CIDxWRCFGR register fields */
+#define RISAB_CIDxWRCFGR_PWREN(_y) BIT(_y)
+
+/* RISAB_PGx_CIDCFGR register fields */
+#define RISAB_PGx_CIDCFGR_CFEN BIT(0)
+#define RISAB_PGx_CIDCFGR_DCEN BIT(2)
+#define RISAB_PGx_CIDCFGR_DCCID_MASK GENMASK(6, 4)
+#define RISAB_PGx_CIDCFGR_DCCID_SHIFT 4
+
+/* RISAB_HWCFGR1 register fields */
+#define RISAB_HWCFGR1_CFG1_MASK GENMASK(3, 0)
+#define RISAB_HWCFGR1_CFG1_SHIFT 0
+#define RISAB_HWCFGR1_CFG2_MASK GENMASK(7, 4)
+#define RISAB_HWCFGR1_CFG2_SHIFT 4
+#define RISAB_HWCFGR1_CFG3_MASK GENMASK(11, 8)
+#define RISAB_HWCFGR1_CFG3_SHIFT 8
+#define RISAB_HWCFGR1_CFG4_MASK GENMASK(15, 12)
+#define RISAB_HWCFGR1_CFG4_SHIFT 12
+#define RISAB_HWCFGR1_CFG5_MASK GENMASK(19, 16)
+#define RISAB_HWCFGR1_CFG5_SHIFT 16
+#define RISAB_HWCFGR1_CFG6_MASK GENMASK(23, 20)
+#define RISAB_HWCFGR1_CFG6_SHIFT 20
+#define RISAB_HWCFGR1_CFG7_MASK GENMASK(27, 24)
+#define RISAB_HWCFGR1_CFG7_SHIFT 24
+
+/* RISAB_VERR register fields */
+#define RISAB_VERR_MINREV_MASK GENMASK(3, 0)
+#define RISAB_VERR_MINREV_SHIFT 0
+#define RISAB_VERR_MAJREV_MASK GENMASK(7, 4)
+#define RISAB_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP_RISAB_REGS_H */
diff --git a/include/drivers/st/stpmic2.h b/include/drivers/st/stpmic2.h
new file mode 100644
index 0000000..58ba64a
--- /dev/null
+++ b/include/drivers/st/stpmic2.h
@@ -0,0 +1,307 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STPMIC2_H
+#define STPMIC2_H
+
+#include <drivers/st/stm32_i2c.h>
+#include <lib/utils_def.h>
+
+enum {
+ STPMIC2_BUCK1 = 0,
+ STPMIC2_BUCK2,
+ STPMIC2_BUCK3,
+ STPMIC2_BUCK4,
+ STPMIC2_BUCK5,
+ STPMIC2_BUCK6,
+ STPMIC2_BUCK7,
+ STPMIC2_REFDDR,
+ STPMIC2_LDO1,
+ STPMIC2_LDO2,
+ STPMIC2_LDO3,
+ STPMIC2_LDO4,
+ STPMIC2_LDO5,
+ STPMIC2_LDO6,
+ STPMIC2_LDO7,
+ STPMIC2_LDO8,
+ STPMIC2_NB_REG
+};
+
+/* Status Registers */
+#define PRODUCT_ID 0x00
+#define VERSION_SR 0x01
+#define TURN_ON_SR 0x02
+#define TURN_OFF_SR 0x03
+#define RESTART_SR 0x04
+#define OCP_SR1 0x05
+#define OCP_SR2 0x06
+#define EN_SR1 0x07
+#define EN_SR2 0x08
+#define FS_CNT_SR1 0x09
+#define FS_CNT_SR2 0x0A
+#define FS_CNT_SR3 0x0B
+#define MODE_SR 0x0C
+/* Control Registers */
+#define MAIN_CR 0x10
+#define VINLOW_CR 0x11
+#define PKEY_LKP_CR 0x12
+#define WDG_CR 0x13
+#define WDG_TMR_CR 0x14
+#define WDG_TMR_SR 0x15
+#define FS_OCP_CR1 0x16
+#define FS_OCP_CR2 0x17
+#define PADS_PULL_CR 0x18
+#define BUCKS_PD_CR1 0x19
+#define BUCKS_PD_CR2 0x1A
+#define LDOS_PD_CR1 0x1B
+#define LDOS_PD_CR2 0x1C
+#define BUCKS_MRST_CR 0x1D
+#define LDOS_MRST_CR 0x1E
+/* Buck CR */
+#define BUCK1_MAIN_CR1 0x20
+#define BUCK1_MAIN_CR2 0x21
+#define BUCK1_ALT_CR1 0x22
+#define BUCK1_ALT_CR2 0x23
+#define BUCK1_PWRCTRL_CR 0x24
+#define BUCK2_MAIN_CR1 0x25
+#define BUCK2_MAIN_CR2 0x26
+#define BUCK2_ALT_CR1 0x27
+#define BUCK2_ALT_CR2 0x28
+#define BUCK2_PWRCTRL_CR 0x29
+#define BUCK3_MAIN_CR1 0x2A
+#define BUCK3_MAIN_CR2 0x2B
+#define BUCK3_ALT_CR1 0x2C
+#define BUCK3_ALT_CR2 0x2D
+#define BUCK3_PWRCTRL_CR 0x2E
+#define BUCK4_MAIN_CR1 0x2F
+#define BUCK4_MAIN_CR2 0x30
+#define BUCK4_ALT_CR1 0x31
+#define BUCK4_ALT_CR2 0x32
+#define BUCK4_PWRCTRL_CR 0x33
+#define BUCK5_MAIN_CR1 0x34
+#define BUCK5_MAIN_CR2 0x35
+#define BUCK5_ALT_CR1 0x36
+#define BUCK5_ALT_CR2 0x37
+#define BUCK5_PWRCTRL_CR 0x38
+#define BUCK6_MAIN_CR1 0x39
+#define BUCK6_MAIN_CR2 0x3A
+#define BUCK6_ALT_CR1 0x3B
+#define BUCK6_ALT_CR2 0x3C
+#define BUCK6_PWRCTRL_CR 0x3D
+#define BUCK7_MAIN_CR1 0x3E
+#define BUCK7_MAIN_CR2 0x3F
+#define BUCK7_ALT_CR1 0x40
+#define BUCK7_ALT_CR2 0x41
+#define BUCK7_PWRCTRL_CR 0x42
+/* LDO CR */
+#define LDO1_MAIN_CR 0x4C
+#define LDO1_ALT_CR 0x4D
+#define LDO1_PWRCTRL_CR 0x4E
+#define LDO2_MAIN_CR 0x4F
+#define LDO2_ALT_CR 0x50
+#define LDO2_PWRCTRL_CR 0x51
+#define LDO3_MAIN_CR 0x52
+#define LDO3_ALT_CR 0x53
+#define LDO3_PWRCTRL_CR 0x54
+#define LDO4_MAIN_CR 0x55
+#define LDO4_ALT_CR 0x56
+#define LDO4_PWRCTRL_CR 0x57
+#define LDO5_MAIN_CR 0x58
+#define LDO5_ALT_CR 0x59
+#define LDO5_PWRCTRL_CR 0x5A
+#define LDO6_MAIN_CR 0x5B
+#define LDO6_ALT_CR 0x5C
+#define LDO6_PWRCTRL_CR 0x5D
+#define LDO7_MAIN_CR 0x5E
+#define LDO7_ALT_CR 0x5F
+#define LDO7_PWRCTRL_CR 0x60
+#define LDO8_MAIN_CR 0x61
+#define LDO8_ALT_CR 0x62
+#define LDO8_PWRCTRL_CR 0x63
+#define REFDDR_MAIN_CR 0x64
+#define REFDDR_ALT_CR 0x65
+#define REFDDR_PWRCTRL_CR 0x66
+/* INTERRUPT CR */
+#define INT_PENDING_R1 0x70
+#define INT_PENDING_R2 0x71
+#define INT_PENDING_R3 0x72
+#define INT_PENDING_R4 0x73
+#define INT_CLEAR_R1 0x74
+#define INT_CLEAR_R2 0x75
+#define INT_CLEAR_R3 0x76
+#define INT_CLEAR_R4 0x77
+#define INT_MASK_R1 0x78
+#define INT_MASK_R2 0x79
+#define INT_MASK_R3 0x7A
+#define INT_MASK_R4 0x7B
+#define INT_SRC_R1 0x7C
+#define INT_SRC_R2 0x7D
+#define INT_SRC_R3 0x7E
+#define INT_SRC_R4 0x7F
+#define INT_DBG_LATCH_R1 0x80
+#define INT_DBG_LATCH_R2 0x81
+#define INT_DBG_LATCH_R3 0x82
+#define INT_DBG_LATCH_R4 0x83
+
+/* BUCKS_MRST_CR bits definition */
+#define BUCK1_MRST BIT(0)
+#define BUCK2_MRST BIT(1)
+#define BUCK3_MRST BIT(2)
+#define BUCK4_MRST BIT(3)
+#define BUCK5_MRST BIT(4)
+#define BUCK6_MRST BIT(5)
+#define BUCK7_MRST BIT(6)
+#define REFDDR_MRST BIT(7)
+
+/* LDOS_MRST_CR bits definition */
+#define LDO1_MRST BIT(0)
+#define LDO2_MRST BIT(1)
+#define LDO3_MRST BIT(2)
+#define LDO4_MRST BIT(3)
+#define LDO5_MRST BIT(4)
+#define LDO6_MRST BIT(5)
+#define LDO7_MRST BIT(6)
+#define LDO8_MRST BIT(7)
+
+/* LDOx_MAIN_CR */
+#define LDO_VOLT_SHIFT 1
+#define LDO_BYPASS BIT(6)
+#define LDO1_INPUT_SRC BIT(7)
+#define LDO3_SNK_SRC BIT(7)
+#define LDO4_INPUT_SRC_SHIFT 6
+#define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6)
+
+/* PWRCTRL register bit definition */
+#define PWRCTRL_EN BIT(0)
+#define PWRCTRL_RS BIT(1)
+#define PWRCTRL_SEL_SHIFT 2
+#define PWRCTRL_SEL_MASK GENMASK_32(3, 2)
+
+/* BUCKx_MAIN_CR2 */
+#define PREG_MODE_SHIFT 1
+#define PREG_MODE_MASK GENMASK_32(2, 1)
+
+/* BUCKS_PD_CR1 */
+#define BUCK1_PD_MASK GENMASK_32(1, 0)
+#define BUCK2_PD_MASK GENMASK_32(3, 2)
+#define BUCK3_PD_MASK GENMASK_32(5, 4)
+#define BUCK4_PD_MASK GENMASK_32(7, 6)
+
+#define BUCK1_PD_FAST BIT(1)
+#define BUCK2_PD_FAST BIT(3)
+#define BUCK3_PD_FAST BIT(5)
+#define BUCK4_PD_FAST BIT(7)
+
+/* BUCKS_PD_CR2 */
+#define BUCK5_PD_MASK GENMASK_32(1, 0)
+#define BUCK6_PD_MASK GENMASK_32(3, 2)
+#define BUCK7_PD_MASK GENMASK_32(5, 4)
+
+#define BUCK5_PD_FAST BIT(1)
+#define BUCK6_PD_FAST BIT(3)
+#define BUCK7_PD_FAST BIT(5)
+
+/* LDOS_PD_CR1 */
+#define LDO1_PD BIT(0)
+#define LDO2_PD BIT(1)
+#define LDO3_PD BIT(2)
+#define LDO4_PD BIT(3)
+#define LDO5_PD BIT(4)
+#define LDO6_PD BIT(5)
+#define LDO7_PD BIT(6)
+#define LDO8_PD BIT(7)
+
+/* LDOS_PD_CR2 */
+#define REFDDR_PD BIT(0)
+
+/* FS_OCP_CR1 */
+#define FS_OCP_BUCK1 BIT(0)
+#define FS_OCP_BUCK2 BIT(1)
+#define FS_OCP_BUCK3 BIT(2)
+#define FS_OCP_BUCK4 BIT(3)
+#define FS_OCP_BUCK5 BIT(4)
+#define FS_OCP_BUCK6 BIT(5)
+#define FS_OCP_BUCK7 BIT(6)
+#define FS_OCP_REFDDR BIT(7)
+
+/* FS_OCP_CR2 */
+#define FS_OCP_LDO1 BIT(0)
+#define FS_OCP_LDO2 BIT(1)
+#define FS_OCP_LDO3 BIT(2)
+#define FS_OCP_LDO4 BIT(3)
+#define FS_OCP_LDO5 BIT(4)
+#define FS_OCP_LDO6 BIT(5)
+#define FS_OCP_LDO7 BIT(6)
+#define FS_OCP_LDO8 BIT(7)
+
+/* IRQ definitions */
+#define IT_PONKEY_F 0
+#define IT_PONKEY_R 1
+#define IT_BUCK1_OCP 16
+#define IT_BUCK2_OCP 17
+#define IT_BUCK3_OCP 18
+#define IT_BUCK4_OCP 19
+#define IT_BUCK5_OCP 20
+#define IT_BUCK6_OCP 21
+#define IT_BUCK7_OCP 22
+#define IT_REFDDR_OCP 23
+#define IT_LDO1_OCP 24
+#define IT_LDO2_OCP 25
+#define IT_LDO3_OCP 26
+#define IT_LDO4_OCP 27
+#define IT_LDO5_OCP 28
+#define IT_LDO6_OCP 29
+#define IT_LDO7_OCP 30
+#define IT_LDO8_OCP 31
+
+enum stpmic2_prop_id {
+ STPMIC2_MASK_RESET = 0,
+ STPMIC2_PULL_DOWN,
+ STPMIC2_BYPASS, /* arg: 1=set 0=reset */
+ STPMIC2_SINK_SOURCE,
+ STPMIC2_OCP,
+};
+
+struct pmic_handle_s {
+ struct i2c_handle_s *i2c_handle;
+ uint32_t i2c_addr;
+ unsigned int pmic_status;
+};
+
+int stpmic2_register_read(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t *value);
+int stpmic2_register_write(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value);
+int stpmic2_register_update(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value, uint8_t mask);
+
+int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool enable);
+int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool *enabled);
+
+int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
+ uint8_t id, const uint16_t **levels,
+ size_t *levels_count);
+int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t *val);
+int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t millivolts);
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+void stpmic2_dump_regulators(struct pmic_handle_s *pmic);
+#endif
+
+int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val);
+int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val);
+
+int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop);
+
+int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop, uint32_t arg);
+
+#endif /*STPMIC2_H*/
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 1015fca..ae5aa23 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -370,8 +370,10 @@
* Mandatory BL31 functions when ENABLE_RME=1
******************************************************************************/
#if ENABLE_RME
+
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size);
+ uintptr_t hash, size_t hash_size,
+ uint64_t *remaining_len);
int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
unsigned int type);
size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared);
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index a567d28..4615ffb 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -90,6 +90,7 @@
#define E_RMM_BAD_PAS -3
#define E_RMM_NOMEM -4
#define E_RMM_INVAL -5
+#define E_RMM_AGAIN -6
/* Return error codes from RMI SMCs */
#define RMI_SUCCESS 0
@@ -156,7 +157,7 @@
* Increase this when a bug is fixed, or a feature is added without
* breaking compatibility.
*/
-#define RMM_EL3_IFC_VERSION_MINOR (U(2))
+#define RMM_EL3_IFC_VERSION_MINOR (U(3))
#define RMM_EL3_INTERFACE_VERSION \
(((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index d028fce..79c4ea5 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -495,7 +495,7 @@
*
* Parameters
* l0_mem_base Base address of memory used for L0 tables.
- * l1_mem_size Size of memory available for L0 tables.
+ * l0_mem_size Size of memory available for L0 tables.
*
* Return
* Negative Linux error code in the event of a failure, 0 for success.
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index ceff4ba..675779f 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -310,7 +310,7 @@
ifeq ($(CTX_INCLUDE_MTE_REGS),1)
$(warning CTX_INCLUDE_MTE_REGS option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
-ifeq ($(ENABLE_FEAT_MTE),1)
+ifneq ($(ENABLE_FEAT_MTE),)
$(warning ENABLE_FEAT_MTE option is deprecated, Check ENABLE_FEAT_MTE2 usage)
endif
diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
index 6f0cbcb..a55042d 100644
--- a/plat/amd/versal2/plat_psci.c
+++ b/plat/amd/versal2/plat_psci.c
@@ -178,6 +178,8 @@
mmio_write_32(PMXC_IOU_SLCR_SRAM_CSR, arg2);
}
break;
+ case IOCTL_USB_SET_STATE:
+ break;
default:
ret = PM_RET_ERROR_NOFEATURE;
break;
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index 83b52fc..0894bf7 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2024, Linaro Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -16,213 +16,244 @@
*/
static const uint8_t sample_platform_token[] = {
0xd2, 0x84, 0x44, 0xa1, 0x01, 0x38, 0x22, 0xa0,
- 0x59, 0x05, 0x7a, 0xa9, 0x19, 0x01, 0x09, 0x78,
- 0x1c, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
- 0x61, 0x72, 0x6d, 0x2e, 0x63, 0x6f, 0x6d, 0x2f,
- 0x43, 0x43, 0x41, 0x2d, 0x53, 0x53, 0x44, 0x2f,
- 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20,
- 0xb5, 0x97, 0x3c, 0xb6, 0x8b, 0xaa, 0x9f, 0xc5,
- 0x55, 0x58, 0x78, 0x6b, 0x7e, 0xc6, 0x7f, 0x69,
- 0xe4, 0x0d, 0xf5, 0xba, 0x5a, 0xa9, 0x21, 0xcd,
- 0x0c, 0x27, 0xf4, 0x05, 0x87, 0xa0, 0x11, 0xea,
- 0x19, 0x09, 0x5c, 0x58, 0x20, 0x7f, 0x45, 0x4c,
- 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3e,
- 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
- 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
- 0x02, 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
- 0x0a, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
- 0x12, 0x11, 0x10, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b,
- 0x1a, 0x19, 0x18, 0x19, 0x09, 0x61, 0x44, 0xcf,
- 0xcf, 0xcf, 0xcf, 0x19, 0x09, 0x5b, 0x19, 0x30,
- 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, 0x68, 0x61,
- 0x2d, 0x32, 0x35, 0x36, 0x19, 0x09, 0x60, 0x78,
- 0x3a, 0x68, 0x74, 0x74, 0x70, 0x73, 0x3a, 0x2f,
- 0x2f, 0x76, 0x65, 0x72, 0x61, 0x69, 0x73, 0x6f,
- 0x6e, 0x2e, 0x65, 0x78, 0x61, 0x6d, 0x70, 0x6c,
- 0x65, 0x2f, 0x2e, 0x77, 0x65, 0x6c, 0x6c, 0x2d,
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+ 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20,
+ 0xa1, 0xfb, 0x50, 0xe6, 0xc8, 0x6f, 0xae, 0x16,
+ 0x79, 0xef, 0x33, 0x51, 0x29, 0x6f, 0xd6, 0x71,
+ 0x34, 0x11, 0xa0, 0x8c, 0xf8, 0xdd, 0x17, 0x90,
+ 0xa4, 0xfd, 0x05, 0xfa, 0xe8, 0x68, 0x81, 0x64,
+ 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35,
+ 0x36, 0xa4, 0x01, 0x69, 0x48, 0x57, 0x5f, 0x43,
+ 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0x1a, 0x25, 0x24, 0x02, 0x97,
+ 0x2f, 0x60, 0x57, 0xfa, 0x53, 0xcc, 0x17, 0x2b,
+ 0x52, 0xb9, 0xff, 0xca, 0x69, 0x8e, 0x18, 0x31,
+ 0x1f, 0xac, 0xd0, 0xf3, 0xb0, 0x6e, 0xca, 0xae,
+ 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69, 0x46,
+ 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47,
+ 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07,
+ 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2,
+ 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30,
+ 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97,
+ 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a, 0x92,
+ 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65, 0x8c,
+ 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56, 0x68,
+ 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c, 0x89,
+ 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06, 0x67,
+ 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4,
+ 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57, 0x5f,
0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
- 0xa3, 0x02, 0x58, 0x20, 0x1a, 0x25, 0x24, 0x02,
- 0x97, 0x2f, 0x60, 0x57, 0xfa, 0x53, 0xcc, 0x17,
- 0x2b, 0x52, 0xb9, 0xff, 0xca, 0x69, 0x8e, 0x18,
- 0x31, 0x1f, 0xac, 0xd0, 0xf3, 0xb0, 0x6e, 0xca,
- 0xae, 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68,
- 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69,
- 0x46, 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49,
- 0x47, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63,
- 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15,
- 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d,
- 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa,
- 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a,
- 0x92, 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65,
- 0x8c, 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56,
- 0x68, 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c,
- 0x89, 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06,
- 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36,
- 0xa4, 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57,
- 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05,
- 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53,
- 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2,
- 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60,
- 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f,
- 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03,
- 0x18, 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b,
- 0x3f, 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec,
- 0x0a, 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc,
- 0x7c, 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73,
- 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01,
- 0x6d, 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f,
- 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
- 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
- 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
- 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
- 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
- 0xa3, 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d,
- 0x26, 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3,
- 0x39, 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85,
- 0x29, 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc,
- 0xe0, 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68,
- 0x61, 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x21,
- 0x51, 0x20, 0x92, 0xd6, 0xd0, 0x2a, 0xe6, 0xbe,
- 0x2f, 0xe3, 0x93, 0x0e, 0xa5, 0x1f, 0xd6, 0x98,
- 0x96, 0x32, 0x24, 0x56, 0xe9, 0xdf, 0xc7, 0x32,
- 0x5e, 0x0b, 0x78, 0x68, 0xb6, 0x90, 0x73, 0x2a,
- 0x0c, 0x0f, 0x07, 0x77, 0xc1, 0x15, 0x40, 0x4b,
- 0xe1, 0xfc, 0x83, 0x9b, 0x7d, 0x30, 0x4f, 0x4f,
- 0xe6, 0xfa, 0x46, 0xae, 0x12, 0xa3, 0x08, 0x3a,
- 0xcf, 0x24, 0x06, 0x67, 0x91, 0x06, 0xbf, 0xae,
- 0x50, 0x31, 0x79, 0xdd, 0x50, 0x33, 0x49, 0x12,
- 0xbf, 0xc6, 0xda, 0x33, 0x6d, 0xd6, 0x18, 0x25,
- 0x43, 0x54, 0x4d, 0xb5, 0x88, 0xd6, 0xae, 0x67,
- 0x35, 0x7a, 0xfd, 0xb0, 0x5f, 0x95, 0xb7
+ 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03, 0x18,
+ 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b, 0x3f,
+ 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec, 0x0a,
+ 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc, 0x7c,
+ 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x6d,
+ 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f, 0x43,
+ 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58, 0x20,
+ 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3,
+ 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56,
+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d, 0x26,
+ 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3, 0x39,
+ 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85, 0x29,
+ 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc, 0xe0,
+ 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x31, 0xd0,
+ 0x4d, 0x52, 0xcc, 0xde, 0x95, 0x2c, 0x1e, 0x32,
+ 0xcb, 0xa1, 0x81, 0x88, 0x5a, 0x40, 0xb8, 0xcc,
+ 0x38, 0xe0, 0x52, 0x8c, 0x1e, 0x89, 0x58, 0x98,
+ 0x07, 0x64, 0x2a, 0xa5, 0xe3, 0xf2, 0xbc, 0x37,
+ 0xf9, 0x53, 0x74, 0x50, 0x6b, 0xff, 0x4d, 0x2e,
+ 0x4b, 0xe7, 0x06, 0x3c, 0x4d, 0x72, 0x41, 0x92,
+ 0x70, 0xc7, 0x22, 0xe8, 0xd4, 0xd9, 0x3e, 0xe8,
+ 0xb6, 0xc9, 0xfa, 0xce, 0x3b, 0x43, 0xc9, 0x76,
+ 0x1a, 0x49, 0x94, 0x1a, 0xb6, 0xf3, 0x8f, 0xfd,
+ 0xff, 0x49, 0x6a, 0xd4, 0x63, 0xb4, 0xcb, 0xfa,
+ 0x11, 0xd8, 0x3e, 0x23, 0xe3, 0x1f, 0x7f, 0x62,
+ 0x32, 0x9d, 0xe3, 0x0c, 0x1c, 0xc8
};
+static uint64_t platform_token_offset;
/*
* Get the hardcoded platform attestation token as FVP does not support
* RSE.
+ *
+ * Note: This implementation caters for retrieval of the platform token
+ * in hunks to facilitate EL3-RMM interface testing. For most platforms,
+ * since the shared buffer size is known, the implementation can be more
+ * optimized.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size)
+ uintptr_t hash, size_t hash_size,
+ size_t *remaining_len)
{
(void)hash;
(void)hash_size;
+ size_t platform_token_size = sizeof(sample_platform_token);
+ size_t local_hunk_len;
+ size_t local_remaining_len;
- if (*len < sizeof(sample_platform_token)) {
+ if (hash_size != 0) {
+ platform_token_offset = 0;
+ } else if (platform_token_offset == 0) {
return -EINVAL;
}
- (void)memcpy((void *)buf, (const void *)sample_platform_token,
- sizeof(sample_platform_token));
- *len = sizeof(sample_platform_token);
+ local_hunk_len = *len;
+ local_remaining_len = platform_token_size - platform_token_offset;
+
+ /*
+ * If the buffer is enough to fit the remaining bytes of the token,
+ * return only the remaining bytes of the token.
+ */
+ if (local_hunk_len >= local_remaining_len) {
+ local_hunk_len = local_remaining_len;
+ }
+ /* Update remaining bytes according to hunk size */
+ local_remaining_len -= local_hunk_len;
+
+ (void)memcpy((void *)buf,
+ (const void *)sample_platform_token
+ + platform_token_offset,
+ local_hunk_len);
+
+ platform_token_offset += local_hunk_len;
+ *len = local_hunk_len;
+ *remaining_len = local_remaining_len;
return 0;
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 56de8b8..e0c9725 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -149,6 +149,10 @@
#define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE
#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+#if RESET_TO_BL31
+#define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET
+#endif
+
#else
#define PLAT_ARM_FW_HANDOFF_SIZE U(0)
#endif
@@ -297,7 +301,9 @@
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
-# define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000)
+# define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
+ ARM_SHARED_RAM_SIZE - \
+ ARM_FW_CONFIGS_SIZE)
#endif /* RESET_TO_SP_MIN */
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 340eb38..feae802 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -76,6 +76,7 @@
ENABLE_FEAT_S1PIE := 2
ENABLE_FEAT_S2POE := 2
ENABLE_FEAT_S1POE := 2
+ENABLE_FEAT_MTE2 := 2
# The FVP platform depends on this macro to build with correct GIC driver.
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
@@ -391,9 +392,10 @@
ifeq ($(RESET_TO_BL31), 1)
HW_CONFIG := ${FVP_HW_CONFIG}
-FW_HANDOFF_SIZE := 20000
+FW_HANDOFF_SIZE := 20000
-$(eval $(call add_define,ARM_PRELOADED_DTB_OFFSET))
+TRANSFER_LIST_DTB_OFFSET := 0x20
+$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET))
endif
endif
diff --git a/plat/arm/board/fvp_r/platform.mk b/plat/arm/board/fvp_r/platform.mk
index f14ea54..71cb9e2 100644
--- a/plat/arm/board/fvp_r/platform.mk
+++ b/plat/arm/board/fvp_r/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,7 +25,7 @@
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
-PLAT_INCLUDES := -Iplat/arm/board/fvp_r/include
+PLAT_INCLUDES += -Iplat/arm/board/fvp_r/include
FVP_R_BL_COMMON_SOURCES := plat/arm/board/fvp_r/fvp_r_common.c \
plat/arm/board/fvp_r/fvp_r_context_mgmt.c \
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
index 188a09f..5584662 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
@@ -4,23 +4,32 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <cca_attestation.h>
#include <common/debug.h>
+#include <plat/common/common_def.h>
#include <psa/error.h>
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size)
+ uintptr_t hash, size_t hash_size,
+ size_t *remaining_len)
{
psa_status_t ret;
+ assert(*len == SZ_4K);
+
ret = cca_attestation_get_plat_token(buf, len, hash, hash_size);
if (ret != PSA_SUCCESS) {
ERROR("Unable to fetch CCA attestation token\n");
return -1;
}
+ assert(*len <= SZ_4K);
+
+ *remaining_len = 0;
+
return 0;
}
diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h
index de7b1aa..4fd8b6b 100644
--- a/plat/arm/board/tc/plat_tc_mbedtls_config.h
+++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h
@@ -21,6 +21,20 @@
#endif
#endif /* TF_MBEDTLS_HEAP_SIZE */
+/**
+ * On Arm TC platforms, the ROTPK is always hashed using the SHA-256
+ * algorithm.
+ * TODO: Update to hash the ROTPK with the selected HASH_ALG to avoid
+ * the need for explicitly enabling the SHA-256 configuration in mbedTLS.
+ */
+#define MBEDTLS_SHA256_C
+
+/*
+ * Use an implementation of SHA-256 with a smaller memory footprint
+ * but reduced speed.
+ */
+#define MBEDTLS_SHA256_SMALLER
+
#define MBEDTLS_PSA_CRYPTO_C
#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
#define MBEDTLS_ECP_C
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index e91746b..65023bf 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -147,8 +147,7 @@
bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
- bl33_image_ep_info.args.arg0 =
- FW_NS_HANDOFF_BASE + ARM_PRELOADED_DTB_OFFSET;
+ bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET;
bl33_image_ep_info.args.arg1 =
TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE;
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 660a3a5..0c9b943 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -119,10 +119,6 @@
endif
endif
-# Use an implementation of SHA-256 with a smaller memory footprint but reduced
-# speed.
-$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
-
# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
# in the FIP if the platform requires.
ifneq ($(BL32_EXTRA1),)
@@ -364,6 +360,17 @@
BL31_SOURCES += plat/arm/common/arm_err.c
endif
+ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),)
+ PLAT_INCLUDES += -Iplat/arm/common \
+ -Iinclude/drivers/auth/mbedtls
+ # Specify mbed TLS configuration file
+ ifeq (${PSA_CRYPTO},1)
+ MBEDTLS_CONFIG_FILE ?= "<plat_arm_psa_mbedtls_config.h>"
+ else
+ MBEDTLS_CONFIG_FILE ?= "<plat_arm_mbedtls_config.h>"
+ endif
+endif
+
ifneq (${TRUSTED_BOARD_BOOT},0)
# Include common TBB sources
@@ -462,20 +469,6 @@
endif
endif
-TRANSFER_LIST_BIN := ${BUILD_PLAT}/tl.bin
-
-.PHONY: tl
-tl: ${HW_CONFIG}
- @echo " TLC ${TRANSFER_LIST_BIN}"
- $(Q)${PYTHON} -m tools.tlc.tlc create --fdt ${HW_CONFIG} -s ${FW_HANDOFF_SIZE} ${TRANSFER_LIST_BIN}
- $(Q)$(eval ARM_PRELOADED_DTB_OFFSET := `tlc info --fdt-offset ${TRANSFER_LIST_BIN}`)
-
-ifeq (${TRANSFER_LIST}, 1)
- ifeq (${RESET_TO_BL31}, 1)
- bl31: tl
- endif
-endif
-
ifneq ($(COTDTPATH),)
cot-dt-defines = IMAGE_BL2 $(BL2_DEFINES) $(PLAT_BL_COMMON_DEFINES)
cot-dt-include-dirs = $(BL2_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)
diff --git a/plat/arm/common/plat_arm_mbedtls_config.h b/plat/arm/common/plat_arm_mbedtls_config.h
new file mode 100644
index 0000000..a5d0ec4
--- /dev/null
+++ b/plat/arm/common/plat_arm_mbedtls_config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_ARM_MBEDTLS_CONFIG_H
+#define PLAT_ARM_MBEDTLS_CONFIG_H
+
+#include <mbedtls_config-3.h>
+
+/**
+ * On Arm platforms, the ROTPK is always hashed using the SHA-256
+ * algorithm.
+ * TODO: Update to hash the ROTPK with the selected HASH_ALG to avoid
+ * the need for explicitly enabling the SHA-256 configuration in mbedTLS.
+ */
+#define MBEDTLS_SHA256_C
+
+/*
+ * Use an implementation of SHA-256 with a smaller memory footprint
+ * but reduced speed.
+ */
+#define MBEDTLS_SHA256_SMALLER
+
+#endif /* PLAT_ARM_MBEDTLS_CONFIG_H */
diff --git a/plat/arm/common/plat_arm_psa_mbedtls_config.h b/plat/arm/common/plat_arm_psa_mbedtls_config.h
new file mode 100644
index 0000000..fd434c9
--- /dev/null
+++ b/plat/arm/common/plat_arm_psa_mbedtls_config.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_ARM_PSA_MBEDTLS_CONFIG_H
+#define PLAT_ARM_PSA_MBEDTLS_CONFIG_H
+
+#include "plat_arm_mbedtls_config.h"
+
+#define MBEDTLS_PSA_CRYPTO_C
+#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS
+
+/*
+ * Using PSA crypto API requires an RNG right now. If we don't define the macro
+ * below then we get build errors.
+ *
+ * This is a functionality gap in mbedTLS. The technical limitation is that
+ * psa_crypto_init() is all-or-nothing, and fixing that would require separate
+ * initialization of the keystore, the RNG, etc.
+ *
+ * By defining MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG, we pretend using an external
+ * RNG. As a result, the PSA crypto init code does nothing when it comes to
+ * initializing the RNG, as we are supposed to take care of that ourselves.
+ */
+#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
+
+#endif /* PLAT_ARM_PSA_MBEDTLS_CONFIG_H */
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 8d3928f..96c4161 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +18,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
+#include "agilex5_cache.h"
#include "agilex5_power_manager.h"
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
@@ -193,7 +195,8 @@
boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
NOTICE("BL31: Boot Core = %x\n", boot_core);
NOTICE("BL31: CPU ID = %x\n", cpuid);
-
+ INFO("BL31: Invalidate Data cache\n");
+ invalidate_dcache_all();
}
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
diff --git a/plat/intel/soc/agilex5/include/agilex5_cache.h b/plat/intel/soc/agilex5/include/agilex5_cache.h
new file mode 100644
index 0000000..095d99e
--- /dev/null
+++ b/plat/intel/soc/agilex5/include/agilex5_cache.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX5_CACHE_H
+#define AGX5_CACHE_H
+
+void invalidate_dcache_all(void);
+
+#endif /* AGX5_CACHE_H */
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 409c7b1..90678e1 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -87,6 +87,7 @@
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_psci_common.c \
plat/intel/soc/agilex5/bl31_plat_setup.c \
+ plat/intel/soc/agilex5/soc/agilex5_cache.S \
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
plat/intel/soc/common/socfpga_psci.c \
diff --git a/plat/intel/soc/agilex5/soc/agilex5_cache.S b/plat/intel/soc/agilex5/soc/agilex5_cache.S
new file mode 100644
index 0000000..a174386
--- /dev/null
+++ b/plat/intel/soc/agilex5/soc/agilex5_cache.S
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+ .globl invalidate_dcache_all
+
+.pushsection .text.asm_dcache_level, "ax"
+func asm_dcache_level
+ lsl x12, x0, #1
+ msr csselr_el1, x12 /* select cache level */
+ isb /* sync change of cssidr_el1 */
+ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
+ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
+ ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
+ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
+ add x2, x2, #4 /* x2 <- log2(cache line size) */
+ clz w5, w3 /* bit position of #ways */
+ /* x12 <- cache level << 1 */
+ /* x2 <- line length offset */
+ /* x3 <- number of cache ways - 1 */
+ /* x4 <- number of cache sets - 1 */
+ /* x5 <- bit position of #ways */
+
+loop_set:
+ mov x6, x3 /* x6 <- working copy of #ways */
+loop_way:
+ lsl x7, x6, x5
+ orr x9, x12, x7 /* map way and level to cisw value */
+ lsl x7, x4, x2
+ orr x9, x9, x7 /* map set number to cisw value */
+ tbz w1, #0, 1f
+ dc isw, x9
+ b 2f
+1: dc cisw, x9 /* clean & invalidate by set/way */
+2: subs x6, x6, #1 /* decrement the way */
+ b.ge loop_way
+ subs x4, x4, #1 /* decrement the set */
+ b.ge loop_set
+
+ ret
+endfunc asm_dcache_level
+.popsection
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.pushsection .text.asm_dcache_all, "ax"
+func asm_dcache_all
+ mov x1, x0
+ dsb sy
+ mrs x10, clidr_el1 /* read clidr_el1 */
+ ubfx x11, x10, #24, #3 /* x11 <- loc */
+ cbz x11, finished /* if loc is 0, exit */
+ mov x15, x30
+ mov x0, #0 /* start flush at cache level 0 */
+ /* x0 <- cache level */
+ /* x10 <- clidr_el1 */
+ /* x11 <- loc */
+ /* x15 <- return address */
+
+loop_level:
+ add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
+ lsr x12, x10, x12
+ and x12, x12, #7 /* x12 <- cache type */
+ cmp x12, #2
+ b.lt skip /* skip if no cache or icache */
+ bl asm_dcache_level /* x1 = 0 flush, 1 invalidate */
+skip:
+ add x0, x0, #1 /* increment cache level */
+ cmp x11, x0
+ b.gt loop_level
+
+ mov x0, #0
+ msr csselr_el1, x0 /* restore csselr_el1 */
+ dsb sy
+ isb
+ mov x30, x15
+
+finished:
+ ret
+endfunc asm_dcache_all
+.popsection
+
+.pushsection .text.invalidate_dcache_all, "ax"
+func invalidate_dcache_all
+ mov x0, #0x1
+ b asm_dcache_all
+endfunc invalidate_dcache_all
+.popsection
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 535e68f..cb4a210 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -579,7 +579,7 @@
/* Wait until idle ack becomes 0 */
ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
- noc_mask, 0, 300);
+ noc_mask, 0, 1000);
if (ret_hps < 0) {
ERROR("S2F bridge enable: Timeout idle ack\n");
}
diff --git a/plat/mediatek/common/mtk_smc_handlers.c b/plat/mediatek/common/mtk_smc_handlers.c
index 5a3ad1f..beb06da 100644
--- a/plat/mediatek/common/mtk_smc_handlers.c
+++ b/plat/mediatek/common/mtk_smc_handlers.c
@@ -99,13 +99,13 @@
{
const struct smc_descriptor *p_smc_desc;
- INFO("print smc descriptor pool\n");
+ VERBOSE("print smc descriptor pool\n");
for (p_smc_desc = &pool[0];
(char *)p_smc_desc < (char *)MTK_SMC_POOL_END_UNALIGNED;
p_smc_desc++) {
- INFO("descriptor name:%s\n", p_smc_desc->smc_name);
- INFO("descriptor index:%d\n", *p_smc_desc->smc_descriptor_index);
- INFO("smc id 32:0x%x, smc id 64:0x%x\n",
+ VERBOSE("descriptor name:%s\n", p_smc_desc->smc_name);
+ VERBOSE("descriptor index:%d\n", *p_smc_desc->smc_descriptor_index);
+ VERBOSE("smc id 32:0x%x, smc id 64:0x%x\n",
p_smc_desc->smc_id_aarch32, p_smc_desc->smc_id_aarch64);
}
}
diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
index 141ff57..7b54271 100644
--- a/plat/qemu/common/qemu_plat_attest_token.c
+++ b/plat/qemu/common/qemu_plat_attest_token.c
@@ -16,194 +16,195 @@
*/
static const uint8_t sample_platform_token[] = {
0xd2, 0x84, 0x44, 0xa1, 0x01, 0x38, 0x22, 0xa0,
- 0x59, 0x05, 0x7a, 0xa9, 0x19, 0x01, 0x09, 0x78,
- 0x1c, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
- 0x61, 0x72, 0x6d, 0x2e, 0x63, 0x6f, 0x6d, 0x2f,
- 0x43, 0x43, 0x41, 0x2d, 0x53, 0x53, 0x44, 0x2f,
- 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20,
- 0xb5, 0x97, 0x3c, 0xb6, 0x8b, 0xaa, 0x9f, 0xc5,
- 0x55, 0x58, 0x78, 0x6b, 0x7e, 0xc6, 0x7f, 0x69,
- 0xe4, 0x0d, 0xf5, 0xba, 0x5a, 0xa9, 0x21, 0xcd,
- 0x0c, 0x27, 0xf4, 0x05, 0x87, 0xa0, 0x11, 0xea,
- 0x19, 0x09, 0x5c, 0x58, 0x20, 0x7f, 0x45, 0x4c,
- 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3e,
- 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
- 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
- 0x02, 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
- 0x0a, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
- 0x12, 0x11, 0x10, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b,
- 0x1a, 0x19, 0x18, 0x19, 0x09, 0x61, 0x44, 0xcf,
- 0xcf, 0xcf, 0xcf, 0x19, 0x09, 0x5b, 0x19, 0x30,
- 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, 0x68, 0x61,
- 0x2d, 0x32, 0x35, 0x36, 0x19, 0x09, 0x60, 0x78,
- 0x3a, 0x68, 0x74, 0x74, 0x70, 0x73, 0x3a, 0x2f,
- 0x2f, 0x76, 0x65, 0x72, 0x61, 0x69, 0x73, 0x6f,
- 0x6e, 0x2e, 0x65, 0x78, 0x61, 0x6d, 0x70, 0x6c,
- 0x65, 0x2f, 0x2e, 0x77, 0x65, 0x6c, 0x6c, 0x2d,
- 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x2f, 0x76, 0x65,
- 0x72, 0x61, 0x69, 0x73, 0x6f, 0x6e, 0x2f, 0x76,
- 0x65, 0x72, 0x69, 0x66, 0x69, 0x63, 0x61, 0x74,
- 0x69, 0x6f, 0x6e, 0x19, 0x09, 0x5f, 0x8d, 0xa4,
- 0x01, 0x69, 0x52, 0x53, 0x45, 0x5f, 0x42, 0x4c,
- 0x31, 0x5f, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78,
- 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
- 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
- 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
- 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
- 0x20, 0x9a, 0x27, 0x1f, 0x2a, 0x91, 0x6b, 0x0b,
- 0x6e, 0xe6, 0xce, 0xcb, 0x24, 0x26, 0xf0, 0xb3,
- 0x20, 0x6e, 0xf0, 0x74, 0x57, 0x8b, 0xe5, 0x5d,
- 0x9b, 0xc9, 0x4f, 0x6f, 0x3f, 0xe3, 0xab, 0x86,
- 0xaa, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
- 0x35, 0x36, 0xa4, 0x01, 0x67, 0x52, 0x53, 0x45,
- 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0x53,
- 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec,
- 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41,
- 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22,
- 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02,
- 0x58, 0x20, 0x53, 0xc2, 0x34, 0xe5, 0xe8, 0x47,
- 0x2b, 0x6a, 0xc5, 0x1c, 0x1a, 0xe1, 0xca, 0xb3,
- 0xfe, 0x06, 0xfa, 0xd0, 0x53, 0xbe, 0xb8, 0xeb,
- 0xfd, 0x89, 0x77, 0xb0, 0x10, 0x65, 0x5b, 0xfd,
- 0xd3, 0xc3, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
- 0x32, 0x35, 0x36, 0xa4, 0x01, 0x65, 0x52, 0x53,
- 0x45, 0x5f, 0x53, 0x05, 0x58, 0x20, 0x53, 0x78,
- 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
- 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
- 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
- 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
- 0x20, 0x11, 0x21, 0xcf, 0xcc, 0xd5, 0x91, 0x3f,
- 0x0a, 0x63, 0xfe, 0xc4, 0x0a, 0x6f, 0xfd, 0x44,
- 0xea, 0x64, 0xf9, 0xdc, 0x13, 0x5c, 0x66, 0x63,
- 0x4b, 0xa0, 0x01, 0xd1, 0x0b, 0xcf, 0x43, 0x02,
- 0xa2, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
- 0x35, 0x36, 0xa4, 0x01, 0x66, 0x41, 0x50, 0x5f,
- 0x42, 0x4c, 0x31, 0x05, 0x58, 0x20, 0x53, 0x78,
- 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
- 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
- 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
- 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
- 0x20, 0x15, 0x71, 0xb5, 0xec, 0x78, 0xbd, 0x68,
- 0x51, 0x2b, 0xf7, 0x83, 0x0b, 0xb6, 0xa2, 0xa4,
- 0x4b, 0x20, 0x47, 0xc7, 0xdf, 0x57, 0xbc, 0xe7,
- 0x9e, 0xb8, 0xa1, 0xc0, 0xe5, 0xbe, 0xa0, 0xa5,
- 0x01, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
- 0x35, 0x36, 0xa4, 0x01, 0x66, 0x41, 0x50, 0x5f,
+ 0x59, 0x05, 0x81, 0xa9, 0x19, 0x01, 0x09, 0x78,
+ 0x23, 0x74, 0x61, 0x67, 0x3a, 0x61, 0x72, 0x6d,
+ 0x2e, 0x63, 0x6f, 0x6d, 0x2c, 0x32, 0x30, 0x32,
+ 0x33, 0x3a, 0x63, 0x63, 0x61, 0x5f, 0x70, 0x6c,
+ 0x61, 0x74, 0x66, 0x6f, 0x72, 0x6d, 0x23, 0x31,
+ 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20, 0x0d,
+ 0x22, 0xe0, 0x8a, 0x98, 0x46, 0x90, 0x58, 0x48,
+ 0x63, 0x18, 0x28, 0x34, 0x89, 0xbd, 0xb3, 0x6f,
+ 0x09, 0xdb, 0xef, 0xeb, 0x18, 0x64, 0xdf, 0x43,
+ 0x3f, 0xa6, 0xe5, 0x4e, 0xa2, 0xd7, 0x11, 0x19,
+ 0x09, 0x5c, 0x58, 0x20, 0x7f, 0x45, 0x4c, 0x46,
+ 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3e, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00, 0x58,
+ 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
+ 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a,
+ 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12,
+ 0x11, 0x10, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a,
+ 0x19, 0x18, 0x19, 0x09, 0x61, 0x44, 0xcf, 0xcf,
+ 0xcf, 0xcf, 0x19, 0x09, 0x5b, 0x19, 0x30, 0x03,
+ 0x19, 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0x19, 0x09, 0x60, 0x78, 0x3a,
+ 0x68, 0x74, 0x74, 0x70, 0x73, 0x3a, 0x2f, 0x2f,
+ 0x76, 0x65, 0x72, 0x61, 0x69, 0x73, 0x6f, 0x6e,
+ 0x2e, 0x65, 0x78, 0x61, 0x6d, 0x70, 0x6c, 0x65,
+ 0x2f, 0x2e, 0x77, 0x65, 0x6c, 0x6c, 0x2d, 0x6b,
+ 0x6e, 0x6f, 0x77, 0x6e, 0x2f, 0x76, 0x65, 0x72,
+ 0x61, 0x69, 0x73, 0x6f, 0x6e, 0x2f, 0x76, 0x65,
+ 0x72, 0x69, 0x66, 0x69, 0x63, 0x61, 0x74, 0x69,
+ 0x6f, 0x6e, 0x19, 0x09, 0x5f, 0x8d, 0xa4, 0x01,
+ 0x69, 0x52, 0x53, 0x45, 0x5f, 0x42, 0x4c, 0x31,
+ 0x5f, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79,
+ 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b,
+ 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c,
+ 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0,
+ 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20,
+ 0x9a, 0x27, 0x1f, 0x2a, 0x91, 0x6b, 0x0b, 0x6e,
+ 0xe6, 0xce, 0xcb, 0x24, 0x26, 0xf0, 0xb3, 0x20,
+ 0x6e, 0xf0, 0x74, 0x57, 0x8b, 0xe5, 0x5d, 0x9b,
+ 0xc9, 0x4f, 0x6f, 0x3f, 0xe3, 0xab, 0x86, 0xaa,
+ 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35,
+ 0x36, 0xa4, 0x01, 0x67, 0x52, 0x53, 0x45, 0x5f,
0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78,
0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
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+ 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3,
+ 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3,
+ 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d, 0x26,
+ 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3, 0x39,
+ 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85, 0x29,
+ 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc, 0xe0,
+ 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x31, 0xd0,
+ 0x4d, 0x52, 0xcc, 0xde, 0x95, 0x2c, 0x1e, 0x32,
+ 0xcb, 0xa1, 0x81, 0x88, 0x5a, 0x40, 0xb8, 0xcc,
+ 0x38, 0xe0, 0x52, 0x8c, 0x1e, 0x89, 0x58, 0x98,
+ 0x07, 0x64, 0x2a, 0xa5, 0xe3, 0xf2, 0xbc, 0x37,
+ 0xf9, 0x53, 0x74, 0x50, 0x6b, 0xff, 0x4d, 0x2e,
+ 0x4b, 0xe7, 0x06, 0x3c, 0x4d, 0x72, 0x41, 0x92,
+ 0x70, 0xc7, 0x22, 0xe8, 0xd4, 0xd9, 0x3e, 0xe8,
+ 0xb6, 0xc9, 0xfa, 0xce, 0x3b, 0x43, 0xc9, 0x76,
+ 0x1a, 0x49, 0x94, 0x1a, 0xb6, 0xf3, 0x8f, 0xfd,
+ 0xff, 0x49, 0x6a, 0xd4, 0x63, 0xb4, 0xcb, 0xfa,
+ 0x11, 0xd8, 0x3e, 0x23, 0xe3, 0x1f, 0x7f, 0x62,
+ 0x32, 0x9d, 0xe3, 0x0c, 0x1c, 0xc8
};
/*
@@ -211,18 +212,21 @@
* RSE.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
- uintptr_t hash, size_t hash_size)
+ uintptr_t hash, size_t hash_size,
+ size_t *remaining_len)
{
+ const size_t token_size = sizeof(sample_platform_token);
(void)hash;
(void)hash_size;
- if (*len < sizeof(sample_platform_token)) {
+ /* Shouldn't happen because RMM uses the whole 4kB shared buffer */
+ if (*len < token_size) {
return -EINVAL;
}
- (void)memcpy((void *)buf, (const void *)sample_platform_token,
- sizeof(sample_platform_token));
- *len = sizeof(sample_platform_token);
+ memcpy((void *)buf, sample_platform_token, token_size);
+ *len = token_size;
+ *remaining_len = 0;
return 0;
}
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index db9d65a..f78be90 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -184,7 +184,7 @@
# define BL32_LIMIT (BL32_SRAM_LIMIT - FW_HANDOFF_SIZE)
#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID
# define BL32_MEM_BASE SEC_DRAM_BASE
-# define BL32_MEM_SIZE SEC_DRAM_SIZE
+# define BL32_MEM_SIZE (SEC_DRAM_SIZE - RME_GPT_DRAM_SIZE)
# define BL32_BASE BL32_DRAM_BASE
# define BL32_LIMIT (BL32_DRAM_LIMIT - FW_HANDOFF_SIZE)
#else
@@ -379,7 +379,8 @@
#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
PLAT_QEMU_L0_GPT_BASE, \
- PLAT_QEMU_L0_GPT_SIZE, \
+ PLAT_QEMU_L0_GPT_SIZE + \
+ PLAT_QEMU_GPT_BITLOCK_SIZE, \
MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index dde66aa..9b8c971 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,6 +32,17 @@
*
*/
func plat_reset_handler
+#ifdef PLAT_RK_CPU_RESET_EARLY
+ mov x18, x30
+ msr spsel, #0
+ bl plat_set_my_stack
+ mov x0, x20
+ mov x1, x21
+ mov x2, x22
+ mov x3, x23
+ bl rockchip_cpu_reset_early
+ mov x30, x18
+#endif
mrs x0, midr_el1
ubfx x0, x0, MIDR_PN_SHIFT, #12
cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
index 83d6cad..f693dbd 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -136,6 +136,22 @@
static __pmusramfunc void ddr_resume(void)
{
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
+ dsb();
+ isb();
+
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ }
+
dsu_restore_early();
}
@@ -1437,3 +1453,60 @@
pm_reg_rgns_init();
}
+
+static uint64_t boot_cpu_save[4];
+/* define in .data section */
+static uint32_t need_en_crypto = 1;
+
+void rockchip_cpu_reset_early(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ if (need_en_crypto == 0)
+ return;
+
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* save x0~x3 */
+ boot_cpu_save[0] = arg0;
+ boot_cpu_save[1] = arg1;
+ boot_cpu_save[2] = arg2;
+ boot_cpu_save[3] = arg3;
+
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4),
+ BITS_WITH_WMASK(0, 0x1, 4));
+
+ /* remap pmusram to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
+ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
+ cpuson_flags[0] = PMU_CPU_HOTPLUG;
+ cpuson_entry_point[0] = (uintptr_t)BL31_BASE;
+ dsb();
+
+ /* Must reset core0 to enable the crypto function.
+ * Core0 will boot from pmu_sram and jump to BL31_BASE.
+ */
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ } else {
+ need_en_crypto = 0;
+
+ /* remap bootrom to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
+
+ /*
+ * the crypto function has been enabled,
+ * restore the x0~x3.
+ */
+ __asm__ volatile ("ldr x20, [%0]\n"
+ "ldr x21, [%0, 0x8]\n"
+ "ldr x22, [%0, 0x10]\n"
+ "ldr x23, [%0, 0x18]\n"
+ : : "r" (&boot_cpu_save[0]));
+ }
+}
diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk
index 07eda40..2fadb5a 100644
--- a/plat/rockchip/rk3588/platform.mk
+++ b/plat/rockchip/rk3588/platform.mk
@@ -95,4 +95,4 @@
ENABLE_SPE_FOR_LOWER_ELS := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
-$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
+$(eval $(call add_define,PLAT_RK_CPU_RESET_EARLY))
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index eaaff7d..e139b49 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -23,6 +23,7 @@
BL1_SOURCES += drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
+ drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
plat/common/aarch64/platform_mp_stack.S \
plat/rpi/rpi3/rpi3_bl1_setup.c \
diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c
index 3ac30e0..6c8fb2d 100644
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,8 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <drivers/generic_delay_timer.h>
+#include <plat/common/platform.h>
#include <rpi_shared.h>
@@ -37,6 +39,15 @@
/* Initialize the console to provide early debug support */
rpi3_console_init();
+ /*
+ * Write the System Timer Frequency to CNTFRQ manually, this
+ * is required to use the delay_timer functionality.
+ */
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+
+ /* Enable arch timer */
+ generic_delay_timer_init();
+
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
bl1_tzram_layout.total_size = BL_RAM_SIZE;
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 6ed09d9..1aecece 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -76,14 +76,28 @@
#define DEFAULT_UUID_NUMBER U(7)
+#ifdef __aarch64__
+#define BL31_UUID_NUMBER U(1)
+#else
+#define BL31_UUID_NUMBER U(0)
+#endif
+
#if TRUSTED_BOARD_BOOT
#define TBBR_UUID_NUMBER U(6)
#else
#define TBBR_UUID_NUMBER U(0)
#endif
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define DDR_FW_UUID_NUMBER U(1)
+#else
+#define DDR_FW_UUID_NUMBER U(0)
+#endif
+
#define FCONF_ST_IO_UUID_NUMBER (DEFAULT_UUID_NUMBER + \
- TBBR_UUID_NUMBER)
+ BL31_UUID_NUMBER + \
+ TBBR_UUID_NUMBER + \
+ DDR_FW_UUID_NUMBER)
static io_uuid_spec_t fconf_stm32mp_uuids[FCONF_ST_IO_UUID_NUMBER];
static OBJECT_POOL_ARRAY(fconf_stm32mp_uuids_pool, fconf_stm32mp_uuids);
@@ -95,7 +109,13 @@
/* image id to property name table */
static const struct policies_load_info load_info[FCONF_ST_IO_UUID_NUMBER] = {
+#if STM32MP_DDR_FIP_IO_STORAGE
+ {DDR_FW_ID, "ddr_fw_uuid"},
+#endif
{FW_CONFIG_ID, "fw_cfg_uuid"},
+#ifdef __aarch64__
+ {BL31_IMAGE_ID, "bl31_uuid"},
+#endif
{BL32_IMAGE_ID, "bl32_uuid"},
{BL32_EXTRA1_IMAGE_ID, "bl32_extra1_uuid"},
{BL32_EXTRA2_IMAGE_ID, "bl32_extra2_uuid"},
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index edada72..eb6c6f8 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -6,6 +6,7 @@
#include <assert.h>
#include <cdefs.h>
+#include <errno.h>
#include <stdint.h>
#include <common/debug.h>
@@ -14,6 +15,8 @@
#include <drivers/mmc.h>
#include <drivers/st/regulator_fixed.h>
#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp_pmic2.h>
+#include <drivers/st/stm32mp_risab_regs.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/mmio.h>
@@ -195,6 +198,17 @@
panic();
}
+#if STM32MP_DDR_FIP_IO_STORAGE
+ /*
+ * RISAB3 setup (dedicated for SRAM1)
+ *
+ * Allow secure read/writes data accesses to non-secure
+ * blocks or pages, all RISAB registers are writable.
+ * DDR firmwares are saved there before being loaded in DDRPHY memory.
+ */
+ mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD);
+#endif
+
stm32_save_boot_info(boot_context);
if (stm32mp_uart_console_setup() != 0) {
@@ -217,6 +231,10 @@
panic();
}
+ if (dt_pmic_status() > 0) {
+ initialize_pmic();
+ }
+
fconf_populate("TB_FW", STM32MP_DTB_BASE);
stm32mp_io_setup();
@@ -229,7 +247,12 @@
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
int err = 0;
- bl_mem_params_node_t *bl_mem_params __maybe_unused = get_bl_mem_params_node(image_id);
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+ const struct dyn_cfg_dtb_info_t *config_info;
+ unsigned int i;
+ const unsigned int image_ids[] = {
+ BL31_IMAGE_ID,
+ };
assert(bl_mem_params != NULL);
@@ -253,6 +276,30 @@
FW_CONFIG_ID);
fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
+ /* Iterate through all the fw config IDs */
+ for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
+ bl_mem_params = get_bl_mem_params_node(image_ids[i]);
+ assert(bl_mem_params != NULL);
+
+ config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
+ if (config_info == NULL) {
+ continue;
+ }
+
+ bl_mem_params->image_info.image_base = config_info->config_addr;
+ bl_mem_params->image_info.image_max_size = config_info->config_max_size;
+
+ bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
+
+ switch (image_ids[i]) {
+ case BL31_IMAGE_ID:
+ bl_mem_params->ep_info.pc = config_info->config_addr;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
/*
* After this step, the BL2 device tree area will be overwritten
* with BL31 binary, no other data should be read from BL2 DT.
diff --git a/plat/st/stm32mp2/bl31_plat_setup.c b/plat/st/stm32mp2/bl31_plat_setup.c
new file mode 100644
index 0000000..dbf1371
--- /dev/null
+++ b/plat/st/stm32mp2/bl31_plat_setup.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/bl_common.h>
+#include <drivers/st/stm32_console.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ bl_params_t *params_from_bl2;
+ int ret;
+
+ /*
+ * Invalidate remaining data from second half of SYSRAM (used by BL2) as this area will
+ * be later used as non-secure.
+ */
+ inv_dcache_range(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_SIZE / 2U);
+
+ mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
+ BL_CODE_END - BL_CODE_BASE,
+ MT_CODE | MT_SECURE);
+
+#if USE_COHERENT_MEM
+ /* Map coherent memory */
+ mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+
+ configure_mmu();
+
+ /*
+ * Map upper SYSRAM where bl_params_t are stored in BL2
+ */
+ ret = mmap_add_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_SIZE / 2U, MT_RO_DATA | MT_SECURE);
+ if (ret < 0) {
+ ERROR("BL2 params area mapping: %d\n", ret);
+ panic();
+ }
+
+ assert(arg0 != 0UL);
+ params_from_bl2 = (bl_params_t *)arg0;
+ assert(params_from_bl2 != NULL);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
+
+ while (bl_params != NULL) {
+ bl_params = bl_params->next_params_info;
+ }
+
+ ret = mmap_remove_dynamic_region(STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE / 2U,
+ STM32MP_SYSRAM_SIZE / 2U);
+ if (ret < 0) {
+ ERROR("BL2 params area unmapping: %d\n", ret);
+ panic();
+ }
+}
+
+void bl31_plat_arch_setup(void)
+{
+}
+
+void bl31_platform_setup(void)
+{
+}
+
+entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
+{
+ return NULL;
+}
diff --git a/plat/st/stm32mp2/include/plat_tbbr_img_def.h b/plat/st/stm32mp2/include/plat_tbbr_img_def.h
index 5dfd41f..830bf88 100644
--- a/plat/st/stm32mp2/include/plat_tbbr_img_def.h
+++ b/plat/st/stm32mp2/include/plat_tbbr_img_def.h
@@ -40,8 +40,16 @@
#define STM32MP_CONFIG_CERT_ID U(24)
#define GPT_IMAGE_ID U(25)
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define DDR_FW_ID U(26)
+/* Increase the MAX_NUMBER_IDS to match the authentication pool required */
+#define MAX_NUMBER_IDS U(27)
+
+#else
/* Increase the MAX_NUMBER_IDS to match the authentication pool required */
#define MAX_NUMBER_IDS U(26)
+#endif
+
#endif /* PLAT_TBBR_IMG_DEF_H */
diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h
index 0f22a93..b98b56d 100644
--- a/plat/st/stm32mp2/include/platform_def.h
+++ b/plat/st/stm32mp2/include/platform_def.h
@@ -8,6 +8,7 @@
#define PLATFORM_DEF_H
#include <arch.h>
+#include <drivers/arm/gic_common.h>
#include <lib/utils_def.h>
#include <plat/common/common_def.h>
@@ -32,9 +33,9 @@
#define PLATFORM_CORE_COUNT U(2)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
-#define PLAT_MAX_PWR_LVL U(5)
-#define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5)
-#define PLAT_NUM_PWR_DOMAINS U(7)
+#define PLAT_MAX_PWR_LVL U(3)
+#define PLAT_MIN_SUSPEND_PWR_LVL U(2)
+#define PLAT_NUM_PWR_DOMAINS U(6)
/* Local power state for power domains in Run state. */
#define STM32MP_LOCAL_STATE_RUN U(0)
@@ -73,7 +74,7 @@
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE 0
-#define BL31_LIMIT STM32MP_BL31_SIZE
+#define BL31_LIMIT (STM32MP_SEC_SYSRAM_SIZE / 2)
/*******************************************************************************
* BL33 specific defines.
@@ -98,4 +99,59 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
+/*
+ * Secure Interrupt: based on the standard ARM mapping
+ */
+#define ARM_IRQ_SEC_PHY_TIMER U(29)
+
+#define ARM_IRQ_NON_SEC_SGI_0 U(0)
+
+#define ARM_IRQ_SEC_SGI_0 U(8)
+#define ARM_IRQ_SEC_SGI_1 U(9)
+#define ARM_IRQ_SEC_SGI_2 U(10)
+#define ARM_IRQ_SEC_SGI_3 U(11)
+#define ARM_IRQ_SEC_SGI_4 U(12)
+#define ARM_IRQ_SEC_SGI_5 U(13)
+#define ARM_IRQ_SEC_SGI_6 U(14)
+#define ARM_IRQ_SEC_SGI_7 U(15)
+
+/* Platform IRQ Priority */
+#define STM32MP_IRQ_SEC_SPI_PRIO U(0x10)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLATFORM_G1S_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define PLATFORM_G0_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
+ GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
index 0ef522e..f845560 100644
--- a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
@@ -19,6 +19,24 @@
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
+#if STM32MP_DDR_FIP_IO_STORAGE
+ /* Fill FW_DDR related information if it exists */
+ {
+ .image_id = DDR_FW_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t,
+ 0),
+
+ .image_info.image_base = STM32MP_DDR_FW_BASE,
+ .image_info.image_max_size = STM32MP_DDR_FW_MAX_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+#endif
+
/* Fill FW_CONFIG related information if it exists */
{
.image_id = FW_CONFIG_ID,
@@ -34,6 +52,23 @@
.next_handoff_image_id = INVALID_IMAGE_ID,
},
+
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index eacbd96..a22fe5c 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -27,6 +27,23 @@
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
+# DDR types
+STM32MP_DDR3_TYPE ?= 0
+STM32MP_DDR4_TYPE ?= 0
+STM32MP_LPDDR4_TYPE ?= 0
+ifeq (${STM32MP_DDR3_TYPE},1)
+DDR_TYPE := ddr3
+endif
+ifeq (${STM32MP_DDR4_TYPE},1)
+DDR_TYPE := ddr4
+endif
+ifeq (${STM32MP_LPDDR4_TYPE},1)
+DDR_TYPE := lpddr4
+endif
+
+# DDR features
+STM32MP_DDR_FIP_IO_STORAGE := 1
+
# Device tree
BL2_DTSI := stm32mp25-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
@@ -38,13 +55,26 @@
STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
+ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
+STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
+STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
+STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
+endif
FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
+ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
+# Add the FW_DDR to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
+endif
# Enable flags for C files
$(eval $(call assert_booleans,\
$(sort \
+ STM32MP_DDR_FIP_IO_STORAGE \
+ STM32MP_DDR3_TYPE \
+ STM32MP_DDR4_TYPE \
+ STM32MP_LPDDR4_TYPE \
STM32MP25 \
)))
@@ -58,9 +88,14 @@
$(eval $(call add_defines,\
$(sort \
DWL_BUFFER_BASE \
+ PLAT_DEF_FIP_UUID \
PLAT_PARTITION_MAX_ENTRIES \
PLAT_TBBR_IMG_DEF \
STM32_TF_A_COPIES \
+ STM32MP_DDR_FIP_IO_STORAGE \
+ STM32MP_DDR3_TYPE \
+ STM32MP_DDR4_TYPE \
+ STM32MP_LPDDR4_TYPE \
STM32MP25 \
)))
@@ -75,6 +110,11 @@
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
+PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
+ drivers/st/pmic/stpmic2.c \
+
+PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c
+
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
@@ -98,5 +138,35 @@
BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c
+# BL31 sources
+BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
+
+BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
+ plat/st/stm32mp2/stm32mp2_pm.c \
+ plat/st/stm32mp2/stm32mp2_topology.c
+# Generic GIC v2
+include drivers/arm/gic/v2/gicv2.mk
+
+BL31_SOURCES += ${GICV2_SOURCES} \
+ plat/common/plat_gicv2.c \
+ plat/st/common/stm32mp_gic.c
+
+# Generic PSCI
+BL31_SOURCES += plat/common/plat_psci_common.c
+
# Compilation rules
+.PHONY: check_ddr_type
+.SUFFIXES:
+
+bl2: check_ddr_type
+
+check_ddr_type:
+ $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
+ $(STM32MP_DDR4_TYPE) + \
+ $(STM32MP_LPDDR4_TYPE)))))
+ @if [ ${DDR_TYPE} != 1 ]; then \
+ echo "One and only one DDR type must be defined"; \
+ false; \
+ fi
+
include plat/st/common/common_rules.mk
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 81fdaae..615e5c9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -71,6 +71,9 @@
******************************************************************************/
#define STM32MP_SYSRAM_BASE U(0x0E000000)
#define STM32MP_SYSRAM_SIZE U(0x00040000)
+#define SRAM1_BASE U(0x0E040000)
+#define SRAM1_SIZE_FOR_TFA U(0x00010000)
+#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
/* DDR configuration */
#define STM32MP_DDR_BASE U(0x80000000)
@@ -106,6 +109,12 @@
#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
+/* Allocate remaining sysram to BL31 Binary only */
+#define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
+ STM32MP_BL2_SIZE)
+
+#define BL31_PROGBITS_LIMIT STM32MP_BL31_SIZE
+
#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
@@ -139,6 +148,11 @@
#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
#endif
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define STM32MP_DDR_FW_BASE SRAM1_BASE
+#define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
+#endif
+
#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
#define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
@@ -359,6 +373,11 @@
#define SYSCFG_BASE U(0x44230000)
/*******************************************************************************
+ * STM32MP RIF
+ ******************************************************************************/
+#define RISAB3_BASE U(0x42110000)
+
+/*******************************************************************************
* STM32MP CA35SSC
******************************************************************************/
#define A35SSC_BASE U(0x48800000)
diff --git a/plat/st/stm32mp2/stm32mp2_pm.c b/plat/st/stm32mp2/stm32mp2_pm.c
new file mode 100644
index 0000000..5bb381d
--- /dev/null
+++ b/plat/st/stm32mp2/stm32mp2_pm.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+static uintptr_t stm32_sec_entrypoint;
+
+static void stm32_cpu_standby(plat_local_state_t cpu_state)
+{
+}
+
+static int stm32_pwr_domain_on(u_register_t mpidr)
+{
+ return PSCI_E_INTERN_FAIL;
+}
+
+static void stm32_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ /* Nothing to do */
+}
+
+static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+ /* Nothing to do, power domain is not disabled */
+}
+
+static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+}
+
+/*******************************************************************************
+ * STM32MP2 handler called when a power domain has just been powered on after
+ * having been suspended earlier. The target_state encodes the low power state
+ * that each level has woken up from.
+ ******************************************************************************/
+static void stm32_pwr_domain_suspend_finish(const psci_power_state_t
+ *target_state)
+{
+ /* Nothing to do, power domain is not disabled */
+}
+
+static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t
+ *target_state)
+{
+ ERROR("stm32mp2 Power Down WFI: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 stm32_system_off(void)
+{
+ ERROR("stm32mp2 System Off: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 stm32_system_reset(void)
+{
+ stm32mp_system_reset();
+}
+
+static int stm32_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ return PSCI_E_INVALID_PARAMS;
+}
+
+static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /* The non-secure entry point must be in DDR */
+ if (entrypoint < STM32MP_DDR_BASE) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+static void stm32_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+}
+
+/*******************************************************************************
+ * Export the platform handlers. The ARM Standard platform layer will take care
+ * of registering the handlers with PSCI.
+ ******************************************************************************/
+static const plat_psci_ops_t stm32_psci_ops = {
+ .cpu_standby = stm32_cpu_standby,
+ .pwr_domain_on = stm32_pwr_domain_on,
+ .pwr_domain_off = stm32_pwr_domain_off,
+ .pwr_domain_suspend = stm32_pwr_domain_suspend,
+ .pwr_domain_on_finish = stm32_pwr_domain_on_finish,
+ .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish,
+ .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi,
+ .system_off = stm32_system_off,
+ .system_reset = stm32_system_reset,
+ .validate_power_state = stm32_validate_power_state,
+ .validate_ns_entrypoint = stm32_validate_ns_entrypoint,
+ .get_sys_suspend_power_state = stm32_get_sys_suspend_power_state,
+};
+
+/*******************************************************************************
+ * Export the platform specific power ops.
+ ******************************************************************************/
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ stm32_sec_entrypoint = sec_entrypoint;
+ *psci_ops = &stm32_psci_ops;
+
+ return 0;
+}
diff --git a/plat/st/stm32mp2/stm32mp2_private.c b/plat/st/stm32mp2/stm32mp2_private.c
index 2801a7f..99f6be2 100644
--- a/plat/st/stm32mp2/stm32mp2_private.c
+++ b/plat/st/stm32mp2/stm32mp2_private.c
@@ -12,12 +12,31 @@
#define BKPR_BOOT_MODE 96U
+#if defined(IMAGE_BL31)
+/* BL31 only uses the first half of the SYSRAM */
+#define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
+ STM32MP_SYSRAM_SIZE / 2U, \
+ MT_MEMORY | \
+ MT_RW | \
+ MT_SECURE | \
+ MT_EXECUTE_NEVER)
+#else
#define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
STM32MP_SYSRAM_SIZE, \
MT_MEMORY | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
+#endif
+
+#if STM32MP_DDR_FIP_IO_STORAGE
+#define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \
+ SRAM1_SIZE_FOR_TFA, \
+ MT_MEMORY | \
+ MT_RW | \
+ MT_SECURE | \
+ MT_EXECUTE_NEVER)
+#endif
#define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \
STM32MP_DEVICE_SIZE, \
@@ -29,6 +48,16 @@
#if defined(IMAGE_BL2)
static const mmap_region_t stm32mp2_mmap[] = {
MAP_SYSRAM,
+#if STM32MP_DDR_FIP_IO_STORAGE
+ MAP_SRAM1,
+#endif
+ MAP_DEVICE,
+ {0}
+};
+#endif
+#if defined(IMAGE_BL31)
+static const mmap_region_t stm32mp2_mmap[] = {
+ MAP_SYSRAM,
MAP_DEVICE,
{0}
};
diff --git a/plat/st/stm32mp2/stm32mp2_topology.c b/plat/st/stm32mp2/stm32mp2_topology.c
new file mode 100644
index 0000000..cc2d58c
--- /dev/null
+++ b/plat/st/stm32mp2/stm32mp2_topology.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+/* 1 cluster, all cores into */
+static const unsigned char stm32mp2_power_domain_tree_desc[] = {
+ PLATFORM_CLUSTER_COUNT,
+ PLATFORM_CORE_COUNT,
+};
+
+/* This function returns the platform topology */
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return stm32mp2_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+ u_register_t mpidr_copy = mpidr;
+
+ mpidr_copy &= MPIDR_AFFINITY_MASK;
+
+ if ((mpidr_copy & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) {
+ return -1;
+ }
+
+ cluster_id = (mpidr_copy >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+ return -1;
+ }
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in one
+ * of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_CORE_COUNT) {
+ return -1;
+ }
+
+ return (int)cpu_id;
+}
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index ebcc31b..4ad7b2d 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -86,6 +86,18 @@
}
#endif
+#if defined(XILINX_OF_BOARD_DTB_ADDR)
+static int check_fdt_reserved_memory(void *dtb, const char *node_name)
+{
+ int offset = fdt_path_offset(dtb, "/reserved-memory");
+
+ if (offset >= 0) {
+ offset = fdt_subnode_offset(dtb, offset, node_name);
+ }
+ return offset;
+}
+#endif
+
void prepare_dtb(void)
{
#if defined(XILINX_OF_BOARD_DTB_ADDR)
@@ -112,12 +124,19 @@
WARN("Failed to add PSCI cpu enable methods in DT\n");
}
- /* Reserve memory used by Trusted Firmware. */
- ret = fdt_add_reserved_memory(dtb, "tf-a",
- BL31_BASE,
- BL31_LIMIT - BL31_BASE);
+ /* Check reserved memory set in DT*/
+ ret = check_fdt_reserved_memory(dtb, "tf-a");
if (ret < 0) {
- WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
+ /* Reserve memory used by Trusted Firmware. */
+ ret = fdt_add_reserved_memory(dtb, "tf-a",
+ BL31_BASE,
+ BL31_LIMIT - BL31_BASE);
+ if (ret < 0) {
+ WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
+ }
+
+ } else {
+ WARN("Reserved memory pre-exists in DT.\n");
}
ret = fdt_pack(dtb);
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index 9e8134a..4236d8a 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -58,6 +58,10 @@
platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]);
platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]);
+
+ if (platform_id == VERSAL_COSIM) {
+ platform_id = VERSAL_QEMU;
+ }
}
const char *board_name_decode(void)
@@ -96,8 +100,6 @@
uart_clock = 212000;
break;
case VERSAL_QEMU:
- uart_clock = 25000000;
- break;
case VERSAL_SILICON:
uart_clock = 100000000;
break;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 0e4ec1c..57377a9 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -93,9 +93,6 @@
cpu_clock = 212000;
break;
case VERSAL_QEMU:
- /* Random values now */
- cpu_clock = 2720000;
- break;
case VERSAL_SILICON:
cpu_clock = 100000000;
break;
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index b7691ad..c50df7e 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -30,6 +30,7 @@
#define VERSAL_SPP U(1)
#define VERSAL_EMU U(2)
#define VERSAL_QEMU U(3)
+#define VERSAL_COSIM U(7)
/* Firmware Image Package */
#define VERSAL_PRIMARY_CPU 0
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index ccbfe77..3e44153 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -155,6 +155,9 @@
case 74:
dev_idx = XPM_NODEIDX_DEV_USB_0;
break;
+ case 122:
+ dev_idx = XPM_NODEIDX_DEV_GPIO_PMC;
+ break;
case 126:
case 127:
dev_idx = XPM_NODEIDX_DEV_SDIO_0;
diff --git a/poetry.lock b/poetry.lock
index 9b98b18..9a90704 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -27,13 +27,13 @@
[[package]]
name = "babel"
-version = "2.15.0"
+version = "2.16.0"
description = "Internationalization utilities"
optional = false
python-versions = ">=3.8"
files = [
- {file = "Babel-2.15.0-py3-none-any.whl", hash = "sha256:08706bdad8d0a3413266ab61bd6c34d0c28d6e1e7badf40a2cebe67644e2e1fb"},
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@@ -44,13 +44,13 @@
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+version = "1.2.2"
description = "A simple, correct Python build frontend"
optional = false
python-versions = ">=3.8"
files = [
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virtualenv = ["virtualenv (>=20.0.35)"]
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description = "Python package for providing Mozilla's CA Bundle."
optional = false
python-versions = ">=3.6"
files = [
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url = "tools/cot_dt2c"
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version = "0.18.1"
description = "Docutils -- Python Documentation Utilities"
@@ -248,14 +281,30 @@
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description = "Internationalized Domain Names in Applications (IDNA)"
optional = false
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description = "Read metadata from Python packages"
optional = false
python-versions = ">=3.8"
files = [
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python-versions = ">=3.8"
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version = "1.1.0"
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+pluggy = ">=1.5"
+pyproject-api = ">=1.7.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+virtualenv = ">=20.26.3"
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-argparse-cli (>=1.17)", "sphinx-autodoc-typehints (>=2.4)", "sphinx-copybutton (>=0.5.2)", "sphinx-inline-tabs (>=2023.4.21)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=24.8)"]
+testing = ["build[virtualenv] (>=1.2.2)", "covdefaults (>=2.3)", "detect-test-pollution (>=1.2)", "devpi-process (>=1)", "diff-cover (>=9.1.1)", "distlib (>=0.3.8)", "flaky (>=3.8.1)", "hatch-vcs (>=0.4)", "hatchling (>=1.25)", "psutil (>=6)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-xdist (>=3.6.1)", "re-assert (>=1.1)", "setuptools (>=74.1.2)", "time-machine (>=2.15)", "wheel (>=0.44)"]
+
+[[package]]
name = "typer"
version = "0.4.2"
description = "Typer, build great CLIs. Easy to code. Based on Python type hints."
@@ -1112,6 +1246,26 @@
zstd = ["zstandard (>=0.18.0)"]
[[package]]
+name = "virtualenv"
+version = "20.26.4"
+description = "Virtual Python Environment builder"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "virtualenv-20.26.4-py3-none-any.whl", hash = "sha256:48f2695d9809277003f30776d155615ffc11328e6a0a8c1f0ec80188d7874a55"},
+ {file = "virtualenv-20.26.4.tar.gz", hash = "sha256:c17f4e0f3e6036e9f26700446f85c76ab11df65ff6d8a9cbfad9f71aabfcf23c"},
+]
+
+[package.dependencies]
+distlib = ">=0.3.7,<1"
+filelock = ">=3.12.2,<4"
+platformdirs = ">=3.9.1,<5"
+
+[package.extras]
+docs = ["furo (>=2023.7.26)", "proselint (>=0.13)", "sphinx (>=7.1.2,!=7.3)", "sphinx-argparse (>=0.4)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=23.6)"]
+test = ["covdefaults (>=2.3)", "coverage (>=7.2.7)", "coverage-enable-subprocess (>=1)", "flaky (>=3.7)", "packaging (>=23.1)", "pytest (>=7.4)", "pytest-env (>=0.8.2)", "pytest-freezer (>=0.4.8)", "pytest-mock (>=3.11.1)", "pytest-randomly (>=3.12)", "pytest-timeout (>=2.1)", "setuptools (>=68)", "time-machine (>=2.10)"]
+
+[[package]]
name = "wcwidth"
version = "0.2.13"
description = "Measures the displayed width of unicode strings in a terminal"
@@ -1124,13 +1278,13 @@
[[package]]
name = "wheel"
-version = "0.43.0"
+version = "0.44.0"
description = "A built-package format for Python"
optional = false
python-versions = ">=3.8"
files = [
- {file = "wheel-0.43.0-py3-none-any.whl", hash = "sha256:55c570405f142630c6b9f72fe09d9b67cf1477fcf543ae5b8dcb1f5b7377da81"},
- {file = "wheel-0.43.0.tar.gz", hash = "sha256:465ef92c69fa5c5da2d1cf8ac40559a8c940886afcef87dcf14b9470862f1d85"},
+ {file = "wheel-0.44.0-py3-none-any.whl", hash = "sha256:2376a90c98cc337d18623527a97c31797bd02bad0033d41547043a1cbfbe448f"},
+ {file = "wheel-0.44.0.tar.gz", hash = "sha256:a29c3f2817e95ab89aa4660681ad547c0e9547f20e75b0562fe7723c9a2a9d49"},
]
[package.extras]
@@ -1138,20 +1292,24 @@
[[package]]
name = "zipp"
-version = "3.19.2"
+version = "3.20.1"
description = "Backport of pathlib-compatible object wrapper for zip files"
optional = false
python-versions = ">=3.8"
files = [
- {file = "zipp-3.19.2-py3-none-any.whl", hash = "sha256:f091755f667055f2d02b32c53771a7a6c8b47e1fdbc4b72a8b9072b3eef8015c"},
- {file = "zipp-3.19.2.tar.gz", hash = "sha256:bf1dcf6450f873a13e952a29504887c89e6de7506209e5b1bcc3460135d4de19"},
+ {file = "zipp-3.20.1-py3-none-any.whl", hash = "sha256:9960cd8967c8f85a56f920d5d507274e74f9ff813a0ab8889a5b5be2daf44064"},
+ {file = "zipp-3.20.1.tar.gz", hash = "sha256:c22b14cc4763c5a5b04134207736c107db42e9d3ef2d9779d465f5f1bcba572b"},
]
[package.extras]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)"]
+cover = ["pytest-cov"]
doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-lint"]
-test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-ignore-flaky", "pytest-mypy", "pytest-ruff (>=0.2.1)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-ignore-flaky"]
+type = ["pytest-mypy"]
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "d893034cad02533bc86fb98c7d93a0eac6a755fea5efd553924e4762ed3f1fdb"
+content-hash = "6a6d2fe9390a4d7d1ecf808d5f303f2dc1eeb44736827b706a858046f3eea1db"
diff --git a/pyproject.toml b/pyproject.toml
index f0b3925..f34c3d1 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -15,7 +15,7 @@
[tool.poetry.dependencies]
python = "^3.8"
cot-dt2c = {path = "tools/cot_dt2c", develop = true}
-tlc = {path = "tools/tlc"}
+tlc = {path = "tools/tlc", develop = true}
[tool.poetry.group.docs]
optional = true
diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c
index 53afb17..8d27e96 100644
--- a/services/std_svc/drtm/drtm_main.c
+++ b/services/std_svc/drtm/drtm_main.c
@@ -463,7 +463,7 @@
* is required to avoid / defend against racing with cache evictions
*/
va_mapping_size = ALIGNED_UP((dlme_end - dlme_start), DRTM_PAGE_SIZE);
- rc = mmap_add_dynamic_region_alloc_va(dlme_img_start, &va_mapping, va_mapping_size,
+ rc = mmap_add_dynamic_region_alloc_va(dlme_start, &va_mapping, va_mapping_size,
MT_MEMORY | MT_NS | MT_RO |
MT_SHAREABILITY_ISH);
if (rc != 0) {
@@ -512,10 +512,10 @@
sctlr &= ~(/* Disable DLME's EL MMU, since the existing page-tables are untrusted. */
SCTLR_M_BIT
| SCTLR_EE_BIT /* Little-endian data accesses. */
+ | SCTLR_C_BIT /* disable data caching */
+ | SCTLR_I_BIT /* disable instruction caching */
);
- sctlr |= SCTLR_C_BIT | SCTLR_I_BIT; /* Allow instruction and data caching. */
-
switch (dlme_el) {
case DLME_AT_EL1:
write_sctlr_el1(sctlr);
@@ -655,6 +655,10 @@
drtm_dl_reset_dlme_el_state(dlme_el);
drtm_dl_reset_dlme_context(dlme_el);
+ /*
+ * Setting the Generic Timer frequency is required before launching
+ * DLME and is already done for running CPU during PSCI setup.
+ */
drtm_dl_prepare_eret_to_dlme(&args, dlme_el);
/*
diff --git a/services/std_svc/rmmd/rmmd_attest.c b/services/std_svc/rmmd/rmmd_attest.c
index 25adf50..f73236c 100644
--- a/services/std_svc/rmmd/rmmd_attest.c
+++ b/services/std_svc/rmmd/rmmd_attest.c
@@ -1,8 +1,9 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <stdint.h>
#include <string.h>
@@ -85,7 +86,8 @@
}
int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size,
- uint64_t c_size)
+ uint64_t c_size,
+ uint64_t *remaining_len)
{
int err;
uint8_t temp_buf[SHA512_DIGEST_SIZE];
@@ -110,9 +112,19 @@
/* Get the platform token. */
err = plat_rmmd_get_cca_attest_token((uintptr_t)buf_pa,
- buf_size, (uintptr_t)temp_buf, c_size);
+ buf_size, (uintptr_t)temp_buf, c_size, remaining_len);
- if (err != 0) {
+ switch (err) {
+ case 0:
+ err = E_RMM_OK;
+ break;
+ case -EAGAIN:
+ err = E_RMM_AGAIN;
+ break;
+ case -EINVAL:
+ err = E_RMM_INVAL;
+ break;
+ default:
ERROR("Failed to get platform token: %d.\n", err);
err = E_RMM_UNK;
}
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 15b3724..153bb01 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -448,6 +448,7 @@
uint64_t x3, uint64_t x4, void *cookie,
void *handle, uint64_t flags)
{
+ uint64_t remaining_len = 0;
uint32_t src_sec_state;
int ret;
@@ -473,8 +474,8 @@
ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM);
SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1));
case RMM_ATTEST_GET_PLAT_TOKEN:
- ret = rmmd_attest_get_platform_token(x1, &x2, x3);
- SMC_RET2(handle, ret, x2);
+ ret = rmmd_attest_get_platform_token(x1, &x2, x3, &remaining_len);
+ SMC_RET3(handle, ret, x2, remaining_len);
case RMM_ATTEST_GET_REALM_KEY:
ret = rmmd_attest_get_signing_key(x1, &x2, x3);
SMC_RET2(handle, ret, x2);
diff --git a/services/std_svc/rmmd/rmmd_private.h b/services/std_svc/rmmd/rmmd_private.h
index 4954a43..6d3b5ec 100644
--- a/services/std_svc/rmmd/rmmd_private.h
+++ b/services/std_svc/rmmd/rmmd_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,7 +47,8 @@
/* Functions implementing attestation utilities for RMM */
int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size,
- uint64_t c_size);
+ uint64_t c_size,
+ uint64_t *remaining_len);
int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size,
uint64_t ecc_curve);
diff --git a/tools/tlc/.gitignore b/tools/tlc/.gitignore
new file mode 100644
index 0000000..ad4a1f1
--- /dev/null
+++ b/tools/tlc/.gitignore
@@ -0,0 +1,176 @@
+# Created by https://www.toptal.com/developers/gitignore/api/python
+# Edit at https://www.toptal.com/developers/gitignore?templates=python
+
+### Python ###
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+share/python-wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+MANIFEST
+
+# PyInstaller
+# Usually these files are written by a python script from a template
+# before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.nox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*.cover
+*.py,cover
+.hypothesis/
+.pytest_cache/
+cover/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+db.sqlite3
+db.sqlite3-journal
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+.pybuilder/
+target/
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# IPython
+profile_default/
+ipython_config.py
+
+# pyenv
+# For a library or package, you might want to ignore these files since the code is
+# intended to run in multiple environments; otherwise, check them in:
+# .python-version
+
+# pipenv
+# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
+# However, in case of collaboration, if having platform-specific dependencies or dependencies
+# having no cross-platform support, pipenv may install dependencies that don't work, or not
+# install all needed dependencies.
+#Pipfile.lock
+
+# poetry
+# Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control.
+# This is especially recommended for binary packages to ensure reproducibility, and is more
+# commonly ignored for libraries.
+# https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control
+#poetry.lock
+
+# pdm
+# Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control.
+#pdm.lock
+# pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it
+# in version control.
+# https://pdm.fming.dev/#use-with-ide
+.pdm.toml
+
+# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm
+__pypackages__/
+
+# Celery stuff
+celerybeat-schedule
+celerybeat.pid
+
+# SageMath parsed files
+*.sage.py
+
+# Environments
+.env
+.venv
+env/
+venv/
+ENV/
+env.bak/
+venv.bak/
+
+# Spyder project settings
+.spyderproject
+.spyproject
+
+# Rope project settings
+.ropeproject
+
+# mkdocs documentation
+/site
+
+# mypy
+.mypy_cache/
+.dmypy.json
+dmypy.json
+
+# Pyre type checker
+.pyre/
+
+# pytype static type analyzer
+.pytype/
+
+# Cython debug symbols
+cython_debug/
+
+# PyCharm
+# JetBrains specific template is maintained in a separate JetBrains.gitignore that can
+# be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore
+# and can be added to the global gitignore or merged into this file. For a more nuclear
+# option (not recommended) you can uncomment the following to ignore the entire idea folder.
+#.idea/
+
+### Python Patch ###
+# Poetry local configuration file - https://python-poetry.org/docs/configuration/#local-configuration
+poetry.toml
+
+# ruff
+.ruff_cache/
+
+# LSP config files
+pyrightconfig.json
+
+# End of https://www.toptal.com/developers/gitignore/api/python
diff --git a/tools/tlc/Makefile b/tools/tlc/Makefile
deleted file mode 100644
index e50b9dd..0000000
--- a/tools/tlc/Makefile
+++ /dev/null
@@ -1,109 +0,0 @@
-#
-# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-
-##* Variables
-SHELL := /usr/bin/env bash
-PYTHON := python
-PYTHONPATH := `pwd`
-
-#* Docker variables
-IMAGE := tlc
-VERSION := latest
-
-#* Installation
-.PHONY: dist
-dist: clean
- poetry build
-
-.PHONY: dev-install
-dev-install:
- poetry lock -n --no-update && poetry export --without-hashes > requirements.txt
- poetry install -n
- -poetry run mypy --install-types --non-interactive ./
-
-.PHONY: install
-install: dist
- pip install dist/*.whl
-
-.PHONY: pre-commit-install
-pre-commit-install:
- poetry run pre-commit install
-
-#* Formatters
-.PHONY: codestyle
-codestyle:
- poetry run pyupgrade --exit-zero-even-if-changed --py38-plus **/*.py
- poetry run isort --settings-path pyproject.toml ./
- poetry run black --config pyproject.toml ./
-
-.PHONY: formatting
-formatting: codestyle
-
-#* Linting
-.PHONY: test
-test:
- PYTHONPATH=$(PYTHONPATH) poetry run pytest -c pyproject.toml --cov-report=html --cov=tlc tests/
- poetry run coverage-badge -o assets/images/coverage.svg -f
-
-.PHONY: check-codestyle
-check-codestyle:
- poetry run isort --diff --check-only --settings-path pyproject.toml ./
- poetry run black --diff --check --config pyproject.toml ./
- poetry run darglint --verbosity 2 tlc tests
-
-.PHONY: mypy
-mypy:
- poetry run mypy --config-file pyproject.toml ./
-
-.PHONY: check-safety
-check-safety:
- poetry check
- poetry run safety check --full-report
- poetry run bandit -ll --recursive tlc tests
-
-.PHONY: lint
-lint: test check-codestyle mypy check-safety
-
-.PHONY: update-dev-deps
-update-dev-deps:
- poetry add -D bandit@latest darglint@latest "isort[colors]@latest" mypy@latest pre-commit@latest pydocstyle@latest pylint@latest pytest@latest pyupgrade@latest safety@latest coverage@latest coverage-badge@latest pytest-html@latest pytest-cov@latest
- poetry add -D --allow-prereleases black@latest
-
-#* Docker
-.PHONY: docker-build docker-remove
-docker-build:
- @echo Building docker $(IMAGE):$(VERSION) ...
- docker build \
- -t $(IMAGE):$(VERSION) . \
- -f ./docker/Dockerfile --no-cache
-
-docker-remove:
- @echo Removing docker $(IMAGE):$(VERSION) ...
- docker rmi -f $(IMAGE):$(VERSION)
-
-
-#* Cleaning
-.PHONY: clean .clean-build clean-pyc clean-test
-clean: clean-build clean-pyc clean-test ## remove all build, test, coverage and Python artifacts
-
-clean-build: ## remove build artifacts
- rm -fr build/
- rm -fr dist/
- rm -fr .eggs/
- find . -name '*.egg-info' -exec rm -fr {} +
- find . -name '*.egg' -exec rm -f {} +
-
-clean-pyc: ## remove Python file artifacts
- find . -name '*.pyc' -exec rm -f {} +
- find . -name '*.pyo' -exec rm -f {} +
- find . -name '*~' -exec rm -f {} +
- find . -name '__pycache__' -exec rm -fr {} +
- find . | grep -E ".pytest_cache" | xargs rm -rf
- find . | grep -E ".mypy_cache" | xargs rm -rf
-
-clean-test: ## remove test and coverage artifacts
- rm -fr .tox/
- rm -f .coverage
- rm -fr htmlcov/
diff --git a/tools/tlc/poetry.lock b/tools/tlc/poetry.lock
index 839f236..decec59 100644
--- a/tools/tlc/poetry.lock
+++ b/tools/tlc/poetry.lock
@@ -45,33 +45,33 @@
[[package]]
name = "black"
-version = "24.4.2"
+version = "24.8.0"
description = "The uncompromising code formatter."
optional = false
python-versions = ">=3.8"
files = [
- {file = "black-24.4.2-cp310-cp310-macosx_10_9_x86_64.whl", hash = "sha256:dd1b5a14e417189db4c7b64a6540f31730713d173f0b63e55fabd52d61d8fdce"},
- {file = "black-24.4.2-cp310-cp310-macosx_11_0_arm64.whl", hash = "sha256:8e537d281831ad0e71007dcdcbe50a71470b978c453fa41ce77186bbe0ed6021"},
- {file = "black-24.4.2-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:eaea3008c281f1038edb473c1aa8ed8143a5535ff18f978a318f10302b254063"},
- {file = "black-24.4.2-cp310-cp310-win_amd64.whl", hash = "sha256:7768a0dbf16a39aa5e9a3ded568bb545c8c2727396d063bbaf847df05b08cd96"},
- {file = "black-24.4.2-cp311-cp311-macosx_10_9_x86_64.whl", hash = "sha256:257d724c2c9b1660f353b36c802ccece186a30accc7742c176d29c146df6e474"},
- {file = "black-24.4.2-cp311-cp311-macosx_11_0_arm64.whl", hash = "sha256:bdde6f877a18f24844e381d45e9947a49e97933573ac9d4345399be37621e26c"},
- {file = "black-24.4.2-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:e151054aa00bad1f4e1f04919542885f89f5f7d086b8a59e5000e6c616896ffb"},
- {file = "black-24.4.2-cp311-cp311-win_amd64.whl", hash = "sha256:7e122b1c4fb252fd85df3ca93578732b4749d9be076593076ef4d07a0233c3e1"},
- {file = "black-24.4.2-cp312-cp312-macosx_10_9_x86_64.whl", hash = "sha256:accf49e151c8ed2c0cdc528691838afd217c50412534e876a19270fea1e28e2d"},
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python-versions = ">=3.6"
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description = "Generate coverage badges for Coverage.py."
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python-versions = "*"
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coverage = "*"
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name = "darglint"
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python-versions = ">=3.8"
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description = "File identification library for Python"
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python-versions = ">=3.8"
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description = "Internationalized Domain Names in Applications (IDNA)"
optional = false
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name = "iniconfig"
version = "2.0.0"
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name = "pbr"
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description = "Python Build Reasonableness"
optional = false
python-versions = ">=2.6"
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optional = false
python-versions = ">=3.8"
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name = "pluggy"
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testutils = ["gitpython (>3)"]
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[package.dependencies]
@@ -852,7 +897,7 @@
pytest = ">=4.6"
[package.extras]
-testing = ["fields", "hunter", "process-tests", "pytest-xdist", "six", "virtualenv"]
+testing = ["fields", "hunter", "process-tests", "pytest-xdist", "virtualenv"]
[[package]]
name = "pytest-html"
@@ -907,62 +952,64 @@
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description = "YAML parser and emitter for Python"
optional = false
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+ {file = "PyYAML-6.0.2-cp38-cp38-win_amd64.whl", hash = "sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff"},
+ {file = "PyYAML-6.0.2-cp39-cp39-macosx_10_9_x86_64.whl", hash = "sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d"},
+ {file = "PyYAML-6.0.2-cp39-cp39-macosx_11_0_arm64.whl", hash = "sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f"},
+ {file = "PyYAML-6.0.2-cp39-cp39-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290"},
+ {file = "PyYAML-6.0.2-cp39-cp39-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12"},
+ {file = "PyYAML-6.0.2-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19"},
+ {file = "PyYAML-6.0.2-cp39-cp39-musllinux_1_1_aarch64.whl", hash = "sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e"},
+ {file = "PyYAML-6.0.2-cp39-cp39-musllinux_1_1_x86_64.whl", hash = "sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725"},
+ {file = "PyYAML-6.0.2-cp39-cp39-win32.whl", hash = "sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631"},
+ {file = "PyYAML-6.0.2-cp39-cp39-win_amd64.whl", hash = "sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8"},
+ {file = "pyyaml-6.0.2.tar.gz", hash = "sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e"},
]
[[package]]
@@ -1107,19 +1154,23 @@
[[package]]
name = "setuptools"
-version = "72.1.0"
+version = "75.1.0"
description = "Easily download, build, install, upgrade, and uninstall Python packages"
optional = false
python-versions = ">=3.8"
files = [
- {file = "setuptools-72.1.0-py3-none-any.whl", hash = "sha256:5a03e1860cf56bb6ef48ce186b0e557fdba433237481a9a625176c2831be15d1"},
- {file = "setuptools-72.1.0.tar.gz", hash = "sha256:8d243eff56d095e5817f796ede6ae32941278f542e0f941867cc05ae52b162ec"},
+ {file = "setuptools-75.1.0-py3-none-any.whl", hash = "sha256:35ab7fd3bcd95e6b7fd704e4a1539513edad446c097797f2985e0e4b960772f2"},
+ {file = "setuptools-75.1.0.tar.gz", hash = "sha256:d59a21b17a275fb872a9c3dae73963160ae079f1049ed956880cd7c09b120538"},
]
[package.extras]
-core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.text (>=3.7)", "more-itertools (>=8.8)", "ordered-set (>=3.1.1)", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
-doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier"]
-test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "importlib-metadata", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "mypy (==1.11.*)", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-home (>=0.5)", "pytest-mypy", "pytest-perf", "pytest-ruff (<0.4)", "pytest-ruff (>=0.2.1)", "pytest-ruff (>=0.3.2)", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel"]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)", "ruff (>=0.5.2)"]
+core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.collections", "jaraco.functools", "jaraco.text (>=3.7)", "more-itertools", "more-itertools (>=8.8)", "packaging", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
+cover = ["pytest-cov"]
+doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier", "towncrier (<24.7)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-home (>=0.5)", "pytest-perf", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel (>=0.44.0)"]
+type = ["importlib-metadata (>=7.0.2)", "jaraco.develop (>=7.21)", "mypy (==1.11.*)", "pytest-mypy"]
[[package]]
name = "shellingham"
@@ -1145,17 +1196,17 @@
[[package]]
name = "stevedore"
-version = "5.2.0"
+version = "5.3.0"
description = "Manage dynamic plugins for Python applications"
optional = false
python-versions = ">=3.8"
files = [
- {file = "stevedore-5.2.0-py3-none-any.whl", hash = "sha256:1c15d95766ca0569cad14cb6272d4d31dae66b011a929d7c18219c176ea1b5c9"},
- {file = "stevedore-5.2.0.tar.gz", hash = "sha256:46b93ca40e1114cea93d738a6c1e365396981bb6bb78c27045b7587c9473544d"},
+ {file = "stevedore-5.3.0-py3-none-any.whl", hash = "sha256:1efd34ca08f474dad08d9b19e934a22c68bb6fe416926479ba29e5013bcc8f78"},
+ {file = "stevedore-5.3.0.tar.gz", hash = "sha256:9a64265f4060312828151c204efbe9b7a9852a0d9228756344dbc7e4023e375a"},
]
[package.dependencies]
-pbr = ">=2.0.0,<2.1.0 || >2.1.0"
+pbr = ">=2.0.0"
[[package]]
name = "tokenize-rt"
@@ -1192,16 +1243,43 @@
[[package]]
name = "tomlkit"
-version = "0.13.0"
+version = "0.13.2"
description = "Style preserving TOML library"
optional = false
python-versions = ">=3.8"
files = [
- {file = "tomlkit-0.13.0-py3-none-any.whl", hash = "sha256:7075d3042d03b80f603482d69bf0c8f345c2b30e41699fd8883227f89972b264"},
- {file = "tomlkit-0.13.0.tar.gz", hash = "sha256:08ad192699734149f5b97b45f1f18dad7eb1b6d16bc72ad0c2335772650d7b72"},
+ {file = "tomlkit-0.13.2-py3-none-any.whl", hash = "sha256:7a974427f6e119197f670fbbbeae7bef749a6c14e793db934baefc1b5f03efde"},
+ {file = "tomlkit-0.13.2.tar.gz", hash = "sha256:fff5fe59a87295b278abd31bec92c15d9bc4a06885ab12bcea52c71119392e79"},
]
[[package]]
+name = "tox"
+version = "4.20.0"
+description = "tox is a generic virtualenv management and test command line tool"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "tox-4.20.0-py3-none-any.whl", hash = "sha256:21a8005e3d3fe5658a8e36b8ca3ed13a4230429063c5cc2a2fdac6ee5aa0de34"},
+ {file = "tox-4.20.0.tar.gz", hash = "sha256:5b78a49b6eaaeab3ae4186415e7c97d524f762ae967c63562687c3e5f0ec23d5"},
+]
+
+[package.dependencies]
+cachetools = ">=5.5"
+chardet = ">=5.2"
+colorama = ">=0.4.6"
+filelock = ">=3.15.4"
+packaging = ">=24.1"
+platformdirs = ">=4.2.2"
+pluggy = ">=1.5"
+pyproject-api = ">=1.7.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+virtualenv = ">=20.26.3"
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-argparse-cli (>=1.17)", "sphinx-autodoc-typehints (>=2.4)", "sphinx-copybutton (>=0.5.2)", "sphinx-inline-tabs (>=2023.4.21)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=24.8)"]
+testing = ["build[virtualenv] (>=1.2.2)", "covdefaults (>=2.3)", "detect-test-pollution (>=1.2)", "devpi-process (>=1)", "diff-cover (>=9.1.1)", "distlib (>=0.3.8)", "flaky (>=3.8.1)", "hatch-vcs (>=0.4)", "hatchling (>=1.25)", "psutil (>=6)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-xdist (>=3.6.1)", "re-assert (>=1.1)", "setuptools (>=74.1.2)", "time-machine (>=2.15)", "wheel (>=0.44)"]
+
+[[package]]
name = "typer"
version = "0.4.2"
description = "Typer, build great CLIs. Easy to code. Based on Python type hints."
@@ -1236,13 +1314,13 @@
[[package]]
name = "urllib3"
-version = "2.2.2"
+version = "2.2.3"
description = "HTTP library with thread-safe connection pooling, file post, and more."
optional = false
python-versions = ">=3.8"
files = [
- {file = "urllib3-2.2.2-py3-none-any.whl", hash = "sha256:a448b2f64d686155468037e1ace9f2d2199776e17f0a46610480d311f73e3472"},
- {file = "urllib3-2.2.2.tar.gz", hash = "sha256:dd505485549a7a552833da5e6063639d0d177c04f23bc3864e41e5dc5f612168"},
+ {file = "urllib3-2.2.3-py3-none-any.whl", hash = "sha256:ca899ca043dcb1bafa3e262d73aa25c465bfb49e0bd9dd5d59f1d0acba2f8fac"},
+ {file = "urllib3-2.2.3.tar.gz", hash = "sha256:e7d814a81dad81e6caf2ec9fdedb284ecc9c73076b62654547cc64ccdcae26e9"},
]
[package.extras]
@@ -1253,13 +1331,13 @@
[[package]]
name = "virtualenv"
-version = "20.26.3"
+version = "20.26.5"
description = "Virtual Python Environment builder"
optional = false
python-versions = ">=3.7"
files = [
- {file = "virtualenv-20.26.3-py3-none-any.whl", hash = "sha256:8cc4a31139e796e9a7de2cd5cf2489de1217193116a8fd42328f1bd65f434589"},
- {file = "virtualenv-20.26.3.tar.gz", hash = "sha256:4c43a2a236279d9ea36a0d76f98d84bd6ca94ac4e0f4a3b9d46d05e10fea542a"},
+ {file = "virtualenv-20.26.5-py3-none-any.whl", hash = "sha256:4f3ac17b81fba3ce3bd6f4ead2749a72da5929c01774948e243db9ba41df4ff6"},
+ {file = "virtualenv-20.26.5.tar.gz", hash = "sha256:ce489cac131aa58f4b25e321d6d186171f78e6cb13fafbf32a840cee67733ff4"},
]
[package.dependencies]
@@ -1353,4 +1431,4 @@
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "cfcb196cda412f6139302937640455aa8154d7979c69017fe45ddd528e4a1bf2"
+content-hash = "aac9123f3fa544b8c3e9b085f41f5a1c6c4ed2d59ce3236dcda6ea2aef5a694c"
diff --git a/tools/tlc/pyproject.toml b/tools/tlc/pyproject.toml
index 5661abf..b606238 100644
--- a/tools/tlc/pyproject.toml
+++ b/tools/tlc/pyproject.toml
@@ -38,9 +38,15 @@
rich = "^10.14.0"
click = "^8.1.7"
pyyaml = "^6.0.1"
+tox = "^4.18.0"
+jinja2 = "^3.1.4"
-[tool.poetry.dev-dependencies]
+[tool.poetry.group.dev]
+optional = true
+
+[tool.poetry.group.dev.dependencies]
bandit = "^1.7.1"
+tox = "^4.18.0"
darglint = "^1.8.1"
black = "^24.4.2"
isort = {extras = ["colors"], version = "^5.10.1"}
@@ -49,13 +55,13 @@
pre-commit = "^2.15.0"
pydocstyle = "^6.1.1"
pylint = "^2.11.1"
-pytest = "^7.0.0"
+pytest = "^8.0.0"
pyupgrade = "^2.29.1"
safety = "^2.2.0"
coverage = "^6.1.2"
coverage-badge = "^1.1.0"
pytest-html = "^4.1.1"
-pytest-cov = "^3.0.0"
+pytest-cov = "5.0.0"
[tool.black]
# https://github.com/psf/black
@@ -135,13 +141,11 @@
[tool.coverage.run]
source = ["tests"]
-
-[coverage.paths]
-source = "tlc"
-
-[coverage.run]
branch = true
-[coverage.report]
+[tool.coverage.paths]
+source = ["tlc"]
+
+[tool.coverage.report]
fail_under = 50
show_missing = true
diff --git a/tools/tlc/tests/test_cli.py b/tools/tlc/tests/test_cli.py
index 99b5816..a5ef30e 100644
--- a/tools/tlc/tests/test_cli.py
+++ b/tools/tlc/tests/test_cli.py
@@ -9,12 +9,12 @@
"""Contains unit tests for the CLI functionality."""
+from math import ceil, log2
from pathlib import Path
+from re import findall, search
from unittest import mock
-from math import log2, ceil
import pytest
-import pytest
import yaml
from click.testing import CliRunner
@@ -384,6 +384,69 @@
assert actual == expected
+@pytest.mark.parametrize("option", ["-O", "--output"])
+def test_gen_tl_header_with_output_name(tlcrunner, tmptlstr, option, filename="test.h"):
+ with tlcrunner.isolated_filesystem():
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ option,
+ filename,
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path(filename).exists()
+
+
+def test_gen_tl_with_fdt_header(tmptlstr, tmpfdt):
+ tlcrunner = CliRunner()
+
+ with tlcrunner.isolated_filesystem():
+ tlcrunner.invoke(cli, ["create", "--size", 1000, "--fdt", tmpfdt, tmptlstr])
+
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path("header.h").exists()
+
+ with open("header.h", "r") as f:
+ dtb_match = search(r"DTB_OFFSET\s+(\d+)", "".join(f.readlines()))
+ assert dtb_match and dtb_match[1].isnumeric()
+
+
+def test_gen_empty_tl_c_header(tlcrunner, tmptlstr):
+ with tlcrunner.isolated_filesystem():
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path("header.h").exists()
+
+ with open("header.h", "r") as f:
+ lines = "".join(f.readlines())
+
+ assert TransferList.hdr_size == int(
+ findall(r"SIZE\s+(0x[0-9a-fA-F]+|\d+)", lines)[0], 16
+ )
+ assert TransferList.version == int(
+ findall(r"VERSION.+(0x[0-9a-fA-F]+|\d+)", lines)[0]
+ )
+
+
def bytes_to_hex(data: bytes) -> str:
"""Convert bytes to a hex string in the same format as the debugger in
ArmDS
diff --git a/tools/tlc/tlc/cli.py b/tools/tlc/tlc/cli.py
index 1d4949d..3d60938 100644
--- a/tools/tlc/tlc/cli.py
+++ b/tools/tlc/tlc/cli.py
@@ -12,6 +12,7 @@
from pathlib import Path
import click
+import jinja2
import yaml
from tlc.tl import *
@@ -166,6 +167,34 @@
@cli.command()
@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "--output",
+ "-O",
+ type=click.Path(exists=False),
+ help="Output filename for the header",
+ default=Path("header.h"),
+)
+def gen_header(filename, output):
+ """Generate a header with common definitions."""
+ tl = TransferList.fromfile(filename)
+ tmp_keys = tl.__dict__
+ tmp_keys["header_guard"] = Path(output).name.replace(".", "_").upper()
+
+ dtb_te = tl.get_entry(1)
+
+ if dtb_te:
+ tmp_keys["dtb_offset"] = dtb_te.offset + dtb_te.hdr_size
+
+ env = jinja2.Environment(
+ loader=jinja2.PackageLoader("tlc", "templates"),
+ )
+ template = env.get_template("header.h.j2")
+ with open(output, "w") as f:
+ f.write(template.render(tmp_keys))
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
def validate(filename):
"""Validate the contents of an existing Transfer List."""
TransferList.fromfile(filename)
diff --git a/tools/tlc/tlc/templates/header.h.j2 b/tools/tlc/tlc/templates/header.h.j2
new file mode 100644
index 0000000..87707ce
--- /dev/null
+++ b/tools/tlc/tlc/templates/header.h.j2
@@ -0,0 +1,16 @@
+/*
+ * Auto-generated by TLC, this file includes declarations and macros
+ * derived from a Transfer List input.
+ */
+
+#ifndef {{ header_guard }}
+#define {{ header_guard }}
+
+{% if dtb_offset -%}
+#define TRANSFER_LIST_DTB_OFFSET {{ "0x%x" % dtb_offset }}
+{%- endif %}
+#define TRANSFER_LIST_CONVENTION_VERSION {{ version }}
+#define TRANSFER_LIST_HEADER_SIZE {{ "0x%x" % hdr_size }}
+#define TRANSFER_LIST_SIZE {{ "0x%x" % size }}
+
+#endif /* {{ header_guard }} */
diff --git a/tools/tlc/tlc/tl.py b/tools/tlc/tlc/tl.py
index 3f0065d..98d2205 100644
--- a/tools/tlc/tlc/tl.py
+++ b/tools/tlc/tlc/tl.py
@@ -8,7 +8,7 @@
"""Module containing definitions pertaining to the 'Transfer List' (TL) type."""
-import typing
+from typing import Any, Dict, List, Optional
import math
import struct
@@ -24,7 +24,7 @@
# used in struct.pack to encode the TE), and a list of field names that can
# appear in the yaml file for that TE. Some fields are missing, if that TE has
# to be processed differently, or if it can only be added with a blob file.
-transfer_entry_formats = {
+transfer_entry_formats: Dict[int, Any] = {
0: {
"tag_name": "empty",
"format": "4x",
@@ -93,7 +93,7 @@
self.size = self.hdr_size
self.total_size = max_size
self.flags = flags
- self.entries: typing.List["TransferEntry"] = []
+ self.entries: List[TransferEntry] = []
self.update_checksum()
def __str__(self) -> str:
@@ -152,7 +152,7 @@
return tl
@classmethod
- def from_dict(cls, config: dict):
+ def from_dict(cls, config: Dict[str, Any]) -> "TransferList":
"""Create a TL from data in a dictionary
The dictionary should have the same format as the yaml config files.
@@ -197,15 +197,23 @@
sum(self.header_to_bytes()) + sum(te.sum_of_bytes for te in self.entries)
) % 256
- def get_entry_data_offset(self, tag_id: int) -> int:
- """Returns offset of data of a TE from the base of the TL."""
+ def get_entry(self, tag_id: int) -> Optional[TransferEntry]:
for te in self.entries:
if te.id == tag_id:
- return te.offset + te.hdr_size
+ return te
- raise ValueError(f"Tag {tag_id} not found in TL!")
+ return None
- def add_transfer_entry(self, tag_id: int, data: bytes) -> "TransferEntry":
+ def get_entry_data_offset(self, tag_id: int) -> int:
+ """Returns offset of data of a TE from the base of the TL."""
+ te = self.get_entry(tag_id)
+
+ if not te:
+ raise ValueError(f"Tag {tag_id} not found in TL!")
+
+ return te.offset + te.hdr_size
+
+ def add_transfer_entry(self, tag_id: int, data: bytes) -> TransferEntry:
"""Appends a TransferEntry into the internal list of TE's."""
if not (self.total_size >= self.size + TransferEntry.hdr_size + len(data)):
raise MemoryError(
@@ -219,13 +227,15 @@
return te
def add_transfer_entry_from_struct_format(
- self, tag_id: int, struct_format: str, *args
- ):
+ self, tag_id: int, struct_format: str, *args: Any
+ ) -> TransferEntry:
struct_format = "<" + struct_format
data = struct.pack(struct_format, *args)
return self.add_transfer_entry(tag_id, data)
- def add_entry_point_info_transfer_entry(self, entry: dict) -> "TransferEntry":
+ def add_entry_point_info_transfer_entry(
+ self, entry: Dict[str, Any]
+ ) -> TransferEntry:
"""Add entry_point_info transfer entry
:param entry: Dictionary of the transfer entry, in the same format as
@@ -282,8 +292,8 @@
def add_transfer_entry_from_dict(
self,
- entry: dict,
- ) -> "TransferEntry":
+ entry: Dict[str, Any],
+ ) -> TransferEntry:
"""Add a transfer entry from data in a dictionary
The dictionary should have the same format as the entries in the yaml
@@ -318,7 +328,7 @@
else:
raise ValueError(f"Invalid transfer entry {entry}.")
- def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> "TransferEntry":
+ def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> TransferEntry:
with open(path, "rb") as f:
return self.add_transfer_entry(tag_id, f.read())
diff --git a/tools/tlc/tox.ini b/tools/tlc/tox.ini
new file mode 100644
index 0000000..4fd141f
--- /dev/null
+++ b/tools/tlc/tox.ini
@@ -0,0 +1,26 @@
+[tox]
+envlist = py38, py39, py310, py311, py312, lint
+
+[testenv]
+allowlist_externals = poetry
+commands =
+ poetry install -v --with dev
+ poetry run pytest
+
+[testenv:format]
+description = Run linters and type checks
+skip_install = true
+allowlist_externals = poetry
+commands =
+ poetry run black .
+ poetry run isort .
+
+[testenv:lint]
+description = Run linters and type checks
+skip_install = true
+allowlist_externals = poetry
+commands =
+ poetry run black --check .
+ poetry run isort --check-only .
+ poetry run mypy .
+ poetry run darglint tlc tests