fix(smccc): properly set RAS feature bit
The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be accessed independently of the rest of the system's RAS
implementation status, BL31's RAS handling capabilities, or the way RAS
errors are routed by the firmware (FFH vs. KFH handling).
Tie the SCR_EL3.TERR bit to the right build symbol, since TF-A's
capability to handle RAS errors has nothing to do with lower EL's
accesses to those CPU system registers.
Change-Id: I4f06f915c0815c80058ec365139a8d818ba85721
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
1 file changed