diff --git a/Makefile b/Makefile
index ac461a5..e455635 100644
--- a/Makefile
+++ b/Makefile
@@ -187,6 +187,34 @@
 endif
 endif
 
+# Memory tagging is supported in architecture Armv8.5-A AArch64 and onwards
+ifeq ($(ARCH), aarch64)
+ifeq ($(shell test $(ARM_ARCH_MAJOR) -gt 8; echo $$?),0)
+mem_tag_arch_support	= 	yes
+else ifeq ($(shell test $(ARM_ARCH_MAJOR) -eq 8 -a $(ARM_ARCH_MINOR) -ge 5; \
+	   echo $$?),0)
+mem_tag_arch_support	= 	yes
+endif
+endif
+
+# Enabled required option for memory stack tagging. Currently, these options are
+# enabled only for clang and armclang compiler.
+ifeq (${SUPPORT_STACK_MEMTAG},yes)
+ifdef mem_tag_arch_support
+ifneq ( ,$(filter $(notdir $(CC)),armclang clang))
+march64-directive       =       -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a+memtag
+ifeq ($(notdir $(CC)),armclang)
+TF_CFLAGS		+=	-mmemtag-stack
+else ifeq ($(notdir $(CC)),clang)
+TF_CFLAGS		+=	-fsanitize=memtag
+endif
+endif
+else
+$(error "Error: stack memory tagging is not supported for architecture \
+	${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
+endif
+endif
+
 ifneq ($(findstring armclang,$(notdir $(CC))),)
 TF_CFLAGS_aarch32	=	-target arm-arm-none-eabi $(march32-directive)
 TF_CFLAGS_aarch64	=	-target aarch64-arm-none-eabi $(march64-directive)
diff --git a/docs/change-log.rst b/docs/change-log.rst
index cf5b57a..7e072a9 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -17,6 +17,7 @@
 
    - Enable Memory Tagging Extension (MTE) support in both secure and non-secure
      worlds
+
        - Adds support for the new Memory Tagging Extension arriving in
          ARMv8.5. MTE support is now enabled by default on systems that
          support it at EL0.
@@ -84,6 +85,7 @@
 
    - gicv3: Enabled multi-socket GIC redistributor frame discovery and migrated
      ARM platforms to the new API
+
        - Adds ``gicv3_rdistif_probe`` function that delegates the responsibility
          of discovering the corresponding redistributor base frame to each CPU
          itself.
@@ -2841,7 +2843,7 @@
 
 --------------
 
-*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
 .. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
diff --git a/docs/components/fconf.rst b/docs/components/fconf.rst
index 3856600..7352ac3 100644
--- a/docs/components/fconf.rst
+++ b/docs/components/fconf.rst
@@ -107,6 +107,7 @@
 sub-namespaces. The following concepts should be considered when adding new
 properties/namespaces.
 The framework differentiates two types of properties:
+
  - Properties used inside common code.
  - Properties used inside platform specific code.
 
@@ -114,6 +115,7 @@
 across multiple platforms. They should be globally accessible and defined
 inside the ``lib/fconf`` directory. The namespace must be chosen to reflect the
 feature/data abstracted.
+
 Example:
  - |TBBR| related properties: tbbr.cot.bl2_id
  - Dynamic configuration information: dyn_cfg.dtb_info.hw_config_id
@@ -123,6 +125,7 @@
 within the platform API and are defined only inside the platform scope. The
 namespace must contain the platform name under which the properties defined
 belong.
+
 Example:
  - Arm io framework: arm.io_policies.bl31_id
 
diff --git a/docs/components/index.rst b/docs/components/index.rst
index ae78b2b..49986ca 100644
--- a/docs/components/index.rst
+++ b/docs/components/index.rst
@@ -17,4 +17,5 @@
    romlib-design
    sdei
    secure-partition-manager-design
+   spci-manifest-binding
    xlat-tables-lib-v2-design
diff --git a/docs/components/spci-manifest-binding.rst b/docs/components/spci-manifest-binding.rst
index 66cca64..5848169 100644
--- a/docs/components/spci-manifest-binding.rst
+++ b/docs/components/spci-manifest-binding.rst
@@ -16,6 +16,7 @@
      minor versions fo the device tree binding for the SPCI manifest represented
      by this node. The minor number is incremented if the binding changes in a
      backwards compatible manner.
+
       - X is an integer representing the major version number of this document.
       - Y is an integer representing the minor version number of this document.
 
@@ -23,6 +24,7 @@
    - value type: <u32>
    - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
      15:0 -> Y, where:
+
       - X is the major version of PSA-FF-A expected by the partition at the SPCI
         instance it will execute.
       - Y is the minor version of PSA-FF-A expected by the partition at the SPCI
@@ -34,10 +36,12 @@
      implemented by this partition. The UUID format is described in RFC 4122.
      UUID can be shared by multiple instances of partitions that offer the same
      service For example:
+
       - If there are multiple instances of a Trusted OS, then the UUID can be
         shared by all instances.
       - The TEE driver in the HLOS can use the UUID with the
         SPCI_PARTITION_INFO_GET interface to determine the:
+
          - Number of Trusted OSs
          - The partition ID of each instance of the Trusted OS
 
@@ -56,6 +60,7 @@
 - execution-ctx-count [mandatory]
    - value type: <u32>
    - Number of vCPUs that a VM or SP wants to instantiate.
+
       - In the absence of virtualization, this is the number of execution
         contexts that a partition implements.
       - If value of this field = 1 and number of PEs > 1 then the partition is
@@ -66,6 +71,7 @@
 - exception-level [mandatory]
    - value type: <u32>
    - The target exception level for the partition:
+
       - 0x0: EL1
       - 0x1: S_EL0
       - 0x2: S_EL1
@@ -76,6 +82,7 @@
 - execution-state [mandatory]
    - value type: <u32>
    - The target execution state of the partition:
+
       - 0: AArch64
       - 1: AArch32
 
@@ -94,6 +101,7 @@
 - xlat-granule [mandatory]
    - value type: <u32>
    - Translation granule used with the partition:
+
       - 0x0: 4k
       - 0x1: 16k
       - 0x2: 32k
@@ -113,6 +121,7 @@
 - messaging-method [mandatory]
    - value type: <u32>
    - Specifies which messaging methods are supported by the partition:
+
       - 0x0: direct messaging method
       - 0x1: indirect messaging method
       - 0x2: both direct and indirect messaging methods
@@ -125,6 +134,7 @@
 - run-time-model
    - value type: <u32>
    - Run time model that the SPM must enforce for this SP:
+
       - 0x0: Run to completion
       - 0x1: Preemptible
 
@@ -195,6 +205,7 @@
 - reg [mandatory]
    - value type: <prop-encoded-array>
    - A (address, num-pages) pair describing the device, where:
+
       - address: The physical base address <u64> value of the device MMIO
         region.
       - num-pages: The <u32> number of pages of the region. The total size of
@@ -214,15 +225,18 @@
 - stream-ids [mandatory]
    - value type: <prop-encoded-array>
    - A list of (id, mem-manage) pair, where:
+
       - id: A unique <u32> value amongst all devices assigned to the partition.
       - mem-manage: A <u32> value used in memory management operations.
 
 - interrupts [mandatory]
    - value type: <prop-encoded-array>
    - A list of (id, attributes) pair describing the device interrupts, where:
+
       - id: The <u32> interrupt IDs.
       - attributes: A ?? TO DEFINE value,
         containing the attributes for each interrupt ID:
+
          - Interrupt type: SPI, PPI, SGI
          - Interrupt configuration: Edge triggered, Level triggered
          - Interrupt security state: Secure, Non-secure
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 69e103d..e1c6c8f 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -667,6 +667,11 @@
    cluster platforms). If this option is enabled, then warm boot path
    enables D-caches immediately after enabling MMU. This option defaults to 0.
 
+-  ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
+   tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
+   default value of this flag is ``no``. Note this option must be enabled only
+   for ARM architecture greater than Armv8.5-A.
+
 GICv3 driver options
 --------------------
 
diff --git a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
index c36e544..e613eef 100644
--- a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
+++ b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
@@ -24,9 +24,9 @@
 activate fconf
 	note over fconf
 		create and populate an
-		image_desc_t for TB_FW_CONFIG
+		image_desc_t for FW_CONFIG
 	end note
-	fconf -> bl_common : load_auth_image(TB_FW_CONFIG_ID, &image_info)
+	fconf -> bl_common : load_auth_image(FW_CONFIG_ID, &image_info)
 	activate bl_common
 	note over bl_common
 		load and auth image from fip
@@ -42,7 +42,7 @@
 	fconf <- plat_bl1_common : BL2_IMAGE_DESC
 	note over fconf
 		set ep_info.args.arg0 of BL2_IMAGE_DESC
-		to TB_FW_CONFIG base address
+		to FW_CONFIG base address
 	end note
 arm_bl1_setup <- fconf
 deactivate fconf
diff --git a/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml b/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml
index 98a3ff1..881f253 100644
--- a/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml
+++ b/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml
@@ -20,12 +20,12 @@
 bl2_entrypoint -> bl2_main : bl2_setup()
 bl2_main -> arm_bl2_setup : bl2_early_platform_setup2(\n\t arg0, arg1, arg2, arg3)
 note over arm_bl2_setup
-	arg0 = tb_fw_config
+	arg0 = fw_config
 	arg1 = mem_layout
 end note
-arm_bl2_setup -> arm_bl2_setup : arm_bl2_early_platform_setup(\n\t tb_fw_config, mem_layout)
+arm_bl2_setup -> arm_bl2_setup : arm_bl2_early_platform_setup(\n\t fw_config, mem_layout)
 activate arm_bl2_setup
-	arm_bl2_setup -> fconf: fconf_polulate(tb_fw_config)
+	arm_bl2_setup -> fconf: fconf_polulate("TB_FW", fw_config)
 	activate fconf
 		fconf -> fconf_tbbr_getter: fconf_populate_tbbr_dyn_config(uintptr_t dtb)
 		note over fconf_tbbr_getter: read tbbr propeties from dtb
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 4e968e2..590a800 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -288,3 +288,8 @@
 # S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
 # Default is 0.
 CTX_INCLUDE_EL2_REGS		:= 0
+
+# Enable Memory tag extension which is supported for architecture greater
+# than Armv8.5-A
+# By default it is set to "no"
+SUPPORT_STACK_MEMTAG		:= no
diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/common/aarch64/plat_helpers.S
similarity index 74%
rename from plat/rpi/rpi4/aarch64/plat_helpers.S
rename to plat/rpi/common/aarch64/plat_helpers.S
index fac1b20..e21233a 100644
--- a/plat/rpi/rpi4/aarch64/plat_helpers.S
+++ b/plat/rpi/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,6 +20,7 @@
 	.globl	plat_reset_handler
 	.globl	plat_rpi3_calc_core_pos
 	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_rpi_get_model
 
 	/* -----------------------------------------------------
 	 *  unsigned int plat_my_core_pos(void)
@@ -56,27 +57,29 @@
 func plat_is_my_cpu_primary
 	mrs	x0, mpidr_el1
 	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #RPI4_PRIMARY_CPU
+	cmp	x0, #RPI_PRIMARY_CPU
 	cset	w0, eq
 	ret
 endfunc plat_is_my_cpu_primary
 
 	/* -----------------------------------------------------
-	 * void plat_secondary_cold_boot_setup (void);
+	 * void plat_wait_for_warm_boot (void);
 	 *
 	 * This function performs any platform specific actions
-	 * needed for a secondary cpu after a cold reset e.g
-	 * mark the cpu's presence, mechanism to place it in a
-	 * holding pen etc.
+	 * needed for a CPU to be put into holding pen to wait
+	 * for a warm boot request.
+	 * The function will never return.
 	 * -----------------------------------------------------
 	 */
-func plat_secondary_cold_boot_setup
-	/* Calculate address of our hold entry */
+func plat_wait_for_warm_boot
+	/*
+	 * Calculate address of our hold entry.
+	 * As the function will never return, there is no need to save LR.
+	 */
 	bl	plat_my_core_pos
 	lsl	x0, x0, #3
 	mov_imm	x2, PLAT_RPI3_TM_HOLD_BASE
 	add	x0, x0, x2
-
 	/*
 	 * This code runs way before requesting the warmboot of this core,
 	 * so it is possible to clear the mailbox before getting a request
@@ -96,6 +99,19 @@
 	mov_imm	x0, PLAT_RPI3_TM_ENTRYPOINT
 	ldr	x1, [x0]
 	br	x1
+endfunc plat_wait_for_warm_boot
+
+	/* -----------------------------------------------------
+	 * void plat_secondary_cold_boot_setup (void);
+	 *
+	 * This function performs any platform specific actions
+	 * needed for a secondary cpu after a cold reset e.g
+	 * mark the cpu's presence, mechanism to place it in a
+	 * holding pen etc.
+	 * -----------------------------------------------------
+	 */
+func plat_secondary_cold_boot_setup
+	b	plat_wait_for_warm_boot
 endfunc plat_secondary_cold_boot_setup
 
 	/* ---------------------------------------------------------------------
@@ -110,9 +126,24 @@
 	 * ---------------------------------------------------------------------
 	 */
 func plat_get_my_entrypoint
-	/* TODO: support warm boot */
-	mov	x0, #0
-	ret
+	mov	x1, x30
+	bl	plat_is_my_cpu_primary
+	/*
+	 * Secondaries always cold boot.
+	*/
+	cbz	w0, 1f
+	/*
+	 * Primaries warm boot if they are requested
+	 * to power off.
+	 */
+	mov_imm	x0, PLAT_RPI3_TM_HOLD_BASE
+	ldr	x0, [x0]
+	cmp	x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF
+	adr	x0, plat_wait_for_warm_boot
+	csel	x0, x0, xzr, eq
+	ret	x1
+1:	mov	x0, #0
+	ret	x1
 endfunc plat_get_my_entrypoint
 
 	/* ---------------------------------------------
@@ -165,10 +196,37 @@
 endfunc plat_crash_console_flush
 
 	/* ---------------------------------------------
+	 * int plat_rpi_get_model()
+	 * Macro to determine whether we are running on
+	 * a Raspberry Pi 3 or 4. Just checks the MIDR for
+	 * being either a Cortex-A72 or a Cortex-A53.
+	 * Out : return 4 if RPi4, 3 otherwise.
+	 * Clobber list : x0
+	 * ---------------------------------------------
+	 */
+	.macro _plat_rpi_get_model
+	mrs	x0, midr_el1
+	and	x0, x0, #0xf0	/* Isolate low byte of part number */
+	cmp	w0, #0x80	/* Cortex-A72 (RPi4) is 0xd08, A53 is 0xd03 */
+	mov	w0, #3
+	csinc	w0, w0, w0, ne
+	.endm
+
+	func plat_rpi_get_model
+	_plat_rpi_get_model
+	ret
+	endfunc plat_rpi_get_model
+
+	/* ---------------------------------------------
 	 * void plat_reset_handler(void);
 	 * ---------------------------------------------
 	 */
 func plat_reset_handler
+	/* L2 cache setup only needed on RPi4 */
+	_plat_rpi_get_model
+	cmp	w0, #4
+	b.ne	1f
+
 	/* ------------------------------------------------
 	 * Set L2 read/write cache latency:
 	 * - L2 Data RAM latency: 3 cycles (0b010)
@@ -181,5 +239,6 @@
 	msr	CORTEX_A72_L2CTLR_EL1, x0
 	isb
 
+1:
 	ret
 endfunc plat_reset_handler
diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h
index 6863438..ddf239e 100644
--- a/plat/rpi/common/include/rpi_shared.h
+++ b/plat/rpi/common/include/rpi_shared.h
@@ -36,4 +36,6 @@
 /* VideoCore firmware commands */
 int rpi3_vc_hardware_get_board_revision(uint32_t *revision);
 
+int plat_rpi_get_model(void);
+
 #endif /* RPI3_PRIVATE_H */
diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c
index 2a6bf07..86c61f7 100644
--- a/plat/rpi/common/rpi3_pm.c
+++ b/plat/rpi/common/rpi3_pm.c
@@ -140,11 +140,14 @@
 {
 	int rc = PSCI_E_SUCCESS;
 	unsigned int pos = plat_core_pos_by_mpidr(mpidr);
-	uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
+	uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
 
 	assert(pos < PLATFORM_CORE_COUNT);
 
-	hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO;
+	hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE;
+
+	mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO);
+	/* No cache maintenance here, hold_base is mapped as device memory. */
 
 	/* Make sure that the write has completed */
 	dsb();
@@ -171,6 +174,32 @@
 #endif
 }
 
+static void __dead2 rpi3_pwr_down_wfi(
+		const psci_power_state_t *target_state)
+{
+	uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
+	unsigned int pos = plat_my_core_pos();
+
+	if (pos == 0) {
+		/*
+		 * The secondaries will always be in a wait
+		 * for warm boot on reset, but the BSP needs
+		 * to be able to distinguish between waiting
+		 * for warm boot (e.g. after psci_off, waiting
+		 * for psci_on) and a cold boot.
+		 */
+		mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF);
+		/* No cache maintenance here, we run with caches off already. */
+		dsb();
+		isb();
+	}
+
+	write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
+
+	while (1)
+		;
+}
+
 /*******************************************************************************
  * Platform handlers for system reset and system off.
  ******************************************************************************/
@@ -236,6 +265,7 @@
 	.pwr_domain_pwr_down_wfi = rpi3_pwr_domain_pwr_down_wfi,
 	.pwr_domain_on = rpi3_pwr_domain_on,
 	.pwr_domain_on_finish = rpi3_pwr_domain_on_finish,
+	.pwr_domain_pwr_down_wfi = rpi3_pwr_down_wfi,
 	.system_off = rpi3_system_off,
 	.system_reset = rpi3_system_reset,
 	.validate_power_state = rpi3_validate_power_state,
diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S
deleted file mode 100644
index ab925b6..0000000
--- a/plat/rpi/rpi3/aarch64/plat_helpers.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <platform_def.h>
-
-	.globl	plat_crash_console_flush
-	.globl	plat_crash_console_init
-	.globl	plat_crash_console_putc
-	.globl	platform_mem_init
-	.globl	plat_get_my_entrypoint
-	.globl	plat_is_my_cpu_primary
-	.globl	plat_my_core_pos
-	.globl	plat_rpi3_calc_core_pos
-	.globl	plat_secondary_cold_boot_setup
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_my_core_pos(void)
-	 *
-	 *  This function uses the plat_rpi3_calc_core_pos()
-	 *  definition to get the index of the calling CPU.
-	 * -----------------------------------------------------
-	 */
-func plat_my_core_pos
-	mrs	x0, mpidr_el1
-	b	plat_rpi3_calc_core_pos
-endfunc plat_my_core_pos
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
-	 *
-	 *  CorePos = (ClusterId * 4) + CoreId
-	 * -----------------------------------------------------
-	 */
-func plat_rpi3_calc_core_pos
-	and	x1, x0, #MPIDR_CPU_MASK
-	and	x0, x0, #MPIDR_CLUSTER_MASK
-	add	x0, x1, x0, LSR #6
-	ret
-endfunc plat_rpi3_calc_core_pos
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_is_my_cpu_primary (void);
-	 *
-	 * Find out whether the current cpu is the primary
-	 * cpu.
-	 * -----------------------------------------------------
-	 */
-func plat_is_my_cpu_primary
-	mrs	x0, mpidr_el1
-	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-	cmp	x0, #RPI3_PRIMARY_CPU
-	cset	w0, eq
-	ret
-endfunc plat_is_my_cpu_primary
-
-	/* -----------------------------------------------------
-	 * void plat_secondary_cold_boot_setup (void);
-	 *
-	 * This function performs any platform specific actions
-	 * needed for a secondary cpu after a cold reset e.g
-	 * mark the cpu's presence, mechanism to place it in a
-	 * holding pen etc.
-	 * -----------------------------------------------------
-	 */
-func plat_secondary_cold_boot_setup
-	/* Calculate address of our hold entry */
-	bl	plat_my_core_pos
-	lsl	x0, x0, #3
-	mov_imm	x2, PLAT_RPI3_TM_HOLD_BASE
-	add	x0, x0, x2
-
-	/*
-	 * This code runs way before requesting the warmboot of this core,
-	 * so it is possible to clear the mailbox before getting a request
-	 * to boot.
-	 */
-	mov	x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
-	str	x1,[x0]
-
-	/* Wait until we have a go */
-poll_mailbox:
-	wfe
-	ldr	x1, [x0]
-	cmp	x1, PLAT_RPI3_TM_HOLD_STATE_GO
-	bne	poll_mailbox
-
-	/* Jump to the provided entrypoint */
-	mov_imm	x0, PLAT_RPI3_TM_ENTRYPOINT
-	ldr	x1, [x0]
-	br	x1
-endfunc plat_secondary_cold_boot_setup
-
-	/* ---------------------------------------------------------------------
-	 * uintptr_t plat_get_my_entrypoint (void);
-	 *
-	 * Main job of this routine is to distinguish between a cold and a warm
-	 * boot.
-	 *
-	 * This functions returns:
-	 *  - 0 for a cold boot.
-	 *  - Any other value for a warm boot.
-	 * ---------------------------------------------------------------------
-	 */
-func plat_get_my_entrypoint
-	/* TODO: support warm boot */
-	mov	x0, #0
-	ret
-endfunc plat_get_my_entrypoint
-
-	/* ---------------------------------------------
-	 * void platform_mem_init (void);
-	 *
-	 * No need to carry out any memory initialization.
-	 * ---------------------------------------------
-	 */
-func platform_mem_init
-	ret
-endfunc platform_mem_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Function to initialize the crash console
-	 * without a C Runtime to print crash report.
-	 * Clobber list : x0 - x3
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_init
-	mov_imm	x0, PLAT_RPI_MINI_UART_BASE
-	mov	x1, xzr
-	mov	x2, xzr
-	b	console_16550_core_init
-endfunc plat_crash_console_init
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_putc(int c)
-	 * Function to print a character on the crash
-	 * console without a C Runtime.
-	 * Clobber list : x1, x2
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_putc
-	mov_imm	x1, PLAT_RPI_MINI_UART_BASE
-	b	console_16550_core_putc
-endfunc plat_crash_console_putc
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_flush()
-	 * Function to force a write of all buffered
-	 * data that hasn't been output.
-	 * Out : return -1 on error else return 0.
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func plat_crash_console_flush
-	mov_imm	x0, PLAT_RPI_MINI_UART_BASE
-	b	console_16550_core_flush
-endfunc plat_crash_console_flush
diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h
index 9cacd99..f44d1f5 100644
--- a/plat/rpi/rpi3/include/platform_def.h
+++ b/plat/rpi/rpi3/include/platform_def.h
@@ -24,7 +24,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define RPI3_PRIMARY_CPU		U(0)
+#define RPI_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
@@ -153,6 +153,7 @@
 
 #define PLAT_RPI3_TM_HOLD_STATE_WAIT	ULL(0)
 #define PLAT_RPI3_TM_HOLD_STATE_GO	ULL(1)
+#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF	ULL(2)
 
 /*
  * BL1 specific defines.
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index a5b8904..bcfc34e 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -15,6 +15,7 @@
 				drivers/gpio/gpio.c			\
 				drivers/delay_timer/delay_timer.c	\
 				drivers/rpi3/gpio/rpi3_gpio.c		\
+				plat/rpi/common/aarch64/plat_helpers.S	\
 				plat/rpi/common/rpi3_common.c		\
 				${XLAT_TABLES_LIB_SRCS}
 
@@ -23,7 +24,6 @@
 				drivers/io/io_storage.c			\
 				lib/cpus/aarch64/cortex_a53.S		\
 				plat/common/aarch64/platform_mp_stack.S	\
-				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/rpi3_bl1_setup.c		\
 				plat/rpi/common/rpi3_io_storage.c	\
 				drivers/rpi3/mailbox/rpi3_mbox.c	\
@@ -38,7 +38,6 @@
 				drivers/mmc/mmc.c			\
 				drivers/rpi3/sdhost/rpi3_sdhost.c	\
 				plat/common/aarch64/platform_mp_stack.S	\
-				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \
 				plat/rpi/rpi3/rpi3_bl2_setup.c		\
 				plat/rpi/common/rpi3_image_load.c	\
@@ -46,7 +45,6 @@
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
 				plat/common/plat_psci_common.c		\
-				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/rpi3_bl31_setup.c		\
 				plat/rpi/common/rpi3_pm.c		\
 				plat/rpi/common/rpi3_topology.c		\
diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h
index 6f6bbbe..6787ebf 100644
--- a/plat/rpi/rpi4/include/platform_def.h
+++ b/plat/rpi/rpi4/include/platform_def.h
@@ -24,7 +24,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define RPI4_PRIMARY_CPU		U(0)
+#define RPI_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
@@ -93,6 +93,7 @@
 
 #define PLAT_RPI3_TM_HOLD_STATE_WAIT	ULL(0)
 #define PLAT_RPI3_TM_HOLD_STATE_GO	ULL(1)
+#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF	ULL(2)
 
 /*
  * BL31 specific defines.
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index 49e78df..0744bce 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -16,7 +16,7 @@
 				${XLAT_TABLES_LIB_SRCS}
 
 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		\
-				plat/rpi/rpi4/aarch64/plat_helpers.S	\
+				plat/rpi/common/aarch64/plat_helpers.S	\
 				plat/rpi/rpi4/aarch64/armstub8_header.S	\
 				drivers/arm/gic/common/gic_common.c     \
 				drivers/arm/gic/v2/gicv2_helpers.c      \
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 0fcef1d..3f8a1f8 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -14,6 +14,13 @@
 # UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses.
 override ENABLE_PIE			:= 1
 
+ALLOW_RO_XLAT_TABLES			:= 1
+
+ifeq ($(ALLOW_RO_XLAT_TABLES),1)
+BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+endif
+
 # Cortex-A53 revision r0p4-51rel0
 # needed for LD20, unneeded for LD11, PXs3 (no ACE)
 ERRATA_A53_855873		:= 1
diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
index 091a6f7..4bbb259 100644
--- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
+++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
@@ -9,7 +9,6 @@
 #include <platform_def.h>
 
 #include <common/bl_common.h>
-#include <lib/xlat_tables/xlat_mmu_helpers.h>
 #include <plat/common/platform.h>
 
 #include "../uniphier.h"
@@ -32,5 +31,4 @@
 void tsp_plat_arch_setup(void)
 {
 	uniphier_mmap_setup(uniphier_soc);
-	enable_mmu_el1(0);
 }
diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c
index 7a7f786..679f14d 100644
--- a/plat/socionext/uniphier/uniphier_bl2_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl2_setup.c
@@ -44,7 +44,6 @@
 	int ret;
 
 	uniphier_mmap_setup(uniphier_soc);
-	enable_mmu_el3(0);
 
 	/* add relocation offset (run-time-address - link-address) */
 	uniphier_mem_base += BL_CODE_BASE - BL2_BASE;
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index f2f0b29..c2baebd 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -14,7 +14,6 @@
 #include <common/debug.h>
 #include <drivers/console.h>
 #include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_mmu_helpers.h>
 #include <plat/common/platform.h>
 
 #include "uniphier.h"
@@ -87,5 +86,4 @@
 void bl31_plat_arch_setup(void)
 {
 	uniphier_mmap_setup(uniphier_soc);
-	enable_mmu_el3(0);
 }
diff --git a/plat/socionext/uniphier/uniphier_xlat_setup.c b/plat/socionext/uniphier/uniphier_xlat_setup.c
index 66c7834..5043f4b 100644
--- a/plat/socionext/uniphier/uniphier_xlat_setup.c
+++ b/plat/socionext/uniphier/uniphier_xlat_setup.c
@@ -10,6 +10,7 @@
 
 #include <common/debug.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
 
 #include "uniphier.h"
 
@@ -63,4 +64,18 @@
 			MT_DEVICE | MT_RW | MT_SECURE);
 
 	init_xlat_tables();
+
+	enable_mmu(0);
+
+#if PLAT_RO_XLAT_TABLES
+	{
+		int ret;
+
+		ret = xlat_make_tables_readonly();
+		if (ret) {
+			ERROR("Failed to make translation tables read-only.");
+			plat_error_handler(ret);
+		}
+	}
+#endif
 }