Merge pull request #1626 from Yann-lms/partition_verbose
drivers: partition: correct compilation error in VERBOSE mode
diff --git a/Makefile b/Makefile
index 0d62dd7..8cba50c 100644
--- a/Makefile
+++ b/Makefile
@@ -74,11 +74,19 @@
# Verbose flag
ifeq (${V},0)
Q:=@
+ ECHO:=@echo
CHECKCODE_ARGS += --no-summary --terse
else
Q:=
+ ECHO:=@\#
endif
-export Q
+
+ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),)
+ Q:=@
+ ECHO:=@\#
+endif
+
+export Q ECHO
# Process Debug flag
$(eval $(call add_define,DEBUG))
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S
index b7892e1..841ea44 100644
--- a/drivers/arm/pl011/aarch32/pl011_console.S
+++ b/drivers/arm/pl011/aarch32/pl011_console.S
@@ -89,8 +89,9 @@
.globl console_pl011_register
/* -------------------------------------------------------
- * init console_pl011_register(console_pl011_t *console,
- * uintptr_t base, uint32_t clk, uint32_t baud)
+ * int console_pl011_register(uintptr_t baseaddr,
+ * uint32_t clock, uint32_t baud,
+ * console_pl011_t *console);
* Function to initialize and register a new PL011
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S
index 448501a..d6a2d6b 100644
--- a/drivers/arm/pl011/aarch64/pl011_console.S
+++ b/drivers/arm/pl011/aarch64/pl011_console.S
@@ -85,8 +85,9 @@
.globl console_pl011_register
/* -----------------------------------------------
- * int console_pl011_register(console_pl011_t *console,
- uintptr_t base, uint32_t clk, uint32_t baud)
+ * int console_pl011_register(uintptr_t baseaddr,
+ * uint32_t clock, uint32_t baud,
+ * console_pl011_t *console);
* Function to initialize and register a new PL011
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index 6732631..71359a6 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -54,8 +54,9 @@
.globl console_cdns_register
/* -----------------------------------------------
- * int console_cdns_register(console_cdns_t *console,
- uintptr_t base, uint32_t clk, uint32_t baud)
+ * int console_cdns_register(uint64_t baseaddr,
+ * uint32_t clock, uint32_t baud,
+ * console_cdns_t *console);
* Function to initialize and register a new CDNS
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
diff --git a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S
index 2fc0603..184853d 100644
--- a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S
+++ b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S
@@ -19,8 +19,8 @@
.globl console_cbmc_flush
/* -----------------------------------------------
- * int console_cbmc_register(console_cbmc_t *console,
- * uintptr_t base)
+ * int console_cbmc_register(uintptr_t base,
+ * console_cbmc_t *console);
* Registers a new CBMEM console instance. Reads
* the size field from the buffer header structure
* and stores it in our console_cbmc_t struct, so
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index ea96833..1f9550e 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -160,7 +160,7 @@
mixctl |= MIXCTRL_DMAEN;
}
- if (cmd->resp_type & MMC_RSP_48)
+ if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
xfertype |= XFERTYPE_RSPTYP_48;
else if (cmd->resp_type & MMC_RSP_136)
xfertype |= XFERTYPE_RSPTYP_136;
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S
index d46fa61..0f9a9d5 100644
--- a/drivers/ti/uart/aarch64/16550_console.S
+++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -87,8 +87,9 @@
.globl console_16550_register
/* -----------------------------------------------
- * int console_16550_register(console_16550_t *console,
- uintptr_t base, uint32_t clk, uint32_t baud)
+ * int console_16550_register(uintptr_t baseaddr,
+ * uint32_t clock, uint32_t baud,
+ * console_16550_t *console);
* Function to initialize and register a new 16550
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
diff --git a/include/common/interrupt_props.h b/include/common/interrupt_props.h
index 9786b40..4ac698d 100644
--- a/include/common/interrupt_props.h
+++ b/include/common/interrupt_props.h
@@ -12,10 +12,10 @@
/* Create an interrupt property descriptor from various interrupt properties */
#define INTR_PROP_DESC(num, pri, grp, cfg) \
{ \
- .intr_num = num, \
- .intr_pri = pri, \
- .intr_grp = grp, \
- .intr_cfg = cfg, \
+ .intr_num = (num), \
+ .intr_pri = (pri), \
+ .intr_grp = (grp), \
+ .intr_cfg = (cfg), \
}
typedef struct interrupt_prop {
diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h
index 9411b73..bb64b00 100644
--- a/include/drivers/arm/tzc_common.h
+++ b/include/drivers/arm/tzc_common.h
@@ -46,10 +46,10 @@
/* Macros for allowing Non-Secure access to a region based on NSAID */
#define TZC_REGION_ACCESS_RD(nsaid) \
- ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
+ ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
TZC_REGION_ACCESS_RD_EN_SHIFT)
#define TZC_REGION_ACCESS_WR(nsaid) \
- ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
+ ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
TZC_REGION_ACCESS_WR_EN_SHIFT)
#define TZC_REGION_ACCESS_RDWR(nsaid) \
(TZC_REGION_ACCESS_RD(nsaid) | \
diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h
new file mode 100644
index 0000000..7d40b41
--- /dev/null
+++ b/include/lib/object_pool.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef OBJECT_POOL_H
+#define OBJECT_POOL_H
+
+#include <debug.h>
+#include <stdlib.h>
+#include <utils_def.h>
+
+/*
+ * Pool of statically allocated objects.
+ *
+ * Objects can be reserved but not freed. This is by design and it is not a
+ * limitation. We do not want to introduce complexity induced by memory freeing,
+ * such as use-after-free bugs, memory fragmentation and so on.
+ *
+ * The object size and capacity of the pool are fixed at build time. So is the
+ * address of the objects back store.
+ */
+struct object_pool {
+ /* Size of 1 object in the pool in byte unit. */
+ const size_t obj_size;
+
+ /* Number of objects in the pool. */
+ const size_t capacity;
+
+ /* Objects back store. */
+ void *const objects;
+
+ /* How many objects are currently allocated. */
+ size_t used;
+};
+
+/* Create a static pool of objects. */
+#define OBJECT_POOL(_pool_name, _obj_backstore, _obj_size, _obj_count) \
+ struct object_pool _pool_name = { \
+ .objects = (_obj_backstore), \
+ .obj_size = (_obj_size), \
+ .capacity = (_obj_count), \
+ .used = 0U, \
+ }
+
+/* Create a static pool of objects out of an array of pre-allocated objects. */
+#define OBJECT_POOL_ARRAY(_pool_name, _obj_array) \
+ OBJECT_POOL(_pool_name, (_obj_array), \
+ sizeof((_obj_array)[0]), ARRAY_SIZE(_obj_array))
+
+/*
+ * Allocate 'count' objects from a pool.
+ * Return the address of the first object. Panic on error.
+ */
+static inline void *pool_alloc_n(struct object_pool *pool, size_t count)
+{
+ if (pool->used + count > pool->capacity) {
+ ERROR("Cannot allocate %zu objects out of pool (%zu objects left).\n",
+ count, pool->capacity - pool->used);
+ panic();
+ }
+
+ void *obj = (char *)(pool->objects) + pool->obj_size * pool->used;
+ pool->used += count;
+ return obj;
+}
+
+/*
+ * Allocate 1 object from a pool.
+ * Return the address of the object. Panic on error.
+ */
+static inline void *pool_alloc(struct object_pool *pool)
+{
+ return pool_alloc_n(pool, 1U);
+}
+
+#endif /* OBJECT_POOL_H */
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index adce843..97aeb83 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -267,7 +267,7 @@
static plat_local_state_t get_non_cpu_pd_node_local_state(
unsigned int parent_idx)
{
-#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY)
+#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
flush_dcache_range(
(uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
sizeof(psci_non_cpu_pd_nodes[parent_idx]));
@@ -283,7 +283,7 @@
plat_local_state_t state)
{
psci_non_cpu_pd_nodes[parent_idx].local_state = state;
-#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY)
+#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
flush_dcache_range(
(uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
sizeof(psci_non_cpu_pd_nodes[parent_idx]));
@@ -948,21 +948,18 @@
/*
* With hardware-assisted coherency, the CPU drivers only initiate the
* power down sequence, without performing cache-maintenance operations
- * in software. Data caches and MMU remain enabled both before and after
- * this call.
+ * in software. Data caches enabled both before and after this call.
*/
prepare_cpu_pwr_dwn(power_level);
#else
/*
* Without hardware-assisted coherency, the CPU drivers disable data
- * caches and MMU, then perform cache-maintenance operations in
- * software.
+ * caches, then perform cache-maintenance operations in software.
*
- * We ought to call prepare_cpu_pwr_dwn() to initiate power down
- * sequence. We currently have data caches and MMU enabled, but the
- * function will return with data caches and MMU disabled. We must
- * ensure that the stack memory is flushed out to memory before we start
- * popping from it again.
+ * This also calls prepare_cpu_pwr_dwn() to initiate power down
+ * sequence, but that function will return with data caches disabled.
+ * We must ensure that the stack memory is flushed out to memory before
+ * we start popping from it again.
*/
psci_do_pwrdown_cache_maintenance(power_level);
#endif
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 28ce2a4..e186fc1 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -177,7 +177,7 @@
# GZIP
define GZIP_RULE
$(1): $(2)
- @echo " GZIP $$@"
+ $(ECHO) " GZIP $$@"
$(Q)gzip -n -f -9 $$< --stdout > $$@
endef
@@ -199,7 +199,7 @@
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs
- @echo " CC $$<"
+ $$(ECHO) " CC $$<"
$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -218,7 +218,7 @@
$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
- @echo " CC $$<"
+ $$(ECHO) " CC $$<"
$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -237,7 +237,7 @@
$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
- @echo " AS $$<"
+ $$(ECHO) " AS $$<"
$$(Q)$$(AS) $$(ASFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -255,7 +255,7 @@
$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
- @echo " PP $$<"
+ $$(ECHO) " PP $$<"
$$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$<
-include $(DEP)
@@ -344,7 +344,7 @@
all: ${LIB_DIR}/lib$(1).a
${LIB_DIR}/lib$(1).a: $(OBJS)
- @echo " AR $$@"
+ $$(ECHO) " AR $$@"
$$(Q)$$(AR) cr $$@ $$?
endef
@@ -392,7 +392,7 @@
endif
$(ELF): $(OBJS) $(LINKERFILE) | bl$(1)_dirs libraries $(BL_LIBS)
- @echo " LD $$@"
+ $$(ECHO) " LD $$@"
ifdef MAKE_BUILD_STRINGS
$(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o)
else
@@ -405,11 +405,11 @@
$(OBJS) $(LDPATHS) $(LDLIBS) $(BL_LIBS)
$(DUMP): $(ELF)
- @echo " OD $$@"
+ $${ECHO} " OD $$@"
$${Q}$${OD} -dx $$< > $$@
$(BIN): $(ELF)
- @echo " BIN $$@"
+ $${ECHO} " BIN $$@"
$$(Q)$$(OC) -O binary $$< $$@
@${ECHO_BLANK_LINE}
@echo "Built $$@ successfully"
@@ -461,10 +461,10 @@
$(eval DTBDEP := $(patsubst %.dtb,%.d,$(DOBJ)))
$(DOBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs
- @echo " CPP $$<"
+ $${ECHO} " CPP $$<"
$(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
$$(Q)$$(CPP) $$(CPPFLAGS) -x assembler-with-cpp -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$<
- @echo " DTC $$<"
+ $${ECHO} " DTC $$<"
$$(Q)$$(DTC) $$(DTC_FLAGS) -i fdts -d $(DTBDEP) -o $$@ $(DPRE)
-include $(DTBDEP)
diff --git a/plat/arm/board/fvp/fvp_security.c b/plat/arm/board/fvp/fvp_security.c
index a6c9227..028522c 100644
--- a/plat/arm/board/fvp/fvp_security.c
+++ b/plat/arm/board/fvp/fvp_security.c
@@ -21,6 +21,6 @@
* configurations, those would be configured here.
*/
- if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC)
+ if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
arm_tzc400_setup(NULL);
}
diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
index a1e3f7f..e21b9d2 100644
--- a/plat/arm/board/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -16,7 +16,8 @@
static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
-CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count);
+CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)),
+ assert_invalid_fvp_cluster_count);
/*******************************************************************************
* This function dynamically constructs the topology according to
@@ -24,7 +25,7 @@
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
- unsigned int i;
+ int i;
/*
* The highest level is the system level. The next level is constituted
@@ -60,7 +61,7 @@
unsigned int clus_id, cpu_id, thread_id;
/* Validate affinity fields */
- if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) {
+ if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) {
thread_id = MPIDR_AFFLVL0_VAL(mpidr);
cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
clus_id = MPIDR_AFFLVL2_VAL(mpidr);
@@ -90,5 +91,5 @@
* bit set.
*/
mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
- return plat_arm_calc_core_pos(mpidr);
+ return (int) plat_arm_calc_core_pos(mpidr);
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index e4df227..8f1a0cd 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -52,7 +52,7 @@
#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
/* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* No SCP in FVP */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0)
@@ -215,9 +215,9 @@
*/
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
- INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_LEVEL), \
- INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index d130beb..ed78b46 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -60,7 +60,7 @@
#define NSRAM_SIZE 0x00008000 /* 32KB */
/* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/*
* Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
@@ -236,21 +236,21 @@
CSS_G1S_IRQ_PROPS(grp), \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL), \
+ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_LEVEL)
+ (grp), GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
diff --git a/plat/arm/board/juno/juno_topology.c b/plat/arm/board/juno/juno_topology.c
index 5f031c8..72bb92e 100644
--- a/plat/arm/board/juno/juno_topology.c
+++ b/plat/arm/board/juno/juno_topology.c
@@ -50,8 +50,8 @@
******************************************************************************/
unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
{
- return (((mpidr) & 0x100) ? JUNO_CLUSTER1_CORE_COUNT :\
- JUNO_CLUSTER0_CORE_COUNT);
+ return (((mpidr & (u_register_t) 0x100) != 0U) ?
+ JUNO_CLUSTER1_CORE_COUNT : JUNO_CLUSTER0_CORE_COUNT);
}
/*
diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c
index 07766a0..2a46b95 100644
--- a/plat/arm/common/arm_nor_psci_mem_protect.c
+++ b/plat/arm/common/arm_nor_psci_mem_protect.c
@@ -50,14 +50,14 @@
******************************************************************************/
int arm_nor_psci_write_mem_protect(int val)
{
- int enable = (val != 0) ? 1 : 0;
+ unsigned long enable = (val != 0) ? 1UL : 0UL;
if (nor_unlock(PLAT_ARM_MEM_PROT_ADDR) != 0) {
ERROR("unlocking memory protect variable\n");
return -1;
}
- if (enable == 1) {
+ if (enable == 1UL) {
/*
* If we want to write a value different than 0
* then we have to erase the full block because
diff --git a/plat/arm/common/arm_topology.c b/plat/arm/common/arm_topology.c
index c6d12da..b0ad4d1 100644
--- a/plat/arm/common/arm_topology.c
+++ b/plat/arm/common/arm_topology.c
@@ -29,12 +29,14 @@
pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
#else
valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
- cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+ cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) &
+ MPIDR_AFFLVL_MASK);
+ cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) &
+ MPIDR_AFFLVL_MASK);
#endif /* ARM_PLAT_MT */
mpidr &= MPIDR_AFFINITY_MASK;
- if (mpidr & valid_mask)
+ if ((mpidr & valid_mask) != 0U)
return -1;
if (cluster_id >= PLAT_ARM_CLUSTER_COUNT)