Merge changes from topic "ms/cpu_errata" into integration
* changes:
refactor(cpus): add Cortex-A72 errata information
refactor(cpus): convert Rainier to use errata framework
refactor(cpus): convert QEMU Max to use the errata framework
diff --git a/Makefile b/Makefile
index 03f9320..8d3ffe1 100644
--- a/Makefile
+++ b/Makefile
@@ -217,18 +217,16 @@
################################################################################
ifeq (${ARM_ARCH_MAJOR},7)
target32-directive = -target arm-none-eabi
-# Will set march32-directive from platform configuration
+# Will set march-directive from platform configuration
else
target32-directive = -target armv8a-none-eabi
# Set the compiler's target architecture profile based on
# ARM_ARCH_MAJOR ARM_ARCH_MINOR options
ifeq (${ARM_ARCH_MINOR},0)
- march32-directive = -march=armv${ARM_ARCH_MAJOR}-a
- march64-directive = -march=armv${ARM_ARCH_MAJOR}-a
+ march-directive = -march=armv${ARM_ARCH_MAJOR}-a
else
- march32-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
- march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
+ march-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
endif #(ARM_ARCH_MINOR)
endif #(ARM_ARCH_MAJOR)
@@ -273,24 +271,20 @@
# Set the compiler's architecture feature modifiers
ifneq ($(arch-features), none)
# Strip "none+" from arch-features
- arch-features := $(subst none+,,$(arch-features))
- ifeq ($(ARCH), aarch32)
- march32-directive := $(march32-directive)+$(arch-features)
- else
- march64-directive := $(march64-directive)+$(arch-features)
- endif
+ arch-features := $(subst none+,,$(arch-features))
+ march-directive := $(march-directive)+$(arch-features)
# Print features
$(info Arm Architecture Features specified: $(subst +, ,$(arch-features)))
endif #(arch-features)
ifneq ($(findstring clang,$(notdir $(CC))),)
ifneq ($(findstring armclang,$(notdir $(CC))),)
- TF_CFLAGS_aarch32 := -target arm-arm-none-eabi $(march32-directive)
- TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi $(march64-directive)
+ TF_CFLAGS_aarch32 := -target arm-arm-none-eabi $(march-directive)
+ TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi $(march-directive)
LD := $(LINKER)
else
- TF_CFLAGS_aarch32 = $(target32-directive) $(march32-directive)
- TF_CFLAGS_aarch64 := -target aarch64-elf $(march64-directive)
+ TF_CFLAGS_aarch32 = $(target32-directive) $(march-directive)
+ TF_CFLAGS_aarch64 := -target aarch64-elf $(march-directive)
LD := $(shell $(CC) --print-prog-name ld.lld)
AR := $(shell $(CC) --print-prog-name llvm-ar)
@@ -302,8 +296,8 @@
PP := $(CC) -E $(TF_CFLAGS_$(ARCH))
AS := $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH))
else ifneq ($(findstring gcc,$(notdir $(CC))),)
- TF_CFLAGS_aarch32 = $(march32-directive)
- TF_CFLAGS_aarch64 = $(march64-directive)
+ TF_CFLAGS_aarch32 = $(march-directive)
+ TF_CFLAGS_aarch64 = $(march-directive)
ifeq ($(ENABLE_LTO),1)
# Enable LTO only for aarch64
ifeq (${ARCH},aarch64)
@@ -314,8 +308,8 @@
endif
LD = $(LINKER)
else
- TF_CFLAGS_aarch32 = $(march32-directive)
- TF_CFLAGS_aarch64 = $(march64-directive)
+ TF_CFLAGS_aarch32 = $(march-directive)
+ TF_CFLAGS_aarch64 = $(march-directive)
LD = $(LINKER)
endif #(clang)
@@ -355,8 +349,7 @@
TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION}
endif #(BP_OPTION)
-ASFLAGS_aarch32 = $(march32-directive)
-ASFLAGS_aarch64 = $(march64-directive)
+ASFLAGS += $(march-directive)
##############################################################################
# WARNINGS Configuration
@@ -444,7 +437,7 @@
################################################################################
CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
$(ERRORS) $(WARNINGS)
-ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \
+ASFLAGS += $(CPPFLAGS) \
-ffreestanding -Wa,--fatal-warnings
TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \
-ffunction-sections -fdata-sections \
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 131cca1..3d648c4 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2733,12 +2733,12 @@
the toolchain target architecture directive.
Platform may choose to not define straight the toolchain target architecture
-directive by defining ``MARCH32_DIRECTIVE``.
+directive by defining ``MARCH_DIRECTIVE``.
I.e:
.. code:: make
- MARCH32_DIRECTIVE := -mach=armv7-a
+ MARCH_DIRECTIVE := -mach=armv7-a
Code Structure
--------------
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index 42c0eda..fcfa04a 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -51,7 +51,6 @@
- ``FVP_Morello`` (Version 0.11/33)
- ``FVP_RD_E1_edge`` (Version 11.17/29)
- ``FVP_RD_V1`` (Version 11.17/29)
-- ``FVP_TC0`` (Version 11.17/18)
- ``FVP_TC1`` (Version 11.17/33)
- ``FVP_TC2`` (Version 11.18/28)
@@ -631,7 +630,7 @@
--------------
-*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts
.. _Arm's website: `FVP models`_
diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
index df1847d..925befc 100644
--- a/docs/plat/arm/tc/index.rst
+++ b/docs/plat/arm/tc/index.rst
@@ -17,7 +17,7 @@
(TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A
is the CPUs supported as below:
-- TC0 has support for Cortex A510, Cortex A710 and Cortex X2.
+- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
- TC2 has support for Hayes and Hunter Arm CPUs.
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index b16510f..abbf976 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,7 @@
static inline uint32_t fdt_blob_size(const void *dtb)
{
- const uint32_t *dtb_header = dtb;
+ const uint32_t *dtb_header = (const uint32_t *)dtb;
return fdt32_to_cpu(dtb_header[1]);
}
@@ -60,7 +60,8 @@
const void *prop = fdt_getprop(fdt, node, "status", &len);
/* A non-existing status property means the device is enabled. */
- return (prop == NULL) || (len == 5 && strcmp(prop, "okay") == 0);
+ return (prop == NULL) || (len == 5 && strcmp((const char *)prop,
+ "okay") == 0);
}
#define fdt_for_each_compatible_node(dtb, node, compatible_str) \
diff --git a/include/lib/cpus/aarch64/neoverse_hermes.h b/include/lib/cpus/aarch64/neoverse_hermes.h
new file mode 100644
index 0000000..22492c3
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_hermes.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_HERMES_H
+#define NEOVERSE_HERMES_H
+
+#define NEOVERSE_HERMES_MIDR U(0x410FD8E0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_HERMES_H */
diff --git a/lib/cpus/aarch64/neoverse_hermes.S b/lib/cpus/aarch64/neoverse_hermes.S
new file mode 100644
index 0000000..cb90b71
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_hermes.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_hermes.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse Hermes must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse Hermes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start neoverse_hermes
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end neoverse_hermes
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func neoverse_hermes_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set NEOVERSE_HERMES_CPUPWRCTLR_EL1, NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc neoverse_hermes_core_pwr_dwn
+
+errata_report_shim neoverse_hermes
+
+ /* ---------------------------------------------
+ * This function provides Neoverse Hermes specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_hermes_regs, "aS"
+neoverse_hermes_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_hermes_cpu_reg_dump
+ adr x6, neoverse_hermes_regs
+ mrs x8, NEOVERSE_HERMES_CPUECTLR_EL1
+ ret
+endfunc neoverse_hermes_cpu_reg_dump
+
+declare_cpu_ops neoverse_hermes, NEOVERSE_HERMES_MIDR, \
+ neoverse_hermes_reset_func, \
+ neoverse_hermes_core_pwr_dwn
diff --git a/make_helpers/armv7-a-cpus.mk b/make_helpers/armv7-a-cpus.mk
index eec85cc..a8e9d50 100644
--- a/make_helpers/armv7-a-cpus.mk
+++ b/make_helpers/armv7-a-cpus.mk
@@ -15,9 +15,9 @@
# armClang requires -march=armv7-a for all ARMv7 Cortex-A. To comply with
# all, just drop -march and supply only -mcpu.
-# Platform can override march32-directive through MARCH32_DIRECTIVE
-ifdef MARCH32_DIRECTIVE
-march32-directive := $(MARCH32_DIRECTIVE)
+# Platform can override march-directive through MARCH_DIRECTIVE
+ifdef MARCH_DIRECTIVE
+march-directive := $(MARCH_DIRECTIVE)
else
march32-set-${ARM_CORTEX_A5} := -mcpu=cortex-a5
march32-set-${ARM_CORTEX_A7} := -mcpu=cortex-a7
@@ -29,7 +29,7 @@
# default to -march=armv7-a as target directive
march32-set-yes ?= -march=armv7-a
-march32-directive := ${march32-set-yes} ${march32-neon-yes}
+march-directive := ${march32-set-yes} ${march32-neon-yes}
endif
# Platform may override these extension support directives:
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index c29537c..d383ead 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -6,8 +6,7 @@
include common/fdt_wrappers.mk
ifeq ($(TARGET_PLATFORM), 0)
-$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
-Some of the features might not work as expected)
+ $(error Platform ${PLAT}$(TARGET_PLATFORM) is deprecated.)
endif
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
@@ -70,13 +69,6 @@
PLAT_INCLUDES += -I${TC_BASE}/include/
-# CPU libraries for TARGET_PLATFORM=0
-ifeq (${TARGET_PLATFORM}, 0)
-TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a710.S \
- lib/cpus/aarch64/cortex_x2.S
-endif
-
# CPU libraries for TARGET_PLATFORM=1
ifeq (${TARGET_PLATFORM}, 1)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 7a1dccd..56c96a1 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -12,7 +12,7 @@
# Qemu Cortex-A15 model does not implement the virtualization extension.
# For this reason, we cannot set ARM_CORTEX_A15=yes and must define all
# the ARMv7 build directives.
-MARCH32_DIRECTIVE := -mcpu=cortex-a15
+MARCH_DIRECTIVE := -mcpu=cortex-a15
$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
$(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER))
$(eval $(call add_define,ARMV7_SUPPORTS_VFP))
diff --git a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
index 37460d7..05ebec4 100644
--- a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
+++ b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
@@ -26,8 +26,10 @@
* need version of whole 'virtual hardware platform'.
*/
#define SIP_SVC_VERSION SIP_FUNCTION_ID(1)
-
#define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100)
+#define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101)
+
+static uint64_t gic_its_addr;
void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
uintptr_t sbsa_get_gicd(void);
@@ -45,9 +47,12 @@
* QEMU gives us this DeviceTree node:
*
* intc {
- reg = < 0x00 0x40060000 0x00 0x10000
- 0x00 0x40080000 0x00 0x4000000>;
- };
+ * reg = < 0x00 0x40060000 0x00 0x10000
+ * 0x00 0x40080000 0x00 0x4000000>;
+ * its {
+ * reg = <0x00 0x44081000 0x00 0x20000>;
+ * };
+ * };
*/
node = fdt_path_offset(dtb, "/intc");
if (node < 0) {
@@ -74,6 +79,18 @@
INFO("GICR base = 0x%lx\n", gicr_base);
sbsa_set_gic_bases(gicd_base, gicr_base);
+
+ node = fdt_path_offset(dtb, "/intc/its");
+ if (node < 0) {
+ return;
+ }
+
+ err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL);
+ if (err < 0) {
+ ERROR("Failed to read GICI reg property of GIC node\n");
+ return;
+ }
+ INFO("GICI base = 0x%lx\n", gic_its_addr);
}
void read_platform_version(void *dtb)
@@ -143,6 +160,9 @@
case SIP_SVC_GET_GIC:
SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr());
+ case SIP_SVC_GET_GIC_ITS:
+ SMC_RET2(handle, NULL, gic_its_addr);
+
default:
ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid,
smc_fid - SIP_FUNCTION);