fix(cpus): workaround for Cortex-A720 erratum 3699561
Cortex-A720 erratum 3699561 that applies to all revisions <= r0p2
and is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421/latest/
Change-Id: I7ea3aaf3e7bf6b4f3648f6872e505a41247b14ba
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 08f8786..e5d14d5 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -12,6 +12,7 @@
#include <cortex_a520.h>
#include <cortex_a710.h>
#include <cortex_a715.h>
+#include <cortex_a720.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -60,6 +61,13 @@
break;
#endif /* ERRATA_A715_3699560 */
+#if ERRATA_A720_3699561
+ case EXTRACT_PARTNUM(CORTEX_A720_MIDR):
+ if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;;
+ break;
+#endif /* ERRATA_A720_3699561 */
+
default:
break;
}