diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index d03daf8..8782f18 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -389,6 +389,10 @@
   an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
   and is still open.
 
+- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to
+  Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
+  This erratum is still open.
+
 - ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
   Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
   This erratum is still open.
@@ -501,6 +505,10 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of
    the CPU.
 
+-  ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1
+   CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
+   It has been fixed in r1p2.
+
 -  ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1
    CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
    It is still open.
@@ -759,6 +767,10 @@
   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
   r1p1. It is fixed in r1p2.
 
+- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3
+  CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
+  CPU. It is fixed in r1p2.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h
index 301be69..d600eca 100644
--- a/include/lib/cpus/aarch64/cortex_a78c.h
+++ b/include/lib/cpus/aarch64/cortex_a78c.h
@@ -47,4 +47,9 @@
 #define CORTEX_A78C_IMP_CPUPOR_EL3			S3_6_C15_C8_2
 #define CORTEX_A78C_IMP_CPUPMR_EL3			S3_6_C15_C8_3
 
+/*******************************************************************************
+ * CPU Auxiliary Control register 5 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A78C_ACTLR5_EL1				S3_0_C15_C9_0
+
 #endif /* CORTEX_A78C_H */
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index 04548ea..4a3ac77 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -47,4 +47,10 @@
 #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH	U(4)
 #define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV	ULL(0x9)
 
+/*******************************************************************************
+ * CPU Auxiliary Control register 3 specific definitions.
+ ******************************************************************************/
+#define CORTEX_X3_CPUACTLR3_EL1			S3_0_C15_C1_2
+#define CORTEX_X3_CPUACTLR3_EL1_BIT_47		(ULL(1) << 47)
+
 #endif /* CORTEX_X3_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 1bb6243..f24069d 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -47,5 +47,6 @@
 #define NEOVERSE_V1_ACTLR5_EL1					S3_0_C15_C9_0
 #define NEOVERSE_V1_ACTLR5_EL1_BIT_55				(ULL(1) << 55)
 #define NEOVERSE_V1_ACTLR5_EL1_BIT_56				(ULL(1) << 56)
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_61				(ULL(1) << 61)
 
 #endif /* NEOVERSE_V1_H */
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index d19c693..2e6e8b6 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -72,6 +72,14 @@
 
 check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
 
+workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232
+	/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+	sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55)
+	sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56)
+workaround_reset_end cortex_a78c, ERRATUM(2743232)
+
+check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2)
+
 workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
 	/* dsb before isb of power down sequence */
 	dsb	sy
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 0cb3b97..95f3d10 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -57,6 +57,13 @@
 
 check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
 
+workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
+	/* Set CPUACTLR3_EL1 bit 47 */
+	sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
+workaround_reset_end cortex_x3, ERRATUM(2779509)
+
+check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
+
 workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	override_vector_table wa_cve_vbar_cortex_x3
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 2a49134..c2fbb11 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -196,6 +196,13 @@
 
 check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2)
 
+workaround_runtime_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377
+	/* Set bit 61 in CPUACTLR5_EL1 */
+	sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61
+workaround_runtime_end neoverse_v1, ERRATUM(2348377)
+
+check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1)
+
 workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
 	/* Set bit 40 in ACTLR2_EL1 */
 	sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4129852..1dc4bd4 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -393,6 +393,10 @@
 # It is still open.
 CPU_FLAG_LIST += ERRATA_A78C_2712575
 
+# Flag to apply erratum 2743232 workaround during reset. This erratum applies
+# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
+CPU_FLAG_LIST += ERRATA_A78C_2743232
+
 # Flag to apply erratum 2772121 workaround during powerdown. This erratum
 # applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
 CPU_FLAG_LIST += ERRATA_A78C_2772121
@@ -520,6 +524,10 @@
 # to revisions r0p0, r1p0, and r1p1 and r1p2 of the Neoverse V1 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_V1_2294912
 
+# Flag to apply erratum 2348377 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_V1_2348377
+
 # Flag to apply erratum 2372203 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_V1_2372203
@@ -774,6 +782,10 @@
 # to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2742421
 
+# Flag to apply erratum 2779509 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2779509
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 0b263e5..cf2e653 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -239,9 +239,10 @@
 		[5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
 		[6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
 			ERRATA_NON_ARM_INTERCONNECT},
-		[7] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
-		[8] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
-		[9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[7] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
+		[8] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
+		[9] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
+		[10 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_A78C_H_INC */
@@ -297,13 +298,14 @@
 		[8] = {2139242, 0x00, 0x11, ERRATA_V1_2139242},
 		[9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392},
 		[10] = {2294912, 0x00, 0x12, ERRATA_V1_2294912},
-		[11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203},
-		[12] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \
+		[11] = {2348377, 0x00, 0x11, ERRATA_V1_2348377},
+		[12] = {2372203, 0x00, 0x11, ERRATA_V1_2372203},
+		[13] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \
 			ERRATA_NON_ARM_INTERCONNECT},
-		[13] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
-		[14] = {2743233, 0x00, 0x12, ERRATA_V1_2743233},
-		[15] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
-		[16 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[14] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
+		[15] = {2743233, 0x00, 0x12, ERRATA_V1_2743233},
+		[16] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
+		[17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* NEOVERSE_V1_H_INC */
@@ -443,7 +445,8 @@
 		[1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
 		[2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
 		[3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
-		[4 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[4] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
+		[5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_X3_H_INC */