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review.trustedfirmware.org / rust-spmc / arm-xlat / f202064b119389443b8b9b3e85fd8961f71ec2df
commitf202064b119389443b8b9b3e85fd8961f71ec2df[log] [tgz]
authorImre Kis <imre.kis@arm.com>Fri Mar 07 13:38:30 2025 +0100
committerImre Kis <imre.kis@arm.com>Thu Mar 13 09:49:35 2025 +0100
treec45834b87927083b3c163d6cfe0967fa6cc07b81
parent5c8a485cac2284af4d50f461c1b6d1284fd94e1d [diff]
Fix TLB invalidation

Add synchronization barriers and use the fix TLBI calls when
invalidating single VA entries. TLBI instructions expect the virtual
address shifted right by 12 bits which was missing from the
implementation.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I413f986fffbdecb875a8ddc3356bae61b73e51d8
3 files changed
tree: c45834b87927083b3c163d6cfe0967fa6cc07b81
  1. src/
  2. .gitignore
  3. Cargo.lock
  4. Cargo.toml
  5. dco.txt
  6. LICENSE-Apache-2.0
  7. LICENSE-MIT
  8. README.md
README.md

AArch64 Virtual Memory Translation Table Handler Library

Features

  • Allocate and map data initialized range
  • Allocate and map zero initialized range
  • Map physical address range
  • Unmap virtual address range
  • Query phyisical address of virtual address
  • Set memory access rights

Translation regimes

  • EL1&0 stage 1 Upper/Lower VA ranges
  • EL2&0 stage 1 Upper/Lower VA ranges (VHE)
  • EL2 stage 1
  • EL3 stage 1

Translation granules

  • 4k
  • 16k
  • 64k

Copyright 2024-2025 Arm Limited and/or its affiliates open-source-office@arm.com