Prepare for 0.1.0 release
Add documentation, update dependencies and Cargo.toml.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ifd7fb644bd49878420f474c177094acafbaabc63
diff --git a/Cargo.lock b/Cargo.lock
index b3983aa..1aa19bb 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -27,9 +27,9 @@
[[package]]
name = "arm-pl011-uart"
-version = "0.3.0"
+version = "0.3.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bed01fb1be86080a2e9d93ae75e485837712a497f6e729e8ea329151a982e032"
+checksum = "ff5b0f1e39ec186e409c6fd80bbb83aa00622ca71c9c0561b5571df3b5f5391f"
dependencies = [
"bitflags",
"embedded-hal-nb",
@@ -41,8 +41,9 @@
[[package]]
name = "arm-sp805"
-version = "0.1.0"
-source = "git+https://git.trustedfirmware.org/rust-spmc/arm-sp805.git#826b861f78f36fd3e51a199b1d6969b5e5d48a5b"
+version = "0.1.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b51f04b17c58f653b74ade8f0f7bfdb01ae32cc1ffdface0802d01760b20f56d"
dependencies = [
"bitflags",
"safe-mmio",
diff --git a/Cargo.toml b/Cargo.toml
index 4132e4b..e9686eb 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -8,17 +8,17 @@
"Balint Dobszay <balint.dobszay@arm.com>",
"Imre Kis <imre.kis@arm.com>",
]
-description = "Peripheral Access Crate for Arm Fixed Virtual Platform"
+description = "Arm Base Fixed Virtual Platform Peripheral Access Crate"
edition = "2021"
license = "MIT OR Apache-2.0"
-repository = "https://git.trustedfirmware.org/rust-spmc/rust-spmc.git"
+repository = "https://git.trustedfirmware.org/rust-spmc/arm-fvp-base-pac.git"
keywords = ["arm", "fvp", "pac", "virtual", "platform"]
[dependencies]
arm-gic = { git = "https://git.trustedfirmware.org/rust-spmc/arm-gic.git" }
arm-pl011-uart = "0.3"
-arm-sp805 = { git = "https://git.trustedfirmware.org/rust-spmc/arm-sp805.git" }
+arm-sp805 = "0.1"
+bitflags = "2.9"
safe-mmio = "0.2"
spin = { version = "0.9", default-features = false, features = ["spin_mutex"] }
-bitflags = "2.9"
zerocopy = { version = "0.8", features = ["derive"] }
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..b1aba3f
--- /dev/null
+++ b/README.md
@@ -0,0 +1,53 @@
+# Arm Base Fixed Virtual Platform Peripheral Access Crate
+
+This crate provides peripheral access for the [Arm Fixed Virtual Platform](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms),
+**specifically for the Base platform FVPs**.
+
+The implementation is based on [Fast Models Fixed Virtual Platforms Reference Guide Revision: 11.28](https://developer.arm.com/documentation/100966/1128)
+and [Fast Models Reference Guide Revision: 11.28](https://developer.arm.com/documentation/100964/1128/).
+
+## Implemented features
+
+* Memory map description.
+* `Peripherals` structure for obtaining individual peripherals while maintaining ownership.
+* FVP power controller driver
+* FVP system peripheral driver
+* Re-exporting `arm-gic`, `arm-pl011-uart` and `arm-sp805` drivers and common `safe-mmio` types.
+ This enables projects to use these peripherals without adding these crates as explicit
+ dependencies to the project. This also prevents having driver version conflicts in the project.
+
+## Limitations
+
+* Not all peripherals are handled yet.
+
+## License
+
+The project is MIT and Apache-2.0 dual licensed, see `LICENSE-APACHE` and `LICENSE-MIT`.
+
+## Maintainers
+
+arm-fvp-base-pac is a trustedfirmware.org maintained project. All contributions are ultimately merged by
+the maintainers listed below.
+
+* Bálint Dobszay <balint.dobszay@arm.com>
+ [balint-dobszay-arm](https://github.com/balint-dobszay-arm)
+* Imre Kis <imre.kis@arm.com>
+ [imre-kis-arm](https://github.com/imre-kis-arm)
+* Sandrine Afsa <sandrine.afsa@arm.com>
+ [sandrine-bailleux-arm](https://github.com/sandrine-bailleux-arm)
+
+## Contributing
+
+Please follow the directions of the [Trusted Firmware Processes](https://trusted-firmware-docs.readthedocs.io/en/latest/generic_processes/index.html).
+
+Contributions are handled through [review.trustedfirmware.org](https://review.trustedfirmware.org/q/project:rust-spmc/arm-psci).
+
+## Reporting Security Issues
+
+Please follow the directions of the [Trusted Firmware Security Center](https://trusted-firmware-docs.readthedocs.io/en/latest/security_center/index.html).
+
+--------------
+
+*Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>*
+
+*Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates).*
diff --git a/src/lib.rs b/src/lib.rs
index b02f407..1e8da79 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,12 +1,11 @@
// SPDX-FileCopyrightText: Copyright 2023-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
// SPDX-License-Identifier: MIT OR Apache-2.0
-//! # Peripheral Access Crate fro Arm Fixed Virtual Platform
-//!
-//! The crate provides access to the peripherals of [Arm Fixed Virtual Platform](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms).
-
#![no_std]
+#![doc = include_str!("../README.md")]
+#![deny(clippy::undocumented_unsafe_blocks)]
+pub mod power_controller;
pub mod system;
// Re-export peripheral drivers and common safe-mmio types
@@ -14,7 +13,6 @@
pub use arm_pl011_uart;
pub use arm_sp805;
pub use safe_mmio::{PhysicalInstance, UniqueMmioPointer};
-pub mod power_controller;
use arm_gic::GICDRegisters;
use arm_pl011_uart::PL011Registers;
@@ -114,8 +112,8 @@
pub uart2: PhysicalInstance<PL011Registers>,
pub uart3: PhysicalInstance<PL011Registers>,
pub watchdog: PhysicalInstance<SP805Registers>,
- pub gicd: PhysicalInstance<GICDRegisters>,
pub power_controller: PhysicalInstance<FvpPowerControllerRegisters>,
+ pub gicd: PhysicalInstance<GICDRegisters>,
}
impl Peripherals {
diff --git a/src/power_controller.rs b/src/power_controller.rs
index 4ca07dc..56838c3 100644
--- a/src/power_controller.rs
+++ b/src/power_controller.rs
@@ -1,13 +1,14 @@
// SPDX-FileCopyrightText: Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
// SPDX-License-Identifier: MIT OR Apache-2.0
+//! FVP Power Controller driver.
+
use bitflags::bitflags;
use safe_mmio::UniqueMmioPointer;
use safe_mmio::{field, fields::ReadPureWrite};
use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout};
-// Register descriptions
-
+/// Power on reason.
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum PowerOnReason {
/// Cold power-on.
@@ -51,7 +52,7 @@
}
/// Power Control SYS Status Register
- pub struct SysStatusRegister: u32 {
+ pub struct SystemStatus: u32 {
/// A value of 1 indicates that affinity level 2 is active/on. If affinity level 2 is not
/// implemented this bit is RAZ.
const L2 = 1 << 31;
@@ -112,9 +113,9 @@
/// This is done by writing the ID for the required core to the PSYS register and then reading
/// the value along with the associated status.
/// Please see `power_on_reason` for other related information.
- pub fn system_status(&mut self, mpidr: u32) -> SysStatusRegister {
+ pub fn system_status(&mut self, mpidr: u32) -> SystemStatus {
// There are no usage constraints
- SysStatusRegister::from_bits_truncate(self.system_status_reg(mpidr))
+ SystemStatus::from_bits_truncate(self.system_status_reg(mpidr))
}
/// Brings up the given processor from low-power mode by writing to the PPONR register
@@ -185,11 +186,6 @@
Self { regs: [0u32; 5] }
}
- #[allow(unused)]
- pub fn reg_write(&mut self, offset: usize, value: u32) {
- self.regs[offset / 4] = value;
- }
-
pub fn reg_read(&self, offset: usize) -> u32 {
self.regs[offset / 4]
}
@@ -216,12 +212,12 @@
let sys_status = fvp_power_controller.system_status(fake_mpidr);
- assert!(!sys_status.contains(SysStatusRegister::L2));
- assert!(!sys_status.contains(SysStatusRegister::L1));
- assert!(!sys_status.contains(SysStatusRegister::L0));
- assert!(!sys_status.contains(SysStatusRegister::WEN));
- assert!(!sys_status.contains(SysStatusRegister::PC));
- assert!(!sys_status.contains(SysStatusRegister::PP));
+ assert!(!sys_status.contains(SystemStatus::L2));
+ assert!(!sys_status.contains(SystemStatus::L1));
+ assert!(!sys_status.contains(SystemStatus::L0));
+ assert!(!sys_status.contains(SystemStatus::WEN));
+ assert!(!sys_status.contains(SystemStatus::PC));
+ assert!(!sys_status.contains(SystemStatus::PP));
}
#[test]