commit e9a3e76d319b59146498c3cc356eac04a3dbab69
author Balint Dobszay <balint.dobszay@arm.com> Wed Feb 26 17:29:57 2025 +0100
committer Balint Dobszay <balint.dobszay@arm.com> Fri Feb 28 15:34:24 2025 +0100
tree 698d96a6740851a175369cda20b3915d82b5c70c
parent a5846855570eb4e66843bb70176739b3f86c1c2a

Fix clippy lints

Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Idfd8209650a7525a49240fe79a7e6245bbb99f95

src/lib.rs

diff --git a/src/lib.rs b/src/lib.rs
index d4855b8..466ec0a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -142,7 +142,7 @@
 
 impl From<TargetInfo> for u32 {
     fn from(value: TargetInfo) -> Self {
-        (value.endpoint_id as u32) << 16 | value.vcpu_id as u32
+        ((value.endpoint_id as u32) << 16) | value.vcpu_id as u32
     }
 }
 
@@ -165,7 +165,7 @@
 
 impl From<Version> for u32 {
     fn from(v: Version) -> Self {
-        (v.0 as u32) << 16 | v.1 as u32
+        ((v.0 as u32) << 16) | v.1 as u32
     }
 }
 
@@ -870,7 +870,7 @@
                 flags,
                 args,
             } => {
-                a[1] = (src_id as u64) << 16 | dst_id as u64;
+                a[1] = ((src_id as u64) << 16) | dst_id as u64;
                 a[2] = flags.into();
                 match args {
                     DirectMsgArgs::Args32(args) => {
@@ -895,7 +895,7 @@
                 flags,
                 args,
             } => {
-                a[1] = (src_id as u64) << 16 | dst_id as u64;
+                a[1] = ((src_id as u64) << 16) | dst_id as u64;
                 a[2] = flags.into();
                 match args {
                     DirectMsgArgs::Args32(args) => {