blob: 795d2f92593317daef79275faf53fd56bdf63136 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Rohit Mathew17675f22024-02-14 22:41:37 +00003# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
Harrison Mutaiee958c12023-09-06 12:16:21 +010017set -E
Harrison Mutai3f483132024-05-09 09:48:58 +000018error() {
19 rc=$?;
20 error_count=$((error_count+1));
21 echo "ERROR: signal $rc at ${1} ${2} (error_count = $error_count)"
22}
23trap 'error "${BASH_SOURCE}" "${LINENO}"' ERR INT
Fathi Boudra422bf772019-12-02 11:10:16 +020024
25TF_SOURCES=$1
26if [ ! -d "$TF_SOURCES" ]; then
27 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
28 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
29 exit 1
30fi
31
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050032containing_dir="$(readlink -f "$(dirname "$0")/")"
33. $containing_dir/common-def.sh
34
Fathi Boudra422bf772019-12-02 11:10:16 +020035# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
36# support. The version of mbed TLS to use here must be the same as when
37# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050038if [ ! -d "$MBED_TLS_DIR" ]; then
39 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020040fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050041
David Vincze82db6932024-02-21 12:05:50 +010042if [ ! -d "$QCBOR_LIB_DIR" ]; then
43 git clone "$QCBOR_URL_REPO" "$QCBOR_LIB_DIR"
44 cd "$QCBOR_LIB_DIR"
45 git checkout v1.2
46fi
47
Fathi Boudra422bf772019-12-02 11:10:16 +020048cd "$TF_SOURCES"
49
50# Clean TF source dir to make sure we don't analyse temporary files.
51make distclean
52
53#
54# Build TF in different configurations to get as much coverage as possible
55#
56
Fathi Boudra422bf772019-12-02 11:10:16 +020057#
58# FVP platform
59# We'll use the following flags for all FVP builds.
60#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050061fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020062
63# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000064clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
65 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020066clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
Sona Mathew40e5be92023-08-10 16:31:45 -050067 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010068clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010069clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010070clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
71 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020072
Zelalemc9531f82020-08-04 15:37:08 -050073# Dualroot chain of trust.
Harrison Mutai0dd5f532024-03-15 13:42:40 +000074clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot \
75 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -050076
laurenw-armf48e9d22022-04-22 11:30:13 -050077# FEAT_RME with CCA chain of trust.
Manish V Badarkhe5304aaf2023-08-18 14:38:20 +010078clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Manish V Badarkhed5e9c752023-11-07 17:57:36 +000079 ENABLE_RME=1 MEASURED_BOOT=1
laurenw-armf48e9d22022-04-22 11:30:13 -050080
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050081clean_build $fvp_common_flags SPD=trusty
82clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020083
Sona Mathewff9c2a72023-05-10 21:18:01 -050084# ERRATA ABI
85clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
86
Fathi Boudra422bf772019-12-02 11:10:16 +020087# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050088clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020089
Zelalemc9531f82020-08-04 15:37:08 -050090# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050091clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050092
Zelalem4f3633e2021-06-18 11:53:47 -050093# PCI Service
94clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
95
Zelalemc9531f82020-08-04 15:37:08 -050096# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050097clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050098
Fathi Boudra422bf772019-12-02 11:10:16 +020099# Without coherent memory
Sona Mathewa06f62d2023-08-24 16:34:13 -0500100clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
101 USE_COHERENT_MEM=0 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200102
103# Using PSCI extended State ID format rather than the original format
Sona Mathewa06f62d2023-08-24 16:34:13 -0500104clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
105 PSCI_EXTENDED_STATE_ID=1 ARM_RECOM_STATE_ID_ENC=1 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200106
107# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100108clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200109clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
110
111# Using the SP804 timer instead of the Generic Timer
112clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
113
114# Using the CCN driver and multi cluster topology
115clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
116
117# PMF
118clean_build $fvp_common_flags ENABLE_PMF=1
119
120# stack protector
121clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
122
123# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500124clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200125 ARCH=aarch32 AARCH32_SP=sp_min \
126 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500127clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200128 ARCH=aarch32 AARCH32_SP=sp_min
129
130# Xlat tables lib version 1 (AArch64 and AArch32)
131clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500132clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200133 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
134
Zelalemc9531f82020-08-04 15:37:08 -0500135# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000136clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200137
Zelalemc9531f82020-08-04 15:37:08 -0500138# SPM support with TOS(optee) as SPM sitting at S-EL1
139clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
140
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100141# SPM support with SPM at EL3 and TSP at S-EL1
142clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
143 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
144 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
145
Zelalemc9531f82020-08-04 15:37:08 -0500146# SPM support with Secure hafnium as SPM sitting at S-EL2
147# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
148# if we have NULL value to it, so passing a dummy string.
149clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000150 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200151
J-Alves85ba07b2023-07-12 14:37:45 +0100152# SPM support with logical partitions in the SPMD.
153clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
154 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy ENABLE_SPMD_LP=1
155
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000156# SPM support with SPM sitting at EL3
157clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
158
Harrison Mutaib352c0e2023-08-11 18:27:57 +0100159# Firmware Handoff framework support
160clean_build $fvp_common_flags TRANSFER_LIST=1
161
Manish Pandeyd47c1cf2024-12-09 11:06:59 +0000162# HOB List support
163clean_build $fvp_common_flags HOB_LIST=1
164
Fathi Boudra422bf772019-12-02 11:10:16 +0200165#BL2 at EL3 support
Harrison Mutaic3c8cfc2023-09-05 12:03:03 +0100166clean_build $fvp_common_flags RESET_TO_BL2=1 FVP_TRUSTED_SRAM_SIZE=384
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500167clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000168 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200169
Zelalemc9531f82020-08-04 15:37:08 -0500170# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000171clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100172 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100173 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500174
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100175# EA handled in EL3 first
176clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
177
Zelalemc9531f82020-08-04 15:37:08 -0500178# Hardware Assisted Coherency(DynamIQ)
179clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
180 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
181
182# Pointer Authentication Support
183clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
Sona Mathewa06f62d2023-08-24 16:34:13 -0500184 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd \
Sona Mathew08c17962023-08-28 09:36:17 -0500185 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -0500186
187# Undefined Behaviour Sanitizer
188# Building with UBSAN SANITIZE_UB=on increases the executable size.
189# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
190make $fvp_common_flags clean
Manish V Badarkhe4e79cab2023-09-07 10:07:58 +0100191make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 FVP_TRUSTED_SRAM_SIZE=384 bl31
Zelalemc9531f82020-08-04 15:37:08 -0500192
193# debugfs feature
194clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
195
196# MPAM feature
Arvind Ram Prakashbd4e43a2023-10-02 11:12:34 -0500197clean_build $fvp_common_flags ENABLE_FEAT_MPAM=1
Zelalemc9531f82020-08-04 15:37:08 -0500198
Arvind Ram Prakashd2e27e62024-06-17 14:28:12 -0500199# Debugv8p9 feature
200clean_build $fvp_common_flags ENABLE_FEAT_DEBUGV8P9=1
201
Arvind Ram Prakasha6b9b4c2024-06-17 13:49:31 -0500202# Feat_FGT2 (Fine-grained Traps 2) feature
203clean_build $fvp_common_flags ENABLE_FEAT_FGT2=1
204
Arvind Ram Prakash92c76212024-12-11 10:26:55 -0600205# Feat_FPMR (Floating Point Mode Register) feature
206clean_build $fvp_common_flags ENABLE_FEAT_FPMR=1
207
Jayanth Dodderi Chidanandfb69c8a2024-09-04 22:03:27 +0100208# FEAT_TCR2
209clean_build $fvp_common_flags ENABLE_FEAT_TCR2=1
210
Govindraj Raja87888b02024-09-13 11:48:44 -0500211# FEAT_THE, FEAT_SCTLR2
212clean_build $fvp_common_flags ENABLE_FEAT_THE=1 ENABLE_FEAT_SCTLR2=1
213
Zelalemc9531f82020-08-04 15:37:08 -0500214# Using GICv3.1 driver with extended PPI and SPI range
215clean_build $fvp_common_flags GIC_EXT_INTID=1
216
217# Using GICv4 features with extended PPI and SPI range
218clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
219
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100220# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500221clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100222
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100223# DRTM
224clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
225
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100226# CoT descriptors in device tree
laurenw-arm23b77592024-06-07 15:54:30 -0500227# TBBR chain of trust
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100228clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
laurenw-arm23b77592024-06-07 15:54:30 -0500229# Dualroot chain of trust
230clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 COT=dualroot FVP_TRUSTED_SRAM_SIZE=384 SPD=tspd
231# CCA chain of trust
232clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 COT=cca FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100233
Chris Kayf4789fe2023-06-12 15:52:28 +0100234# PSA FWU support
235clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100236
Manish V Badarkhe92616ae2023-09-18 10:06:00 +0100237# PSA Crypto support
238clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} PSA_CRYPTO=1 FVP_TRUSTED_SRAM_SIZE=384
239
johpow01153c8b22021-11-03 14:38:36 -0500240# SME and HCX features
241clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
242
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000243# SME2
244clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
245
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100246# Architectural Feature Detection mechanism
247clean_build $fvp_common_flags FEATURE_DETECTION=1
248
Manish Pandeye3561fd2023-01-05 10:46:25 +0000249# RNG trap feature
250clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
251
Yi Choua765ae42023-05-26 15:51:02 +0800252# OPTEE_ALLOW_SMC_LOAD and CROS_WIDEVINE_SMC features
253clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 CROS_WIDEVINE_SMC=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800254
Jayanth Dodderi Chidanand508936d2023-12-22 14:33:38 +0000255# Report Context_Memory
256clean_build $fvp_common_flags PLATFORM_REPORT_CTX_MEM_USE=1
257
Govindraj Rajaef67db82024-05-02 09:57:13 -0500258# Build newer CPU's with no model available yet.
259clean_build $fvp_common_flags CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 \
260 USE_COHERENT_MEM=0 BUILD_CPUS_WITH_NO_FVP_MODEL=1 FVP_TRUSTED_SRAM_SIZE=384
261
Raghu Krishnamurthye27e25d2024-09-21 10:25:56 -0700262# Sign Realm tokens with EL3 signing service
263clean_build $fvp_common_flags ENABLE_RME=1 RMMD_ENABLE_EL3_TOKEN_SIGN=1
264
Fathi Boudra422bf772019-12-02 11:10:16 +0200265#
266# Juno platform
267# We'll use the following flags for all Juno builds.
268#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500269juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200270clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100271clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Manish V Badarkhe05626442023-09-12 09:54:50 +0100272clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1
Harrison Mutaid8aff2a2024-05-08 10:40:21 +0000273# FIXME: temporarily disable debug builds for this configuration until BL2 size
274# issues are resolved.
Harrison Mutaic70ba542024-05-09 13:17:12 +0000275clean_build "$(common_flags release) PLAT=juno" ${ARM_TBB_OPTIONS} \
Harrison Mutaid8aff2a2024-05-08 10:40:21 +0000276 ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1 ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200277clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500278
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100279# TRNG Service
280clean_build $juno_common_flags TRNG_SUPPORT=1
281
Fathi Boudra422bf772019-12-02 11:10:16 +0200282#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530283# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500284#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530285make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500286
287#
Aditya Angadi61c54762021-01-04 09:30:52 +0530288# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500289#
Rohit Mathew17675f22024-02-14 22:41:37 +0000290make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} NRD_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500291
292#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530293# Reference Design Platform RD-N2
294#
295make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Manish Pandeyf3816802023-10-11 17:13:58 +0100296
Nishant Sharmabd7092e2023-10-11 09:17:13 +0100297# SPMC At EL3 Support
298make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
299 SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
300 PLAT_RO_XLAT_TABLES=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530301
302#
Jerry Wang700472b2024-07-12 11:36:42 +0100303# Reference Design Platform RD-V3
Nuno Lopesd791e272024-04-25 14:46:49 +0100304#
Jerry Wang700472b2024-07-12 11:36:42 +0100305make $(common_flags) PLAT=rdv3 ${ARM_TBB_OPTIONS} COT=cca DEBUG=1 \
Nuno Lopesd791e272024-04-25 14:46:49 +0100306 ENABLE_RME=1 MEASURED_BOOT=1 PLAT_MHU_VERSION=3 RMM=/dev/null \
307 RME_GPT_BITLOCK_BLOCK=0 all
308
309#
Zelalemc9531f82020-08-04 15:37:08 -0500310# Neoverse N1 SDP platform
311#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500312make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500313
314#
315# FVP VE platform
316#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500317make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500318 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
319 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
320 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
321
322#
323# A5 DesignStart Platform
324#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500325make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500326 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
327 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
328
329#
330# Corstone700 Platform
331#
332
333corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500334 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500335 PLAT=corstone700 \
336 ARCH=aarch32 \
337 RESET_TO_SP_MIN=1 \
338 AARCH32_SP=sp_min \
339 ARM_LINUX_KERNEL_AS_BL33=0 \
340 ARM_PRELOADED_DTB_BASE=0x80400000 \
341 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500342 ENABLE_STACK_PROTECTOR=all \
343 all"
344
345echo "Info: Building Corstone700 FVP ..."
346
347make TARGET_PLATFORM=fvp ${corstone700_common_flags}
348
349echo "Info: Building Corstone700 FPGA ..."
350
351make TARGET_PLATFORM=fpga ${corstone700_common_flags}
352
353#
354# Arm internal FPGA port
355#
Andre Przywara13361b62022-04-26 11:16:55 +0100356make PLAT=arm_fpga $(common_flags release) \
357 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500358
359#
Usama Arifcba711d2021-08-04 15:53:42 +0100360# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500361#
David Vincze5d87f6a2024-10-30 15:17:45 +0000362clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
Joel Goddard571a93c2024-02-29 15:31:48 +0000363 PLAT_MHU_VERSION=3
David Vincze5d87f6a2024-10-30 15:17:45 +0000364clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
David Vincze82db6932024-02-21 12:05:50 +0100365 DICE_PROTECTION_ENVIRONMENT=1 QCBOR_DIR=$(pwd)/qcbor
Quoc Khanh Le2acaceb2024-06-20 15:07:43 +0100366clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-rotpk
367clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-nv-counters
368clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=3 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
David Vincze5d87f6a2024-10-30 15:17:45 +0000369 MEASURED_BOOT=1 QCBOR_DIR=$(pwd)/qcbor TF_M_TESTS_PATH=$(pwd)/../tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/../tf-m-extras
Leo Yan45d51632024-08-27 16:02:28 +0100370clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=4 ${ARM_TBB_OPTIONS} \
371 PLAT_MHU_VERSION=3
Leo Yan1a9345f2024-10-03 11:00:16 +0100372clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=4 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-rotpk
373clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=4 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rse-nv-counters
374clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=4 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
Manish V Badarkhe519c2ce2024-11-11 10:51:26 +0000375 MEASURED_BOOT=1 QCBOR_DIR=$(pwd)/qcbor TF_M_TESTS_PATH=$(pwd)/../tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/../tf-m-extras
Leo Yan1a9345f2024-10-03 11:00:16 +0100376clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=4 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1 \
377 DICE_PROTECTION_ENVIRONMENT=1 QCBOR_DIR=$(pwd)/qcbor
Fathi Boudra422bf772019-12-02 11:10:16 +0200378
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530379#
380# Morello platform
381#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530382clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
383clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530384
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100385#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000386# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100387#
388
Ziad Elhanafy9352d0c2024-10-03 17:13:25 +0100389clean_build $(common_flags) \
390 PLAT=corstone1000 \
391 SPD=spmd \
392 TARGET_PLATFORM=fpga \
393 ENABLE_STACK_PROTECTOR=strong \
394 ENABLE_PIE=1 \
395 RESET_TO_BL2=1 \
396 SPMD_SPM_AT_SEL2=0 \
397 ${ARM_TBB_OPTIONS} \
398 CREATE_KEYS=1 \
399 COT=tbbr \
400 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
401 bl2 \
402 bl31
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100403
johpow01aac58582021-10-05 16:51:34 -0500404#
405# FVP-R platform
406#
407clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
408
Divin Raj6aa589d2024-04-17 11:38:07 +0100409#
410# RD-1 AE platform
411#
Ziad Elhanafy9352d0c2024-10-03 17:13:25 +0100412clean_build $(common_flags) \
413 PLAT=rd1ae \
414 ARCH=aarch64 \
415 ${ARM_TBB_OPTIONS} \
416 GENERATE_COT=1 \
417 COT=tbbr \
418 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
419 bl2 \
420 bl31 \
421 SPD=spmd \
422 SPMD_SPM_AT_SEL2=0
Divin Raj6aa589d2024-04-17 11:38:07 +0100423
Fathi Boudra422bf772019-12-02 11:10:16 +0200424# Partners' platforms.
425# Enable as many features as possible.
426# We don't need to clean between each build here because we only do one build
427# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200428
Manish Pandey9c0ee742021-07-08 09:55:59 +0100429# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500430make PLAT=mt8173 $(common_flags) all
431make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800432make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800433make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500434make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100435make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Gavin Liu55eaafd2024-10-18 16:34:06 +0800436make PLAT=mt8196 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500437
438# Platforms from Qualcomm
439make PLAT=sc7180 $(common_flags) COREBOOT=1 all
quic_assethif307a782024-12-10 17:32:18 +0530440make PLAT=qcs615 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200441
Zelalemc9531f82020-08-04 15:37:08 -0500442make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500443 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600444make PLAT=rk3368 $(common_flags) COREBOOT=1 \
445 ENABLE_STACK_PROTECTOR=strong all
446make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
447 ENABLE_STACK_PROTECTOR=strong all
448make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
449 ENABLE_STACK_PROTECTOR=strong all
XiaoDong Huang9c7c0af2023-07-05 14:26:39 +0800450make PLAT=rk3588 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
451 ENABLE_STACK_PROTECTOR=strong all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600452make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
453 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200454
455# Although we do several consecutive builds for the Tegra platform below, we
456# don't need to clean between each one because the Tegra makefiles specify
457# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500458make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500459make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
460make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200461
462# For the Xilinx platform, artificially increase the extents of BL31 memory
463# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
464# If we keep the default values, BL31 doesn't fit when it is built with all
465# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500466make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200467 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500468 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200469 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
470 all
471
Zelalemc9531f82020-08-04 15:37:08 -0500472# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500473clean_build PLAT=versal $(common_flags)
474clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500475
Michal Simek0f135242022-09-20 15:24:56 +0200476# Build Xilinx Versal NET platform
477clean_build PLAT=versal_net $(common_flags)
478
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100479# Build Xilinx Versal NET without Platform Management support
480clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
481
Amit Nagalfb428442024-06-11 12:01:23 +0530482# Build Xilinx Versal Gen 2 platform
483clean_build PLAT=versal2 $(common_flags)
484
Zelalemc9531f82020-08-04 15:37:08 -0500485# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100486clean_build PLAT=sun50i_a64 $(common_flags release) all
487clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
488clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
489clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100490clean_build PLAT=sun50i_h6 $(common_flags) all
491clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
492clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
493clean_build PLAT=sun50i_h616 $(common_flags) all
494clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500495
496# Platforms from i.MX
497make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
498 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500499 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500500make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500501 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800502make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500503 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500504make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800505make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500506
Jacky Baib6cecc82021-06-07 09:49:46 +0800507# Due to the limited OCRAM space that can be used for TF-A, build test
508# will report failure caused by too small RAM size, so comment out the
509# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500510# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800511#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500512
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500513make PLAT=imx8qm $(common_flags) all
514make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500515
Jacky Baif5e936c2023-12-27 11:11:09 +0800516make PLAT=imx8ulp $(common_flags) all
517
Jacky Bai87091a62023-06-21 16:25:12 +0800518make PLAT=imx93 $(common_flags) all
519
Olivier Deprezbac70192021-04-02 08:55:36 +0200520# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800521nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
522nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
523
524# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200525make PLAT=lx2160aqds $(common_flags) all
526make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500527
528#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800529clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
530 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500531
532#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800533clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
534 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500535 MBEDTLS_DIR=$(pwd)/mbedtls
536
537#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800538clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
539 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
540
541# Platform ls1028ardb
542clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
543clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
544clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
545
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800546# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800547clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
548clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
549clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200550
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800551# Platform ls1043ardb
552clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
553clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
554clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
555
556# ls1043ardb Secure Boot
557clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
558clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
559clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
560
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800561# ls1046ardb Secure Boot
562clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
563clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
564clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
565
566# ls1046afrwy Secure Boot
567clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
568clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
569
570# ls1046aqds Secure Boot
571clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
572clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
573clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
574clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
575
Jiafei Pan332cd792022-02-24 16:44:48 +0800576# ls1088ardb Secure Boot
577clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
578clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
579
580# ls1088aqds Secure Boot
581clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
582clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
583clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
584
Ghennadi Procopciuc731b0042024-02-01 09:22:26 +0200585# s32g274ardb2
586clean_build PLAT=s32g274ardb2 $(common_flags) all
587
Zelalemc9531f82020-08-04 15:37:08 -0500588# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500589make PLAT=stratix10 $(common_flags) all
590make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800591make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800592make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500593
594# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600595clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
596 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
597clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
598 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500599
600# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500601make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100602 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500603
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600604# Source files from mv-ddr-marvell repository are necessary
605# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000606wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
607tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600608mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500609
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600610# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200611make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200612 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200613make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200614 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200615make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200616 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200617make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200618 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200619make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
620 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200621make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200622 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200623make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200624 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500625make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
626 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500627
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600628# Removing the source files
629rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500630
631# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500632make PLAT=gxbb $(common_flags) all
633make PLAT=gxl $(common_flags) all
634make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500635
636# Platforms from Renesas
637# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500638clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500639 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
640 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
641 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
642 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
643
644# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500645clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500646 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
647 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
648 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
649 TRUSTED_BOARD_BOOT=1
650
651# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500652clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500653 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
654 SPD=opteed TRUSTED_BOARD_BOOT=1
655
656# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500657clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500658 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
659 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
660 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
661 TRUSTED_BOARD_BOOT=1
662
663# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500664clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500665 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
666 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
667 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
668
669# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500670clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500671 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
672 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
673 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
674
675# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500676clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500677 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
678 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
679 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
680
Zelalemf4299672021-01-29 12:52:59 -0600681# Renesas HiHope RZ/G2M development kit
682clean_build PLAT=rzg $(common_flags) \
683 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
684 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
685
Zelalemc9531f82020-08-04 15:37:08 -0500686# Platforms from ST
Yann Gautier868044b2024-06-19 10:42:51 +0200687stm32mp1_common_flags="ARCH=aarch32 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100688 ARM_ARCH_MAJOR=7 \
689 CROSS_COMPILE=arm-none-eabi- \
690 ENABLE_STACK_PROTECTOR=strong \
691 PLAT=stm32mp1"
692
Yann Gautiera69cf792021-09-01 11:19:01 +0200693# STM32MP1 SDMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200694clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200695 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100696 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200697
Yann Gautier15c45392023-08-21 11:03:33 +0200698# STM32MP1 SDMMC boot BL2 without AARCH32_SP
Yann Gautierb6821192024-06-19 10:45:56 +0200699clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier15c45392023-08-21 11:03:33 +0200700 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
701 bl2
702
Yann Gautierbd871522024-01-05 15:13:58 +0100703# STM32MP1 SDMMC boot BL2 with OP-TEE & FWU
Yann Gautierb6821192024-06-19 10:45:56 +0200704clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautierbd871522024-01-05 15:13:58 +0100705 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
706 PSA_FWU_SUPPORT=1 AARCH32_SP=optee \
707 bl2
708
Yann Gautiera69cf792021-09-01 11:19:01 +0200709# STM32MP1 eMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200710clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200711 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100712 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200713
714# STM32MP1 Raw NAND boot
Yann Gautierb6821192024-06-19 10:45:56 +0200715clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200716 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierbd871522024-01-05 15:13:58 +0100717 PSA_FWU_SUPPORT=1 AARCH32_SP=optee \
718 bl2
Yann Gautiera69cf792021-09-01 11:19:01 +0200719
720# STM32MP1 SPI NAND boot
Yann Gautierb6821192024-06-19 10:45:56 +0200721clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200722 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100723 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200724
725# STM32MP1 SPI NOR boot
Yann Gautierb6821192024-06-19 10:45:56 +0200726clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200727 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000728 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200729
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100730# STM32MP1 UART boot
Yann Gautierb6821192024-06-19 10:45:56 +0200731clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100732 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100733 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100734
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200735# STM32MP1 USB boot
Yann Gautierb6821192024-06-19 10:45:56 +0200736clean_build $(common_flags) ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200737 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100738 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200739
Lionel Debieve8f464c02022-10-13 09:25:45 +0200740# STM32MP1 TBBR
Yann Gautierb6821192024-06-19 10:45:56 +0200741clean_build $(common_flags release) ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100742 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200743 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100744 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200745
Govindraj Raja95f855c2023-03-01 13:11:42 +0000746stm32mp13_common_flags="${stm32mp1_common_flags} \
747 AARCH32_SP=optee \
Yann Gautier937684e2024-06-20 11:41:19 +0200748 DTB_FILE_NAME=stm32mp135f-dk.dtb \
Yann Gautierbd871522024-01-05 15:13:58 +0100749 PSA_FWU_SUPPORT=1 \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000750 STM32MP13=1"
751
Yann Gautier773c5502022-03-10 17:24:47 +0100752# STM32MP13 SDMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200753clean_build $(common_flags) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100754 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100755
Yann Gautierbd871522024-01-05 15:13:58 +0100756# STM32MP13 SDMMC boot with FWU
Yann Gautierb6821192024-06-19 10:45:56 +0200757clean_build $(common_flags) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierbd871522024-01-05 15:13:58 +0100758 PSA_FWU_SUPPORT=1 \
759 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
760
Lionel Debieve8f464c02022-10-13 09:25:45 +0200761# STM32MP13 TBBR
Yann Gautierb6821192024-06-19 10:45:56 +0200762clean_build $(common_flags release) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200763 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100764 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200765
Yann Gautiera66e5012022-12-13 13:52:35 +0100766# STM32MP13 TBBR DECRYPTION AES GCM
Yann Gautierb6821192024-06-19 10:45:56 +0200767clean_build $(common_flags release) ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100768 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
769 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
770 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
771
Yann Gautier868044b2024-06-19 10:42:51 +0200772stm32mp2_common_flags="ARCH=aarch64 \
Yann Gautiere9da1e22023-08-11 14:50:04 +0200773 CROSS_COMPILE=aarch64-none-elf- \
774 PLAT=stm32mp2"
775
776# STM32MP25 SDMMC boot
Yann Gautierb6821192024-06-19 10:45:56 +0200777clean_build $(common_flags) ${stm32mp2_common_flags} STM32MP_SDMMC=1 \
Yann Gautiere9da1e22023-08-11 14:50:04 +0200778 SPD=opteed STM32MP_DDR4_TYPE=1 \
779 BUILD_PLAT=build/stm32mp2-mp25-sdmmc/debug
780
Yann Gautier83dc8702024-03-19 15:07:26 +0100781# STM32MP25 USB boot
Yann Gautierb6821192024-06-19 10:45:56 +0200782clean_build $(common_flags) ${stm32mp2_common_flags} STM32MP_USB_PROGRAMMER=1 \
Yann Gautier83dc8702024-03-19 15:07:26 +0100783 SPD=opteed STM32MP_DDR4_TYPE=1 \
Yann Gautier63ee8832024-03-20 13:49:15 +0100784 BUILD_PLAT=build/stm32mp2-mp25-usb/debug
Yann Gautier83dc8702024-03-19 15:07:26 +0100785
Zelalemc9531f82020-08-04 15:37:08 -0500786# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500787make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500788make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500789
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500790clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500791# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500792clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500793 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800794# Use GICV3 driver with SDEI support
795clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
796 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500797# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500798clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500799 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
800 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100801# QEMU with SPMD support
802clean_build PLAT=qemu $(common_flags) BL32=Makefile \
803 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
804 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530805# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500806clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Raymond Mao7681ba02023-08-10 14:05:44 -0700807# Transfer List
808clean_build PLAT=qemu $(common_flags) TRANSFER_LIST=1
Zelalemc9531f82020-08-04 15:37:08 -0500809
Jean-Philippe Bruckerb586eee2023-11-02 18:13:30 +0000810# FEAT_RME
811clean_build PLAT=qemu $(common_flags) ENABLE_RME=1 \
812 QEMU_USE_GIC_DRIVER=QEMU_GICV3
813
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500814clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200815
Zelalemd86e8762020-08-21 18:24:28 -0500816# QEMU with SPM support
817clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300818 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500819
Fathi Boudra422bf772019-12-02 11:10:16 +0200820# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500821make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
822make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200823make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
824 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500825make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200826
Zelalemc9531f82020-08-04 15:37:08 -0500827# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500828clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
829clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200830
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500831clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500832 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
833 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500834
835# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500836clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500837 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500838
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500839# Support for BL2 and TBBR
840clean_build PLAT=synquacer $(common_flags) \
841 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
842 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
843
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500844make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200845
Zelalemc9531f82020-08-04 15:37:08 -0500846# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500847make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500848 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100849clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Mario Bălănicăea4da5e2024-03-08 20:09:24 +0200850clean_build PLAT=rpi5 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200851
Zelalemc9531f82020-08-04 15:37:08 -0500852# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500853clean_build PLAT=axg $(common_flags) SPD=opteed
854clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500855
Stephan Gerhold141a7662021-12-07 20:42:14 +0100856# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200857clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
858 ARCH=aarch32 AARCH32_SP=sp_min
859clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
860 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100861clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100862clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
863 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200864clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200865clean_build PLAT=msm8939 $(common_flags)
866clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
867 ARCH=aarch32 AARCH32_SP=sp_min
868clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100869
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800870# Platforms from Aspeed
871clean_build PLAT=ast2700 $(common_flags) SPD=opteed
872
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200873# Nuvoton npcm845x platform
874make PLAT=npcm845x $(common_flags) all SPD=opteed
875
Harrison Mutaiee958c12023-09-06 12:16:21 +0100876if [[ "$rc" -gt 0 ]]; then
Harrison Mutai3f483132024-05-09 09:48:58 +0000877 echo "ERROR: tf-cov-make failed with $error_count failures"
Harrison Mutaiee958c12023-09-06 12:16:21 +0100878 exit $rc
879fi
880
Fathi Boudra422bf772019-12-02 11:10:16 +0200881cd ..