blob: 21202bf61af6885e51dbbdfd7799e85036b22feb [file] [log] [blame]
Rupinderjit Singh385f17d2022-07-18 20:28:10 +01001#!/usr/bin/env bash
2#
3# Copyright (c) 2022, Arm Limited. All rights reserved.
4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
Manish V Badarkheee82f622022-10-14 16:45:23 +01008set_model_path "$warehouse/SysGen/SubSystemModels/11.18/28/models/$model_flavour/FVP_TC2"
Rupinderjit Singh385f17d2022-07-18 20:28:10 +01009
10cat <<EOF >"$model_param_file"
Chris Kaye6a6ec82023-01-31 16:43:49 +000011-C board.terminal_0.start_port=5000
12-C board.terminal_1.start_port=5001
13-C css.terminal_uart1_ap.start_port=5002
14-C css.terminal_uart_ap.start_port=5003
15-C soc.terminal_s0.start_port=5004
16-C soc.terminal_s1.start_port=5005
17
Rupinderjit Singh385f17d2022-07-18 20:28:10 +010018${fip_bin+-C board.flashloader0.fname=$fip_bin}
19${initrd_bin+--data board.dram=$initrd_bin@${initrd_addr:?}}
20${kernel_bin+--data board.dram=$kernel_bin@${kernel_addr:?}}
21${uart0_out+-C soc.pl011_uart0.out_file=$uart0_out}
22${uart0_out+-C soc.pl011_uart0.unbuffered_output=1}
23${uart1_out+-C soc.pl011_uart1.out_file=$uart1_out}
24${uart1_out+-C soc.pl011_uart1.unbuffered_output=1}
Rupinderjit Singh396938a2022-07-22 21:19:41 +010025-C displayController=2
Manish V Badarkhe93093dd2022-11-09 10:29:27 +000026${rss_rom_bin+--data css.rss.cpu=$rss_rom_bin@${rss_rom_addr:?}}
27${rss_flash_bin+--data css.rss.cpu=$rss_flash_bin@${rss_flash_addr:?}}
Rupinderjit Singh396938a2022-07-22 21:19:41 +010028${vmmaddrwidth+-C css.rss.VMADDRWIDTH=$vmmaddrwidth}
29${rvbaddr_lw+-C css.scp.c0_pik.rvbaraddr_lw=$rvbaddr_lw}
30${rvbaddr_up+-C css.scp.c0_pik.rvbaraddr_up=$rvbaddr_up}
Rupinderjit Singh385f17d2022-07-18 20:28:10 +010031EOF