blob: c0485327712cafce7fddd8231e8e962a10062953 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Govindraj Raja95f855c2023-03-01 13:11:42 +00003# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
Harrison Mutaiee958c12023-09-06 12:16:21 +010017set -E
18trap 'rc=$?; error_count=$((error_count+1));' ERR INT
Fathi Boudra422bf772019-12-02 11:10:16 +020019
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Manish V Badarkhe58a88f02023-11-06 21:42:11 +000037# Get TF-M tests and extras repo for TC build with tf-m test suite.
38if [ ! -d "$TF_M_TESTS_DIR" ]; then
39 git clone "$TF_M_TESTS_URL_REPO" "$TF_M_TESTS_DIR"
40 cd "$TF_M_TESTS_DIR"
Manish V Badarkhed89b71d2024-02-17 23:39:23 +000041 git checkout main
Manish V Badarkhe58a88f02023-11-06 21:42:11 +000042fi
43
44cd "$TF_SOURCES"
45
46if [ ! -d "$TF_M_EXTRAS_DIR" ]; then
47 git clone "$TF_M_EXTRAS_URL_REPO" "$TF_M_EXTRAS_DIR"
48 cd "$TF_M_EXTRAS_DIR"
Manish V Badarkhed89b71d2024-02-17 23:39:23 +000049 git checkout main
Manish V Badarkhe58a88f02023-11-06 21:42:11 +000050fi
51
Fathi Boudra422bf772019-12-02 11:10:16 +020052cd "$TF_SOURCES"
53
54# Clean TF source dir to make sure we don't analyse temporary files.
55make distclean
56
57#
58# Build TF in different configurations to get as much coverage as possible
59#
60
Fathi Boudra422bf772019-12-02 11:10:16 +020061#
62# FVP platform
63# We'll use the following flags for all FVP builds.
64#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050065fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020066
67# Try all possible SPDs.
Chris Kayab29d432023-08-10 13:06:18 +000068clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
69 SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020070clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
Sona Mathew40e5be92023-08-10 16:31:45 -050071 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe48ed0bf2023-06-28 09:33:16 +010072clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
Elizabeth Ho1a04df12023-07-27 16:06:24 +010073clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhee7528ff2023-07-01 10:20:05 +010074clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \
75 SPD_PNCD_S_IRQ=15 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +020076
Zelalemc9531f82020-08-04 15:37:08 -050077# Dualroot chain of trust.
78clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
79
laurenw-armf48e9d22022-04-22 11:30:13 -050080# FEAT_RME with CCA chain of trust.
Manish V Badarkhe5304aaf2023-08-18 14:38:20 +010081clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} USE_ROMLIB=1 \
Manish V Badarkhed5e9c752023-11-07 17:57:36 +000082 ENABLE_RME=1 MEASURED_BOOT=1
laurenw-armf48e9d22022-04-22 11:30:13 -050083
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050084clean_build $fvp_common_flags SPD=trusty
85clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020086
Sona Mathewff9c2a72023-05-10 21:18:01 -050087# ERRATA ABI
88clean_build $fvp_common_flags ERRATA_ABI_SUPPORT=1
89
Fathi Boudra422bf772019-12-02 11:10:16 +020090# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050091clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020092
Zelalemc9531f82020-08-04 15:37:08 -050093# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050094clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050095
Zelalem4f3633e2021-06-18 11:53:47 -050096# PCI Service
97clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
98
Zelalemc9531f82020-08-04 15:37:08 -050099# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500100clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -0500101
Fathi Boudra422bf772019-12-02 11:10:16 +0200102# Without coherent memory
Sona Mathewa06f62d2023-08-24 16:34:13 -0500103clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
104 USE_COHERENT_MEM=0 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200105
106# Using PSCI extended State ID format rather than the original format
Sona Mathewa06f62d2023-08-24 16:34:13 -0500107clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd \
108 PSCI_EXTENDED_STATE_ID=1 ARM_RECOM_STATE_ID_ENC=1 FVP_TRUSTED_SRAM_SIZE=384
Fathi Boudra422bf772019-12-02 11:10:16 +0200109
110# Alternative boot flows (This changes some of the platform initialisation code)
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100111clean_build $fvp_common_flags EL3_PAYLOAD_BASE=0x80000000
Fathi Boudra422bf772019-12-02 11:10:16 +0200112clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
113
114# Using the SP804 timer instead of the Generic Timer
115clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
116
117# Using the CCN driver and multi cluster topology
118clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
119
120# PMF
121clean_build $fvp_common_flags ENABLE_PMF=1
122
123# stack protector
124clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
125
126# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500127clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200128 ARCH=aarch32 AARCH32_SP=sp_min \
129 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500130clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200131 ARCH=aarch32 AARCH32_SP=sp_min
132
133# Xlat tables lib version 1 (AArch64 and AArch32)
134clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500135clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200136 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
137
Zelalemc9531f82020-08-04 15:37:08 -0500138# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000139clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200140
Zelalemc9531f82020-08-04 15:37:08 -0500141# SPM support with TOS(optee) as SPM sitting at S-EL1
142clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
143
Shruti Gupta8cc89b92022-08-09 12:23:46 +0100144# SPM support with SPM at EL3 and TSP at S-EL1
145clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 CTX_INCLUDE_EL2_REGS=0 EL3_EXCEPTION_HANDLING=0 \
146 SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1 \
147 ARM_SPMC_MANIFEST_DTS=plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
148
Zelalemc9531f82020-08-04 15:37:08 -0500149# SPM support with Secure hafnium as SPM sitting at S-EL2
150# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
151# if we have NULL value to it, so passing a dummy string.
152clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000153 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200154
J-Alves85ba07b2023-07-12 14:37:45 +0100155# SPM support with logical partitions in the SPMD.
156clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
157 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy ENABLE_SPMD_LP=1
158
Marc Bonnici502fdaa2022-01-10 12:38:23 +0000159# SPM support with SPM sitting at EL3
160clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
161
Harrison Mutaib352c0e2023-08-11 18:27:57 +0100162# Firmware Handoff framework support
163clean_build $fvp_common_flags TRANSFER_LIST=1
164
Fathi Boudra422bf772019-12-02 11:10:16 +0200165#BL2 at EL3 support
Harrison Mutaic3c8cfc2023-09-05 12:03:03 +0100166clean_build $fvp_common_flags RESET_TO_BL2=1 FVP_TRUSTED_SRAM_SIZE=384
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500167clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000168 ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200169
Zelalemc9531f82020-08-04 15:37:08 -0500170# RAS Extension Support
Manish Pandeyc1fa25b2023-02-16 17:35:36 +0000171clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100172 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 \
Manish Pandey010e9b42023-04-24 15:49:27 +0100173 SDEI_SUPPORT=1 PLATFORM_TEST_RAS_FFH=1
Zelalemc9531f82020-08-04 15:37:08 -0500174
Manish Pandeyfd4c6b72023-04-24 10:29:52 +0100175# EA handled in EL3 first
176clean_build $fvp_common_flags HANDLE_EA_EL3_FIRST_NS=1 PLATFORM_TEST_EA_FFH=1
177
Zelalemc9531f82020-08-04 15:37:08 -0500178# Hardware Assisted Coherency(DynamIQ)
179clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
180 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
181
182# Pointer Authentication Support
183clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
Sona Mathewa06f62d2023-08-24 16:34:13 -0500184 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd \
Sona Mathew08c17962023-08-28 09:36:17 -0500185 TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
Zelalemc9531f82020-08-04 15:37:08 -0500186
187# Undefined Behaviour Sanitizer
188# Building with UBSAN SANITIZE_UB=on increases the executable size.
189# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
190make $fvp_common_flags clean
Manish V Badarkhe4e79cab2023-09-07 10:07:58 +0100191make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 FVP_TRUSTED_SRAM_SIZE=384 bl31
Zelalemc9531f82020-08-04 15:37:08 -0500192
193# debugfs feature
194clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
195
196# MPAM feature
Arvind Ram Prakashbd4e43a2023-10-02 11:12:34 -0500197clean_build $fvp_common_flags ENABLE_FEAT_MPAM=1
Zelalemc9531f82020-08-04 15:37:08 -0500198
199# Using GICv3.1 driver with extended PPI and SPI range
200clean_build $fvp_common_flags GIC_EXT_INTID=1
201
202# Using GICv4 features with extended PPI and SPI range
203clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
204
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100205# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500206clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1 USE_ROMLIB=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100207
Manish V Badarkhef43e3f52022-06-21 20:37:25 +0100208# DRTM
209clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 DRTM_SUPPORT=1 USE_ROMLIB=1
210
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100211# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100212clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100213
Chris Kayf4789fe2023-06-12 15:52:28 +0100214# PSA FWU support
215clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1 FVP_TRUSTED_SRAM_SIZE=384
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100216
Manish V Badarkhe92616ae2023-09-18 10:06:00 +0100217# PSA Crypto support
218clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} PSA_CRYPTO=1 FVP_TRUSTED_SRAM_SIZE=384
219
johpow01153c8b22021-11-03 14:38:36 -0500220# SME and HCX features
221clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
222
Jayanth Dodderi Chidanand41edd012023-01-12 14:50:34 +0000223# SME2
224clean_build $fvp_common_flags ENABLE_SME2_FOR_NS=1 ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
225
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100226# Architectural Feature Detection mechanism
227clean_build $fvp_common_flags FEATURE_DETECTION=1
228
Manish Pandeye3561fd2023-01-05 10:46:25 +0000229# RNG trap feature
230clean_build $fvp_common_flags ENABLE_FEAT_RNG=1 ENABLE_FEAT_RNG_TRAP=1
231
Yi Choua765ae42023-05-26 15:51:02 +0800232# OPTEE_ALLOW_SMC_LOAD and CROS_WIDEVINE_SMC features
233clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 CROS_WIDEVINE_SMC=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
Jeffrey Kardatzke09e18e22023-01-25 12:24:13 -0800234
Jayanth Dodderi Chidanand508936d2023-12-22 14:33:38 +0000235# Report Context_Memory
236clean_build $fvp_common_flags PLATFORM_REPORT_CTX_MEM_USE=1
237
Fathi Boudra422bf772019-12-02 11:10:16 +0200238#
239# Juno platform
240# We'll use the following flags for all Juno builds.
241#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500242juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200243clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
Elizabeth Ho4cdb2f42023-07-11 12:27:14 +0100244clean_build $juno_common_flags EL3_PAYLOAD_BASE=0x80000000
Manish V Badarkhe05626442023-09-12 09:54:50 +0100245clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1
246clean_build $juno_common_flags ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=strong ETHOSN_NPU_DRIVER=1 ETHOSN_NPU_TZMP1=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200247clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500248
Jayanth Dodderi Chidanand055394a2022-10-19 09:20:20 +0100249# TRNG Service
250clean_build $juno_common_flags TRNG_SUPPORT=1
251
Fathi Boudra422bf772019-12-02 11:10:16 +0200252#
Fathi Boudra422bf772019-12-02 11:10:16 +0200253# System Guidance for Infrastructure platform RD-E1Edge
254#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500255make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500256
257#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530258# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500259#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530260make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500261
262#
Aditya Angadi61c54762021-01-04 09:30:52 +0530263# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500264#
Aditya Angadi61c54762021-01-04 09:30:52 +0530265make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500266
267#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530268# Reference Design Platform RD-N2
269#
270make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
Omkar Anand Kulkarnif6e268e2023-06-21 20:32:22 +0530271# RAS Extension Support
272make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
Manish Pandeyf3816802023-10-11 17:13:58 +0100273 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
274
Nishant Sharmabd7092e2023-10-11 09:17:13 +0100275# SPMC At EL3 Support
276make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
277 SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
278 PLAT_RO_XLAT_TABLES=1 all
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530279
280#
Zelalemc9531f82020-08-04 15:37:08 -0500281# Neoverse N1 SDP platform
282#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500283make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500284
285#
286# FVP VE platform
287#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500288make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500289 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
290 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
291 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
292
293#
294# A5 DesignStart Platform
295#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500296make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500297 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
298 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
299
300#
301# Corstone700 Platform
302#
303
304corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500305 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500306 PLAT=corstone700 \
307 ARCH=aarch32 \
308 RESET_TO_SP_MIN=1 \
309 AARCH32_SP=sp_min \
310 ARM_LINUX_KERNEL_AS_BL33=0 \
311 ARM_PRELOADED_DTB_BASE=0x80400000 \
312 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500313 ENABLE_STACK_PROTECTOR=all \
314 all"
315
316echo "Info: Building Corstone700 FVP ..."
317
318make TARGET_PLATFORM=fvp ${corstone700_common_flags}
319
320echo "Info: Building Corstone700 FPGA ..."
321
322make TARGET_PLATFORM=fpga ${corstone700_common_flags}
323
324#
325# Arm internal FPGA port
326#
Andre Przywara13361b62022-04-26 11:16:55 +0100327make PLAT=arm_fpga $(common_flags release) \
328 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500329
330#
Usama Arifcba711d2021-08-04 15:53:42 +0100331# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500332#
laurenw-arm915f70a2023-07-14 16:20:49 -0500333clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS}
334clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} MEASURED_BOOT=1
335clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-rotpk
336clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=rss-nv-counters
Manish V Badarkhe58a88f02023-11-06 21:42:11 +0000337clean_build $(common_flags) PLAT=tc TARGET_PLATFORM=2 ${ARM_TBB_OPTIONS} PLATFORM_TEST=tfm-testsuite \
338 MEASURED_BOOT=1 TF_M_TESTS_PATH=$(pwd)/tf-m-tests TF_M_EXTRAS_PATH=$(pwd)/tf-m-extras
Fathi Boudra422bf772019-12-02 11:10:16 +0200339
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530340#
341# Morello platform
342#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530343clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
344clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530345
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100346#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000347# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100348#
349
350make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000351 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100352 SPD=spmd \
353 TARGET_PLATFORM=fpga \
354 ENABLE_STACK_PROTECTOR=strong \
355 ENABLE_PIE=1 \
Maksims Svecovs7a0da522023-03-06 16:28:27 +0000356 RESET_TO_BL2=1 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100357 SPMD_SPM_AT_SEL2=0 \
358 ${ARM_TBB_OPTIONS} \
359 CREATE_KEYS=1 \
360 COT=tbbr \
361 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
362 bl2 \
363 bl31
364
johpow01aac58582021-10-05 16:51:34 -0500365#
366# FVP-R platform
367#
368clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
369
Fathi Boudra422bf772019-12-02 11:10:16 +0200370# Partners' platforms.
371# Enable as many features as possible.
372# We don't need to clean between each build here because we only do one build
373# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200374
Manish Pandey9c0ee742021-07-08 09:55:59 +0100375# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500376make PLAT=mt8173 $(common_flags) all
377make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800378make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Bo-Chen Chen4d63afd2022-08-30 16:34:57 +0800379make PLAT=mt8188 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500380make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100381make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500382
383# Platforms from Qualcomm
384make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200385
Zelalemc9531f82020-08-04 15:37:08 -0500386make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500387 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600388make PLAT=rk3368 $(common_flags) COREBOOT=1 \
389 ENABLE_STACK_PROTECTOR=strong all
390make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
391 ENABLE_STACK_PROTECTOR=strong all
392make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
393 ENABLE_STACK_PROTECTOR=strong all
394make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
395 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200396
397# Although we do several consecutive builds for the Tegra platform below, we
398# don't need to clean between each one because the Tegra makefiles specify
399# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500400make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500401make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
402make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200403
404# For the Xilinx platform, artificially increase the extents of BL31 memory
405# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
406# If we keep the default values, BL31 doesn't fit when it is built with all
407# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500408make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200409 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500410 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200411 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
412 all
413
Zelalemc9531f82020-08-04 15:37:08 -0500414# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500415clean_build PLAT=versal $(common_flags)
416clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500417
Michal Simek0f135242022-09-20 15:24:56 +0200418# Build Xilinx Versal NET platform
419clean_build PLAT=versal_net $(common_flags)
420
Jayanth Dodderi Chidanand0a2dd1e2022-10-27 11:17:37 +0100421# Build Xilinx Versal NET without Platform Management support
422clean_build PLAT=versal_net $(common_flags) TFA_NO_PM=1
423
Zelalemc9531f82020-08-04 15:37:08 -0500424# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100425clean_build PLAT=sun50i_a64 $(common_flags release) all
426clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
427clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
428clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100429clean_build PLAT=sun50i_h6 $(common_flags) all
430clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
431clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
432clean_build PLAT=sun50i_h616 $(common_flags) all
433clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500434
435# Platforms from i.MX
436make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
437 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500438 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500439make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500440 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800441make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
laurenw-arm8531e702022-06-09 15:32:37 -0500442 MBOOT_EL_HASH_ALG=sha256 ${TBB_OPTIONS} all
Madhukar Pappireddyc3ec06b2022-05-18 11:15:16 -0500443make PLAT=imx8mn $(common_flags) SDEI_SUPPORT=1 all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800444make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500445
Jacky Baib6cecc82021-06-07 09:49:46 +0800446# Due to the limited OCRAM space that can be used for TF-A, build test
447# will report failure caused by too small RAM size, so comment out the
448# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500449# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800450#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500451
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500452make PLAT=imx8qm $(common_flags) all
453make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500454
Jacky Bai87091a62023-06-21 16:25:12 +0800455make PLAT=imx93 $(common_flags) all
456
Olivier Deprezbac70192021-04-02 08:55:36 +0200457# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800458nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
459nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
460
461# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200462make PLAT=lx2160aqds $(common_flags) all
463make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500464
465#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800466clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
467 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500468
469#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800470clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
471 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500472 MBEDTLS_DIR=$(pwd)/mbedtls
473
474#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800475clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
476 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
477
478# Platform ls1028ardb
479clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
480clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
481clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
482
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800483# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800484clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
485clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
486clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200487
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800488# Platform ls1043ardb
489clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
490clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
491clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
492
493# ls1043ardb Secure Boot
494clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
495clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
496clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
497
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800498# ls1046ardb Secure Boot
499clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
500clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
501clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
502
503# ls1046afrwy Secure Boot
504clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
505clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
506
507# ls1046aqds Secure Boot
508clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
509clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
510clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
511clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
512
Jiafei Pan332cd792022-02-24 16:44:48 +0800513# ls1088ardb Secure Boot
514clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
515clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
516
517# ls1088aqds Secure Boot
518clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
519clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
520clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
521
Zelalemc9531f82020-08-04 15:37:08 -0500522# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500523make PLAT=stratix10 $(common_flags) all
524make PLAT=agilex $(common_flags) all
Sieu Mun Tang9081bac2023-05-29 18:08:24 +0800525make PLAT=agilex5 $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800526make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500527
528# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600529clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
530 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
531clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
532 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500533
534# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500535make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
Manish Pandey9ef33c52022-10-25 16:41:49 +0100536 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST_NS=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500537
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600538# Source files from mv-ddr-marvell repository are necessary
539# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000540wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
541tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600542mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500543
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600544# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200545make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200546 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200547make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200548 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200549make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200550 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200551make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200552 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200553make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
554 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200555make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200556 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200557make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200558 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500559make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
560 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500561
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600562# Removing the source files
563rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500564
565# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500566make PLAT=gxbb $(common_flags) all
567make PLAT=gxl $(common_flags) all
568make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500569
570# Platforms from Renesas
571# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500572clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500573 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
574 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
575 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
576 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
577
578# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500579clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500580 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
581 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
582 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
583 TRUSTED_BOARD_BOOT=1
584
585# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500586clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500587 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
588 SPD=opteed TRUSTED_BOARD_BOOT=1
589
590# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500591clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500592 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
593 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
594 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
595 TRUSTED_BOARD_BOOT=1
596
597# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500598clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500599 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
600 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
601 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
602
603# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500604clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500605 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
606 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
607 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
608
609# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500610clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500611 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
612 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
613 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
614
Zelalemf4299672021-01-29 12:52:59 -0600615# Renesas HiHope RZ/G2M development kit
616clean_build PLAT=rzg $(common_flags) \
617 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
618 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
619
Zelalemc9531f82020-08-04 15:37:08 -0500620# Platforms from ST
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100621stm32mp1_common_flags="$(common_flags) \
622 ARCH=aarch32 \
623 ARM_ARCH_MAJOR=7 \
624 CROSS_COMPILE=arm-none-eabi- \
625 ENABLE_STACK_PROTECTOR=strong \
626 PLAT=stm32mp1"
627
Yann Gautiera69cf792021-09-01 11:19:01 +0200628# STM32MP1 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000629make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200630 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100631 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200632
Yann Gautier15c45392023-08-21 11:03:33 +0200633# STM32MP1 SDMMC boot BL2 without AARCH32_SP
634make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
635 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
636 bl2
637
Yann Gautiera69cf792021-09-01 11:19:01 +0200638# STM32MP1 eMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000639make ${stm32mp1_common_flags} STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200640 BUILD_PLAT=build/stm32mp1-emmc/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100641 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200642
643# STM32MP1 Raw NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000644make ${stm32mp1_common_flags} STM32MP_RAW_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200645 BUILD_PLAT=build/stm32mp1-nand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100646 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200647
648# STM32MP1 SPI NAND boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000649make ${stm32mp1_common_flags} STM32MP_SPI_NAND=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200650 BUILD_PLAT=build/stm32mp1-snand/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100651 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200652
653# STM32MP1 SPI NOR boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000654make ${stm32mp1_common_flags} STM32MP_SPI_NOR=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200655 BUILD_PLAT=build/stm32mp1-snor/debug \
Govindraj Raja95f855c2023-03-01 13:11:42 +0000656 AARCH32_SP=sp_min bl2 bl32
Yann Gautiera69cf792021-09-01 11:19:01 +0200657
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100658# STM32MP1 UART boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000659make ${stm32mp1_common_flags} STM32MP_UART_PROGRAMMER=1 \
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100660 BUILD_PLAT=build/stm32mp1-uart/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100661 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100662
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200663# STM32MP1 USB boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000664make ${stm32mp1_common_flags} STM32MP_USB_PROGRAMMER=1 \
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200665 BUILD_PLAT=build/stm32mp1-usb/debug \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100666 AARCH32_SP=sp_min bl2 bl32
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200667
Lionel Debieve8f464c02022-10-13 09:25:45 +0200668# STM32MP1 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000669make ${stm32mp1_common_flags} STM32MP_SDMMC=1 \
Yann Gautier741e8492022-11-14 19:04:27 +0100670 BUILD_PLAT=build/stm32mp1-sdmmc-tbbr/debug \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200671 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100672 AARCH32_SP=sp_min bl2 bl32
Lionel Debieve8f464c02022-10-13 09:25:45 +0200673
Govindraj Raja95f855c2023-03-01 13:11:42 +0000674stm32mp13_common_flags="${stm32mp1_common_flags} \
675 AARCH32_SP=optee \
676 STM32MP13=1"
677
Yann Gautier773c5502022-03-10 17:24:47 +0100678# STM32MP13 SDMMC boot
Govindraj Raja95f855c2023-03-01 13:11:42 +0000679make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100680 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug bl2
Yann Gautier773c5502022-03-10 17:24:47 +0100681
Lionel Debieve8f464c02022-10-13 09:25:45 +0200682# STM32MP13 TBBR
Govindraj Raja95f855c2023-03-01 13:11:42 +0000683make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Lionel Debieve8f464c02022-10-13 09:25:45 +0200684 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
Yann Gautierdfd8aa82022-11-02 14:34:26 +0100685 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr/debug bl2
Lionel Debieve8f464c02022-10-13 09:25:45 +0200686
Yann Gautiera66e5012022-12-13 13:52:35 +0100687# STM32MP13 TBBR DECRYPTION AES GCM
Govindraj Raja95f855c2023-03-01 13:11:42 +0000688make ${stm32mp13_common_flags} STM32MP_SDMMC=1 \
Yann Gautiera66e5012022-12-13 13:52:35 +0100689 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
690 DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL32=1 \
691 BUILD_PLAT=build/stm32mp1-mp13-sdmmc-tbbr-dec/debug bl2
692
Yann Gautiere9da1e22023-08-11 14:50:04 +0200693stm32mp2_common_flags="$(common_flags) \
694 ARCH=aarch64 \
695 CROSS_COMPILE=aarch64-none-elf- \
696 PLAT=stm32mp2"
697
698# STM32MP25 SDMMC boot
699make ${stm32mp2_common_flags} STM32MP_SDMMC=1 \
700 SPD=opteed STM32MP_DDR4_TYPE=1 \
701 BUILD_PLAT=build/stm32mp2-mp25-sdmmc/debug
702
Zelalemc9531f82020-08-04 15:37:08 -0500703# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500704make PLAT=k3 $(common_flags) all
Hari Nagalladadd89f2022-08-30 12:10:00 -0500705make PLAT=k3 TARGET_BOARD=j784s4 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500706
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500707clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500708# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500709clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500710 ENABLE_STACK_PROTECTOR=strong
Dongjiu Geng72819ee2023-06-16 18:48:57 +0800711# Use GICV3 driver with SDEI support
712clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
713 ENABLE_STACK_PROTECTOR=strong SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -0500714# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500715clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500716 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
717 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100718# QEMU with SPMD support
719clean_build PLAT=qemu $(common_flags) BL32=Makefile \
720 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
721 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530722# Measured Boot
laurenw-arm8531e702022-06-09 15:32:37 -0500723clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} MBOOT_EL_HASH_ALG=sha256 MEASURED_BOOT=1
Raymond Mao7681ba02023-08-10 14:05:44 -0700724# Transfer List
725clean_build PLAT=qemu $(common_flags) TRANSFER_LIST=1
Zelalemc9531f82020-08-04 15:37:08 -0500726
Jean-Philippe Bruckerb586eee2023-11-02 18:13:30 +0000727# FEAT_RME
728clean_build PLAT=qemu $(common_flags) ENABLE_RME=1 \
729 QEMU_USE_GIC_DRIVER=QEMU_GICV3
730
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500731clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200732
Zelalemd86e8762020-08-21 18:24:28 -0500733# QEMU with SPM support
734clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Paul Sokolovskycf9fe862023-01-02 16:22:21 +0300735 EL3_EXCEPTION_HANDLING=1 ENABLE_SME_FOR_NS=0 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500736
Fathi Boudra422bf772019-12-02 11:10:16 +0200737# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500738make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
739make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
Lukas Haneld0752392022-10-13 11:13:19 +0200740make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} SPD=spmd SPMC_AT_EL3=1 \
741 SPMD_SPM_AT_SEL2=0 BL32=optee PLAT_SP_MANIFEST_DTS=foo NEED_FDT=no all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500742make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200743
Zelalemc9531f82020-08-04 15:37:08 -0500744# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500745clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
746clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200747
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500748clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Jassi Brar86080922022-06-27 14:16:34 -0500749 RESET_TO_BL31=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 \
750 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500751
752# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500753clean_build PLAT=synquacer $(common_flags) \
Jassi Brar86080922022-06-27 14:16:34 -0500754 RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
Zelalemc9531f82020-08-04 15:37:08 -0500755
Jassi Brarb8c7ca02022-06-27 14:22:10 -0500756# Support for BL2 and TBBR
757clean_build PLAT=synquacer $(common_flags) \
758 MBEDTLS_DIR=$(pwd)/mbedtls TRUSTED_BOARD_BOOT=1 \
759 SQ_USE_SCMI_DRIVER=1 SPD=opteed all
760
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500761make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200762
Zelalemc9531f82020-08-04 15:37:08 -0500763# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500764make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500765 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100766clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200767
Zelalemc9531f82020-08-04 15:37:08 -0500768# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500769clean_build PLAT=axg $(common_flags) SPD=opteed
770clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500771
Stephan Gerhold141a7662021-12-07 20:42:14 +0100772# QTI MSM8916 platform
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200773clean_build PLAT=mdm9607 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
774 ARCH=aarch32 AARCH32_SP=sp_min
775clean_build PLAT=msm8909 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
776 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold141a7662021-12-07 20:42:14 +0100777clean_build PLAT=msm8916 $(common_flags)
Manish V Badarkhec540e622023-06-28 17:56:40 +0100778clean_build PLAT=msm8916 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
779 ARCH=aarch32 AARCH32_SP=sp_min
Stephan Gerhold998f0d62023-04-17 16:22:52 +0200780clean_build PLAT=msm8916 $(common_flags) SPD=tspd
Stephan Gerhold3b3976f2023-04-17 16:27:11 +0200781clean_build PLAT=msm8939 $(common_flags)
782clean_build PLAT=msm8939 CROSS_COMPILE=arm-none-eabi- $(common_flags) \
783 ARCH=aarch32 AARCH32_SP=sp_min
784clean_build PLAT=msm8939 $(common_flags) SPD=tspd
Stephan Gerhold141a7662021-12-07 20:42:14 +0100785
Chia-Wei Wang7dcb0d02023-06-09 09:52:52 +0800786# Platforms from Aspeed
787clean_build PLAT=ast2700 $(common_flags) SPD=opteed
788
rutigl@gmail.com86cfcf92023-03-21 10:10:11 +0200789# Nuvoton npcm845x platform
790make PLAT=npcm845x $(common_flags) all SPD=opteed
791
Harrison Mutaiee958c12023-09-06 12:16:21 +0100792if [[ "$rc" -gt 0 ]]; then
793 echo "ERROR: tc-cov-make failed with $error_count failures"
794 exit $rc
795fi
796
Fathi Boudra422bf772019-12-02 11:10:16 +0200797cd ..