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Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Manish V Badarkhe107c8e32021-08-02 19:49:32 +01003# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
58
Zelalemc9531f82020-08-04 15:37:08 -050059# Dualroot chain of trust.
60clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
61
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050062clean_build $fvp_common_flags SPD=trusty
63clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020064
65# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050066clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020067
Zelalemc9531f82020-08-04 15:37:08 -050068# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050069clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050070
Zelalem4f3633e2021-06-18 11:53:47 -050071# PCI Service
72clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
73
Zelalemc9531f82020-08-04 15:37:08 -050074# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050075clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050076
Fathi Boudra422bf772019-12-02 11:10:16 +020077# Without coherent memory
78clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
79
80# Using PSCI extended State ID format rather than the original format
81clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
82 ARM_RECOM_STATE_ID_ENC=1
83
84# Alternative boot flows (This changes some of the platform initialisation code)
85clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
86clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
87
88# Using the SP804 timer instead of the Generic Timer
89clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
90
91# Using the CCN driver and multi cluster topology
92clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
93
94# PMF
95clean_build $fvp_common_flags ENABLE_PMF=1
96
97# stack protector
98clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
99
100# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500101clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200102 ARCH=aarch32 AARCH32_SP=sp_min \
103 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500104clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200105 ARCH=aarch32 AARCH32_SP=sp_min
106
107# Xlat tables lib version 1 (AArch64 and AArch32)
108clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500109clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200110 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
111
Zelalemc9531f82020-08-04 15:37:08 -0500112# SPM support based on Management Mode Interface Specification
113clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200114
Zelalemc9531f82020-08-04 15:37:08 -0500115# SPM support with TOS(optee) as SPM sitting at S-EL1
116clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
117
118# SPM support with Secure hafnium as SPM sitting at S-EL2
119# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
120# if we have NULL value to it, so passing a dummy string.
121clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000122 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200123
124#BL2 at EL3 support
125clean_build $fvp_common_flags BL2_AT_EL3=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500126clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200127 ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
128
Zelalemc9531f82020-08-04 15:37:08 -0500129# RAS Extension Support
130clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
131 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 \
132 SDEI_SUPPORT=1
133
134# Hardware Assisted Coherency(DynamIQ)
135clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
136 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
137
138# Pointer Authentication Support
139clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
140 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
141
142# Undefined Behaviour Sanitizer
143# Building with UBSAN SANITIZE_UB=on increases the executable size.
144# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
145make $fvp_common_flags clean
146make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
147
148# debugfs feature
149clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
150
151# MPAM feature
152clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
153
154# Using GICv3.1 driver with extended PPI and SPI range
155clean_build $fvp_common_flags GIC_EXT_INTID=1
156
157# Using GICv4 features with extended PPI and SPI range
158clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
159
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100160# Measured Boot
161clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} MEASURED_BOOT=1
162
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100163# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100164clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100165
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100166# PSA FWU support
167clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
168
Gary Morrisond57f3d92021-09-15 15:33:21 -0500169# FVP-R platform
170clean_build PLAT=fvp_r $(common_flags) all
171
Fathi Boudra422bf772019-12-02 11:10:16 +0200172#
173# Juno platform
174# We'll use the following flags for all Juno builds.
175#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500176juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200177clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
178clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500179clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200180clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500181
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600182clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200183
184#
185# System Guidance for Infrastructure platform SGI575
Zelalemc9531f82020-08-04 15:37:08 -0500186# Enable build config with RAS_EXTENSION to cover more files
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500187make $(common_flags) PLAT=sgi575 ${ARM_TBB_OPTIONS} EL3_EXCEPTION_HANDLING=1 FAULT_INJECTION_SUPPORT=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500188 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 SDEI_SUPPORT=1 SPM_MM=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200189
190#
Vijayenthiran Subramaniam2a47a6d2020-07-22 14:16:58 +0530191# System Guidance for Infrastructure platform RD-N1-Edge-Dual
Fathi Boudra422bf772019-12-02 11:10:16 +0200192#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500193make $(common_flags) PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200194
195#
196# System Guidance for Infrastructure platform RD-E1Edge
197#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500198make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500199
200#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530201# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500202#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530203make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500204
205#
Aditya Angadi61c54762021-01-04 09:30:52 +0530206# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500207#
Aditya Angadi61c54762021-01-04 09:30:52 +0530208make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500209
210#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530211# Reference Design Platform RD-N2
212#
213make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
214
215#
Zelalemc9531f82020-08-04 15:37:08 -0500216# Neoverse N1 SDP platform
217#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500218make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500219
220#
221# FVP VE platform
222#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500223make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500224 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
225 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
226 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
227
228#
229# A5 DesignStart Platform
230#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500231make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500232 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
233 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
234
235#
236# Corstone700 Platform
237#
238
239corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500240 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500241 PLAT=corstone700 \
242 ARCH=aarch32 \
243 RESET_TO_SP_MIN=1 \
244 AARCH32_SP=sp_min \
245 ARM_LINUX_KERNEL_AS_BL33=0 \
246 ARM_PRELOADED_DTB_BASE=0x80400000 \
247 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500248 ENABLE_STACK_PROTECTOR=all \
249 all"
250
251echo "Info: Building Corstone700 FVP ..."
252
253make TARGET_PLATFORM=fvp ${corstone700_common_flags}
254
255echo "Info: Building Corstone700 FPGA ..."
256
257make TARGET_PLATFORM=fpga ${corstone700_common_flags}
258
259#
260# Arm internal FPGA port
261#
Andre Przywara268c5c72021-09-03 14:56:56 +0100262make PLAT=arm_fpga $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500263 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
264
265#
Usama Arifcba711d2021-08-04 15:53:42 +0100266# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500267#
Usama Arifcba711d2021-08-04 15:53:42 +0100268make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
269make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200270
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530271#
272# Morello platform
273#
274make $(common_flags) PLAT=morello all
275
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100276#
277# diphda Platform
278#
279
280make $(common_flags) \
281 PLAT=diphda \
282 SPD=spmd \
283 TARGET_PLATFORM=fpga \
284 ENABLE_STACK_PROTECTOR=strong \
285 ENABLE_PIE=1 \
286 BL2_AT_EL3=1 \
287 SPMD_SPM_AT_SEL2=0 \
288 ${ARM_TBB_OPTIONS} \
289 CREATE_KEYS=1 \
290 COT=tbbr \
291 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
292 bl2 \
293 bl31
294
Fathi Boudra422bf772019-12-02 11:10:16 +0200295# Partners' platforms.
296# Enable as many features as possible.
297# We don't need to clean between each build here because we only do one build
298# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200299
Manish Pandey9c0ee742021-07-08 09:55:59 +0100300# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500301make PLAT=mt8173 $(common_flags) all
302make PLAT=mt8183 $(common_flags) all
Zelalemd86e8762020-08-21 18:24:28 -0500303make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100304make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500305
306# Platforms from Qualcomm
307make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200308
Zelalemc9531f82020-08-04 15:37:08 -0500309make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500310 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600311make PLAT=rk3368 $(common_flags) COREBOOT=1 \
312 ENABLE_STACK_PROTECTOR=strong all
313make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
314 ENABLE_STACK_PROTECTOR=strong all
315make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
316 ENABLE_STACK_PROTECTOR=strong all
317make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
318 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200319
320# Although we do several consecutive builds for the Tegra platform below, we
321# don't need to clean between each one because the Tegra makefiles specify
322# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500323make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500324make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
325make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200326
327# For the Xilinx platform, artificially increase the extents of BL31 memory
328# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
329# If we keep the default values, BL31 doesn't fit when it is built with all
330# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500331make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200332 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500333 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200334 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
335 all
336
Zelalemc9531f82020-08-04 15:37:08 -0500337# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500338clean_build PLAT=versal $(common_flags)
339clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500340
341# Platforms from Allwinner
Andre Przywaracf78a512021-09-03 14:59:38 +0100342clean_build PLAT=sun50i_a64 $(common_flags) all
343clean_build PLAT=sun50i_a64 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
344clean_build PLAT=sun50i_a64 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
345clean_build PLAT=sun50i_h6 $(common_flags) all
346clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
347clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
348clean_build PLAT=sun50i_h616 $(common_flags) all
349clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500350
351# Platforms from i.MX
352make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
353 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500354 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500355make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500356 $(common_flags) all
357make PLAT=imx8mm $(common_flags) all
358make PLAT=imx8mn $(common_flags) all
359make PLAT=imx8mp $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500360
Jacky Baib6cecc82021-06-07 09:49:46 +0800361# Due to the limited OCRAM space that can be used for TF-A, build test
362# will report failure caused by too small RAM size, so comment out the
363# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500364# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800365#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500366
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500367make PLAT=imx8qm $(common_flags) all
368make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500369
Olivier Deprezbac70192021-04-02 08:55:36 +0200370# Platforms for NXP Layerscape
371make PLAT=lx2160aqds $(common_flags) all
372make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500373
374#CSF Based CoT:
375clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor SPD=opteed \
376 TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) DDR_PHY_BIN_PATH=$(pwd)
377
378#X509 Based CoT
379clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor SPD=opteed \
380 TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) GENERATE_COT=1 \
381 MBEDTLS_DIR=$(pwd)/mbedtls
382
383#BOOT_MODE=emmc and Stack protector
384clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc SPD=opteed \
385 TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) ENABLE_STACK_PROTECTOR=strong
Olivier Deprezbac70192021-04-02 08:55:36 +0200386
Zelalemc9531f82020-08-04 15:37:08 -0500387# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500388make PLAT=stratix10 $(common_flags) all
389make PLAT=agilex $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500390
391# Platforms from Broadcom
Olivier Deprez07cc98b2021-04-02 09:56:55 +0200392clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500393clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 INCLUDE_EMMC_DRIVER_ERASE_CODE=1
Zelalemc9531f82020-08-04 15:37:08 -0500394
395# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500396make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
397 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500398
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600399# Source files from mv-ddr-marvell repository are necessary
400# to build below four platforms
Pali Rohár6d8ddb42021-07-15 21:33:50 +0200401wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-02e23dbcf8dd22e038986052d99319a0eba8f25f.tar.gz 2> /dev/null
402tar -xzf mv-ddr-marvell-02e23dbcf8dd22e038986052d99319a0eba8f25f.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600403mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500404
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600405# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200406make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200407 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200408make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200409 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200410make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200411 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200412make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200413 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200414make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200415 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200416make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200417 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500418make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
419 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500420
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600421# Removing the source files
422rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500423
424# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500425make PLAT=gxbb $(common_flags) all
426make PLAT=gxl $(common_flags) all
427make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500428
429# Platforms from Renesas
430# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500431clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500432 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
433 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
434 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
435 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
436
437# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500438clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500439 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
440 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
441 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
442 TRUSTED_BOARD_BOOT=1
443
444# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500445clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500446 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
447 SPD=opteed TRUSTED_BOARD_BOOT=1
448
449# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500450clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500451 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
452 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
453 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
454 TRUSTED_BOARD_BOOT=1
455
456# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500457clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500458 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
459 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
460 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
461
462# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500463clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500464 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
465 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
466 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
467
468# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500469clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500470 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
471 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
472 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
473
Zelalemf4299672021-01-29 12:52:59 -0600474# Renesas HiHope RZ/G2M development kit
475clean_build PLAT=rzg $(common_flags) \
476 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
477 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
478
Zelalemc9531f82020-08-04 15:37:08 -0500479# Platforms from ST
480make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500481 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_EMMC=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500482 STM32MP_RAW_NAND=1 STM32MP_SDMMC=1 STM32MP_SPI_NAND=1 STM32MP_SPI_NOR=1 \
483 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl1 bl2 bl32
484
485# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500486make PLAT=k3 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500487
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500488clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500489# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500490clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500491 ENABLE_STACK_PROTECTOR=strong
492# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500493clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500494 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
495 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
496
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500497clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200498
Zelalemd86e8762020-08-21 18:24:28 -0500499# QEMU with SPM support
500clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
501 EL3_EXCEPTION_HANDLING=1
502
Fathi Boudra422bf772019-12-02 11:10:16 +0200503# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500504make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
505make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
506make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200507
Zelalemc9531f82020-08-04 15:37:08 -0500508# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500509clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
510clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200511
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500512clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500513 EL3_EXCEPTION_HANDLING=1 PRELOADED_BL33_BASE=0x0
514
515# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500516clean_build PLAT=synquacer $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500517 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
518
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500519make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200520
Zelalemc9531f82020-08-04 15:37:08 -0500521# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500522make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500523 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100524clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200525
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500526# Cannot use $(common_flags) for LS1043 platform, as then
Fathi Boudra422bf772019-12-02 11:10:16 +0200527# the binaries do not fit in memory.
528clean_build PLAT=ls1043 SPD=opteed ENABLE_STACK_PROTECTOR=strong
529clean_build PLAT=ls1043 SPD=tspd
530
Zelalemc9531f82020-08-04 15:37:08 -0500531# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500532clean_build PLAT=axg $(common_flags) SPD=opteed
533clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500534
Fathi Boudra422bf772019-12-02 11:10:16 +0200535cd ..