blob: 34ad438863f9ace896e15d68c6cf303527052407 [file] [log] [blame]
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -05001#!/usr/bin/env bash
Fathi Boudra422bf772019-12-02 11:10:16 +02002#
Yann Gautier773c5502022-03-10 17:24:47 +01003# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
Fathi Boudra422bf772019-12-02 11:10:16 +02004#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8#
9# This script builds the TF in different configs.
10# Rather than telling cov-build to build TF using a simple 'make all' command,
11# the goal here is to combine several build flags to analyse more of our source
12# code in a single 'build'. The Coverity Scan service does not have the notion
13# of separate types of build - there is just one linear sequence of builds in
14# the project history.
15#
16
17# Bail out as soon as an error is encountered.
18set -e
19
20TF_SOURCES=$1
21if [ ! -d "$TF_SOURCES" ]; then
22 echo "ERROR: '$TF_SOURCES' does not exist or is not a directory"
23 echo "Usage: $(basename "$0") <trusted-firmware-directory>"
24 exit 1
25fi
26
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050027containing_dir="$(readlink -f "$(dirname "$0")/")"
28. $containing_dir/common-def.sh
29
Fathi Boudra422bf772019-12-02 11:10:16 +020030# Get mbed TLS library code to build Trusted Firmware with Trusted Board Boot
31# support. The version of mbed TLS to use here must be the same as when
32# building TF in the usual context.
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050033if [ ! -d "$MBED_TLS_DIR" ]; then
34 git clone -q --depth 1 -b "$MBED_TLS_SOURCES_TAG" "$MBED_TLS_URL_REPO" "$MBED_TLS_DIR"
Fathi Boudra422bf772019-12-02 11:10:16 +020035fi
Leonardo Sandovalc4dfbb02020-08-17 10:21:44 -050036
Fathi Boudra422bf772019-12-02 11:10:16 +020037cd "$TF_SOURCES"
38
39# Clean TF source dir to make sure we don't analyse temporary files.
40make distclean
41
42#
43# Build TF in different configurations to get as much coverage as possible
44#
45
Fathi Boudra422bf772019-12-02 11:10:16 +020046#
47# FVP platform
48# We'll use the following flags for all FVP builds.
49#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050050fvp_common_flags="$(common_flags) PLAT=fvp"
Fathi Boudra422bf772019-12-02 11:10:16 +020051
52# Try all possible SPDs.
53clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
54clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
55 TSP_NS_INTR_ASYNC_PREEMPT=1
56clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
57clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
58
Zelalemc9531f82020-08-04 15:37:08 -050059# Dualroot chain of trust.
60clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tspd COT=dualroot
61
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050062clean_build $fvp_common_flags SPD=trusty
63clean_build $fvp_common_flags SPD=trusty TRUSTY_SPD_WITH_GENERIC_SERVICES=1
Fathi Boudra422bf772019-12-02 11:10:16 +020064
65# SDEI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050066clean_build $fvp_common_flags SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Fathi Boudra422bf772019-12-02 11:10:16 +020067
Zelalemc9531f82020-08-04 15:37:08 -050068# SDEI with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050069clean_build $fvp_common_flags SDEI_IN_FCONF=1 SDEI_SUPPORT=1 EL3_EXCEPTION_HANDLING=1
Zelalemc9531f82020-08-04 15:37:08 -050070
Zelalem4f3633e2021-06-18 11:53:47 -050071# PCI Service
72clean_build $fvp_common_flags SMC_PCI_SUPPORT=1
73
Zelalemc9531f82020-08-04 15:37:08 -050074# Secure interrupt descriptors with fconf
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -050075clean_build $fvp_common_flags SEC_INT_DESC_IN_FCONF=1
Zelalemc9531f82020-08-04 15:37:08 -050076
Fathi Boudra422bf772019-12-02 11:10:16 +020077# Without coherent memory
78clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd USE_COHERENT_MEM=0
79
80# Using PSCI extended State ID format rather than the original format
81clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd PSCI_EXTENDED_STATE_ID=1 \
82 ARM_RECOM_STATE_ID_ENC=1
83
84# Alternative boot flows (This changes some of the platform initialisation code)
85clean_build $fvp_common_flags EL3_PAYLOAD=0x80000000
86clean_build $fvp_common_flags PRELOADED_BL33_BASE=0x80000000
87
88# Using the SP804 timer instead of the Generic Timer
89clean_build $fvp_common_flags FVP_USE_SP804_TIMER=1
90
91# Using the CCN driver and multi cluster topology
92clean_build $fvp_common_flags FVP_CLUSTER_COUNT=4
93
94# PMF
95clean_build $fvp_common_flags ENABLE_PMF=1
96
97# stack protector
98clean_build $fvp_common_flags ENABLE_STACK_PROTECTOR=strong
99
100# AArch32 build
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500101clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200102 ARCH=aarch32 AARCH32_SP=sp_min \
103 RESET_TO_SP_MIN=1 PRELOADED_BL33_BASE=0x80000000
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500104clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200105 ARCH=aarch32 AARCH32_SP=sp_min
106
107# Xlat tables lib version 1 (AArch64 and AArch32)
108clean_build $fvp_common_flags ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500109clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200110 ARCH=aarch32 AARCH32_SP=sp_min ARM_XLAT_TABLES_LIB_V1=1 RECLAIM_INIT_CODE=0
111
Zelalemc9531f82020-08-04 15:37:08 -0500112# SPM support based on Management Mode Interface Specification
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000113clean_build $fvp_common_flags SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Fathi Boudra422bf772019-12-02 11:10:16 +0200114
Zelalemc9531f82020-08-04 15:37:08 -0500115# SPM support with TOS(optee) as SPM sitting at S-EL1
116clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0
117
118# SPM support with Secure hafnium as SPM sitting at S-EL2
119# SP_LAYOUT_FILE is used only during FIP creation but build won't progress
120# if we have NULL value to it, so passing a dummy string.
121clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
Max Shvetsov44d2a702021-02-18 16:41:45 +0000122 CTX_INCLUDE_EL2_REGS=1 SP_LAYOUT_FILE=dummy
Fathi Boudra422bf772019-12-02 11:10:16 +0200123
124#BL2 at EL3 support
125clean_build $fvp_common_flags BL2_AT_EL3=1
Leonardo Sandoval1c24ae52020-07-08 11:47:23 -0500126clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
Fathi Boudra422bf772019-12-02 11:10:16 +0200127 ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
128
Zelalemc9531f82020-08-04 15:37:08 -0500129# RAS Extension Support
130clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
131 FAULT_INJECTION_SUPPORT=1 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 \
132 SDEI_SUPPORT=1
133
134# Hardware Assisted Coherency(DynamIQ)
135clean_build $fvp_common_flags FVP_CLUSTER_COUNT=1 FVP_MAX_CPUS_PER_CLUSTER=8 \
136 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0
137
138# Pointer Authentication Support
139clean_build $fvp_common_flags CTX_INCLUDE_PAUTH_REGS=1 \
140 ARM_ARCH_MINOR=5 EL3_EXCEPTION_HANDLING=1 BRANCH_PROTECTION=1 SDEI_SUPPORT=1 SPD=tspd TSP_NS_INTR_ASYNC_PREEMPT=1
141
142# Undefined Behaviour Sanitizer
143# Building with UBSAN SANITIZE_UB=on increases the executable size.
144# Hence it is only properly supported in bl31 with RESET_TO_BL31 enabled
145make $fvp_common_flags clean
146make $fvp_common_flags SANITIZE_UB=on RESET_TO_BL31=1 bl31
147
148# debugfs feature
149clean_build $fvp_common_flags DEBUG=1 USE_DEBUGFS=1
150
151# MPAM feature
152clean_build $fvp_common_flags ENABLE_MPAM_FOR_LOWER_ELS=1
153
154# Using GICv3.1 driver with extended PPI and SPI range
155clean_build $fvp_common_flags GIC_EXT_INTID=1
156
157# Using GICv4 features with extended PPI and SPI range
158clean_build $fvp_common_flags GIC_ENABLE_V4_EXTN=1 GIC_EXT_INTID=1
159
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100160# Measured Boot
Manish V Badarkhe36b884b2022-01-27 19:21:26 +0000161clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} TPM_HASH_ALG=sha256 MEASURED_BOOT=1
Alexei Fedorov20fdf502020-07-27 17:36:38 +0100162
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100163# CoT descriptors in device tree
Manish V Badarkhe81102d12020-10-05 08:02:30 +0100164clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} COT_DESC_IN_DTB=1 USE_ROMLIB=1
Manish V Badarkhe447e31a2020-09-03 07:57:17 +0100165
Manish V Badarkhe107c8e32021-08-02 19:49:32 +0100166# PSA FWU support
167clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_GPT_SUPPORT=1 PSA_FWU_SUPPORT=1 USE_ROMLIB=1
168
Zelalem Aweke773e19b2021-08-20 17:41:00 -0500169# FEAT_RME
170clean_build $fvp_common_flags ENABLE_RME=1
171
johpow01153c8b22021-11-03 14:38:36 -0500172# SME and HCX features
173clean_build $fvp_common_flags ENABLE_SME_FOR_NS=1 ENABLE_FEAT_HCX=1
174
Jayanth Dodderi Chidanand84da1962022-04-11 11:38:44 +0100175# Architectural Feature Detection mechanism
176clean_build $fvp_common_flags FEATURE_DETECTION=1
177
Fathi Boudra422bf772019-12-02 11:10:16 +0200178#
179# Juno platform
180# We'll use the following flags for all Juno builds.
181#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500182juno_common_flags="$(common_flags) PLAT=juno"
Fathi Boudra422bf772019-12-02 11:10:16 +0200183clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS}
184clean_build $juno_common_flags EL3_PAYLOAD=0x80000000
Madhukar Pappireddydcb31f62021-05-06 11:36:36 -0500185clean_build $juno_common_flags ENABLE_STACK_PROTECTOR=strong ARM_ETHOSN_NPU_DRIVER=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200186clean_build $juno_common_flags CSS_USE_SCMI_SDS_DRIVER=0
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500187
Leonardo Sandoval5163b562020-11-20 17:17:59 -0600188clean_build $juno_common_flags SPD=tspd ${ARM_TBB_OPTIONS} ARM_CRYPTOCELL_INTEG=1 CCSBROM_LIB_PATH=${CRYPTOCELL_LIB_PATH} KEY_SIZE=2048
Fathi Boudra422bf772019-12-02 11:10:16 +0200189
190#
191# System Guidance for Infrastructure platform SGI575
Zelalemc9531f82020-08-04 15:37:08 -0500192# Enable build config with RAS_EXTENSION to cover more files
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500193make $(common_flags) PLAT=sgi575 ${ARM_TBB_OPTIONS} EL3_EXCEPTION_HANDLING=1 FAULT_INJECTION_SUPPORT=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000194 HANDLE_EA_EL3_FIRST=1 RAS_EXTENSION=1 SDEI_SUPPORT=1 SPM_MM=1 ENABLE_SVE_FOR_NS=0 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200195
196#
Vijayenthiran Subramaniam2a47a6d2020-07-22 14:16:58 +0530197# System Guidance for Infrastructure platform RD-N1-Edge-Dual
Fathi Boudra422bf772019-12-02 11:10:16 +0200198#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500199make $(common_flags) PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200200
201#
202# System Guidance for Infrastructure platform RD-E1Edge
203#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500204make $(common_flags) PLAT=rde1edge ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500205
206#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530207# Reference Design platform RD-V1
Zelalemc9531f82020-08-04 15:37:08 -0500208#
Aditya Angadi634d61f2021-01-04 09:30:20 +0530209make $(common_flags) PLAT=rdv1 ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500210
211#
Aditya Angadi61c54762021-01-04 09:30:52 +0530212# Reference Design platform RD-V1-MC
Zelalemc9531f82020-08-04 15:37:08 -0500213#
Aditya Angadi61c54762021-01-04 09:30:52 +0530214make $(common_flags) PLAT=rdv1mc ${ARM_TBB_OPTIONS} CSS_SGI_CHIP_COUNT=4 all
Zelalemc9531f82020-08-04 15:37:08 -0500215
216#
Vijayenthiran Subramaniama66de332020-11-23 14:20:14 +0530217# Reference Design Platform RD-N2
218#
219make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} all
220
221#
Zelalemc9531f82020-08-04 15:37:08 -0500222# Neoverse N1 SDP platform
223#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500224make $(common_flags) PLAT=n1sdp ${ARM_TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500225
226#
227# FVP VE platform
228#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500229make $(common_flags) PLAT=fvp_ve AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500230 CROSS_COMPILE=arm-none-eabi- ARM_ARCH_MAJOR=7 \
231 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
232 FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts all
233
234#
235# A5 DesignStart Platform
236#
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500237make $(common_flags) PLAT=a5ds AARCH32_SP=sp_min ARCH=aarch32 \
Zelalemc9531f82020-08-04 15:37:08 -0500238 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes ARM_XLAT_TABLES_LIB_V1=1 \
239 CROSS_COMPILE=arm-none-eabi- FVP_HW_CONFIG_DTS=fdts/a5ds.dts
240
241#
242# Corstone700 Platform
243#
244
245corstone700_common_flags="CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500246 $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500247 PLAT=corstone700 \
248 ARCH=aarch32 \
249 RESET_TO_SP_MIN=1 \
250 AARCH32_SP=sp_min \
251 ARM_LINUX_KERNEL_AS_BL33=0 \
252 ARM_PRELOADED_DTB_BASE=0x80400000 \
253 ENABLE_PIE=1 \
Zelalemc9531f82020-08-04 15:37:08 -0500254 ENABLE_STACK_PROTECTOR=all \
255 all"
256
257echo "Info: Building Corstone700 FVP ..."
258
259make TARGET_PLATFORM=fvp ${corstone700_common_flags}
260
261echo "Info: Building Corstone700 FPGA ..."
262
263make TARGET_PLATFORM=fpga ${corstone700_common_flags}
264
265#
266# Arm internal FPGA port
267#
Andre Przywara13361b62022-04-26 11:16:55 +0100268make PLAT=arm_fpga $(common_flags release) \
269 FPGA_PRELOADED_DTB_BASE=0x88000000 PRELOADED_BL33_BASE=0x82080000 all
Zelalemc9531f82020-08-04 15:37:08 -0500270
271#
Usama Arifcba711d2021-08-04 15:53:42 +0100272# Total Compute platforms
Zelalemc9531f82020-08-04 15:37:08 -0500273#
Usama Arifcba711d2021-08-04 15:53:42 +0100274make $(common_flags) PLAT=tc TARGET_PLATFORM=0 ${ARM_TBB_OPTIONS} all
275make $(common_flags) PLAT=tc TARGET_PLATFORM=1 ${ARM_TBB_OPTIONS} all
Fathi Boudra422bf772019-12-02 11:10:16 +0200276
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530277#
278# Morello platform
279#
Chandni Cherukuricbd45962021-12-12 13:37:33 +0530280clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=fvp ${ARM_TBB_OPTIONS}
281clean_build $(common_flags) PLAT=morello TARGET_PLATFORM=soc ${ARM_TBB_OPTIONS}
Chandni Cherukurifb803e12020-10-01 17:49:08 +0530282
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100283#
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000284# corstone1000 Platform
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100285#
286
287make $(common_flags) \
Vishnu Banavath2cb72b32022-01-20 14:27:55 +0000288 PLAT=corstone1000 \
Abdellatif El Khlific16fe912021-08-03 12:35:16 +0100289 SPD=spmd \
290 TARGET_PLATFORM=fpga \
291 ENABLE_STACK_PROTECTOR=strong \
292 ENABLE_PIE=1 \
293 BL2_AT_EL3=1 \
294 SPMD_SPM_AT_SEL2=0 \
295 ${ARM_TBB_OPTIONS} \
296 CREATE_KEYS=1 \
297 COT=tbbr \
298 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
299 bl2 \
300 bl31
301
johpow01aac58582021-10-05 16:51:34 -0500302#
303# FVP-R platform
304#
305clean_build $(common_flags) PLAT=fvp_r ${ARM_TBB_OPTIONS} ENABLE_STACK_PROTECTOR=all
306
Fathi Boudra422bf772019-12-02 11:10:16 +0200307# Partners' platforms.
308# Enable as many features as possible.
309# We don't need to clean between each build here because we only do one build
310# per platform so we don't hit the build flags dependency problem.
Fathi Boudra422bf772019-12-02 11:10:16 +0200311
Manish Pandey9c0ee742021-07-08 09:55:59 +0100312# Platforms from Mediatek
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500313make PLAT=mt8173 $(common_flags) all
314make PLAT=mt8183 $(common_flags) all
Rex-BC Chen946cace2021-11-17 10:15:42 +0800315make PLAT=mt8186 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500316make PLAT=mt8192 $(common_flags) COREBOOT=1 all
Manish Pandey9c0ee742021-07-08 09:55:59 +0100317make PLAT=mt8195 $(common_flags) COREBOOT=1 all
Zelalemd86e8762020-08-21 18:24:28 -0500318
319# Platforms from Qualcomm
320make PLAT=sc7180 $(common_flags) COREBOOT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200321
Zelalemc9531f82020-08-04 15:37:08 -0500322make PLAT=rk3288 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500323 $(common_flags) ARCH=aarch32 AARCH32_SP=sp_min all
Madhukar Pappireddyd491ad02020-12-03 10:37:05 -0600324make PLAT=rk3368 $(common_flags) COREBOOT=1 \
325 ENABLE_STACK_PROTECTOR=strong all
326make PLAT=rk3399 $(common_flags) COREBOOT=1 PLAT_RK_DP_HDCP=1 \
327 ENABLE_STACK_PROTECTOR=strong all
328make PLAT=rk3328 $(common_flags) COREBOOT=1 PLAT_RK_SECURE_DDR_MINILOADER=1 \
329 ENABLE_STACK_PROTECTOR=strong all
330make PLAT=px30 $(common_flags) PLAT_RK_SECURE_DDR_MINILOADER=1 \
331 ENABLE_STACK_PROTECTOR=strong all
Fathi Boudra422bf772019-12-02 11:10:16 +0200332
333# Although we do several consecutive builds for the Tegra platform below, we
334# don't need to clean between each one because the Tegra makefiles specify
335# a different build directory per SoC.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500336make PLAT=tegra TARGET_SOC=t210 $(common_flags) all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500337make PLAT=tegra TARGET_SOC=t186 $(common_flags) all
338make PLAT=tegra TARGET_SOC=t194 $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200339
340# For the Xilinx platform, artificially increase the extents of BL31 memory
341# (using the platform-specific build options ZYNQMP_ATF_MEM_{BASE,SIZE}).
342# If we keep the default values, BL31 doesn't fit when it is built with all
343# these build flags.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500344make PLAT=zynqmp $(common_flags) \
Fathi Boudra422bf772019-12-02 11:10:16 +0200345 RESET_TO_BL31=1 SPD=tspd \
Zelalem4f3633e2021-06-18 11:53:47 -0500346 SDEI_SUPPORT=1 \
Fathi Boudra422bf772019-12-02 11:10:16 +0200347 ZYNQMP_ATF_MEM_BASE=0xFFFC0000 ZYNQMP_ATF_MEM_SIZE=0x00040000 \
348 all
349
Zelalemc9531f82020-08-04 15:37:08 -0500350# Build both for silicon (default) and virtual QEMU platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500351clean_build PLAT=versal $(common_flags)
352clean_build PLAT=versal $(common_flags) VERSAL_PLATFORM=versal_virt
Zelalemc9531f82020-08-04 15:37:08 -0500353
354# Platforms from Allwinner
Andre Przywara3a78c102022-04-26 11:08:54 +0100355clean_build PLAT=sun50i_a64 $(common_flags release) all
356clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_NATIVE=0 all
357clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_PSCI_USE_SCPI=0 all
358clean_build PLAT=sun50i_a64 $(common_flags release) SUNXI_AMEND_DTB=1 all
Andre Przywaracf78a512021-09-03 14:59:38 +0100359clean_build PLAT=sun50i_h6 $(common_flags) all
360clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_NATIVE=0 all
361clean_build PLAT=sun50i_h6 $(common_flags) SUNXI_PSCI_USE_SCPI=0 all
362clean_build PLAT=sun50i_h616 $(common_flags) all
363clean_build PLAT=sun50i_r329 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500364
365# Platforms from i.MX
366make AARCH32_SP=optee ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
367 CROSS_COMPILE=arm-none-eabi- PLAT=warp7 ${TBB_OPTIONS} \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500368 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500369make AARCH32_SP=optee ARCH=aarch32 CROSS_COMPILE=arm-none-eabi- PLAT=picopi \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500370 $(common_flags) all
Ying-Chun Liu (PaulLiu)f6528982021-11-17 17:20:00 +0800371make PLAT=imx8mm $(common_flags) NEED_BL2=yes MEASURED_BOOT=1 \
372 TPM_HASH_ALG=sha256 ${TBB_OPTIONS} all
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500373make PLAT=imx8mn $(common_flags) all
Ying-Chun Liu (PaulLiu)413e6102021-09-14 00:22:08 +0800374make PLAT=imx8mp $(common_flags) NEED_BL2=yes ${TBB_OPTIONS} all
Zelalemc9531f82020-08-04 15:37:08 -0500375
Jacky Baib6cecc82021-06-07 09:49:46 +0800376# Due to the limited OCRAM space that can be used for TF-A, build test
377# will report failure caused by too small RAM size, so comment out the
378# build test for imx8mq in CI. It can also resolve the following ticket:
Zelalemc9531f82020-08-04 15:37:08 -0500379# https://developer.trustedfirmware.org/T626
Jacky Baib6cecc82021-06-07 09:49:46 +0800380#make PLAT=imx8mq $(common_flags release) all
Zelalemc9531f82020-08-04 15:37:08 -0500381
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500382make PLAT=imx8qm $(common_flags) all
383make PLAT=imx8qx $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500384
Olivier Deprezbac70192021-04-02 08:55:36 +0200385# Platforms for NXP Layerscape
Jiafei Pane48e56c2021-09-30 10:32:54 +0800386nxp_sb_flags="TRUSTED_BOARD_BOOT=1 CST_DIR=$(pwd) SPD=opteed"
387nxp_sb_fuse_flags="${nxp_sb_flags} FUSE_PROG=1"
388
389# Platform lx2
Olivier Deprezbac70192021-04-02 08:55:36 +0200390make PLAT=lx2160aqds $(common_flags) all
391make PLAT=lx2160ardb $(common_flags) all
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500392
393#CSF Based CoT:
Jiafei Pane48e56c2021-09-30 10:32:54 +0800394clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
395 $nxp_sb_fuse_flags DDR_PHY_BIN_PATH=$(pwd)
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500396
397#X509 Based CoT
Jiafei Pane48e56c2021-09-30 10:32:54 +0800398clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=flexspi_nor \
399 $nxp_sb_flags GENERATE_COT=1 \
Madhukar Pappireddyf93a4d42021-06-01 17:44:51 -0500400 MBEDTLS_DIR=$(pwd)/mbedtls
401
402#BOOT_MODE=emmc and Stack protector
Jiafei Pane48e56c2021-09-30 10:32:54 +0800403clean_build PLAT=lx2162aqds $(common_flags) BOOT_MODE=emmc \
404 $nxp_sb_fuse_flags ENABLE_STACK_PROTECTOR=strong
405
406# Platform ls1028ardb
407clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor
408clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc
409clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd
410
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800411# ls1028a Secure Boot
Jiafei Pane48e56c2021-09-30 10:32:54 +0800412clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=flexspi_nor $nxp_sb_fuse_flags
413clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
414clean_build PLAT=ls1028ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
Olivier Deprezbac70192021-04-02 08:55:36 +0200415
Jiafei Pan5aa8fc72021-11-17 22:12:12 +0800416# Platform ls1043ardb
417clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor
418clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand
419clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd
420
421# ls1043ardb Secure Boot
422clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
423clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
424clean_build PLAT=ls1043ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
425
Jiafei Panbd0c22a2022-01-29 00:04:44 +0800426# ls1046ardb Secure Boot
427clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
428clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
429clean_build PLAT=ls1046ardb $(common_flags) all BOOT_MODE=emmc $nxp_sb_fuse_flags
430
431# ls1046afrwy Secure Boot
432clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
433clean_build PLAT=ls1046afrwy $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
434
435# ls1046aqds Secure Boot
436clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
437clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
438clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
439clean_build PLAT=ls1046aqds $(common_flags) all BOOT_MODE=nand $nxp_sb_fuse_flags
440
Jiafei Pan332cd792022-02-24 16:44:48 +0800441# ls1088ardb Secure Boot
442clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
443clean_build PLAT=ls1088ardb $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
444
445# ls1088aqds Secure Boot
446clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=qspi $nxp_sb_fuse_flags
447clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=sd $nxp_sb_fuse_flags
448clean_build PLAT=ls1088aqds $(common_flags) all BOOT_MODE=nor $nxp_sb_fuse_flags
449
Zelalemc9531f82020-08-04 15:37:08 -0500450# Platforms from Intel
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500451make PLAT=stratix10 $(common_flags) all
452make PLAT=agilex $(common_flags) all
Sieu Mun Tang03b57362022-03-05 01:54:59 +0800453make PLAT=n5x $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500454
455# Platforms from Broadcom
Madhukar Pappireddy97ad2582021-11-15 10:29:23 -0600456clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t \
457 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 DRIVER_I2C_ENABLE=1
458clean_build PLAT=stingray $(common_flags) BOARD_CFG=bcm958742t-ns3 \
459 INCLUDE_EMMC_DRIVER_ERASE_CODE=1 USE_USB=yes
Zelalemc9531f82020-08-04 15:37:08 -0500460
461# Platforms from Marvell
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500462make PLAT=a3700 $(common_flags) SCP_BL2=/dev/null CM3_SYSTEM_RESET=1 \
463 A3720_DB_PM_WAKEUP_SRC=1 HANDLE_EA_EL3_FIRST=1 all
Zelalemc9531f82020-08-04 15:37:08 -0500464
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600465# Source files from mv-ddr-marvell repository are necessary
466# to build below four platforms
Manish Pandey7c1e7452021-11-05 12:54:15 +0000467wget https://downloads.trustedfirmware.org/tf-a/mv-ddr-marvell/mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
468tar -xzf mv-ddr-marvell-5d41a995637de1dbc93f193db6ef0c8954cab316.tar.gz 2> /dev/null
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600469mv mv-ddr-marvell drivers/marvell/mv_ddr
Zelalemc9531f82020-08-04 15:37:08 -0500470
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600471# These platforms from Marvell have dependency on GCC-6.2.1 toolchain
Pali Rohár8f890402021-07-19 13:48:05 +0200472make PLAT=a80x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200473 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200474make PLAT=a80x0_mcbin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200475 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200476make PLAT=a70x0 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200477 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200478make PLAT=a70x0_amc DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200479 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Robert Markodf3319e2021-10-20 11:01:12 +0200480make PLAT=a70x0_mochabin DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
481 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200482make PLAT=a80x0_puzzle DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200483 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Pali Rohár8f890402021-07-19 13:48:05 +0200484make PLAT=t9130 DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
Pali Rohárc344a622021-07-15 22:01:04 +0200485 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Madhukar Pappireddy4fce99e2021-09-15 14:33:35 -0500486make PLAT=t9130_cex7_eval DEBUG=1 SCP_BL2=/dev/null BL33=/dev/null MV_DDR_PATH=$PWD/drivers/marvell/mv_ddr \
487 CROSS_COMPILE="$(set_cross_compile_gcc_linaro_toolchain)" all mrvl_flash
Leonardo Sandovaleb1d3ce2020-08-06 16:04:29 -0500488
Leonardo Sandovalc0443772020-11-12 11:22:48 -0600489# Removing the source files
490rm -rf drivers/marvell/mv_ddr 2> /dev/null
Zelalemc9531f82020-08-04 15:37:08 -0500491
492# Platforms from Meson
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500493make PLAT=gxbb $(common_flags) all
494make PLAT=gxl $(common_flags) all
495make PLAT=g12a $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500496
497# Platforms from Renesas
498# Renesas R-Car D3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500499clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500500 BL33=Makefile LIFEC_DBSC_PROTECT_ENABLE=0 LSI=D3 \
501 MBEDTLS_DIR=$(pwd)/mbedtls PMIC_ROHM_BD9571=0 \
502 RCAR_AVS_SETTING_ENABLE=0 SPD=none RCAR_LOSSY_ENABLE=0 \
503 RCAR_SA0_SIZE=0 RCAR_SYSTEM_SUSPEND=0 TRUSTED_BOARD_BOOT=1
504
505# Renesas R-Car H3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500506clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500507 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3 \
508 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
509 RCAR_DRAM_SPLIT=1 RCAR_GEN3_ULCB=1 SPD=opteed \
510 TRUSTED_BOARD_BOOT=1
511
512# Renesas R-Car H3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500513clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500514 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=H3N \
515 SPD=opteed TRUSTED_BOARD_BOOT=1
516
517# Renesas R-Car M3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500518clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500519 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3 \
520 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
521 RCAR_DRAM_SPLIT=2 RCAR_GEN3_ULCB=1 SPD=opteed \
522 TRUSTED_BOARD_BOOT=1
523
524# Renesas R-Car M3N Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500525clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500526 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=M3N \
527 MACHINE=ulcb PMIC_LEVEL_MODE=0 RCAR_DRAM_LPDDR4_MEMCONF=0 \
528 RCAR_GEN3_ULCB=1 SPD=opteed TRUSTED_BOARD_BOOT=1
529
530# Renesas R-Car E3 Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500531clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500532 BL33=Makefile MBEDTLS_DIR=$(pwd)/mbedtls LSI=E3 \
533 RCAR_AVS_SETTING_ENABLE=0 RCAR_DRAM_DDR3L_MEMCONF=0 \
534 RCAR_SA0_SIZE=0 SPD=opteed TRUSTED_BOARD_BOOT=1
535
536# Renesas R-Car V3M Automotive SoC
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500537clean_build PLAT=rcar $(common_flags) BL32=Makefile \
Zelalemc9531f82020-08-04 15:37:08 -0500538 MBEDTLS_DIR=$(pwd)/mbedtls BL33=Makefile LSI=V3M MACHINE=eagle \
539 PMIC_ROHM_BD9571=0 RCAR_DRAM_SPLIT=0 RCAR_SYSTEM_SUSPEND=0 \
540 AVS_SETTING_ENABLE=0 SPD=none TRUSTED_BOARD_BOOT=1
541
Zelalemf4299672021-01-29 12:52:59 -0600542# Renesas HiHope RZ/G2M development kit
543clean_build PLAT=rzg $(common_flags) \
544 MBEDTLS_DIR=$(pwd)/mbedtls LSI=G2M \
545 RCAR_DRAM_SPLIT=2 RCAR_LOSSY_ENABLE=1 SPD=none
546
Zelalemc9531f82020-08-04 15:37:08 -0500547# Platforms from ST
Yann Gautiera69cf792021-09-01 11:19:01 +0200548# STM32MP1 SDMMC boot
549make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
550 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
551 BUILD_PLAT=build/stm32mp1-sdmmc/debug \
552 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
553
554# STM32MP1 eMMC boot
Zelalemc9531f82020-08-04 15:37:08 -0500555make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500556 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_EMMC=1 \
Yann Gautiera69cf792021-09-01 11:19:01 +0200557 BUILD_PLAT=build/stm32mp1-emmc/debug \
558 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
559
560# STM32MP1 Raw NAND boot
561make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
562 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_RAW_NAND=1 \
563 BUILD_PLAT=build/stm32mp1-nand/debug \
564 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
565
566# STM32MP1 SPI NAND boot
567make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
568 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NAND=1 \
569 BUILD_PLAT=build/stm32mp1-snand/debug \
570 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
571
572# STM32MP1 SPI NOR boot
573make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
574 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SPI_NOR=1 \
575 BUILD_PLAT=build/stm32mp1-snor/debug \
576 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
577
Patrick Delaunayd2017a42021-11-02 14:57:50 +0100578# STM32MP1 UART boot
579make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
580 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_UART_PROGRAMMER=1 \
581 BUILD_PLAT=build/stm32mp1-uart/debug \
582 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
583
Patrick Delaunay7d65acf2021-09-10 15:58:26 +0200584# STM32MP1 USB boot
585make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
586 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_USB_PROGRAMMER=1 \
587 BUILD_PLAT=build/stm32mp1-usb/debug \
588 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
589
Yann Gautiera69cf792021-09-01 11:19:01 +0200590# STM32MP1 SDMMC boot without FIP
591make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
592 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
593 BUILD_PLAT=build/stm32mp1-sdmmc-stm32image/debug \
594 STM32MP_USE_STM32IMAGE=1 \
595 ARCH=aarch32 AARCH32_SP=sp_min ENABLE_STACK_PROTECTOR=strong bl2 bl32
Zelalemc9531f82020-08-04 15:37:08 -0500596
Yann Gautier773c5502022-03-10 17:24:47 +0100597# STM32MP13 SDMMC boot
598make PLAT=stm32mp1 CROSS_COMPILE=arm-none-eabi- \
599 $(common_flags) ARM_ARCH_MAJOR=7 STM32MP_SDMMC=1 \
600 BUILD_PLAT=build/stm32mp1-mp13-sdmmc/debug STM32MP13=1 \
601 ARCH=aarch32 AARCH32_SP=optee ENABLE_STACK_PROTECTOR=strong bl2
602
Zelalemc9531f82020-08-04 15:37:08 -0500603# Platforms from TI
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500604make PLAT=k3 $(common_flags) all
Zelalemc9531f82020-08-04 15:37:08 -0500605
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500606clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS}
Zelalemc9531f82020-08-04 15:37:08 -0500607# Use GICV3 driver
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500608clean_build PLAT=qemu $(common_flags) QEMU_USE_GIC_DRIVER=QEMU_GICV3 \
Zelalemc9531f82020-08-04 15:37:08 -0500609 ENABLE_STACK_PROTECTOR=strong
610# Use encrypted FIP feature.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500611clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500612 BL32_RAM_LOCATION=tdram DECRYPTION_SUPPORT=aes_gcm ENCRYPT_BL31=1 \
613 ENCRYPT_BL32=1 FW_ENC_STATUS=0 SPD=opteed
Jens Wiklander1a9c2be2021-11-26 09:56:55 +0100614# QEMU with SPMD support
615clean_build PLAT=qemu $(common_flags) BL32=Makefile \
616 BL32_RAM_LOCATION=tdram ARM_BL31_IN_DRAM=1 \
617 SPD=spmd CTX_INCLUDE_EL2_REGS=0 SPMD_SPM_AT_SEL2=0 SPMC_OPTEE=1
Ruchika Gupta86e7f682022-04-12 10:25:46 +0530618# Measured Boot
619clean_build PLAT=qemu $(common_flags) ${TBB_OPTIONS} TPM_HASH_ALG=sha256 MEASURED_BOOT=1
Zelalemc9531f82020-08-04 15:37:08 -0500620
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500621clean_build PLAT=qemu_sbsa $(common_flags)
Fathi Boudra422bf772019-12-02 11:10:16 +0200622
Zelalemd86e8762020-08-21 18:24:28 -0500623# QEMU with SPM support
624clean_build PLAT=qemu_sbsa $(common_flags) BL32=Makefile SPM_MM=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000625 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0
Zelalemd86e8762020-08-21 18:24:28 -0500626
Fathi Boudra422bf772019-12-02 11:10:16 +0200627# For hikey enable PMF to include all files in the platform port
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500628make PLAT=hikey $(common_flags) ${TBB_OPTIONS} ENABLE_PMF=1 all
629make PLAT=hikey960 $(common_flags) ${TBB_OPTIONS} all
630make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200631
Zelalemc9531f82020-08-04 15:37:08 -0500632# Platforms from Socionext
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500633clean_build PLAT=uniphier $(common_flags) ${TBB_OPTIONS} SPD=tspd
634clean_build PLAT=uniphier $(common_flags) FIP_GZIP=1
Fathi Boudra422bf772019-12-02 11:10:16 +0200635
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500636clean_build PLAT=synquacer $(common_flags) SPM_MM=1 \
Manish Pandeyaa9a03b2021-11-17 10:03:17 +0000637 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 PRELOADED_BL33_BASE=0x0
Zelalemc9531f82020-08-04 15:37:08 -0500638
639# Support for SCP Message Interface protocol with platform specific drivers
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500640clean_build PLAT=synquacer $(common_flags) \
Zelalemc9531f82020-08-04 15:37:08 -0500641 PRELOADED_BL33_BASE=0x0 SQ_USE_SCMI_DRIVER=1
642
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500643make PLAT=poplar $(common_flags) all
Fathi Boudra422bf772019-12-02 11:10:16 +0200644
Zelalemc9531f82020-08-04 15:37:08 -0500645# Raspberry Pi Platforms
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500646make PLAT=rpi3 $(common_flags) ${TBB_OPTIONS} \
Zelalemc9531f82020-08-04 15:37:08 -0500647 ENABLE_STACK_PROTECTOR=strong PRELOADED_BL33_BASE=0xDEADBEEF all
Andre Przywarae917ec82021-09-03 15:01:30 +0100648clean_build PLAT=rpi4 $(common_flags) SMC_PCI_SUPPORT=1 all
Fathi Boudra422bf772019-12-02 11:10:16 +0200649
Zelalemc9531f82020-08-04 15:37:08 -0500650# A113D (AXG) platform.
Leonardo Sandoval97e2ef02020-08-06 13:29:08 -0500651clean_build PLAT=axg $(common_flags) SPD=opteed
652clean_build PLAT=axg $(common_flags) AML_USE_ATOS=1
Zelalemc9531f82020-08-04 15:37:08 -0500653
Stephan Gerhold141a7662021-12-07 20:42:14 +0100654# QTI MSM8916 platform
655clean_build PLAT=msm8916 $(common_flags)
656
Fathi Boudra422bf772019-12-02 11:10:16 +0200657cd ..