blob: b499003dc3de2b940ae32f3688afd6890ec23fec [file] [log] [blame]
Sandrine Bailleux1b77c812020-08-07 11:30:15 +02001#!/usr/bin/env bash
Vijayenthiran Subramaniam8c50c6f2020-07-21 19:05:09 +05302#
3# Copyright (c) 2020, Arm Limited. All rights reserved.
4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8fetch_tf_resource() {
9 #Fetch the pre-built SCP/MCP binaries if they haven't been built
10 if [ ! -f "$archive/mcp_rom.bin" ]; then
11 url="$sgi_prebuilts/mcp_rom.bin" fetch_file
12 archive_file "mcp_rom.bin"
13 fi
14 if [ ! -f "$archive/scp_ram.bin" ]; then
15 url="$sgi_prebuilts/scp_ram.bin" fetch_file
16 archive_file "scp_ram.bin"
17 fi
18 if [ ! -f "$archive/scp_rom.bin" ]; then
19 url="$sgi_prebuilts/scp_rom.bin" fetch_file
20 archive_file "scp_rom.bin"
21 fi
22
23 # Hold scp terminal_uart_aon on css0
24 uart="2" file="hold_uart.exp" track_expect
25
26 # Hold scp terminal_uart_aon on css1
27 uart="3" file="hold_uart.exp" track_expect
28}
29
Vijayenthiran Subramaniamdfda93d2020-07-23 12:53:35 +053030pre_tf_build() {
31 #
32 # Dual-Chip RD-N1-Edge FVP has reliability issues with stlr instruction
33 # while sending events across the chip through CCIX link. Apply 'send
34 # explicit event after store release instruction' patch to improve the
35 # reliability of cross chip events.
36 #
37 apply_tf_patch "css_rd_multichip_fvp/spinlock-send-explicit-event-after-store-release.patch"
38}
39
Vijayenthiran Subramaniam8c50c6f2020-07-21 19:05:09 +053040post_fetch_tf_resource() {
41 model="css-rdn1edgex2" gen_model_params
42 set_run_env "ports_script" "$ci_root/model/css-rdinfra-ports.awk"
43 set_run_env "num_uarts" "4"
44 uart="0" set_expect_variable "num_cpus" "16"
45}