| commit | d8c4d2885f137ee458c9b44383b57f156b033df1 | [log] [tgz] |
|---|---|---|
| author | Manish Pandey <manish.pandey2@arm.com> | Mon Mar 11 14:18:10 2024 +0000 |
| committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | Fri Mar 15 17:17:03 2024 +0100 |
| tree | be0bc0e6d1c1ddda77145dd628cc6e1e0ac7d969 | |
| parent | e11b6591a0dfb5705aa9a59022d7eacd7392bba2 [diff] |
ci: use tspd enabled tf build for cpu extensions Few of CPU extension tests gets SKIPPED if TSP is not present in secure side, run all config CPU extension test with tspd Change-Id: I208a40dfedd3b9c66809d8f1f71c23ae4c09052b Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
diff --git a/group/tf-l3-code-coverage/fvp-aarch64-only-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.all.bmcov-debug b/group/tf-l3-code-coverage/fvp-tspd-aarch64-only-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.all.bmcov-debug similarity index 100% rename from group/tf-l3-code-coverage/fvp-aarch64-only-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.all.bmcov-debug rename to group/tf-l3-code-coverage/fvp-tspd-aarch64-only-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.all.bmcov-debug
diff --git a/tf_config/fvp-tspd-aarch64-only b/tf_config/fvp-tspd-aarch64-only index 14eaede..9504a4b 100644 --- a/tf_config/fvp-tspd-aarch64-only +++ b/tf_config/fvp-tspd-aarch64-only
@@ -1,4 +1,7 @@ CROSS_COMPILE=aarch64-none-elf- CTX_INCLUDE_AARCH32_REGS=0 +ENABLE_SME_FOR_NS=2 +ENABLE_SME2_FOR_NS=2 +ENABLE_FEAT_AMU=2 PLAT=fvp SPD=tspd
diff --git a/tf_config/fvp-tspd-aarch64-only-cc b/tf_config/fvp-tspd-aarch64-only-cc index 878cbd4..dca0489 100644 --- a/tf_config/fvp-tspd-aarch64-only-cc +++ b/tf_config/fvp-tspd-aarch64-only-cc
@@ -1,5 +1,8 @@ CROSS_COMPILE=aarch64-none-elf- CTX_INCLUDE_AARCH32_REGS=0 +ENABLE_SME_FOR_NS=2 +ENABLE_SME2_FOR_NS=2 +ENABLE_FEAT_AMU=2 PLAT=fvp SPD=tspd ENABLE_ASSERTIONS=0