diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.etm_trace_ext.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.etm_trace_ext.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.etm_trace_ext.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-roxlattables-cc,fvp-aarch32-default:fvp-tftf-fip.tftf-aemv8a.aarch32.roxlattables.spmin_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-roxlattables-cc,fvp-aarch32-default:fvp-tftf-fip.tftf-aemv8a.aarch32.roxlattables.spmin_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-roxlattables-cc,fvp-aarch32-default:fvp-tftf-fip.tftf-aemv8a.aarch32.roxlattables.spmin_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.tspd_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.tspd_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.tspd_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-bl31-separate-nobits-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-bl31-separate-nobits-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-bl31-separate-nobits-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-crash-report-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.runtime_bl31_main_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-crash-report-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.runtime_bl31_main_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-crash-report-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.runtime_bl31_main_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_7.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_7.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_7.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv3_spi.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv3_spi.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv3_spi.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-invalid-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-invalid-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-invalid-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-clang-bfd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-clang-bfd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-clang-bfd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-clang-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-clang-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-clang-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-detect-features-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.arch_features.bmcov b/group/tf-l3-code-coverage-extensive/fvp-detect-features-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.arch_features.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-detect-features-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.arch_features.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-gicv4-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-gicv4-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-gicv4-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-hcx-aarch64-only-cc,fvp-hcx:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-hcx-aarch64-only-cc,fvp-hcx:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-hcx-aarch64-only-cc,fvp-hcx:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..c473896
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-brbe-regs-access-cc,fvp-default:fvp-tftf-fip.tftf-aemva.feat_brbe.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-brbe-regs-access-cc,fvp-default:fvp-tftf-fip.tftf-aemva.feat_brbe.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-brbe-regs-access-cc,fvp-default:fvp-tftf-fip.tftf-aemva.feat_brbe.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-sys-regs-trace-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-sys-regs-trace-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-sys-regs-trace-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-trbe-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-trbe-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-trbe-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-trf-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-trf-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-trf-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-aarch64-only-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-aarch64-only-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-aarch64-only-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemva.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemva.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemva.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-quad-cluster-cc,fvp-4x4:fvp-tftf-fip.tftf-aemv8a.quad.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-quad-cluster-cc,fvp-4x4:fvp-tftf-fip.tftf-aemv8a.quad.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-quad-cluster-cc,fvp-4x4:fvp-tftf-fip.tftf-aemv8a.quad.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu.mbedtls2-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu.mbedtls2-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu.mbedtls2-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#