diff --git a/group/spm-l3-boot-tests-rme/fvp-default,fvp-spm-rme,fvp-default:fvp-spm.trp.tftf-tftf.rme b/group/spm-l3-boot-tests-rme/fvp-default,fvp-spm-rme,fvp-default:fvp-spm.trp.tftf-tftf.rme
new file mode 100644
index 0000000..45065d8
--- /dev/null
+++ b/group/spm-l3-boot-tests-rme/fvp-default,fvp-spm-rme,fvp-default:fvp-spm.trp.tftf-tftf.rme
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-boot-tests-rme/fvp-rme,fvp-default:fvp-trp.tftf-tftf.rme b/group/tf-l3-boot-tests-rme/fvp-rme,fvp-default:fvp-trp.tftf-tftf.rme
new file mode 100644
index 0000000..45065d8
--- /dev/null
+++ b/group/tf-l3-boot-tests-rme/fvp-rme,fvp-default:fvp-trp.tftf-tftf.rme
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/model/base-aemv8a.sh b/model/base-aemv8a.sh
index 682ab94..fba3b73 100644
--- a/model/base-aemv8a.sh
+++ b/model/base-aemv8a.sh
@@ -7,7 +7,14 @@
 
 # Use revc model
 if  is_arm_jenkins_env || upon "$local_ci"; then
-        set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/external/models/$model_flavour/FVP_Base_RevC-2xAEMvA"
+	# TODO: For now rme-enabled model is located at a differnt location.
+	# Fix this path once the model becomes part of the "external" models.
+	if [ "$has_rme" = "1" ]; then
+		set_model_path "$project_filer/models/rme/FVP_Base_RevC-2xAEMvA_11.15_18/Base_RevC_AEMvA_pkg/models/Linux64_GCC-6.4/FVP_Base_RevC-2xAEMvA"
+	else
+        	set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/external/models/$model_flavour/FVP_Base_RevC-2xAEMvA"
+	fi
+
         default_var sve_plugin_path "$warehouse/SysGen/PVModelLib/$model_version/$model_build/external/plugins/$model_flavour/sve2-HEAD/ScalableVectorExtension.so"
 else
         # OpenCI enviroment
diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index 26aecfc..3d9d7be 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -60,6 +60,9 @@
 # Enable SMMUv3 functionality
 reset_var has_smmuv3_params
 
+# Enable FEAT_RME
+reset_var has_rme
+
 # Layout of MPIDR. 0=AFF0 is CPUID, 1=AFF1 is CPUID
 reset_var mpidr_layout
 
@@ -117,6 +120,14 @@
 EOF
 fi
 
+# FEAT_RME is enabled
+if [ "$has_rme" = "1" ]; then
+	cat <<EOF >>"$model_param_file"
+-C bp.refcounter.non_arch_start_at_default=1
+-C bp.refcounter.use_real_time=0
+EOF
+fi
+
 #------------ Cluster0 configuration --------------
 
 cat <<EOF >>"$model_param_file"
@@ -175,7 +186,23 @@
 EOF
 
 if [ "$has_smmuv3_params" = "1" ]; then
-	cat <<EOF >>"$model_param_file"
+# The pci.pci_smmuv3.mmu.SMMU_IDR5
+# parameter is modified for 48 bit
+# physical address if rme is enabled.
+# Also ignores the tracing parameters.
+	if [ "$has_rme" = "1" ]; then
+		cat <<EOF >>"$model_param_file"
+-C pci.pci_smmuv3.mmu.SMMU_AIDR=2
+-C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
+-C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002
+-C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714
+-C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475
+-C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002
+-C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0
+-C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0
+EOF
+	else
+		cat <<EOF >>"$model_param_file"
 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2
 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
 -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002
@@ -193,6 +220,7 @@
 -C TRACE.GenericTrace.trace-sources=verbose_commentary,smmu_initial_transaction,smmu_final_transaction,*.pci.pci_smmuv3.mmu.*.*,*.pci.smmulogger.*,*.pci.tbu0_pre_smmu_logger.*,FVP_Base_RevC_2xAEMv8A.pci.pci_smmuv3,smmu_poison_tw_data
 --plugin $warehouse/SysGen/PVModelLib/$model_version/$model_build/external/plugins/$model_flavour/GenericTrace.so
 EOF
+	fi
 fi
 
 # Parameters to select architecture version
@@ -230,6 +258,21 @@
 EOF
 fi
 
+# FEAT_RME is enabled
+if [ "$has_rme" = "1" ]; then
+        cat <<EOF >>"$model_param_file"
+-C cluster0.has_rme=1
+-C cluster0.has_rndr=1
+-C cluster0.has_v8_7_pmu_extension=2
+-C cluster0.ecv_support_level=2
+-C cluster0.gicv3.cpuintf-mmap-access-level=2
+-C cluster0.gicv4.mask-virtual-interrupt=1
+-C cluster0.gicv3.without-DS-support=1
+-C cluster0.max_32bit_el=-1
+-C cluster0.PA_SIZE=48
+EOF
+fi
+
 #------------ Cluster1 configuration (if exists) --------------
 if [ "$is_dual_cluster" = "1" ]; then
 	cat <<EOF >>"$model_param_file"
@@ -318,4 +361,19 @@
 -C cluster1.pseudo_fault_generation_feature_register='{"OF":false,"CI":false,"ER":false,"PN":false,"AV":false,"MV":false,"SYN":false,"UC":true,"UEU":true,"UER":false,"UEO":false,"DE":false,"CE":0,"R":false}'
 EOF
 fi
+
+# FEAT_RME is enabled
+if [ "$has_rme" = "1" ]; then
+	cat <<EOF >>"$model_param_file"
+-C cluster1.has_rme=1
+-C cluster1.has_rndr=1
+-C cluster1.has_v8_7_pmu_extension=2
+-C cluster1.ecv_support_level=2
+-C cluster1.gicv3.cpuintf-mmap-access-level=2
+-C cluster1.gicv4.mask-virtual-interrupt=1
+-C cluster1.gicv3.without-DS-support=1
+-C cluster1.max_32bit_el=-1
+-C cluster1.PA_SIZE=48
+EOF
+fi
 fi
diff --git a/run_config/fvp-spm.trp.tftf b/run_config/fvp-spm.trp.tftf
new file mode 100644
index 0000000..21a294a
--- /dev/null
+++ b/run_config/fvp-spm.trp.tftf
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Build TF-A with tf-a-tests, TRP and Hafnium
+post_tf_build() {
+	# Stash the TRP binary
+	archive_file "${tf_root}/build/fvp/${bin_mode}/rmm.bin"
+
+	build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin" \
+		RMM="$archive/rmm.bin"
+}
diff --git a/run_config/fvp-tftf.rme b/run_config/fvp-tftf.rme
new file mode 100644
index 0000000..91aaae2
--- /dev/null
+++ b/run_config/fvp-tftf.rme
@@ -0,0 +1,38 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+	# RME systems go BL1->BL2->BL31 so we must set this variable for expect
+	# scripts to work properly and not hang up waiting for BL1->BL31.
+	uart="0" set_expect_variable "skip_early_boot_msgs" "1"
+
+	# Use standard TFTF expect script on primary UART.
+	uart="0" file="tftf.exp" track_expect
+
+	# Track the rest of the UARTs to aid in debugging.
+	uart="1" file="hold_uart.exp" track_expect
+	uart="2" file="hold_uart.exp" track_expect
+	uart="3" file="hold_uart.exp" track_expect
+
+	payload_type="tftf" gen_fvp_yaml_template
+}
+
+post_fetch_tf_resource() {
+        local model="base-aemv8a"
+
+	model="$model" \
+	model_build="18" \
+	arch_version="8.6" \
+	has_branch_target_exception="1" \
+	restriction_on_speculative_execution="2" \
+	amu_present="1" \
+	has_rme="1" \
+	has_smmuv3_params="1" \
+		gen_model_params
+
+	model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-trp.tftf b/run_config/fvp-trp.tftf
new file mode 100644
index 0000000..0793c8f
--- /dev/null
+++ b/run_config/fvp-trp.tftf
@@ -0,0 +1,14 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Build TF-A with tf-a-tests and TRP
+post_tf_build() {
+	# Stash the TRP binary
+	archive_file "${tf_root}/build/fvp/${bin_mode}/rmm.bin"
+
+	build_fip BL33="$archive/tftf.bin" RMM="$archive/rmm.bin"
+}
diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index f402ee4..a5e4419 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -169,6 +169,9 @@
 # FVP-R platform
 clean_build PLAT=fvp_r $(common_flags) all
 
+# FEAT_RME
+clean_build $fvp_common_flags ENABLE_RME=1
+
 #
 # Juno platform
 # We'll use the following flags for all Juno builds.
diff --git a/tf_config/fvp-rme b/tf_config/fvp-rme
new file mode 100644
index 0000000..da2e805
--- /dev/null
+++ b/tf_config/fvp-rme
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ENABLE_RME=1
+FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts
diff --git a/tf_config/fvp-spm-rme b/tf_config/fvp-spm-rme
new file mode 100644
index 0000000..8d8446d
--- /dev/null
+++ b/tf_config/fvp-spm-rme
@@ -0,0 +1,9 @@
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_RME=1
+FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts
+PLAT=fvp
+SPD=spmd
+SPMD_SPM_AT_SEL2=1
+BRANCH_PROTECTION=1
+CTX_INCLUDE_PAUTH_REGS=1
+SP_LAYOUT_FILE=${tftf_root}/build/fvp/${bin_mode}/sp_layout.json