Add test configurations for FEAT_RME
The patch makes the following changes:
* Adds test configurations for the following scenarios:
==================================================
BL32 RMM BL33 Test configuration
==================================================
SPM TRP TFTF fvp-spm.trp.tftf-tftf.rme
None TRP TFTF fvp-trp.tftf-tftf.rme
* Adds an FVP model that supports FEAT_RME
* Updates tf-cov-make with FEAT_RME build configuration
Change-Id: Ibc404c0c60022406027dba06bbcb230df3ab133e
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index 26aecfc..3d9d7be 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -60,6 +60,9 @@
# Enable SMMUv3 functionality
reset_var has_smmuv3_params
+# Enable FEAT_RME
+reset_var has_rme
+
# Layout of MPIDR. 0=AFF0 is CPUID, 1=AFF1 is CPUID
reset_var mpidr_layout
@@ -117,6 +120,14 @@
EOF
fi
+# FEAT_RME is enabled
+if [ "$has_rme" = "1" ]; then
+ cat <<EOF >>"$model_param_file"
+-C bp.refcounter.non_arch_start_at_default=1
+-C bp.refcounter.use_real_time=0
+EOF
+fi
+
#------------ Cluster0 configuration --------------
cat <<EOF >>"$model_param_file"
@@ -175,7 +186,23 @@
EOF
if [ "$has_smmuv3_params" = "1" ]; then
- cat <<EOF >>"$model_param_file"
+# The pci.pci_smmuv3.mmu.SMMU_IDR5
+# parameter is modified for 48 bit
+# physical address if rme is enabled.
+# Also ignores the tracing parameters.
+ if [ "$has_rme" = "1" ]; then
+ cat <<EOF >>"$model_param_file"
+-C pci.pci_smmuv3.mmu.SMMU_AIDR=2
+-C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
+-C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002
+-C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714
+-C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475
+-C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002
+-C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0
+-C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0
+EOF
+ else
+ cat <<EOF >>"$model_param_file"
-C pci.pci_smmuv3.mmu.SMMU_AIDR=2
-C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
-C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002
@@ -193,6 +220,7 @@
-C TRACE.GenericTrace.trace-sources=verbose_commentary,smmu_initial_transaction,smmu_final_transaction,*.pci.pci_smmuv3.mmu.*.*,*.pci.smmulogger.*,*.pci.tbu0_pre_smmu_logger.*,FVP_Base_RevC_2xAEMv8A.pci.pci_smmuv3,smmu_poison_tw_data
--plugin $warehouse/SysGen/PVModelLib/$model_version/$model_build/external/plugins/$model_flavour/GenericTrace.so
EOF
+ fi
fi
# Parameters to select architecture version
@@ -230,6 +258,21 @@
EOF
fi
+# FEAT_RME is enabled
+if [ "$has_rme" = "1" ]; then
+ cat <<EOF >>"$model_param_file"
+-C cluster0.has_rme=1
+-C cluster0.has_rndr=1
+-C cluster0.has_v8_7_pmu_extension=2
+-C cluster0.ecv_support_level=2
+-C cluster0.gicv3.cpuintf-mmap-access-level=2
+-C cluster0.gicv4.mask-virtual-interrupt=1
+-C cluster0.gicv3.without-DS-support=1
+-C cluster0.max_32bit_el=-1
+-C cluster0.PA_SIZE=48
+EOF
+fi
+
#------------ Cluster1 configuration (if exists) --------------
if [ "$is_dual_cluster" = "1" ]; then
cat <<EOF >>"$model_param_file"
@@ -318,4 +361,19 @@
-C cluster1.pseudo_fault_generation_feature_register='{"OF":false,"CI":false,"ER":false,"PN":false,"AV":false,"MV":false,"SYN":false,"UC":true,"UEU":true,"UER":false,"UEO":false,"DE":false,"CE":0,"R":false}'
EOF
fi
+
+# FEAT_RME is enabled
+if [ "$has_rme" = "1" ]; then
+ cat <<EOF >>"$model_param_file"
+-C cluster1.has_rme=1
+-C cluster1.has_rndr=1
+-C cluster1.has_v8_7_pmu_extension=2
+-C cluster1.ecv_support_level=2
+-C cluster1.gicv3.cpuintf-mmap-access-level=2
+-C cluster1.gicv4.mask-virtual-interrupt=1
+-C cluster1.gicv3.without-DS-support=1
+-C cluster1.max_32bit_el=-1
+-C cluster1.PA_SIZE=48
+EOF
+fi
fi