tree 5aceec093438c9527f0e4837a20523666351adbe
parent 70b012a49ee1df329d9db50349ca12e57a6ecb40
author Olivier Deprez <olivier.deprez@arm.com> 1718090347 +0200
committer Manish Pandey <manish.pandey2@arm.com> 1718375855 +0200

refactor: drop Cortex-A32 reset to SP_MIN config

The Cortex-A32 FVP model is pinned in the CI to FM 11.12 which is a
largely outdated version. The following test config:
tf-l2-boot-tests-aarch32/fvp-aarch32-rst-to-sp-min:
fvp-linux32.rstspmin-dtb.aarch32-fip.uboot32-cortexa32x4.rstspmin-debug

relies on the RVBARADDR FVP parameter defining AP cores reset vector.
However this parameter has been removed in recent FVP models.
The reasoning is that the corresponding RTL doesn't implement this
capability hence the model was aligned accordingly.

The reset vector address is no longer freely configurable as required
by this test. The only possible reset vector address values per the
AArch32 architecture are either 0x0 (low address reset vector, when
VINITHI external signal low) or 0xFFFF0000 (high address reset vector,
when VINITHI=1). Using high address reset vector has been investigated,
however impractical because lying in NS DRAM. Secondly this leaves only
64KB for all BL32 SPMIN images sections. Using low address reset vector
is possible however the flash component emulated at this address is
read-only memory. Based on these concerns it is decided to drop this
test entirely provided this scenario doesn't reflect a valid case
against the Cortex-A32 architecture. The 'reset to SP_MIN' scenario is
covered by other tests in the TF-A CI test suites.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2f28612f5e27d8896900a861ad98a2d31237bd93