diff --git a/expect/unhandled_exception_at_el3.exp b/expect/unhandled_exception_at_el3.exp
new file mode 100644
index 0000000..cef8fca
--- /dev/null
+++ b/expect/unhandled_exception_at_el3.exp
@@ -0,0 +1,91 @@
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Expect script for Trusted Firmware Test Framework
+#
+
+source [file join [file dirname [info script]] handle-arguments.inc]
+
+expect_string "Unhandled Exception in EL3."
+expect_string "x30"
+expect_string "x0"
+expect_string "x1"
+expect_string "x2"
+expect_string "x3"
+expect_string "x4"
+expect_string "x5"
+expect_string "x6"
+expect_string "x7"
+expect_string "x8"
+expect_string "x9"
+expect_string "x10"
+expect_string "x11"
+expect_string "x12"
+expect_string "x13"
+expect_string "x14"
+expect_string "x15"
+expect_string "x16"
+expect_string "x17"
+expect_string "x18"
+expect_string "x19"
+expect_string "x20"
+expect_string "x21"
+expect_string "x22"
+expect_string "x23"
+expect_string "x24"
+expect_string "x25"
+expect_string "x26"
+expect_string "x27"
+expect_string "x28"
+expect_string "x29"
+expect_string "scr_el3"
+expect_string "sctlr_el3"
+expect_string "cptr_el3"
+expect_string "tcr_el3"
+expect_string "daif"
+expect_string "mair_el3"
+expect_string "spsr_el3"
+expect_string "elr_el3"
+expect_string "ttbr0_el3"
+expect_string "esr_el3"
+expect_string "far_el3"
+expect_string "spsr_el1"
+expect_string "elr_el1"
+expect_string "spsr_abt"
+expect_string "spsr_und"
+expect_string "spsr_irq"
+expect_string "spsr_fiq"
+expect_string "sctlr_el1"
+expect_string "actlr_el1"
+expect_string "cpacr_el1"
+expect_string "csselr_el1"
+expect_string "sp_el1"
+expect_string "esr_el1"
+expect_string "ttbr0_el1"
+expect_string "ttbr1_el1"
+expect_string "mair_el1"
+expect_string "amair_el1"
+expect_string "tcr_el1"
+expect_string "tpidr_el1"
+expect_string "tpidr_el0"
+expect_string "tpidrro_el0"
+expect_string "par_el1"
+expect_string "mpidr_el1"
+expect_string "afsr0_el1"
+expect_string "afsr1_el1"
+expect_string "contextidr_el1"
+expect_string "vbar_el1"
+expect_string "cntp_ctl_el0"
+expect_string "cntp_cval_el0"
+expect_string "cntv_ctl_el0"
+expect_string "cntv_cval_el0"
+expect_string "cntkctl_el1"
+expect_string "sp_el0"
+expect_string "isr_el1"
+expect_string "dacr32_el2"
+expect_string "ifsr32_el2"
+expect_string "icc_hppir0_el1"
+expect_string "icc_hppir1_el1"
+expect_string "icc_ctlr_el3"
diff --git a/group/tf-l2-boot-tests-misc/fvp-no-sys-regs-trace-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug b/group/tf-l2-boot-tests-misc/fvp-no-sys-regs-trace-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug
new file mode 100644
index 0000000..1bbc737
--- /dev/null
+++ b/group/tf-l2-boot-tests-misc/fvp-no-sys-regs-trace-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l2-boot-tests-misc/fvp-no-trbe-regs-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug b/group/tf-l2-boot-tests-misc/fvp-no-trbe-regs-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug
new file mode 100644
index 0000000..1bbc737
--- /dev/null
+++ b/group/tf-l2-boot-tests-misc/fvp-no-trbe-regs-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l2-boot-tests-misc/fvp-no-trf-regs-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug b/group/tf-l2-boot-tests-misc/fvp-no-trf-regs-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug
new file mode 100644
index 0000000..1bbc737
--- /dev/null
+++ b/group/tf-l2-boot-tests-misc/fvp-no-trf-regs-access,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/lava-expect/unhandled_exception_at_el3.exp b/lava-expect/unhandled_exception_at_el3.exp
new file mode 100644
index 0000000..1ac84c0
--- /dev/null
+++ b/lava-expect/unhandled_exception_at_el3.exp
@@ -0,0 +1,89 @@
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Expect script for Trusted Firmware Test Framework
+#
+
+expect_string+=('Unhandled Exception in EL3.')
+expect_string+=('x30')
+expect_string+=('x0')
+expect_string+=('x1')
+expect_string+=('x2')
+expect_string+=('x3')
+expect_string+=('x4')
+expect_string+=('x5')
+expect_string+=('x6')
+expect_string+=('x7')
+expect_string+=('x8')
+expect_string+=('x9')
+expect_string+=('x10')
+expect_string+=('x11')
+expect_string+=('x12')
+expect_string+=('x13')
+expect_string+=('x14')
+expect_string+=('x15')
+expect_string+=('x16')
+expect_string+=('x17')
+expect_string+=('x18')
+expect_string+=('x19')
+expect_string+=('x20')
+expect_string+=('x21')
+expect_string+=('x22')
+expect_string+=('x23')
+expect_string+=('x24')
+expect_string+=('x25')
+expect_string+=('x26')
+expect_string+=('x27')
+expect_string+=('x28')
+expect_string+=('x29')
+expect_string+=('scr_el3')
+expect_string+=('sctlr_el3')
+expect_string+=('cptr_el3')
+expect_string+=('tcr_el3')
+expect_string+=('daif')
+expect_string+=('mair_el3')
+expect_string+=('spsr_el3')
+expect_string+=('elr_el3')
+expect_string+=('ttbr0_el3')
+expect_string+=('esr_el3')
+expect_string+=('far_el3')
+expect_string+=('spsr_el1')
+expect_string+=('elr_el1')
+expect_string+=('spsr_abt')
+expect_string+=('spsr_und')
+expect_string+=('spsr_irq')
+expect_string+=('spsr_fiq')
+expect_string+=('sctlr_el1')
+expect_string+=('actlr_el1')
+expect_string+=('cpacr_el1')
+expect_string+=('csselr_el1')
+expect_string+=('sp_el1')
+expect_string+=('esr_el1')
+expect_string+=('ttbr0_el1')
+expect_string+=('ttbr1_el1')
+expect_string+=('mair_el1')
+expect_string+=('amair_el1')
+expect_string+=('tcr_el1')
+expect_string+=('tpidr_el1')
+expect_string+=('tpidr_el0')
+expect_string+=('tpidrro_el0')
+expect_string+=('par_el1')
+expect_string+=('mpidr_el1')
+expect_string+=('afsr0_el1')
+expect_string+=('afsr1_el1')
+expect_string+=('contextidr_el1')
+expect_string+=('vbar_el1')
+expect_string+=('cntp_ctl_el0')
+expect_string+=('cntp_cval_el0')
+expect_string+=('cntv_ctl_el0')
+expect_string+=('cntv_cval_el0')
+expect_string+=('cntkctl_el1')
+expect_string+=('sp_el0')
+expect_string+=('isr_el1')
+expect_string+=('dacr32_el2')
+expect_string+=('ifsr32_el2')
+expect_string+=('icc_hppir0_el1')
+expect_string+=('icc_hppir1_el1')
+expect_string+=('icc_ctlr_el3')
diff --git a/run_config/fvp-aemva.ete_trace_ext.bl31_panic b/run_config/fvp-aemva.ete_trace_ext.bl31_panic
new file mode 100644
index 0000000..eae33e8
--- /dev/null
+++ b/run_config/fvp-aemva.ete_trace_ext.bl31_panic
@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+	local model="base-aemva"
+
+	model_version="0.0" \
+	model_build="6684" \
+	etm_present="1" \
+	ete_plugin="1" \
+	supports_trace_buffer_control_regs="1" \
+	supports_trace_filter_regs="2" \
+	model="$model" gen_model_params
+
+	model="$model" gen_fvp_yaml
+}
+
+fetch_tf_resource() {
+	uart="0"  timeout="60" file="timeout_test.exp" track_expect
+	uart="1"  timeout="60" file="unhandled_exception_at_el3.exp" track_expect
+}
diff --git a/tf_config/fvp-no-sys-regs-trace-access b/tf_config/fvp-no-sys-regs-trace-access
new file mode 100644
index 0000000..4a5adb3
--- /dev/null
+++ b/tf_config/fvp-no-sys-regs-trace-access
@@ -0,0 +1,3 @@
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_SYS_REG_TRACE_FOR_NS=0
+PLAT=fvp
diff --git a/tf_config/fvp-no-trbe-regs-access b/tf_config/fvp-no-trbe-regs-access
new file mode 100644
index 0000000..d1ea80d
--- /dev/null
+++ b/tf_config/fvp-no-trbe-regs-access
@@ -0,0 +1,3 @@
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_TRBE_FOR_NS=0
+PLAT=fvp
diff --git a/tf_config/fvp-no-trf-regs-access b/tf_config/fvp-no-trf-regs-access
new file mode 100644
index 0000000..c18ad40
--- /dev/null
+++ b/tf_config/fvp-no-trf-regs-access
@@ -0,0 +1,3 @@
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_TRF_FOR_NS=0
+PLAT=fvp