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review.trustedfirmware.org / next / TF-M / trusted-firmware-m / ba8a3faa0c1acb042d44a6d9d8b7f593a5b7664c / . / interface / include / psa_manifest / sid.h
blob: 49169ee4860e9d7a2f1cb85bd0261b42f513d39e [file] [log] [blame]
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]1/*
2 * Copyright (c) 2019, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8/*********** WARNING: This is an auto-generated file. Do not edit! ***********/
9
10#ifndef __PSA_MANIFEST_SID_H__
11#define __PSA_MANIFEST_SID_H__
12
13#ifdef __cplusplus
14extern "C" {
15#endif
16
17/******** TFM_SP_STORAGE ********/
18#define TFM_SST_SET_SID (0x00000060U)
19#define TFM_SST_SET_VERSION (1U)
20#define TFM_SST_GET_SID (0x00000061U)
21#define TFM_SST_GET_VERSION (1U)
22#define TFM_SST_GET_INFO_SID (0x00000062U)
23#define TFM_SST_GET_INFO_VERSION (1U)
24#define TFM_SST_REMOVE_SID (0x00000063U)
25#define TFM_SST_REMOVE_VERSION (1U)
26#define TFM_SST_GET_SUPPORT_SID (0x00000064U)
27#define TFM_SST_GET_SUPPORT_VERSION (1U)
28
29/******** TFM_SP_CRYPTO ********/
30#define TFM_CRYPTO_SID (0x00000080U)
31#define TFM_CRYPTO_VERSION (1U)
32
33/******** TFM_SP_INITIAL_ATTESTATION ********/
34#define TFM_ATTEST_GET_TOKEN_SID (0x00000020U)
35#define TFM_ATTEST_GET_TOKEN_VERSION (1U)
36#define TFM_ATTEST_GET_TOKEN_SIZE_SID (0x00000021U)
37#define TFM_ATTEST_GET_TOKEN_SIZE_VERSION (1U)
38
39#ifdef TFM_PARTITION_TEST_CORE
40/******** TFM_SP_CORE_TEST ********/
41#define SPM_CORE_TEST_INIT_SUCCESS_SID (0x0000F020U)
42#define SPM_CORE_TEST_INIT_SUCCESS_VERSION (1U)
43#define SPM_CORE_TEST_DIRECT_RECURSION_SID (0x0000F021U)
44#define SPM_CORE_TEST_DIRECT_RECURSION_VERSION (1U)
45#define SPM_CORE_TEST_MPU_ACCESS_SID (0x0000F022U)
46#define SPM_CORE_TEST_MPU_ACCESS_VERSION (1U)
47#define SPM_CORE_TEST_MEMORY_PERMISSIONS_SID (0x0000F023U)
48#define SPM_CORE_TEST_MEMORY_PERMISSIONS_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]49#define SPM_CORE_TEST_SS_TO_SS_SID (0x0000F024U)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]50#define SPM_CORE_TEST_SS_TO_SS_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]51#define SPM_CORE_TEST_SS_TO_SS_BUFFER_SID (0x0000F025U)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]52#define SPM_CORE_TEST_SS_TO_SS_BUFFER_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]53#define SPM_CORE_TEST_OUTVEC_WRITE_SID (0x0000F026U)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]54#define SPM_CORE_TEST_OUTVEC_WRITE_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]55#define SPM_CORE_TEST_PERIPHERAL_ACCESS_SID (0x0000F027U)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]56#define SPM_CORE_TEST_PERIPHERAL_ACCESS_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]57#define SPM_CORE_TEST_GET_CALLER_CLIENT_ID_SID (0x0000F028U)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]58#define SPM_CORE_TEST_GET_CALLER_CLIENT_ID_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]59#define SPM_CORE_TEST_SPM_REQUEST_SID (0x0000F029U)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]60#define SPM_CORE_TEST_SPM_REQUEST_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]61#define SPM_CORE_TEST_BLOCK_SID (0x0000F02AU)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]62#define SPM_CORE_TEST_BLOCK_VERSION (1U)
Shawn Shancfd7c1c2019-09-02 17:50:52 +0800[diff] [blame]63#define SPM_CORE_TEST_NS_THREAD_SID (0x0000F02BU)
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]64#define SPM_CORE_TEST_NS_THREAD_VERSION (1U)
65#endif /* TFM_PARTITION_TEST_CORE */
66
67#ifdef TFM_PARTITION_TEST_CORE
68/******** TFM_SP_CORE_TEST_2 ********/
69#define SPM_CORE_TEST_2_SLAVE_SERVICE_SID (0x0000F040U)
70#define SPM_CORE_TEST_2_SLAVE_SERVICE_VERSION (1U)
71#define SPM_CORE_TEST_2_CHECK_CALLER_CLIENT_ID_SID (0x0000F041U)
72#define SPM_CORE_TEST_2_CHECK_CALLER_CLIENT_ID_VERSION (1U)
73#define SPM_CORE_TEST_2_GET_EVERY_SECOND_BYTE_SID (0x0000F042U)
74#define SPM_CORE_TEST_2_GET_EVERY_SECOND_BYTE_VERSION (1U)
75#define SPM_CORE_TEST_2_INVERT_SID (0x0000F043U)
76#define SPM_CORE_TEST_2_INVERT_VERSION (1U)
77#define SPM_CORE_TEST_2_PREPARE_TEST_SCENARIO_SID (0x0000F044U)
78#define SPM_CORE_TEST_2_PREPARE_TEST_SCENARIO_VERSION (1U)
79#define SPM_CORE_TEST_2_EXECUTE_TEST_SCENARIO_SID (0x0000F045U)
80#define SPM_CORE_TEST_2_EXECUTE_TEST_SCENARIO_VERSION (1U)
81#endif /* TFM_PARTITION_TEST_CORE */
82
83#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
84/******** TFM_SP_SECURE_TEST_PARTITION ********/
85#define TFM_SECURE_CLIENT_SFN_RUN_TESTS_SID (0x0000F000U)
86#define TFM_SECURE_CLIENT_SFN_RUN_TESTS_VERSION (1U)
87#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
88
89#ifdef TFM_PARTITION_TEST_CORE_IPC
90/******** TFM_SP_IPC_SERVICE_TEST ********/
91#define IPC_SERVICE_TEST_BASIC_SID (0x0000F080U)
92#define IPC_SERVICE_TEST_BASIC_VERSION (1U)
93#define IPC_SERVICE_TEST_PSA_ACCESS_APP_MEM_SID (0x0000F081U)
94#define IPC_SERVICE_TEST_PSA_ACCESS_APP_MEM_VERSION (1U)
95#define IPC_SERVICE_TEST_PSA_ACCESS_APP_READ_ONLY_MEM_SID (0x0000F082U)
96#define IPC_SERVICE_TEST_PSA_ACCESS_APP_READ_ONLY_MEM_VERSION (1U)
97#define IPC_SERVICE_TEST_APP_ACCESS_PSA_MEM_SID (0x0000F083U)
98#define IPC_SERVICE_TEST_APP_ACCESS_PSA_MEM_VERSION (1U)
99#endif /* TFM_PARTITION_TEST_CORE_IPC */
100
101#ifdef TFM_PARTITION_TEST_CORE_IPC
102/******** TFM_SP_IPC_CLIENT_TEST ********/
103#define IPC_CLIENT_TEST_BASIC_SID (0x0000F060U)
104#define IPC_CLIENT_TEST_BASIC_VERSION (1U)
105#define IPC_CLIENT_TEST_PSA_ACCESS_APP_MEM_SID (0x0000F061U)
106#define IPC_CLIENT_TEST_PSA_ACCESS_APP_MEM_VERSION (1U)
107#define IPC_CLIENT_TEST_PSA_ACCESS_APP_READ_ONLY_MEM_SID (0x0000F062U)
108#define IPC_CLIENT_TEST_PSA_ACCESS_APP_READ_ONLY_MEM_VERSION (1U)
109#define IPC_CLIENT_TEST_APP_ACCESS_PSA_MEM_SID (0x0000F063U)
110#define IPC_CLIENT_TEST_APP_ACCESS_PSA_MEM_VERSION (1U)
111#define IPC_CLIENT_TEST_MEM_CHECK_SID (0x0000F064U)
112#define IPC_CLIENT_TEST_MEM_CHECK_VERSION (1U)
113#endif /* TFM_PARTITION_TEST_CORE_IPC */
114
David Hu33f2fd22019-08-16 15:32:39 +0800[diff] [blame]115#ifdef TFM_ENABLE_IRQ_TEST
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]116/******** TFM_IRQ_TEST_1 ********/
117#define SPM_CORE_IRQ_TEST_1_PREPARE_TEST_SCENARIO_SID (0x0000F0A0U)
118#define SPM_CORE_IRQ_TEST_1_PREPARE_TEST_SCENARIO_VERSION (1U)
119#define SPM_CORE_IRQ_TEST_1_EXECUTE_TEST_SCENARIO_SID (0x0000F0A1U)
120#define SPM_CORE_IRQ_TEST_1_EXECUTE_TEST_SCENARIO_VERSION (1U)
David Hu33f2fd22019-08-16 15:32:39 +0800[diff] [blame]121#endif /* TFM_ENABLE_IRQ_TEST */
Edison Ai5bf0bfc2019-06-10 13:42:43 +0800[diff] [blame]122
123#ifdef __cplusplus
124}
125#endif
126
127#endif /* __PSA_MANIFEST_SID_H__ */