Platform: Add GNUARM support for Musca platform
Details:
- add necessary startup files and linker scripts
- update platform/ext/musca_a.cmake
- fix region_defs.h syntax to be compatible with the linker
- add special 4 byte aligned memset and memcpy functions to flash
driver
Change-Id: I2339abeff1f0187053d39c1f000bf95c7f8a200f
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
diff --git a/CommonConfig.cmake b/CommonConfig.cmake
index b05561a..591f8b7 100755
--- a/CommonConfig.cmake
+++ b/CommonConfig.cmake
@@ -57,7 +57,7 @@
include("Common/FindGNUARM")
include("Common/${GNUARM_MODULE}")
- set (COMMON_COMPILE_FLAGS -fshort-enums -fshort-wchar -funsigned-char -msoft-float -mcmse)
+ set (COMMON_COMPILE_FLAGS -fshort-enums -fshort-wchar -funsigned-char -msoft-float -mcmse --specs=nano.specs)
##Shared compiler and linker settings.
function(config_setting_shared_compiler_flags tgt)
embedded_set_target_compile_flags(TARGET ${tgt} LANGUAGE C FLAGS -xc -std=c99 ${COMMON_COMPILE_FLAGS} -Wall -Werror -Wno-format -Wno-return-type -Wno-unused-but-set-variable)
@@ -69,7 +69,7 @@
#with short wchars, however the standard library is compiled with normal
#wchar, and this generates linker time warnings. TF-M code does not use
#wchar, so the warning can be suppressed.
- embedded_set_target_link_flags(TARGET ${tgt} FLAGS -Xlinker -check-sections -Xlinker -fatal-warnings --entry=Reset_Handler -Wl,--no-wchar-size-warning)
+ embedded_set_target_link_flags(TARGET ${tgt} FLAGS -Xlinker -check-sections -Xlinker -fatal-warnings --entry=Reset_Handler -Wl,--no-wchar-size-warning --specs=nano.specs)
endfunction()
else()
message(FATAL_ERROR "ERROR: Compiler \"${COMPILER}\" is not supported.")
@@ -195,7 +195,14 @@
endif()
if (NOT DEFINED MBEDTLS_DEBUG)
- set (MBEDTLS_DEBUG ON)
+ if (${COMPILER} STREQUAL "GNUARM" AND ${TARGET_PLATFORM} STREQUAL "MUSCA_A" AND BL2)
+ #The size of the MCUboot binary compiled with GCC exceeds the size limit on
+ #Musca A. By turning off the mbed TLS debug build is a good way to go below
+ #that limit, while it is still possible to debug TFM/bootloader code.
+ set (MBEDTLS_DEBUG OFF)
+ else ()
+ set (MBEDTLS_DEBUG ON)
+ endif ()
endif()
##Set mbedTLS compiler flags for BL2 bootloader
diff --git a/platform/ext/musca_a.cmake b/platform/ext/musca_a.cmake
index f230c2e..7eafeca 100755
--- a/platform/ext/musca_a.cmake
+++ b/platform/ext/musca_a.cmake
@@ -13,16 +13,28 @@
set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
#Specify the location of platform specific build dependencies.
-set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_bl2.sct")
-set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_s.sct")
-set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_ns.sct")
-set (FLASH_LAYOUT "${PLATFORM_DIR}/target/musca_a/partition/flash_layout.h")
+if(COMPILER STREQUAL "ARMCLANG")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_bl2.sct")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_s.sct")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_ns.sct")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
+ endif()
+elseif(COMPILER STREQUAL "GNUARM")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/musca_bl2.ld")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/musca_s.ld")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/musca_ns.ld")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
+ endif()
+else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+endif()
+set (FLASH_LAYOUT "${PLATFORM_DIR}/target/musca_a/partition/flash_layout.h")
set (PLATFORM_LINK_INCLUDES "${PLATFORM_DIR}/target/musca_a/partition")
set (SIGN_BIN_SIZE 0x30000)
-if (DEFINED CMSIS_5_DIR)
- # not all project defines CMSIS_5_DIR, only the ones that use it.
- set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
-endif()
if (BL2)
set (BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
@@ -87,6 +99,12 @@
list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s")
list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s")
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S")
+ set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
+ PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld
index 3ac664e..4a005b7 100644
--- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld
+++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld
@@ -40,6 +40,14 @@
ENTRY(Reset_Handler)
+/*
+ * The test service veneers may not be referenced in the secure binary so the
+ * veneer objects are explicitly declared here as extern, so the linker includes
+ * the veneers in the resulting binary.
+ */
+EXTERN(sst_test_service_veneer_setup)
+EXTERN(tfm_secure_client_service_veneer_run_tests)
+
SECTIONS
{
.TFM_VECTORS : ALIGN(4)
diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template
index 59f271f..318b91d 100644
--- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template
+++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template
@@ -40,6 +40,14 @@
ENTRY(Reset_Handler)
+/*
+ * The test service veneers may not be referenced in the secure binary so the
+ * veneer objects are explicitly declared here as extern, so the linker includes
+ * the veneers in the resulting binary.
+ */
+EXTERN(sst_test_service_veneer_setup)
+EXTERN(tfm_secure_client_service_veneer_run_tests)
+
SECTIONS
{
.TFM_VECTORS : ALIGN(4)
diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
index 60499d8..1ba884d 100644
--- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
@@ -40,6 +40,14 @@
ENTRY(Reset_Handler)
+/*
+ * The test service veneers may not be referenced in the secure binary so the
+ * veneer objects are explicitly declared here as extern, so the linker includes
+ * the veneers in the resulting binary.
+ */
+EXTERN(sst_test_service_veneer_setup)
+EXTERN(tfm_secure_client_service_veneer_run_tests)
+
SECTIONS
{
.TFM_VECTORS : ALIGN(4)
diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template
index f3fbc0a..805ec3f 100644
--- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template
@@ -40,6 +40,14 @@
ENTRY(Reset_Handler)
+/*
+ * The test service veneers may not be referenced in the secure binary so the
+ * veneer objects are explicitly declared here as extern, so the linker includes
+ * the veneers in the resulting binary.
+ */
+EXTERN(sst_test_service_veneer_setup)
+EXTERN(tfm_secure_client_service_veneer_run_tests)
+
SECTIONS
{
.TFM_VECTORS : ALIGN(4)
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
index a5c6e0e..807702a 100755
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_Flash.c
@@ -31,6 +31,44 @@
/* Driver version */
#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
+/* FIXME: The following utility functions should be moved to a common place. */
+static int32_t memcpy4(void * to, const void * from, size_t size)
+{
+ /* make sure that the parameters are aligned to 4 */
+ if (((uint32_t)to & 0x03u) || ((uint32_t)from & 0x03u) || (size & 0x03u)) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ for (int i = 0; i < size/4; ++i)
+ {
+ ((uint32_t*)to)[i] = ((uint32_t*)from)[i];
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t memset4(void * addr, int pattern, size_t count)
+{
+ uint32_t pattern32;
+
+ /* make sure that the parameters are aligned to 4 */
+ if (((uint32_t)addr & 0x03u) || (count & 0x03u)) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ pattern32 = (uint32_t)pattern |
+ (uint32_t)pattern << 8 |
+ (uint32_t)pattern << 16 |
+ (uint32_t)pattern << 24;
+
+ for (int i = 0; i < count/4; ++i)
+ {
+ ((uint32_t*)addr)[i] = pattern32;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
/*
* ARM FLASH device structure
*/
@@ -194,17 +232,23 @@
if(addr >= SST_FLASH_AREA_ADDR &&
addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
start_addr = S_CODE_SRAM_ALIAS_BASE + addr;
+ /* Flash interface emulated over CODE SRAM. Writing it on 4 aligned
+ * addresses is necessary, so use a special memcpy function.
+ */
+ rc = memcpy4((void *)start_addr, data, cnt);
+ if (rc != ARM_DRIVER_OK) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+ } else {
+ /* Flash interface just emulated over SRAM, use memcpy */
+ memcpy((void *)start_addr, data, cnt);
}
-
- /* Flash interface just emulated over SRAM, use memcpy */
- memcpy((void *)start_addr, data, cnt);
return ARM_DRIVER_OK;
}
static int32_t ARM_Flash_EraseSector(uint32_t addr)
{
volatile uint32_t mem_base = FLASH0_DEV->memory_base;
- uint32_t start_addr = mem_base + addr;
uint32_t rc = 0;
rc = is_range_valid(FLASH0_DEV, addr);
@@ -216,13 +260,22 @@
/* Redirecting SST storage to code sram */
if(addr >= SST_FLASH_AREA_ADDR &&
addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
- start_addr = S_CODE_SRAM_ALIAS_BASE + addr;
- }
+ /* Flash interface emulated over CODE SRAM. Writing it on 4 aligned
+ * addresses is necessary, so use a special memset function.
+ */
+ rc = memset4((void *)(S_CODE_SRAM_ALIAS_BASE + addr),
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ if (rc != ARM_DRIVER_OK) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
- /* Flash interface just emulated over SRAM, use memset */
- memset((void *)start_addr,
- FLASH0_DEV->data->erased_value,
- FLASH0_DEV->data->sector_size);
+ } else {
+ /* Flash interface just emulated over SRAM, use memset */
+ memset((void *)mem_base + addr,
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ }
return ARM_DRIVER_OK;
}
@@ -238,10 +291,14 @@
/* Redirecting SST storage to code sram */
if(addr >= SST_FLASH_AREA_ADDR &&
addr <= SST_FLASH_AREA_ADDR + FLASH_SST_AREA_SIZE) {
- memset((void *)addr - FLASH0_DEV->memory_base
+ rc = memset4((void *)addr - FLASH0_DEV->memory_base
+ S_CODE_SRAM_ALIAS_BASE,
- FLASH0_DEV->data->erased_value,
- FLASH0_DEV->data->sector_size);
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ if (rc != ARM_DRIVER_OK) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
} else {
/* Flash interface just emulated over SRAM, use memset */
memset((void *)addr,
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld
new file mode 100644
index 0000000..842bd58
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld
@@ -0,0 +1,202 @@
+;/*
+; * Copyright (c) 2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
+ RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
+}
+
+__heap_size__ = 0x00010000;
+__psp_stack_size__ = 0x00000800;
+__msp_stack_size__ = 0x00000800;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * define etext2/data2_start/data2_end and
+ * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_musca_bl2.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (DEFINED(__etext2) ? __etext2 : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+ __copy_table_end__ = .;
+ } > FLASH
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_musca_bl2.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+ LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+ __zero_table_end__ = .;
+ } > FLASH
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ .psp_stack :
+ {
+ . = ALIGN(8);
+ KEEP(*(.psp_stack*))
+ . += __psp_stack_size__;
+ } > RAM
+ __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+ Stack_Mem = ADDR(.psp_stack);
+
+ .msp_stack :
+ {
+ . = ALIGN(8);
+ KEEP(*(.psp_stack*))
+ . += __msp_stack_size__;
+ } > RAM
+ __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM
+
+ PROVIDE( __stack = __initial_msp);
+}
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld
new file mode 100644
index 0000000..81a92c7
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld
@@ -0,0 +1,202 @@
+;/*
+; * Copyright (c) 2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
+ RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
+}
+
+__heap_size__ = 0x00001000;
+__psp_stack_size__ = 0x00000C00;
+__msp_stack_size__ = 0x00000400;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * define etext2/data2_start/data2_end and
+ * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_musca_ns.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (DEFINED(__etext2) ? __etext2 : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+ __copy_table_end__ = .;
+ } > FLASH
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_musca_ns.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+ LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+ __zero_table_end__ = .;
+ } > FLASH
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ .psp_stack :
+ {
+ . = ALIGN(8);
+ KEEP(*(.psp_stack*))
+ . += __psp_stack_size__;
+ } > RAM
+ __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+ Stack_Mem = ADDR(.psp_stack);
+
+ .msp_stack :
+ {
+ . = ALIGN(8);
+ KEEP(*(.psp_stack*))
+ . += __msp_stack_size__;
+ } > RAM
+ __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM
+
+ PROVIDE(__stack = __initial_sp);
+}
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
new file mode 100644
index 0000000..4a005b7
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld
@@ -0,0 +1,588 @@
+;/*
+; * Copyright (c) 2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/*********** WARNING: This is an auto-generated file. Do not edit! ***********/
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+ RAM (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
+ VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE
+}
+
+__heap_size__ = 0x00001000;
+__psp_stack_size__ = 0x00001000;
+__msp_stack_size__ = 0x00000800;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+/*
+ * The test service veneers may not be referenced in the secure binary so the
+ * veneer objects are explicitly declared here as extern, so the linker includes
+ * the veneers in the resulting binary.
+ */
+EXTERN(sst_test_service_veneer_setup)
+EXTERN(tfm_secure_client_service_veneer_run_tests)
+
+SECTIONS
+{
+ .TFM_VECTORS : ALIGN(4)
+ {
+ __vectors_start__ = .;
+ KEEP(*(.vectors))
+ *startup*(.text*)
+ . = ALIGN(4);
+ __vectors_end__ = .;
+ } > FLASH
+
+#if TFM_LVL == 1
+ .copy.table : ALIGN(4)
+ {
+ __copy_table_start__ = .;
+ LONG (LOADADDR(.TFM_DATA))
+ LONG (ADDR(.TFM_DATA))
+ LONG (SIZEOF(.TFM_DATA))
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table : ALIGN(4)
+ {
+ __zero_table_start__ = .;
+ LONG (ADDR(.TFM_BSS))
+ LONG (SIZEOF(.TFM_BSS))
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+ LONG (ADDR(.TFM_UNPRIV_SCRATCH))
+ LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
+ __zero_table_end__ = .;
+ } > FLASH
+
+#else /* TFM_LVL == 1 */
+ .copy.table : ALIGN(4)
+ {
+ __copy_table_start__ = .;
+ LONG (LOADADDR(.TFM_DATA))
+ LONG (ADDR(.TFM_DATA))
+ LONG (SIZEOF(.TFM_DATA))
+ LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))
+ LONG (ADDR(.TFM_UNPRIV_RO_DATA))
+ LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))
+ LONG (LOADADDR(.TFM_SP_STORAGE_DATA))
+ LONG (ADDR(.TFM_SP_STORAGE_DATA))
+ LONG (SIZEOF(.TFM_SP_STORAGE_DATA))
+ LONG (LOADADDR(.TFM_SP_AUDIT_LOG_DATA))
+ LONG (ADDR(.TFM_SP_AUDIT_LOG_DATA))
+ LONG (SIZEOF(.TFM_SP_AUDIT_LOG_DATA))
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (LOADADDR(.TFM_SP_CORE_TEST_DATA))
+ LONG (ADDR(.TFM_SP_CORE_TEST_DATA))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_DATA))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (LOADADDR(.TFM_SP_CORE_TEST_2_DATA))
+ LONG (ADDR(.TFM_SP_CORE_TEST_2_DATA))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_2_DATA))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SST
+ LONG (LOADADDR(.TFM_SP_SST_TEST_PARTITION_DATA))
+ LONG (ADDR(.TFM_SP_SST_TEST_PARTITION_DATA))
+ LONG (SIZEOF(.TFM_SP_SST_TEST_PARTITION_DATA))
+#endif /* TFM_PARTITION_TEST_SST */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ LONG (LOADADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA))
+ LONG (ADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA))
+ LONG (SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_DATA))
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table : ALIGN(4)
+ {
+ __zero_table_start__ = .;
+ LONG (ADDR(.TFM_BSS))
+ LONG (SIZEOF(.TFM_BSS))
+ LONG (ADDR(.TFM_UNPRIV_RO_BSS))
+ LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))
+ LONG (ADDR(.TFM_SP_STORAGE_BSS))
+ LONG (SIZEOF(.TFM_SP_STORAGE_BSS))
+ LONG (ADDR(.TFM_SP_STORAGE_STACK))
+ LONG (SIZEOF(.TFM_SP_STORAGE_STACK))
+ LONG (ADDR(.TFM_SP_AUDIT_LOG_BSS))
+ LONG (SIZEOF(.TFM_SP_AUDIT_LOG_BSS))
+ LONG (ADDR(.TFM_SP_AUDIT_LOG_STACK))
+ LONG (SIZEOF(.TFM_SP_AUDIT_LOG_STACK))
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (ADDR(.TFM_SP_CORE_TEST_BSS))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_BSS))
+ LONG (ADDR(.TFM_SP_CORE_TEST_STACK))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_STACK))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ LONG (ADDR(.TFM_SP_CORE_TEST_2_BSS))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_2_BSS))
+ LONG (ADDR(.TFM_SP_CORE_TEST_2_STACK))
+ LONG (SIZEOF(.TFM_SP_CORE_TEST_2_STACK))
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SST
+ LONG (ADDR(.TFM_SP_SST_TEST_PARTITION_BSS))
+ LONG (SIZEOF(.TFM_SP_SST_TEST_PARTITION_BSS))
+ LONG (ADDR(.TFM_SP_SST_TEST_PARTITION_STACK))
+ LONG (SIZEOF(.TFM_SP_SST_TEST_PARTITION_STACK))
+#endif /* TFM_PARTITION_TEST_SST */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ LONG (ADDR(.TFM_SP_SECURE_TEST_PARTITION_BSS))
+ LONG (SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_BSS))
+ LONG (ADDR(.TFM_SP_SECURE_TEST_PARTITION_STACK))
+ LONG (SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_STACK))
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+ LONG (ADDR(.TFM_UNPRIV_SCRATCH))
+ LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
+ __zero_table_end__ = .;
+ } > FLASH
+
+ .TFM_UNPRIV_CODE : ALIGN(32)
+ {
+ *tfm_unpriv_api.o(.text*)
+ *tfm_unpriv_api.o(.rodata*)
+ *tfm_sst_secure_api.o(.text*)
+ *tfm_sst_secure_api.o(.rodata*)
+ *dummy_crypto_keys.o(.text*)
+ *dummy_crypto_keys.o(.rodata*)
+ *platform_retarget_dev.o(.text*)
+ *platform_retarget_dev.o(.rodata*)
+ *(SFN)
+ *libgcc*:*(.text*)
+ *libgcc*:*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
+ Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+
+ .TFM_SP_STORAGE : ALIGN(32)
+ {
+ *tfm_storage*:*(.text*)
+ *tfm_storage*:*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_SP_STORAGE$$RO$$Base = ADDR(.TFM_SP_STORAGE);
+ Image$$TFM_SP_STORAGE$$RO$$Limit = ADDR(.TFM_SP_STORAGE) + SIZEOF(.TFM_SP_STORAGE);
+ Image$$TFM_SP_STORAGE$$Base = ADDR(.TFM_SP_STORAGE);
+ Image$$TFM_SP_STORAGE$$Limit = ADDR(.TFM_SP_STORAGE) + SIZEOF(.TFM_SP_STORAGE);
+
+ .TFM_SP_AUDIT_LOG : ALIGN(32)
+ {
+ *tfm_audit*:*(.text*)
+ *tfm_audit*:*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_SP_AUDIT_LOG$$RO$$Base = ADDR(.TFM_SP_AUDIT_LOG);
+ Image$$TFM_SP_AUDIT_LOG$$RO$$Limit = ADDR(.TFM_SP_AUDIT_LOG) + SIZEOF(.TFM_SP_AUDIT_LOG);
+ Image$$TFM_SP_AUDIT_LOG$$Base = ADDR(.TFM_SP_AUDIT_LOG);
+ Image$$TFM_SP_AUDIT_LOG$$Limit = ADDR(.TFM_SP_AUDIT_LOG) + SIZEOF(.TFM_SP_AUDIT_LOG);
+
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST : ALIGN(32)
+ {
+ *tfm_ss_core_test.*(.text*)
+ *tfm_ss_core_test.*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_SP_CORE_TEST$$RO$$Base = ADDR(.TFM_SP_CORE_TEST);
+ Image$$TFM_SP_CORE_TEST$$RO$$Limit = ADDR(.TFM_SP_CORE_TEST) + SIZEOF(.TFM_SP_CORE_TEST);
+ Image$$TFM_SP_CORE_TEST$$Base = ADDR(.TFM_SP_CORE_TEST);
+ Image$$TFM_SP_CORE_TEST$$Limit = ADDR(.TFM_SP_CORE_TEST) + SIZEOF(.TFM_SP_CORE_TEST);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST_2 : ALIGN(32)
+ {
+ *tfm_ss_core_test_2.*(.text*)
+ *tfm_ss_core_test_2.*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_SP_CORE_TEST_2$$RO$$Base = ADDR(.TFM_SP_CORE_TEST_2);
+ Image$$TFM_SP_CORE_TEST_2$$RO$$Limit = ADDR(.TFM_SP_CORE_TEST_2) + SIZEOF(.TFM_SP_CORE_TEST_2);
+ Image$$TFM_SP_CORE_TEST_2$$Base = ADDR(.TFM_SP_CORE_TEST_2);
+ Image$$TFM_SP_CORE_TEST_2$$Limit = ADDR(.TFM_SP_CORE_TEST_2) + SIZEOF(.TFM_SP_CORE_TEST_2);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SST
+ .TFM_SP_SST_TEST_PARTITION : ALIGN(32)
+ {
+ *sst_test_service.*(.text*)
+ *sst_test_service.*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_SP_SST_TEST_PARTITION$$RO$$Base = ADDR(.TFM_SP_SST_TEST_PARTITION);
+ Image$$TFM_SP_SST_TEST_PARTITION$$RO$$Limit = ADDR(.TFM_SP_SST_TEST_PARTITION) + SIZEOF(.TFM_SP_SST_TEST_PARTITION);
+ Image$$TFM_SP_SST_TEST_PARTITION$$Base = ADDR(.TFM_SP_SST_TEST_PARTITION);
+ Image$$TFM_SP_SST_TEST_PARTITION$$Limit = ADDR(.TFM_SP_SST_TEST_PARTITION) + SIZEOF(.TFM_SP_SST_TEST_PARTITION);
+
+#endif /* TFM_PARTITION_TEST_SST */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ .TFM_SP_SECURE_TEST_PARTITION : ALIGN(32)
+ {
+ *tfm_secure_client_service.*(.text*)
+ *tfm_secure_client_service.*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$RO$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION);
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$RO$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION);
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION);
+ Image$$TFM_SP_SECURE_TEST_PARTITION$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION);
+
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+#endif /* TFM_LVL == 1 */
+
+ .ER_TFM_CODE :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+#if TFM_LVL == 1
+
+ .TFM_SECURE_STACK : ALIGN(128)
+ {
+ . += 0x4000;
+ } > RAM AT> FLASH
+ Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
+ Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
+
+ .TFM_UNPRIV_SCRATCH : ALIGN(32)
+ {
+ . += 0x400;
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+#else /* TFM_LVL == 1 */
+ .TFM_UNPRIV_RO_DATA :
+ {
+ */tfm_unpriv_api.o(.data*)
+ */tfm_sst_secure_api.o(.data*)
+ */dummy_crypto_keys.o(.data*)
+ */platform_retarget_dev.o(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);
+ Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);
+
+ .TFM_UNPRIV_RO_BSS : ALIGN(32)
+ {
+ */tfm_unpriv_api.o(.bss*)
+ */tfm_sst_secure_api.o(.bss*)
+ */platform_retarget_dev.o(.bss*)
+ */dummy_crypto_keys.o(.bss*)
+ */tfm_unpriv_api.o(COMMON)
+ */tfm_sst_secure_api.o(COMMON)
+ */platform_retarget_dev.o(COMMON)
+ */dummy_crypto_keys.o(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);
+ Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);
+
+ .TFM_UNPRIV_SCRATCH : ALIGN(32)
+ {
+ . += 0x400;
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+ .TFM_SP_STORAGE_DATA : ALIGN(32)
+ {
+ *tfm_storage*:*(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_STORAGE_DATA$$RW$$Base = ADDR(.TFM_SP_STORAGE_DATA);
+ Image$$TFM_SP_STORAGE_DATA$$RW$$Limit = ADDR(.TFM_SP_STORAGE_DATA) + SIZEOF(.TFM_SP_STORAGE_DATA);
+
+ .TFM_SP_STORAGE_BSS : ALIGN(32)
+ {
+ *tfm_storage*:*(.bss*)
+ *tfm_storage*:*(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_STORAGE_DATA$$ZI$$Base = ADDR(.TFM_SP_STORAGE_BSS);
+ Image$$TFM_SP_STORAGE_DATA$$ZI$$Limit = ADDR(.TFM_SP_STORAGE_BSS) + SIZEOF(.TFM_SP_STORAGE_BSS);
+
+ .TFM_SP_STORAGE_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > RAM AT> FLASH
+ Image$$TFM_SP_STORAGE_STACK$$ZI$$Base = ADDR(.TFM_SP_STORAGE_STACK);
+ Image$$TFM_SP_STORAGE_STACK$$ZI$$Limit = ADDR(.TFM_SP_STORAGE_STACK) + SIZEOF(.TFM_SP_STORAGE_STACK);
+
+ .TFM_SP_AUDIT_LOG_DATA : ALIGN(32)
+ {
+ *tfm_audit*:*(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_AUDIT_LOG_DATA$$RW$$Base = ADDR(.TFM_SP_AUDIT_LOG_DATA);
+ Image$$TFM_SP_AUDIT_LOG_DATA$$RW$$Limit = ADDR(.TFM_SP_AUDIT_LOG_DATA) + SIZEOF(.TFM_SP_AUDIT_LOG_DATA);
+
+ .TFM_SP_AUDIT_LOG_BSS : ALIGN(32)
+ {
+ *tfm_audit*:*(.bss*)
+ *tfm_audit*:*(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_AUDIT_LOG_DATA$$ZI$$Base = ADDR(.TFM_SP_AUDIT_LOG_BSS);
+ Image$$TFM_SP_AUDIT_LOG_DATA$$ZI$$Limit = ADDR(.TFM_SP_AUDIT_LOG_BSS) + SIZEOF(.TFM_SP_AUDIT_LOG_BSS);
+
+ .TFM_SP_AUDIT_LOG_STACK : ALIGN(128)
+ {
+ . += 0x1000;
+ } > RAM AT> FLASH
+ Image$$TFM_SP_AUDIT_LOG_STACK$$ZI$$Base = ADDR(.TFM_SP_AUDIT_LOG_STACK);
+ Image$$TFM_SP_AUDIT_LOG_STACK$$ZI$$Limit = ADDR(.TFM_SP_AUDIT_LOG_STACK) + SIZEOF(.TFM_SP_AUDIT_LOG_STACK);
+
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST_DATA : ALIGN(32)
+ {
+ *tfm_ss_core_test.*(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_CORE_TEST_DATA$$RW$$Base = ADDR(.TFM_SP_CORE_TEST_DATA);
+ Image$$TFM_SP_CORE_TEST_DATA$$RW$$Limit = ADDR(.TFM_SP_CORE_TEST_DATA) + SIZEOF(.TFM_SP_CORE_TEST_DATA);
+
+ .TFM_SP_CORE_TEST_BSS : ALIGN(32)
+ {
+ *tfm_ss_core_test.*(.bss*)
+ *tfm_ss_core_test.*(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_CORE_TEST_DATA$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_BSS);
+ Image$$TFM_SP_CORE_TEST_DATA$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_BSS) + SIZEOF(.TFM_SP_CORE_TEST_BSS);
+
+ .TFM_SP_CORE_TEST_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > RAM AT> FLASH
+ Image$$TFM_SP_CORE_TEST_STACK$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_STACK);
+ Image$$TFM_SP_CORE_TEST_STACK$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_STACK) + SIZEOF(.TFM_SP_CORE_TEST_STACK);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_CORE
+ .TFM_SP_CORE_TEST_2_DATA : ALIGN(32)
+ {
+ *tfm_ss_core_test_2.*(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_CORE_TEST_2_DATA$$RW$$Base = ADDR(.TFM_SP_CORE_TEST_2_DATA);
+ Image$$TFM_SP_CORE_TEST_2_DATA$$RW$$Limit = ADDR(.TFM_SP_CORE_TEST_2_DATA) + SIZEOF(.TFM_SP_CORE_TEST_2_DATA);
+
+ .TFM_SP_CORE_TEST_2_BSS : ALIGN(32)
+ {
+ *tfm_ss_core_test_2.*(.bss*)
+ *tfm_ss_core_test_2.*(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_CORE_TEST_2_DATA$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_2_BSS);
+ Image$$TFM_SP_CORE_TEST_2_DATA$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_2_BSS) + SIZEOF(.TFM_SP_CORE_TEST_2_BSS);
+
+ .TFM_SP_CORE_TEST_2_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > RAM AT> FLASH
+ Image$$TFM_SP_CORE_TEST_2_STACK$$ZI$$Base = ADDR(.TFM_SP_CORE_TEST_2_STACK);
+ Image$$TFM_SP_CORE_TEST_2_STACK$$ZI$$Limit = ADDR(.TFM_SP_CORE_TEST_2_STACK) + SIZEOF(.TFM_SP_CORE_TEST_2_STACK);
+
+#endif /* TFM_PARTITION_TEST_CORE */
+#ifdef TFM_PARTITION_TEST_SST
+ .TFM_SP_SST_TEST_PARTITION_DATA : ALIGN(32)
+ {
+ *sst_test_service.*(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_SST_TEST_PARTITION_DATA$$RW$$Base = ADDR(.TFM_SP_SST_TEST_PARTITION_DATA);
+ Image$$TFM_SP_SST_TEST_PARTITION_DATA$$RW$$Limit = ADDR(.TFM_SP_SST_TEST_PARTITION_DATA) + SIZEOF(.TFM_SP_SST_TEST_PARTITION_DATA);
+
+ .TFM_SP_SST_TEST_PARTITION_BSS : ALIGN(32)
+ {
+ *sst_test_service.*(.bss*)
+ *sst_test_service.*(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_SST_TEST_PARTITION_DATA$$ZI$$Base = ADDR(.TFM_SP_SST_TEST_PARTITION_BSS);
+ Image$$TFM_SP_SST_TEST_PARTITION_DATA$$ZI$$Limit = ADDR(.TFM_SP_SST_TEST_PARTITION_BSS) + SIZEOF(.TFM_SP_SST_TEST_PARTITION_BSS);
+
+ .TFM_SP_SST_TEST_PARTITION_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > RAM AT> FLASH
+ Image$$TFM_SP_SST_TEST_PARTITION_STACK$$ZI$$Base = ADDR(.TFM_SP_SST_TEST_PARTITION_STACK);
+ Image$$TFM_SP_SST_TEST_PARTITION_STACK$$ZI$$Limit = ADDR(.TFM_SP_SST_TEST_PARTITION_STACK) + SIZEOF(.TFM_SP_SST_TEST_PARTITION_STACK);
+
+#endif /* TFM_PARTITION_TEST_SST */
+#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
+ .TFM_SP_SECURE_TEST_PARTITION_DATA : ALIGN(32)
+ {
+ *tfm_secure_client_service.*(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$RW$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA);
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$RW$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION_DATA) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_DATA);
+
+ .TFM_SP_SECURE_TEST_PARTITION_BSS : ALIGN(32)
+ {
+ *tfm_secure_client_service.*(.bss*)
+ *tfm_secure_client_service.*(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$ZI$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION_BSS);
+ Image$$TFM_SP_SECURE_TEST_PARTITION_DATA$$ZI$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION_BSS) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_BSS);
+
+ .TFM_SP_SECURE_TEST_PARTITION_STACK : ALIGN(128)
+ {
+ . += 0x2000;
+ } > RAM AT> FLASH
+ Image$$TFM_SP_SECURE_TEST_PARTITION_STACK$$ZI$$Base = ADDR(.TFM_SP_SECURE_TEST_PARTITION_STACK);
+ Image$$TFM_SP_SECURE_TEST_PARTITION_STACK$$ZI$$Limit = ADDR(.TFM_SP_SECURE_TEST_PARTITION_STACK) + SIZEOF(.TFM_SP_SECURE_TEST_PARTITION_STACK);
+
+#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
+#endif /* TFM_LVL == 1 */
+
+ .TFM_DATA :
+ {
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ } > RAM AT> FLASH
+ Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
+ Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
+
+ .TFM_BSS : ALIGN(4)
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM AT> FLASH
+ Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
+ Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
+
+ .psp_stack : ALIGN(128)
+ {
+ . += __psp_stack_size__;
+ } > RAM AT> FLASH
+ __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+ Stack_Mem = ADDR(.psp_stack);
+
+ .msp_stack : ALIGN(128)
+ {
+ . += __msp_stack_size__;
+ } > RAM AT> FLASH
+ __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap : ALIGN(8)
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM AT> FLASH
+
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) after the code, in a
+ * separate 32 bytes aligned region so that the SAU can programmed to just set
+ * this region as Non-Secure Callable.
+ */
+ .gnu.sgstubs : ALIGN(32)
+ {
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ } > VENEERS AT> VENEERS
+ Load$$LR$$LR_VENEER$$Base = ADDR(.gnu.sgstubs);
+ Load$$LR$$LR_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
+
+ Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;
+ Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;
+
+ PROVIDE(__stack = __initial_sp);
+ PROVIDE(Stack_top = __initial_sp);
+}
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
new file mode 100644
index 0000000..318b91d
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template
@@ -0,0 +1,395 @@
+;/*
+; * Copyright (c) 2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+@!GENERATOR_DONOTEDIT_WARNING!@
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+ RAM (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
+ VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE
+}
+
+__heap_size__ = 0x00001000;
+__psp_stack_size__ = 0x00001000;
+__msp_stack_size__ = 0x00000800;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+/*
+ * The test service veneers may not be referenced in the secure binary so the
+ * veneer objects are explicitly declared here as extern, so the linker includes
+ * the veneers in the resulting binary.
+ */
+EXTERN(sst_test_service_veneer_setup)
+EXTERN(tfm_secure_client_service_veneer_run_tests)
+
+SECTIONS
+{
+ .TFM_VECTORS : ALIGN(4)
+ {
+ __vectors_start__ = .;
+ KEEP(*(.vectors))
+ *startup*(.text*)
+ . = ALIGN(4);
+ __vectors_end__ = .;
+ } > FLASH
+
+#if TFM_LVL == 1
+ .copy.table : ALIGN(4)
+ {
+ __copy_table_start__ = .;
+ LONG (LOADADDR(.TFM_DATA))
+ LONG (ADDR(.TFM_DATA))
+ LONG (SIZEOF(.TFM_DATA))
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table : ALIGN(4)
+ {
+ __zero_table_start__ = .;
+ LONG (ADDR(.TFM_BSS))
+ LONG (SIZEOF(.TFM_BSS))
+ LONG (ADDR(.TFM_SECURE_STACK))
+ LONG (SIZEOF(.TFM_SECURE_STACK))
+ LONG (ADDR(.TFM_UNPRIV_SCRATCH))
+ LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
+ __zero_table_end__ = .;
+ } > FLASH
+
+#else /* TFM_LVL == 1 */
+ .copy.table : ALIGN(4)
+ {
+ __copy_table_start__ = .;
+ LONG (LOADADDR(.TFM_DATA))
+ LONG (ADDR(.TFM_DATA))
+ LONG (SIZEOF(.TFM_DATA))
+ LONG (LOADADDR(.TFM_UNPRIV_RO_DATA))
+ LONG (ADDR(.TFM_UNPRIV_RO_DATA))
+ LONG (SIZEOF(.TFM_UNPRIV_RO_DATA))
+@!GENERATOR_BLOCK_START!@
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#ifdef @@attr.conditional@@
+@!GENERATOR_CONDITIONAL_END!@
+ LONG (LOADADDR(.@@manifest.tfm_partition_name@@_DATA))
+ LONG (ADDR(.@@manifest.tfm_partition_name@@_DATA))
+ LONG (SIZEOF(.@@manifest.tfm_partition_name@@_DATA))
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#endif /* @@attr.conditional@@ */
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_BLOCK_END!@
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table : ALIGN(4)
+ {
+ __zero_table_start__ = .;
+ LONG (ADDR(.TFM_BSS))
+ LONG (SIZEOF(.TFM_BSS))
+ LONG (ADDR(.TFM_UNPRIV_RO_BSS))
+ LONG (SIZEOF(.TFM_UNPRIV_RO_BSS))
+@!GENERATOR_BLOCK_START!@
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#ifdef @@attr.conditional@@
+@!GENERATOR_CONDITIONAL_END!@
+ LONG (ADDR(.@@manifest.tfm_partition_name@@_BSS))
+ LONG (SIZEOF(.@@manifest.tfm_partition_name@@_BSS))
+ LONG (ADDR(.@@manifest.tfm_partition_name@@_STACK))
+ LONG (SIZEOF(.@@manifest.tfm_partition_name@@_STACK))
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#endif /* @@attr.conditional@@ */
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_BLOCK_END!@
+ LONG (ADDR(.TFM_UNPRIV_SCRATCH))
+ LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
+ __zero_table_end__ = .;
+ } > FLASH
+
+ .TFM_UNPRIV_CODE : ALIGN(32)
+ {
+ *tfm_unpriv_api.o(.text*)
+ *tfm_unpriv_api.o(.rodata*)
+ *tfm_sst_secure_api.o(.text*)
+ *tfm_sst_secure_api.o(.rodata*)
+ *dummy_crypto_keys.o(.text*)
+ *dummy_crypto_keys.o(.rodata*)
+ *platform_retarget_dev.o(.text*)
+ *platform_retarget_dev.o(.rodata*)
+ *(SFN)
+ *libgcc*:*(.text*)
+ *libgcc*:*(.rodata*)
+ . = ALIGN(32);
+ } > FLASH
+ Image$$TFM_UNPRIV_CODE$$RO$$Base = ADDR(.TFM_UNPRIV_CODE);
+ Image$$TFM_UNPRIV_CODE$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE);
+
+@!GENERATOR_BLOCK_START!@
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#ifdef @@attr.conditional@@
+@!GENERATOR_CONDITIONAL_END!@
+ .@@manifest.tfm_partition_name@@ : ALIGN(32)
+ {
+@!GENERATOR_CONDITIONAL_START!@ @@manifest.tfm_linker_pattern.library_list@@
+ @@manifest.tfm_linker_pattern.library_list@@:*(.text*)
+ @@manifest.tfm_linker_pattern.library_list@@:*(.rodata*)
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_CONDITIONAL_START!@ @@manifest.tfm_linker_pattern.object_list@@
+ @@manifest.tfm_linker_pattern.object_list@@(.text*)
+ @@manifest.tfm_linker_pattern.object_list@@(.rodata*)
+@!GENERATOR_CONDITIONAL_END!@
+ . = ALIGN(32);
+ } > FLASH
+ Image$$@@manifest.tfm_partition_name@@$$RO$$Base = ADDR(.@@manifest.tfm_partition_name@@);
+ Image$$@@manifest.tfm_partition_name@@$$RO$$Limit = ADDR(.@@manifest.tfm_partition_name@@) + SIZEOF(.@@manifest.tfm_partition_name@@);
+ Image$$@@manifest.tfm_partition_name@@$$Base = ADDR(.@@manifest.tfm_partition_name@@);
+ Image$$@@manifest.tfm_partition_name@@$$Limit = ADDR(.@@manifest.tfm_partition_name@@) + SIZEOF(.@@manifest.tfm_partition_name@@);
+
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#endif /* @@attr.conditional@@ */
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_BLOCK_END!@
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+#endif /* TFM_LVL == 1 */
+
+ .ER_TFM_CODE :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+#if TFM_LVL == 1
+
+ .TFM_SECURE_STACK : ALIGN(128)
+ {
+ . += 0x4000;
+ } > RAM AT> FLASH
+ Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
+ Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
+
+ .TFM_UNPRIV_SCRATCH : ALIGN(32)
+ {
+ . += 0x400;
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+#else /* TFM_LVL == 1 */
+ .TFM_UNPRIV_RO_DATA :
+ {
+ */tfm_unpriv_api.o(.data*)
+ */tfm_sst_secure_api.o(.data*)
+ */dummy_crypto_keys.o(.data*)
+ */platform_retarget_dev.o(.data*)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_RO_DATA$$RW$$Base = ADDR(.TFM_UNPRIV_RO_DATA);
+ Image$$TFM_UNPRIV_RO_DATA$$RW$$Limit = ADDR(.TFM_UNPRIV_RO_DATA) + SIZEOF(.TFM_UNPRIV_RO_DATA);
+
+ .TFM_UNPRIV_RO_BSS : ALIGN(32)
+ {
+ */tfm_unpriv_api.o(.bss*)
+ */tfm_sst_secure_api.o(.bss*)
+ */platform_retarget_dev.o(.bss*)
+ */dummy_crypto_keys.o(.bss*)
+ */tfm_unpriv_api.o(COMMON)
+ */tfm_sst_secure_api.o(COMMON)
+ */platform_retarget_dev.o(COMMON)
+ */dummy_crypto_keys.o(COMMON)
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_RO_DATA$$ZI$$Base = ADDR(.TFM_UNPRIV_RO_BSS);
+ Image$$TFM_UNPRIV_RO_DATA$$ZI$$Limit = ADDR(.TFM_UNPRIV_RO_BSS) + SIZEOF(.TFM_UNPRIV_RO_BSS);
+
+ .TFM_UNPRIV_SCRATCH : ALIGN(32)
+ {
+ . += 0x400;
+ } > RAM AT> FLASH
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+ Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+@!GENERATOR_BLOCK_START!@
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#ifdef @@attr.conditional@@
+@!GENERATOR_CONDITIONAL_END!@
+ .@@manifest.tfm_partition_name@@_DATA : ALIGN(32)
+ {
+@!GENERATOR_CONDITIONAL_START!@ @@manifest.tfm_linker_pattern.library_list@@
+ @@manifest.tfm_linker_pattern.library_list@@:*(.data*)
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_CONDITIONAL_START!@ @@manifest.tfm_linker_pattern.object_list@@
+ @@manifest.tfm_linker_pattern.object_list@@(.data*)
+@!GENERATOR_CONDITIONAL_END!@
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$@@manifest.tfm_partition_name@@_DATA$$RW$$Base = ADDR(.@@manifest.tfm_partition_name@@_DATA);
+ Image$$@@manifest.tfm_partition_name@@_DATA$$RW$$Limit = ADDR(.@@manifest.tfm_partition_name@@_DATA) + SIZEOF(.@@manifest.tfm_partition_name@@_DATA);
+
+ .@@manifest.tfm_partition_name@@_BSS : ALIGN(32)
+ {
+@!GENERATOR_CONDITIONAL_START!@ @@manifest.tfm_linker_pattern.library_list@@
+ @@manifest.tfm_linker_pattern.library_list@@:*(.bss*)
+ @@manifest.tfm_linker_pattern.library_list@@:*(COMMON)
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_CONDITIONAL_START!@ @@manifest.tfm_linker_pattern.object_list@@
+ @@manifest.tfm_linker_pattern.object_list@@(.bss*)
+ @@manifest.tfm_linker_pattern.object_list@@(COMMON)
+@!GENERATOR_CONDITIONAL_END!@
+ . = ALIGN(32);
+ } > RAM AT> FLASH
+ Image$$@@manifest.tfm_partition_name@@_DATA$$ZI$$Base = ADDR(.@@manifest.tfm_partition_name@@_BSS);
+ Image$$@@manifest.tfm_partition_name@@_DATA$$ZI$$Limit = ADDR(.@@manifest.tfm_partition_name@@_BSS) + SIZEOF(.@@manifest.tfm_partition_name@@_BSS);
+
+ .@@manifest.tfm_partition_name@@_STACK : ALIGN(128)
+ {
+ . += @@manifest.stack_size@@;
+ } > RAM AT> FLASH
+ Image$$@@manifest.tfm_partition_name@@_STACK$$ZI$$Base = ADDR(.@@manifest.tfm_partition_name@@_STACK);
+ Image$$@@manifest.tfm_partition_name@@_STACK$$ZI$$Limit = ADDR(.@@manifest.tfm_partition_name@@_STACK) + SIZEOF(.@@manifest.tfm_partition_name@@_STACK);
+
+@!GENERATOR_CONDITIONAL_START!@ @@attr.conditional@@
+#endif /* @@attr.conditional@@ */
+@!GENERATOR_CONDITIONAL_END!@
+@!GENERATOR_BLOCK_END!@
+#endif /* TFM_LVL == 1 */
+
+ .TFM_DATA :
+ {
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ } > RAM AT> FLASH
+ Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
+ Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
+
+ .TFM_BSS : ALIGN(4)
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM AT> FLASH
+ Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
+ Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
+
+ .psp_stack : ALIGN(128)
+ {
+ . += __psp_stack_size__;
+ } > RAM AT> FLASH
+ __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+ Stack_Mem = ADDR(.psp_stack);
+
+ .msp_stack : ALIGN(128)
+ {
+ . += __msp_stack_size__;
+ } > RAM AT> FLASH
+ __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap : ALIGN(8)
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM AT> FLASH
+
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) after the code, in a
+ * separate 32 bytes aligned region so that the SAU can programmed to just set
+ * this region as Non-Secure Callable.
+ */
+ .gnu.sgstubs : ALIGN(32)
+ {
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ } > VENEERS AT> VENEERS
+ Load$$LR$$LR_VENEER$$Base = ADDR(.gnu.sgstubs);
+ Load$$LR$$LR_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
+
+ Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;
+ Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START;
+
+ PROVIDE(__stack = __initial_sp);
+ PROVIDE(Stack_top = __initial_sp);
+}
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S
new file mode 100644
index 0000000..32d2173
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S
@@ -0,0 +1,367 @@
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __initial_msp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+ /* Only run on core 0 */
+ mov r0, #0x50000000
+ add r0, #0x0001F000
+ ldr r0, [r0]
+ cmp r0,#0
+not_the_core_to_run_on:
+ bne not_the_core_to_run_on
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+ ldr r0, =__initial_sp
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S
new file mode 100644
index 0000000..43db00b
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S
@@ -0,0 +1,356 @@
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __initial_msp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long 0 /* 9: Reserved */
+ .long 0 /* 10: Reserved */
+ .long 0 /* 11: Reserved */
+ .long 0 /* 12: Reserved */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #1 /* Select switch to unprivilage mode */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =__initial_sp
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S
new file mode 100644
index 0000000..371638d
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S
@@ -0,0 +1,362 @@
+;/*
+; * Copyright (c) 2009-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
+; */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __initial_msp /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Core interrupts */
+ .long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ .long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ .long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ .long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ .long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ .long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ .long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ .long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ .long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ .long MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ .long PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ .long S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ .long S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ .long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ .long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ .long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ .long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ .long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ .long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ .long 0 /* 21: Reserved */
+ .long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ .long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ .long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ .long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ .long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ .long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+
+ /* External interrupts */
+ .long 0 /* 32: Reserved */
+ .long GpTimer_IRQHandler /* 33: General Purpose Timer */
+ .long I2C0_IRQHandler /* 34: I2C0 */
+ .long I2C1_IRQHandler /* 35: I2C1 */
+ .long I2S_IRQHandler /* 36: I2S */
+ .long SPI_IRQHandler /* 37: SPI */
+ .long QSPI_IRQHandler /* 38: QSPI */
+ .long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ .long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ .long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ .long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ .long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ .long UART0_IRQHandler /* 44: UART0 interrupt */
+ .long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ .long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ .long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ .long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ .long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ .long UART1_IRQHandler /* 50: UART0 interrupt */
+ .long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ .long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ .long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ .long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ .long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ .long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ .long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ .long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ .long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ .long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ .long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ .long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ .long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ .long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ .long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ .long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ .long Combined_IRQHandler /* 67: Combined interrupt */
+ .long PVT_IRQHandler /* 68: PVT sensor interrupt */
+ .long 0 /* 69: Reserved */
+ .long PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ .long RTC_IRQHandler /* 71: RTC interrupt */
+ .long GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ .long GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ .long PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ .long PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ .long IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =__initial_sp
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ /* Core interrupts */
+ def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
+ def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
+ def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
+ def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
+ def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
+ def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
+ def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
+ def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
+ def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
+ def_irq_handler MPC_Handler /* 9: Secure Combined MPC Interrupt */
+ def_irq_handler PPC_Handler /* 10: Secure Combined PPC Interrupt */
+ def_irq_handler S_MSC_COMBINED_IRQHandler /* 11: Secure Combined MSC Interrupt */
+ def_irq_handler S_BRIDGE_ERR_IRQHandler /* 12: Secure Bridge Error Combined Interrupt */
+ def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
+ def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
+ def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
+ def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
+ def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
+ def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
+ def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
+ def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
+ def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
+ def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
+ def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
+ def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
+ def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
+ def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
+
+ /* External interrupts */
+ def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
+ def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
+ def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
+ def_irq_handler I2S_IRQHandler /* 36: I2S */
+ def_irq_handler SPI_IRQHandler /* 37: SPI */
+ def_irq_handler QSPI_IRQHandler /* 38: QSPI */
+ def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
+ def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
+ def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
+ def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
+ def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
+ def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
+ def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
+ def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
+ def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
+ def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
+ def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
+ def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
+ def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
+ def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
+ def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
+ def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
+ def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
+ def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
+ def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
+ def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
+ def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
+ def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
+ def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
+ def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
+ def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
+ def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
+ def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
+ def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
+ def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
+ def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
+ def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
+ def_irq_handler GpTimer0_IRQHandler /* 72: General Purpose Timer0 */
+ def_irq_handler GpTimer1_IRQHandler /* 73: General Purpose Timer1 */
+ def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
+ def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
+ def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
+
+ .end
diff --git a/platform/ext/target/musca_a/partition/region_defs.h b/platform/ext/target/musca_a/partition/region_defs.h
index f3aa9aa..0ea5af0 100755
--- a/platform/ext/target/musca_a/partition/region_defs.h
+++ b/platform/ext/target/musca_a/partition/region_defs.h
@@ -85,7 +85,7 @@
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
-#define S_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
/* CMSE Veneers region */
@@ -98,8 +98,8 @@
#define NS_CODE_SIZE (IMAGE_CODE_SIZE - FLASH_AREA_BL2_SIZE)
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
-#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
-#define NS_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE / 2))
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE / 2)
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
/* NS partition information is used for MPC and SAU configuration */
@@ -122,11 +122,11 @@
#define BL2_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
#define S_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
#define S_CODE_SRAM_EXEC_LIMIT (S_CODE_SRAM_EXEC_BASE + \
- (TOTAL_CODE_SRAM_SIZE/2) - 1)
+ (TOTAL_CODE_SRAM_SIZE / 2) - 1)
#define NS_CODE_SRAM_EXEC_BASE (NS_CODE_SRAM_ALIAS_BASE + \
- (TOTAL_CODE_SRAM_SIZE/2))
+ (TOTAL_CODE_SRAM_SIZE / 2))
#define NS_CODE_SRAM_EXEC_LIMIT (NS_CODE_SRAM_EXEC_BASE + \
- (TOTAL_CODE_SRAM_SIZE/2) - 1)
+ (TOTAL_CODE_SRAM_SIZE / 2) - 1)
diff --git a/secure_fw/CMakeLists.txt b/secure_fw/CMakeLists.txt
index f81a4b3..ddb9a26 100644
--- a/secure_fw/CMakeLists.txt
+++ b/secure_fw/CMakeLists.txt
@@ -122,7 +122,7 @@
if(${COMPILER} STREQUAL "ARMCLANG")
target_link_libraries(${EXE_NAME} tfm_storage tfm_audit $<TARGET_LINKER_FILE:tfm_secure_tests>\(*veneers.o\) tfm_secure_tests)
elseif(${COMPILER} STREQUAL "GNUARM")
- target_link_libraries(${EXE_NAME} -Wl,--whole-archive tfm_secure_tests -Wl,--no-whole-archive tfm_storage tfm_audit)
+ target_link_libraries(${EXE_NAME} tfm_secure_tests tfm_storage tfm_audit)
else()
message(FATAL_ERROR "unknown compiler" )
endif()
diff --git a/tools/tfm_generated_file_list.yaml b/tools/tfm_generated_file_list.yaml
index 8cdc1fa..42a2ab1 100644
--- a/tools/tfm_generated_file_list.yaml
+++ b/tools/tfm_generated_file_list.yaml
@@ -35,6 +35,11 @@
"name": "AN519 secure ld file",
"short_name": "mps2_an519_s.ld",
"output": "platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld"
+ },
+ {
+ "name": "MUSCA secure ld file",
+ "short_name": "musca_s.ld",
+ "output": "platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld"
}
]
}