Platform: AN547: CMSIS conformity and related fixes
- Remove cpu0_identity register as it is already defined by CMSIS-CORE
- Add no-return attribute for the default handler
- Create platform specific header file
- Fix platform specific init file
- Fix CMSIS configuration wizard annotations in RTE_device.h
Change-Id: I2d74b3fdb7ef2332f1c2e9b5553043ec4809b4c0
Signed-off-by: Gerda Zsejke More <gerdazsejke.more@arm.com>
Signed-off-by: Gabor Abonyi <gabor.abonyi@arm.com>
Signed-off-by: Mark Horvath <mark.horvath@arm.com>
diff --git a/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/RTE_Device.h b/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/RTE_Device.h
index ef808ce..20d0b64 100644
--- a/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/RTE_Device.h
+++ b/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/RTE_Device.h
@@ -14,96 +14,81 @@
* limitations under the License.
*/
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
-// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
#define RTE_USART0 1
-// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
-// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
#define RTE_USART1 0
-// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
-// <e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <q> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
#define RTE_ISRAM0_MPC 1
-// </e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
-// <e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <q> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
#define RTE_ISRAM1_MPC 1
-// </e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
-// <e> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
+// <q> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
// <i> Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC
#define RTE_SRAM_MPC 1
-// </e> MPC (Memory Protection Controller) [Driver_SRAM_MPC]
-// <e> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+// <q> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
#define RTE_QSPI_MPC 1
-// </e> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN0 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN0]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP0 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP0]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP1 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP1]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP2]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP2]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP2 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP2 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP2]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP3]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP3]
// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP3 in component ::Drivers:PPC
#define RTE_PPC_SSE300_MAIN_EXP3 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP3]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH0 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH0]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH1 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH1]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP0 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP0]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP1 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP1]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP2 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP2]
-// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP3]
+// <q> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP3]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP3 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH_EXP3 1
-// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP3]
-// <e> Flash device emulated by SRAM [Driver_Flash0]
+
+// <q> Flash device emulated by SRAM [Driver_Flash0]
// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
#define RTE_FLASH0 1
-// </e> Flash device emulated by SRAM [Driver_Flash0]
#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/cmsis_driver_config.h b/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/cmsis_driver_config.h
index edc4633..a7c7917 100644
--- a/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/cmsis_driver_config.h
+++ b/platform/ext/target/arm/mps3/an547/cmsis_drivers/config/cmsis_driver_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -17,7 +17,7 @@
#ifndef __CMSIS_DRIVER_CONFIG_H__
#define __CMSIS_DRIVER_CONFIG_H__
-#include "platform_description.h"
+#include "cmsis.h"
#include "device_definition.h"
#include "RTE_Device.h"
diff --git a/platform/ext/target/arm/mps3/an547/device/include/an547.h b/platform/ext/target/arm/mps3/an547/device/include/an547.h
new file mode 100644
index 0000000..804ea2e
--- /dev/null
+++ b/platform/ext/target/arm/mps3/an547/device/include/an547.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AN547_H__
+#define __AN547_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ====================== Start of section using anonymous unions ============== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* ======== Configuration of Core Peripherals ================================== */
+#define __CM55_REV 0x0001U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __FPU_DP 1U /* double precision FPU */
+#define __DSP_PRESENT 1U /* DSP extension present */
+#define __PMU_PRESENT 1U /* PMU present */
+#define __PMU_NUM_EVENTCNT 8U /* Number of PMU event counters */
+#define __ICACHE_PRESENT 1U /* Instruction Cache present */
+#define __DCACHE_PRESENT 1U /* Data Cache present */
+
+#include "platform_irq.h"
+#include "core_cm55.h" /* Processor and core peripherals */
+#include "platform_base_address.h"
+#include "platform_regs.h"
+#include "platform_pins.h"
+#include "system_core_init.h"
+
+/* ===================== End of section using anonymous unions ================ */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AN547_H__ */
diff --git a/platform/ext/target/arm/mps3/an547/device/include/cmsis.h b/platform/ext/target/arm/mps3/an547/device/include/cmsis.h
index dbd93f4..8ae29b6 100644
--- a/platform/ext/target/arm/mps3/an547/device/include/cmsis.h
+++ b/platform/ext/target/arm/mps3/an547/device/include/cmsis.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited
+ * Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -17,62 +17,6 @@
#ifndef __CMSIS_H__
#define __CMSIS_H__
-/* ====================== Start of section using anonymous unions ============== */
-#if defined (__CC_ARM)
- #pragma push
- #pragma anon_unions
-#elif defined (__ICCARM__)
- #pragma language=extended
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wc11-extensions"
- #pragma clang diagnostic ignored "-Wreserved-id-macro"
-#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined (__TASKING__)
- #pragma warning 586
-#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
-#else
- #warning Not supported compiler type
-#endif
-
-
-/* ======== Configuration of Core Peripherals ================================== */
-#define __SAUREGION_PRESENT 1U /* SAU regions present */
-#define __MPU_PRESENT 1U /* MPU present */
-#define __VTOR_PRESENT 1U /* VTOR present */
-#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1U /* FPU present */
-#define __FPU_DP 1U /* double precision FPU */
-#define __DSP_PRESENT 1U /* DSP extension present */
-#define __MVE_PRESENT 1U /* MVE extensions present */
-#define __MVE_FP 1U /* MVE floating point present */
-
-#include "platform_description.h"
-#include "platform_irq.h"
-#include "core_armv81mml.h" /* Processor and core peripherals */
-
-/* ===================== End of section using anonymous unions ================ */
-#if defined (__CC_ARM)
- #pragma pop
-#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
-#elif (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic pop
-#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined (__TASKING__)
- #pragma warning restore
-#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
-#else
- #warning Not supported compiler type
-#endif
+#include "an547.h"
#endif /* __CMSIS_H__ */
diff --git a/platform/ext/target/arm/mps3/an547/device/include/platform_description.h b/platform/ext/target/arm/mps3/an547/device/include/platform_description.h
deleted file mode 100644
index 6800c05..0000000
--- a/platform/ext/target/arm/mps3/an547/device/include/platform_description.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2019-2021 Arm Limited
- *
- * Licensed under the Apache License Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing software
- * distributed under the License is distributed on an "AS IS" BASIS
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __PLATFORM_DESCRIPTION_H__
-#define __PLATFORM_DESCRIPTION_H__
-
-#include "cmsis.h"
-#include "platform_base_address.h"
-#include "platform_regs.h"
-#include "platform_pins.h"
-#include "system_core_init.h"
-
-#endif /* __PLATFORM_DESCRIPTION_H__ */
diff --git a/platform/ext/target/arm/mps3/an547/device/include/platform_regs.h b/platform/ext/target/arm/mps3/an547/device/include/platform_regs.h
index a40fabb..4013e1e 100644
--- a/platform/ext/target/arm/mps3/an547/device/include/platform_regs.h
+++ b/platform/ext/target/arm/mps3/an547/device/include/platform_regs.h
@@ -341,22 +341,6 @@
volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */
};
-struct cpu0_identity_t {
- volatile uint32_t cpuid; /* 0x000 (R/ ) Unique CPU 0 Identity
- * Number */
- volatile uint32_t reserved0[1011];
- volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */
- volatile uint32_t reserved1[3];
- volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */
- volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */
- volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */
- volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */
- volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */
- volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */
- volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */
- volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */
-};
-
struct cpu0_secctrl_t {
volatile uint32_t cpuseccfg; /* 0x000 (R/W) CPU Local Security
* Configuration */
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c
index b64ffa0..cdab22b 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_bl2.c
@@ -45,7 +45,7 @@
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
-void __WEAK handler_name(void); \
+void __WEAK handler_name(void) __NO_RETURN; \
void handler_name(void) { \
while(1); \
}
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
index 66d6ce1..72691ec 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
@@ -53,7 +53,7 @@
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
-void __WEAK handler_name(void); \
+void __WEAK handler_name(void) __NO_RETURN; \
void handler_name(void) { \
while(1); \
}
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c
index 5d91403..567e12f 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_s.c
@@ -50,7 +50,7 @@
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
#define DEFAULT_IRQ_HANDLER(handler_name) \
-void __WEAK handler_name(void); \
+void __WEAK handler_name(void) __NO_RETURN; \
void handler_name(void) { \
while(1); \
}
diff --git a/platform/ext/target/arm/mps3/an547/device/source/system_core_init.c b/platform/ext/target/arm/mps3/an547/device/source/system_core_init.c
index 6fe49b3..dece397 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/system_core_init.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/system_core_init.c
@@ -59,11 +59,11 @@
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
#endif
#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
- (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE == 1U))
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 0U))
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
@@ -71,4 +71,14 @@
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+ __ISB();
+
+ /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set
+ * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU
+ * into retention state
+ */
+ PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL;
}
diff --git a/platform/ext/target/arm/mps3/an547/plat_test.c b/platform/ext/target/arm/mps3/an547/plat_test.c
index 46b7921..7954246 100644
--- a/platform/ext/target/arm/mps3/an547/plat_test.c
+++ b/platform/ext/target/arm/mps3/an547/plat_test.c
@@ -5,7 +5,7 @@
*
*/
-#include "platform_description.h"
+#include "cmsis.h"
#include "systimer_armv8-m_drv.h"
#include "syscounter_armv8-m_cntrl_drv.h"
#include "tfm_plat_test.h"
diff --git a/platform/ext/target/arm/mps3/an547/target_cfg.c b/platform/ext/target/arm/mps3/an547/target_cfg.c
index 9d3018e..078f919 100644
--- a/platform/ext/target/arm/mps3/an547/target_cfg.c
+++ b/platform/ext/target/arm/mps3/an547/target_cfg.c
@@ -19,7 +19,6 @@
#include "target_cfg.h"
#include "Driver_SSE300_PPC.h"
#include "Driver_MPC.h"
-#include "platform_description.h"
#include "region_defs.h"
#include "tfm_plat_defs.h"
#include "region.h"