SPM: Mask NS interrupts in Secure thread mode execution
Set the priority of thread mode execution to the highest priority that
Non-Secure can boost(0x80). Clear BASEPRI to 0x00 before jumping to
Non-Secure as BASEPRI_S impacts the thread mode execution of Non-Secure.
A new build option named CONFIG_TFM_SECURE_THREAD_MASK_NS_INTERRUPT
is added for this functionality.
Signed-off-by: Sherry Zhang <sherry.zhang2@arm.com>
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Change-Id: I61bfebb0309c1bd6b82a48c9f6d761ca6cf196b2
diff --git a/config/config_base.h b/config/config_base.h
index 1b550a1..ac96b74 100644
--- a/config/config_base.h
+++ b/config/config_base.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
* Copyright (c) 2023-2024 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation. All rights
* reserved.
@@ -265,6 +265,11 @@
#define CONFIG_TFM_SCHEDULE_WHEN_NS_INTERRUPTED 0
#endif
+/* Mask Non-Secure interrupts when executing in secure state. */
+#ifndef CONFIG_TFM_SECURE_THREAD_MASK_NS_INTERRUPT
+#define CONFIG_TFM_SECURE_THREAD_MASK_NS_INTERRUPT 0
+#endif
+
/* Enable OTP/NV_COUNTERS emulation in RAM */
#ifndef OTP_NV_COUNTERS_RAM_EMULATION
#define OTP_NV_COUNTERS_RAM_EMULATION 0