Build: Added more targets for IAR builds
- Added AN519, AN521, AN524, AN539 and SSE-200_AWS targets.
- Verified on: AN519, AN521, AN524, AN539, Musca A.
- SSE-200AWS builds but is untested due to lack of HW.
- Musca B1 and Musca S1 not yet supported due to lack of HW.
- All targets fails the NaN QCBOR tests due to the tests not
following the Arm ABI.
Change-Id: I422ed7a85e09f895d781309d17166b81be954943
Signed-off-by: TTornblom <thomas.tornblom@iar.com>
diff --git a/cmake/Common/CompilerIarArm842.cmake b/cmake/Common/CompilerIarArm842.cmake
index 7d5c422..378774d 100644
--- a/cmake/Common/CompilerIarArm842.cmake
+++ b/cmake/Common/CompilerIarArm842.cmake
@@ -52,7 +52,7 @@
string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
- string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M3.no_dsp3")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M23")
string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M23")
string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M23")
diff --git a/cmake/Common/CompilerIarArm850.cmake b/cmake/Common/CompilerIarArm850.cmake
index bf40e64..dfa9a36 100644
--- a/cmake/Common/CompilerIarArm850.cmake
+++ b/cmake/Common/CompilerIarArm850.cmake
@@ -52,7 +52,7 @@
string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
- string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M3.no_dsp3")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu Cortex-M33.no_dsp")
elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M23")
string_append_unique_item (CMAKE_C_FLAGS_CPU "--cpu Cortex-M23")
string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--cpu Cortex-M23")
diff --git a/platform/ext/Mps2AN519.cmake b/platform/ext/Mps2AN519.cmake
index 616b2fe..ba9e2e8 100644
--- a/platform/ext/Mps2AN519.cmake
+++ b/platform/ext/Mps2AN519.cmake
@@ -29,6 +29,14 @@
# not all project defines CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a")
endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/iar/mps2_an519_bl2.icf")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/iar/mps2_an519_ns.icf")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a")
+ endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
@@ -116,6 +124,10 @@
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "IARARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/mps2/an519/iar/startup_cmsdk_mps2_an519_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/mps2/an519/iar/startup_cmsdk_mps2_an519_bl2.s")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/Mps2AN521.cmake b/platform/ext/Mps2AN521.cmake
index 13ffa4e..0156637 100644
--- a/platform/ext/Mps2AN521.cmake
+++ b/platform/ext/Mps2AN521.cmake
@@ -30,6 +30,14 @@
# not all project defines CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an521/iar/mps2_an521_bl2.icf")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an521/iar/mps2_an521_ns.icf")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a")
+ endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
@@ -117,6 +125,10 @@
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "IARARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/mps2/an521/iar/startup_cmsdk_mps2_an521_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/mps2/an521/iar/startup_cmsdk_mps2_an521_bl2.s")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/Mps2AN539.cmake b/platform/ext/Mps2AN539.cmake
index 363630a..249a274 100644
--- a/platform/ext/Mps2AN539.cmake
+++ b/platform/ext/Mps2AN539.cmake
@@ -31,6 +31,14 @@
# Not all projects define CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a")
endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set (BL2_SCATTER_FILE_NAME "${AN539_DIR}/device/source/iar/an539_mps2_bl2.icf")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set (NS_SCATTER_FILE_NAME "${AN539_DIR}/device/source/iar/an539_mps2_ns.icf")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a")
+ endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
@@ -113,6 +121,10 @@
list(APPEND ALL_SRC_ASM_BL2 "${AN539_DIR}/device/source/gcc/startup_cmsdk_an539_mps2_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "IARARM")
+ list(APPEND ALL_SRC_ASM_S "${AN539_DIR}/device/source/iar/startup_cmsdk_an539_mps2_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${AN539_DIR}/device/source/iar/startup_cmsdk_an539_mps2_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${AN539_DIR}/device/source/iar/startup_cmsdk_an539_mps2_bl2.s")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/Mps3AN524.cmake b/platform/ext/Mps3AN524.cmake
index 26a55a7..7c3c584 100644
--- a/platform/ext/Mps3AN524.cmake
+++ b/platform/ext/Mps3AN524.cmake
@@ -37,6 +37,14 @@
# Not all projects define CMSIS_5_DIR, only the ones that use it.
set(RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set (BL2_SCATTER_FILE_NAME "${AN524_DIR}/device/source/iar/mps3_an524_bl2.icf")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set (NS_SCATTER_FILE_NAME "${AN524_DIR}/device/source/iar/mps3_an524_ns.icf")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a")
+ endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
@@ -125,6 +133,10 @@
list(APPEND ALL_SRC_ASM_BL2 "${AN524_DIR}/device/source/gcc/startup_cmsdk_mps3_an524_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "IARARM")
+ list(APPEND ALL_SRC_ASM_S "${AN524_DIR}/device/source/iar/startup_cmsdk_mps3_an524_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${AN524_DIR}/device/source/iar/startup_cmsdk_mps3_an524_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${AN524_DIR}/device/source/iar/startup_cmsdk_mps3_an524_bl2.s")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/SSE-200_AWS.cmake b/platform/ext/SSE-200_AWS.cmake
index 32c0847..4f32c17 100644
--- a/platform/ext/SSE-200_AWS.cmake
+++ b/platform/ext/SSE-200_AWS.cmake
@@ -30,6 +30,14 @@
# not all project defines CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/sse-200_aws/iar/sse-200_aws_bl2.icf")
+ set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/sse-200_aws/iar/sse-200_aws_ns.icf")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a")
+ endif()
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
@@ -117,6 +125,12 @@
list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_bl2.S")
set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "IARARM")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s")
+ set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
+ PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
else()
message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
endif()
diff --git a/platform/ext/common/iar/tfm_common_s.icf b/platform/ext/common/iar/tfm_common_s.icf
index 4df798a..3502825 100644
--- a/platform/ext/common/iar/tfm_common_s.icf
+++ b/platform/ext/common/iar/tfm_common_s.icf
@@ -34,6 +34,7 @@
ro object device_definition.o,
section SFN,
ro section .rodata object tfm_*_secure_api.o,
+ ro object *6M_tl*.a,
ro object *7M_tl*.a,
ro object *libtfmsprt.a
};
@@ -309,7 +310,7 @@
};
#if defined (TFM_PSA_API)
-define block TFM_SP_ITS_LINKER_STACK with alignment = 128, size = 0x500 { };
+define block TFM_SP_ITS_LINKER_STACK with alignment = 128, size = 0x680 { };
#endif
#endif /* TFM_PARTITION_INTERNAL_TRUSTED_STORAGE */
@@ -377,7 +378,7 @@
};
#if defined (TFM_PSA_API)
-define block TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK with alignment = 128, size = 0x0C80 { };
+define block TFM_SP_SECURE_TEST_PARTITION_LINKER_STACK with alignment = 128, size = 0x0D00 { };
#endif
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */
diff --git a/platform/ext/common/iar/tfm_common_s.icf.template b/platform/ext/common/iar/tfm_common_s.icf.template
index 2ae4cab..e3954ff 100644
--- a/platform/ext/common/iar/tfm_common_s.icf.template
+++ b/platform/ext/common/iar/tfm_common_s.icf.template
@@ -34,6 +34,7 @@
ro object device_definition.o,
section SFN,
ro section .rodata object tfm_*_secure_api.o,
+ ro object *6M_tl*.a,
ro object *7M_tl*.a,
ro object *libtfmsprt.a
};
diff --git a/platform/ext/target/mps2/an519/boot_hal.c b/platform/ext/target/mps2/an519/boot_hal.c
index 1b11c7b..acb1fe3 100644
--- a/platform/ext/target/mps2/an519/boot_hal.c
+++ b/platform/ext/target/mps2/an519/boot_hal.c
@@ -14,7 +14,9 @@
__attribute__((naked)) void boot_clear_bl2_ram_area(void)
{
__ASM volatile(
+#ifndef __ICCARM__
".syntax unified \n"
+#endif
"movs r0, #0 \n"
"subs %1, %1, %0 \n"
"Loop: \n"
diff --git a/platform/ext/target/mps2/an519/iar/mps2_an519_bl2.icf b/platform/ext/target/mps2/an519/iar/mps2_an519_bl2.icf
new file mode 100644
index 0000000..3be1657
--- /dev/null
+++ b/platform/ext/target/mps2/an519/iar/mps2_an519_bl2.icf
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps2_an519_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region BL2_CODE_region = mem:[from BL2_CODE_START size BL2_CODE_SIZE];
+
+define region BL2_RAM_region = mem:[from BL2_DATA_START size BL2_DATA_SIZE];
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+keep {block TFM_SHARED_DATA};
+
+define block ER_DATA with maximum size = BL2_DATA_SIZE, alignment = 32 {readwrite};
+ /* MSP */
+
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block TFM_SHARED_DATA,
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in BL2_CODE_region { block LR_CODE };
+place in BL2_RAM_region { block DATA};
diff --git a/platform/ext/target/mps2/an519/iar/mps2_an519_ns.icf b/platform/ext/target/mps2/an519/iar/mps2_an519_ns.icf
new file mode 100644
index 0000000..9938884
--- /dev/null
+++ b/platform/ext/target/mps2/an519/iar/mps2_an519_ns.icf
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps2_an521_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+define block ARM_LIB_STACK_MSP with alignment = 8, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 8, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+
+define block ER_DATA with alignment = 8 {readwrite};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in NS_CODE_region { block LR_CODE };
+place in NS_RAM_region { block DATA };
diff --git a/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_bl2.s b/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_bl2.s
new file mode 100644
index 0000000..753e5f6
--- /dev/null
+++ b/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_bl2.s
@@ -0,0 +1,275 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an519_bl2.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ DATA
+
+
+__vector_table DCD sfe(ARM_LIB_STACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TIMER0_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_ns.s b/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_ns.s
new file mode 100644
index 0000000..62b98c6
--- /dev/null
+++ b/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_ns.s
@@ -0,0 +1,345 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_ns.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+Reset_Handler
+ MRS R0, control ; Get control value
+ MOVS R1, #1
+ ORRS R0, R0, R1 ; Select switch to unprivileged mode
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of ARM_LIB_STACK
+ MOV SP, R0 ; Initialise PSP
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TIMER0_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 51 SPI 0 Handler
+ PUBWEAK SPI1_Handler ; 52 SPI 1 Handler
+ PUBWEAK SPI2_Handler ; 53 SPI 2 Handler
+ PUBWEAK SPI3_Handler ; 54 SPI 3 Handler
+ PUBWEAK SPI4_Handler ; 55 SPI 4 Handler
+ PUBWEAK DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ PUBWEAK DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ PUBWEAK DMA0_Handler ; 58 DMA 0 Combined Handler
+ PUBWEAK DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ PUBWEAK DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ PUBWEAK DMA1_Handler ; 61 DMA 1 Combined Handler
+ PUBWEAK DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ PUBWEAK DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ PUBWEAK DMA2_Handler ; 64 DMA 2 Combined Handler
+ PUBWEAK DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ PUBWEAK DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ PUBWEAK DMA3_Handler ; 67 DMA 3 Combined Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO 1 has 16 individual Handlers
+ PUBWEAK GPIO0_1_Handler ; 73
+ PUBWEAK GPIO0_2_Handler ; 74
+ PUBWEAK GPIO0_3_Handler ; 75
+ PUBWEAK GPIO0_4_Handler ; 76
+ PUBWEAK GPIO0_5_Handler ; 77
+ PUBWEAK GPIO0_6_Handler ; 78
+ PUBWEAK GPIO0_7_Handler ; 79
+ PUBWEAK GPIO0_8_Handler ; 80
+ PUBWEAK GPIO0_9_Handler ; 81
+ PUBWEAK GPIO0_10_Handler ; 82
+ PUBWEAK GPIO0_11_Handler ; 83
+ PUBWEAK GPIO0_12_Handler ; 84
+ PUBWEAK GPIO0_13_Handler ; 85
+ PUBWEAK GPIO0_14_Handler ; 86
+ PUBWEAK GPIO0_15_Handler ; 87
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+ PUBWEAK GPIO1_1_Handler ; 89
+ PUBWEAK GPIO1_2_Handler ; 90
+ PUBWEAK GPIO1_3_Handler ; 91
+ PUBWEAK GPIO1_4_Handler ; 92
+ PUBWEAK GPIO1_5_Handler ; 93
+ PUBWEAK GPIO1_6_Handler ; 94
+ PUBWEAK GPIO1_7_Handler ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s
new file mode 100644
index 0000000..d1043e9
--- /dev/null
+++ b/platform/ext/target/mps2/an519/iar/startup_cmsdk_mps2_an519_s.s
@@ -0,0 +1,348 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_s.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK
+ MOVS R1, #7
+ BICS R0, R1 ; Make sure that the SP address is aligned to 8
+ MOV SP, R0 ; Initialise PSP
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 51 SPI 0 Handler
+ PUBWEAK SPI1_Handler ; 52 SPI 1 Handler
+ PUBWEAK SPI2_Handler ; 53 SPI 2 Handler
+ PUBWEAK SPI3_Handler ; 54 SPI 3 Handler
+ PUBWEAK SPI4_Handler ; 55 SPI 4 Handler
+ PUBWEAK DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ PUBWEAK DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ PUBWEAK DMA0_Handler ; 58 DMA 0 Combined Handler
+ PUBWEAK DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ PUBWEAK DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ PUBWEAK DMA1_Handler ; 61 DMA 1 Combined Handler
+ PUBWEAK DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ PUBWEAK DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ PUBWEAK DMA2_Handler ; 64 DMA 2 Combined Handler
+ PUBWEAK DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ PUBWEAK DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ PUBWEAK DMA3_Handler ; 67 DMA 3 Combined Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO 1 has 16 individual Handlers
+ PUBWEAK GPIO0_1_Handler ; 73
+ PUBWEAK GPIO0_2_Handler ; 74
+ PUBWEAK GPIO0_3_Handler ; 75
+ PUBWEAK GPIO0_4_Handler ; 76
+ PUBWEAK GPIO0_5_Handler ; 77
+ PUBWEAK GPIO0_6_Handler ; 78
+ PUBWEAK GPIO0_7_Handler ; 79
+ PUBWEAK GPIO0_8_Handler ; 80
+ PUBWEAK GPIO0_9_Handler ; 81
+ PUBWEAK GPIO0_10_Handler ; 82
+ PUBWEAK GPIO0_11_Handler ; 83
+ PUBWEAK GPIO0_12_Handler ; 84
+ PUBWEAK GPIO0_13_Handler ; 85
+ PUBWEAK GPIO0_14_Handler ; 86
+ PUBWEAK GPIO0_15_Handler ; 87
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+ PUBWEAK GPIO1_1_Handler ; 89
+ PUBWEAK GPIO1_2_Handler ; 90
+ PUBWEAK GPIO1_3_Handler ; 91
+ PUBWEAK GPIO1_4_Handler ; 92
+ PUBWEAK GPIO1_5_Handler ; 93
+ PUBWEAK GPIO1_6_Handler ; 94
+ PUBWEAK GPIO1_7_Handler ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps2/an521/iar/mps2_an521_bl2.icf b/platform/ext/target/mps2/an521/iar/mps2_an521_bl2.icf
new file mode 100644
index 0000000..4ea3350
--- /dev/null
+++ b/platform/ext/target/mps2/an521/iar/mps2_an521_bl2.icf
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps2_an521_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region BL2_CODE_region = mem:[from BL2_CODE_START size BL2_CODE_SIZE];
+
+define region BL2_RAM_region = mem:[from BL2_DATA_START size BL2_DATA_SIZE];
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+keep {block TFM_SHARED_DATA};
+
+define block ER_DATA with maximum size = BL2_DATA_SIZE, alignment = 32 {readwrite};
+ /* MSP */
+
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block TFM_SHARED_DATA,
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in BL2_CODE_region { block LR_CODE };
+place in BL2_RAM_region { block DATA};
diff --git a/platform/ext/target/mps2/an521/iar/mps2_an521_ns.icf b/platform/ext/target/mps2/an521/iar/mps2_an521_ns.icf
new file mode 100644
index 0000000..9938884
--- /dev/null
+++ b/platform/ext/target/mps2/an521/iar/mps2_an521_ns.icf
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps2_an521_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+define block ARM_LIB_STACK_MSP with alignment = 8, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 8, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+
+define block ER_DATA with alignment = 8 {readwrite};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in NS_CODE_region { block LR_CODE };
+place in NS_RAM_region { block DATA };
diff --git a/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_bl2.s b/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_bl2.s
new file mode 100644
index 0000000..5b50790
--- /dev/null
+++ b/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_bl2.s
@@ -0,0 +1,286 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_bl2.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ DATA
+
+
+__vector_table DCD sfe(ARM_LIB_STACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ ; Only run on core 0
+ MOV r0, #0x50000000
+ ADD r0, #0x0001F000
+ LDR r0, [r0]
+ CMP r0,#0
+not_the_core_to_run_on
+ BNE not_the_core_to_run_on
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SecureFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TIMER0_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_ns.s b/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_ns.s
new file mode 100644
index 0000000..403a90e
--- /dev/null
+++ b/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_ns.s
@@ -0,0 +1,343 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_ns.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+Reset_Handler
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of ARM_LIB_STACK
+ MSR PSP, R0
+ MRS R0, CONTROL ; Get control value
+ ORR R0, R0, #1 ; Select switch to non privileged mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR CONTROL, R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TIMER0_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 51 SPI 0 Handler
+ PUBWEAK SPI1_Handler ; 52 SPI 1 Handler
+ PUBWEAK SPI2_Handler ; 53 SPI 2 Handler
+ PUBWEAK SPI3_Handler ; 54 SPI 3 Handler
+ PUBWEAK SPI4_Handler ; 55 SPI 4 Handler
+ PUBWEAK DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ PUBWEAK DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ PUBWEAK DMA0_Handler ; 58 DMA 0 Combined Handler
+ PUBWEAK DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ PUBWEAK DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ PUBWEAK DMA1_Handler ; 61 DMA 1 Combined Handler
+ PUBWEAK DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ PUBWEAK DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ PUBWEAK DMA2_Handler ; 64 DMA 2 Combined Handler
+ PUBWEAK DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ PUBWEAK DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ PUBWEAK DMA3_Handler ; 67 DMA 3 Combined Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO 1 has 16 individual Handlers
+ PUBWEAK GPIO0_1_Handler ; 73
+ PUBWEAK GPIO0_2_Handler ; 74
+ PUBWEAK GPIO0_3_Handler ; 75
+ PUBWEAK GPIO0_4_Handler ; 76
+ PUBWEAK GPIO0_5_Handler ; 77
+ PUBWEAK GPIO0_6_Handler ; 78
+ PUBWEAK GPIO0_7_Handler ; 79
+ PUBWEAK GPIO0_8_Handler ; 80
+ PUBWEAK GPIO0_9_Handler ; 81
+ PUBWEAK GPIO0_10_Handler ; 82
+ PUBWEAK GPIO0_11_Handler ; 83
+ PUBWEAK GPIO0_12_Handler ; 84
+ PUBWEAK GPIO0_13_Handler ; 85
+ PUBWEAK GPIO0_14_Handler ; 86
+ PUBWEAK GPIO0_15_Handler ; 87
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+ PUBWEAK GPIO1_1_Handler ; 89
+ PUBWEAK GPIO1_2_Handler ; 90
+ PUBWEAK GPIO1_3_Handler ; 91
+ PUBWEAK GPIO1_4_Handler ; 92
+ PUBWEAK GPIO1_5_Handler ; 93
+ PUBWEAK GPIO1_6_Handler ; 94
+ PUBWEAK GPIO1_7_Handler ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s
new file mode 100644
index 0000000..713f22c
--- /dev/null
+++ b/platform/ext/target/mps2/an521/iar/startup_cmsdk_mps2_an521_s.s
@@ -0,0 +1,350 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_s.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK
+ MSR PSP, R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SecureFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 51 SPI 0 Handler
+ PUBWEAK SPI1_Handler ; 52 SPI 1 Handler
+ PUBWEAK SPI2_Handler ; 53 SPI 2 Handler
+ PUBWEAK SPI3_Handler ; 54 SPI 3 Handler
+ PUBWEAK SPI4_Handler ; 55 SPI 4 Handler
+ PUBWEAK DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ PUBWEAK DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ PUBWEAK DMA0_Handler ; 58 DMA 0 Combined Handler
+ PUBWEAK DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ PUBWEAK DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ PUBWEAK DMA1_Handler ; 61 DMA 1 Combined Handler
+ PUBWEAK DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ PUBWEAK DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ PUBWEAK DMA2_Handler ; 64 DMA 2 Combined Handler
+ PUBWEAK DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ PUBWEAK DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ PUBWEAK DMA3_Handler ; 67 DMA 3 Combined Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO 1 has 16 individual Handlers
+ PUBWEAK GPIO0_1_Handler ; 73
+ PUBWEAK GPIO0_2_Handler ; 74
+ PUBWEAK GPIO0_3_Handler ; 75
+ PUBWEAK GPIO0_4_Handler ; 76
+ PUBWEAK GPIO0_5_Handler ; 77
+ PUBWEAK GPIO0_6_Handler ; 78
+ PUBWEAK GPIO0_7_Handler ; 79
+ PUBWEAK GPIO0_8_Handler ; 80
+ PUBWEAK GPIO0_9_Handler ; 81
+ PUBWEAK GPIO0_10_Handler ; 82
+ PUBWEAK GPIO0_11_Handler ; 83
+ PUBWEAK GPIO0_12_Handler ; 84
+ PUBWEAK GPIO0_13_Handler ; 85
+ PUBWEAK GPIO0_14_Handler ; 86
+ PUBWEAK GPIO0_15_Handler ; 87
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+ PUBWEAK GPIO1_1_Handler ; 89
+ PUBWEAK GPIO1_2_Handler ; 90
+ PUBWEAK GPIO1_3_Handler ; 91
+ PUBWEAK GPIO1_4_Handler ; 92
+ PUBWEAK GPIO1_5_Handler ; 93
+ PUBWEAK GPIO1_6_Handler ; 94
+ PUBWEAK GPIO1_7_Handler ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps2/an539/boot_hal.c b/platform/ext/target/mps2/an539/boot_hal.c
index 1b11c7b..acb1fe3 100644
--- a/platform/ext/target/mps2/an539/boot_hal.c
+++ b/platform/ext/target/mps2/an539/boot_hal.c
@@ -14,7 +14,9 @@
__attribute__((naked)) void boot_clear_bl2_ram_area(void)
{
__ASM volatile(
+#ifndef __ICCARM__
".syntax unified \n"
+#endif
"movs r0, #0 \n"
"subs %1, %1, %0 \n"
"Loop: \n"
diff --git a/platform/ext/target/mps2/an539/device/source/iar/an539_mps2_bl2.icf b/platform/ext/target/mps2/an539/device/source/iar/an539_mps2_bl2.icf
new file mode 100644
index 0000000..3be1657
--- /dev/null
+++ b/platform/ext/target/mps2/an539/device/source/iar/an539_mps2_bl2.icf
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps2_an519_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region BL2_CODE_region = mem:[from BL2_CODE_START size BL2_CODE_SIZE];
+
+define region BL2_RAM_region = mem:[from BL2_DATA_START size BL2_DATA_SIZE];
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+keep {block TFM_SHARED_DATA};
+
+define block ER_DATA with maximum size = BL2_DATA_SIZE, alignment = 32 {readwrite};
+ /* MSP */
+
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block TFM_SHARED_DATA,
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in BL2_CODE_region { block LR_CODE };
+place in BL2_RAM_region { block DATA};
diff --git a/platform/ext/target/mps2/an539/device/source/iar/an539_mps2_ns.icf b/platform/ext/target/mps2/an539/device/source/iar/an539_mps2_ns.icf
new file mode 100644
index 0000000..9938884
--- /dev/null
+++ b/platform/ext/target/mps2/an539/device/source/iar/an539_mps2_ns.icf
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps2_an521_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+define block ARM_LIB_STACK_MSP with alignment = 8, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 8, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+
+define block ER_DATA with alignment = 8 {readwrite};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in NS_CODE_region { block LR_CODE };
+place in NS_RAM_region { block DATA };
diff --git a/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_bl2.s b/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_bl2.s
new file mode 100644
index 0000000..51b75cb
--- /dev/null
+++ b/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_bl2.s
@@ -0,0 +1,321 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an519_bl2.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ DATA
+
+
+__vector_table DCD sfe(ARM_LIB_STACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD 0 ; - 2 Reserved
+ DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 IRQ Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 IRQ Handler
+ DCD 0 ; - 5 Reserved
+ DCD CTI_REQ0_IRQHandler ; - 6 CTI request 0 IRQ Handler
+ DCD CTI_REQ1_IRQHandler ; - 7 CTI request 1 IRQ Handler
+ DCD 0 ; 8 Reserved
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ DCD 0 ; - 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD PD_SYS_PPU_IRQHandler ; - 15 SYS PPU Handler
+ DCD 0 ; - 16 Reserved
+ DCD 0 ; - 17 Reserved
+ DCD 0 ; - 18 Reserved
+ DCD 0 ; - 19 Reserved
+ DCD 0 ; - 20 Reserved
+ DCD 0 ; - 21 Reserved
+ DCD 0 ; - 22 Reserved
+ DCD 0 ; - 23 Reserved
+ DCD 0 ; - 24 Reserved
+ DCD 0 ; - 25 Reserved
+ DCD 0 ; - 26 Reserved
+ DCD 0 ; - 27 Reserved
+ DCD 0 ; - 28 Reserved
+ DCD 0 ; - 29 Reserved
+ DCD 0 ; - 30 Reserved
+ DCD 0 ; - 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 /* There are 16 pins for GPIO 0 */
+ DCD GPIO0_1_Handler ; 73
+ DCD GPIO0_2_Handler ; 74
+ DCD GPIO0_3_Handler ; 75
+ DCD GPIO0_4_Handler ; 76
+ DCD GPIO0_5_Handler ; 77
+ DCD GPIO0_6_Handler ; 78
+ DCD GPIO0_7_Handler ; 79
+ DCD GPIO0_8_Handler ; 80
+ DCD GPIO0_9_Handler ; 81
+ DCD GPIO0_10_Handler ; 82
+ DCD GPIO0_11_Handler ; 83
+ DCD GPIO0_12_Handler ; 84
+ DCD GPIO0_13_Handler ; 85
+ DCD GPIO0_14_Handler ; 86
+ DCD GPIO0_15_Handler ; 87
+ DCD GPIO1_0_Handler ; 88 /* There are 16 pins for GPIO 1 */
+ DCD GPIO1_1_Handler ; 89
+ DCD GPIO1_2_Handler ; 90
+ DCD GPIO1_3_Handler ; 91
+ DCD GPIO1_4_Handler ; 92
+ DCD GPIO1_5_Handler ; 93
+ DCD GPIO1_6_Handler ; 94
+ DCD GPIO1_7_Handler ; 95
+ DCD GPIO1_8_Handler ; 96
+ DCD GPIO1_9_Handler ; 97
+ DCD GPIO1_10_Handler ; 98
+ DCD GPIO1_11_Handler ; 99
+ DCD GPIO1_12_Handler ; 100
+ DCD GPIO1_13_Handler ; 101
+ DCD GPIO1_14_Handler ; 102
+ DCD GPIO1_15_Handler ; 103
+ DCD GPIO2_0_Handler ; 104 /* There are 16 pins for GPIO 2 */
+ DCD GPIO2_1_Handler ; 105
+ DCD GPIO2_2_Handler ; 106
+ DCD GPIO2_3_Handler ; 107
+ DCD GPIO2_4_Handler ; 108
+ DCD GPIO2_5_Handler ; 109
+ DCD GPIO2_6_Handler ; 110
+ DCD GPIO2_7_Handler ; 111
+ DCD GPIO2_8_Handler ; 112
+ DCD GPIO2_9_Handler ; 113
+ DCD GPIO2_10_Handler ; 114
+ DCD GPIO2_11_Handler ; 115
+ DCD GPIO2_12_Handler ; 116
+ DCD GPIO2_13_Handler ; 117
+ DCD GPIO2_14_Handler ; 118
+ DCD GPIO2_15_Handler ; 119
+ DCD GPIO3_0_Handler ; 120 /* There are 4 pins for GPIO 4 */
+ DCD GPIO3_1_Handler ; 121
+ DCD GPIO3_2_Handler ; 122
+ DCD GPIO3_3_Handler ; 123
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+; Core IoT Interrupts
+ Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ Default_Handler TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler
+ Default_Handler CTI_REQ0_IRQHandler ; - 6 CTI request 0 IRQ Handler
+ Default_Handler CTI_REQ1_IRQHandler ; - 7 CTI request 1 IRQ Handler
+ Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ Default_Handler PD_SYS_PPU_IRQHandler ; - 15 SYS PPU Handler
+ ; External Interrupts
+ Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler
+ Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler
+ Default_Handler UARTRX1_Handler ; 34 UART 1 RX Handler
+ Default_Handler UARTTX1_Handler ; 35 UART 1 TX Handler
+ Default_Handler UARTRX2_Handler ; 36 UART 2 RX Handler
+ Default_Handler UARTTX2_Handler ; 37 UART 2 TX Handler
+ Default_Handler UARTRX3_Handler ; 38 UART 3 RX Handler
+ Default_Handler UARTTX3_Handler ; 39 UART 3 TX Handler
+ Default_Handler UARTRX4_Handler ; 40 UART 4 RX Handler
+ Default_Handler UARTTX4_Handler ; 41 UART 4 TX Handler
+ Default_Handler UART0_Handler ; 42 UART 0 combined Handler
+ Default_Handler UART1_Handler ; 43 UART 1 combined Handler
+ Default_Handler UART2_Handler ; 44 UART 2 combined Handler
+ Default_Handler UART3_Handler ; 45 UART 3 combined Handler
+ Default_Handler UART4_Handler ; 46 UART 4 combined Handler
+ Default_Handler UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ Default_Handler ETHERNET_Handler ; 48 Ethernet Handler
+ Default_Handler I2S_Handler ; 49 I2S Handler
+ Default_Handler TSC_Handler ; 50 Touch Screen Handler
+ Default_Handler SPI0_Handler ; 51 SPI 0 Handler
+ Default_Handler SPI1_Handler ; 52 SPI 1 Handler
+ Default_Handler SPI2_Handler ; 53 SPI 2 Handler
+ Default_Handler SPI3_Handler ; 54 SPI 3 Handler
+ Default_Handler SPI4_Handler ; 55 SPI 4 Handler
+ Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler
+ Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler
+ Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler
+ Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler
+ Default_Handler GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ Default_Handler GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ Default_Handler GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ Default_Handler GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ Default_Handler GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+ Default_Handler GPIO0_1_Handler ; 73
+ Default_Handler GPIO0_2_Handler ; 74
+ Default_Handler GPIO0_3_Handler ; 75
+ Default_Handler GPIO0_4_Handler ; 76
+ Default_Handler GPIO0_5_Handler ; 77
+ Default_Handler GPIO0_6_Handler ; 78
+ Default_Handler GPIO0_7_Handler ; 79
+ Default_Handler GPIO0_8_Handler ; 80
+ Default_Handler GPIO0_9_Handler ; 81
+ Default_Handler GPIO0_10_Handler ; 82
+ Default_Handler GPIO0_11_Handler ; 83
+ Default_Handler GPIO0_12_Handler ; 84
+ Default_Handler GPIO0_13_Handler ; 85
+ Default_Handler GPIO0_14_Handler ; 86
+ Default_Handler GPIO0_15_Handler ; 87
+ Default_Handler GPIO1_0_Handler ; 88 GPIO 1 has 16 individual Handlers
+ Default_Handler GPIO1_1_Handler ; 89
+ Default_Handler GPIO1_2_Handler ; 90
+ Default_Handler GPIO1_3_Handler ; 91
+ Default_Handler GPIO1_4_Handler ; 92
+ Default_Handler GPIO1_5_Handler ; 93
+ Default_Handler GPIO1_6_Handler ; 94
+ Default_Handler GPIO1_7_Handler ; 95
+ Default_Handler GPIO1_8_Handler ; 96
+ Default_Handler GPIO1_9_Handler ; 97
+ Default_Handler GPIO1_10_Handler ; 98
+ Default_Handler GPIO1_11_Handler ; 99
+ Default_Handler GPIO1_12_Handler ; 100
+ Default_Handler GPIO1_13_Handler ; 101
+ Default_Handler GPIO1_14_Handler ; 102
+ Default_Handler GPIO1_15_Handler ; 103
+ Default_Handler GPIO2_0_Handler ; 104 GPIO 2 has 16 individual Handlers
+ Default_Handler GPIO2_1_Handler ; 105
+ Default_Handler GPIO2_2_Handler ; 106
+ Default_Handler GPIO2_3_Handler ; 107
+ Default_Handler GPIO2_4_Handler ; 108
+ Default_Handler GPIO2_5_Handler ; 109
+ Default_Handler GPIO2_6_Handler ; 110
+ Default_Handler GPIO2_7_Handler ; 111
+ Default_Handler GPIO2_8_Handler ; 112
+ Default_Handler GPIO2_9_Handler ; 113
+ Default_Handler GPIO2_10_Handler ; 114
+ Default_Handler GPIO2_11_Handler ; 115
+ Default_Handler GPIO2_12_Handler ; 116
+ Default_Handler GPIO2_13_Handler ; 117
+ Default_Handler GPIO2_14_Handler ; 118
+ Default_Handler GPIO2_15_Handler ; 119
+ Default_Handler GPIO3_0_Handler ; 120 GPIO 3 has 16 individual Handlers
+ Default_Handler GPIO3_1_Handler ; 121
+ Default_Handler GPIO3_2_Handler ; 122
+ Default_Handler GPIO3_3_Handler ; 123
+
+ END
diff --git a/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_ns.s b/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_ns.s
new file mode 100644
index 0000000..eaf72b4
--- /dev/null
+++ b/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_ns.s
@@ -0,0 +1,328 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_ns.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD 0 ; - 2 Reserved
+ DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 IRQ Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 IRQ Handler
+ DCD 0 ; - 5 Reserved
+ DCD CTI_REQ0_IRQHandler ; - 6 CTI request 0 IRQ Handler
+ DCD CTI_REQ1_IRQHandler ; - 7 CTI request 1 IRQ Handler
+ DCD 0 ; 8 Reserved
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ DCD 0 ; - 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD PD_SYS_PPU_IRQHandler ; - 15 SYS PPU Handler
+ DCD 0 ; - 16 Reserved
+ DCD 0 ; - 17 Reserved
+ DCD 0 ; - 18 Reserved
+ DCD 0 ; - 19 Reserved
+ DCD 0 ; - 20 Reserved
+ DCD 0 ; - 21 Reserved
+ DCD 0 ; - 22 Reserved
+ DCD 0 ; - 23 Reserved
+ DCD 0 ; - 24 Reserved
+ DCD 0 ; - 25 Reserved
+ DCD 0 ; - 26 Reserved
+ DCD 0 ; - 27 Reserved
+ DCD 0 ; - 28 Reserved
+ DCD 0 ; - 29 Reserved
+ DCD 0 ; - 30 Reserved
+ DCD 0 ; - 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Ha
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Ha
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 /* There are 16 pins for GPIO 0 */
+ DCD GPIO0_1_Handler ; 73
+ DCD GPIO0_2_Handler ; 74
+ DCD GPIO0_3_Handler ; 75
+ DCD GPIO0_4_Handler ; 76
+ DCD GPIO0_5_Handler ; 77
+ DCD GPIO0_6_Handler ; 78
+ DCD GPIO0_7_Handler ; 79
+ DCD GPIO0_8_Handler ; 80
+ DCD GPIO0_9_Handler ; 81
+ DCD GPIO0_10_Handler ; 82
+ DCD GPIO0_11_Handler ; 83
+ DCD GPIO0_12_Handler ; 84
+ DCD GPIO0_13_Handler ; 85
+ DCD GPIO0_14_Handler ; 86
+ DCD GPIO0_15_Handler ; 87
+ DCD GPIO1_0_Handler ; 88 /* There are 16 pins for GPIO 1 */
+ DCD GPIO1_1_Handler ; 89
+ DCD GPIO1_2_Handler ; 90
+ DCD GPIO1_3_Handler ; 91
+ DCD GPIO1_4_Handler ; 92
+ DCD GPIO1_5_Handler ; 93
+ DCD GPIO1_6_Handler ; 94
+ DCD GPIO1_7_Handler ; 95
+ DCD GPIO1_8_Handler ; 96
+ DCD GPIO1_9_Handler ; 97
+ DCD GPIO1_10_Handler ; 98
+ DCD GPIO1_11_Handler ; 99
+ DCD GPIO1_12_Handler ; 100
+ DCD GPIO1_13_Handler ; 101
+ DCD GPIO1_14_Handler ; 102
+ DCD GPIO1_15_Handler ; 103
+ DCD GPIO2_0_Handler ; 104 /* There are 16 pins for GPIO 2 */
+ DCD GPIO2_1_Handler ; 105
+ DCD GPIO2_2_Handler ; 106
+ DCD GPIO2_3_Handler ; 107
+ DCD GPIO2_4_Handler ; 108
+ DCD GPIO2_5_Handler ; 109
+ DCD GPIO2_6_Handler ; 110
+ DCD GPIO2_7_Handler ; 111
+ DCD GPIO2_8_Handler ; 112
+ DCD GPIO2_9_Handler ; 113
+ DCD GPIO2_10_Handler ; 114
+ DCD GPIO2_11_Handler ; 115
+ DCD GPIO2_12_Handler ; 116
+ DCD GPIO2_13_Handler ; 117
+ DCD GPIO2_14_Handler ; 118
+ DCD GPIO2_15_Handler ; 119
+ DCD GPIO3_0_Handler ; 120 /* There are 4 pins for GPIO 4 */
+ DCD GPIO3_1_Handler ; 121
+ DCD GPIO3_2_Handler ; 122
+ DCD GPIO3_3_Handler ; 123
+
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+Reset_Handler
+ MRS R0, control ; Get control value
+ MOVS R1, #1
+ ORRS R0, R0, R1 ; Select switch to unprivileged mode
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of ARM_LIB_STACK
+ MOV SP, R0 ; Initialise PSP
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+; Core IoT Interrupts
+ Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ Default_Handler TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler
+ Default_Handler CTI_REQ0_IRQHandler ; - 6 CTI request 0 IRQ Handler
+ Default_Handler CTI_REQ1_IRQHandler ; - 7 CTI request 1 IRQ Handler
+ Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ Default_Handler PD_SYS_PPU_IRQHandler ; - 15 SYS PPU Handler
+ ; External Interrupts
+ Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler
+ Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler
+ Default_Handler UARTRX1_Handler ; 34 UART 1 RX Handler
+ Default_Handler UARTTX1_Handler ; 35 UART 1 TX Handler
+ Default_Handler UARTRX2_Handler ; 36 UART 2 RX Handler
+ Default_Handler UARTTX2_Handler ; 37 UART 2 TX Handler
+ Default_Handler UARTRX3_Handler ; 38 UART 3 RX Handler
+ Default_Handler UARTTX3_Handler ; 39 UART 3 TX Handler
+ Default_Handler UARTRX4_Handler ; 40 UART 4 RX Handler
+ Default_Handler UARTTX4_Handler ; 41 UART 4 TX Handler
+ Default_Handler UART0_Handler ; 42 UART 0 combined Handler
+ Default_Handler UART1_Handler ; 43 UART 1 combined Handler
+ Default_Handler UART2_Handler ; 44 UART 2 combined Handler
+ Default_Handler UART3_Handler ; 45 UART 3 combined Handler
+ Default_Handler UART4_Handler ; 46 UART 4 combined Handler
+ Default_Handler UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ Default_Handler ETHERNET_Handler ; 48 Ethernet Handler
+ Default_Handler I2S_Handler ; 49 I2S Handler
+ Default_Handler TSC_Handler ; 50 Touch Screen Handler
+ Default_Handler SPI0_Handler ; 51 SPI 0 Handler
+ Default_Handler SPI1_Handler ; 52 SPI 1 Handler
+ Default_Handler SPI2_Handler ; 53 SPI 2 Handler
+ Default_Handler SPI3_Handler ; 54 SPI 3 Handler
+ Default_Handler SPI4_Handler ; 55 SPI 4 Handler
+ Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler
+ Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler
+ Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler
+ Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler
+ Default_Handler GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ Default_Handler GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ Default_Handler GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ Default_Handler GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ Default_Handler GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+ Default_Handler GPIO0_1_Handler ; 73
+ Default_Handler GPIO0_2_Handler ; 74
+ Default_Handler GPIO0_3_Handler ; 75
+ Default_Handler GPIO0_4_Handler ; 76
+ Default_Handler GPIO0_5_Handler ; 77
+ Default_Handler GPIO0_6_Handler ; 78
+ Default_Handler GPIO0_7_Handler ; 79
+ Default_Handler GPIO0_8_Handler ; 80
+ Default_Handler GPIO0_9_Handler ; 81
+ Default_Handler GPIO0_10_Handler ; 82
+ Default_Handler GPIO0_11_Handler ; 83
+ Default_Handler GPIO0_12_Handler ; 84
+ Default_Handler GPIO0_13_Handler ; 85
+ Default_Handler GPIO0_14_Handler ; 86
+ Default_Handler GPIO0_15_Handler ; 87
+ Default_Handler GPIO1_0_Handler ; 88 GPIO 1 has 16 individual Handlers
+ Default_Handler GPIO1_1_Handler ; 89
+ Default_Handler GPIO1_2_Handler ; 90
+ Default_Handler GPIO1_3_Handler ; 91
+ Default_Handler GPIO1_4_Handler ; 92
+ Default_Handler GPIO1_5_Handler ; 93
+ Default_Handler GPIO1_6_Handler ; 94
+ Default_Handler GPIO1_7_Handler ; 95
+ Default_Handler GPIO1_8_Handler ; 96
+ Default_Handler GPIO1_9_Handler ; 97
+ Default_Handler GPIO1_10_Handler ; 98
+ Default_Handler GPIO1_11_Handler ; 99
+ Default_Handler GPIO1_12_Handler ; 100
+ Default_Handler GPIO1_13_Handler ; 101
+ Default_Handler GPIO1_14_Handler ; 102
+ Default_Handler GPIO1_15_Handler ; 103
+ Default_Handler GPIO2_0_Handler ; 104 GPIO 2 has 16 individual Handlers
+ Default_Handler GPIO2_1_Handler ; 105
+ Default_Handler GPIO2_2_Handler ; 106
+ Default_Handler GPIO2_3_Handler ; 107
+ Default_Handler GPIO2_4_Handler ; 108
+ Default_Handler GPIO2_5_Handler ; 109
+ Default_Handler GPIO2_6_Handler ; 110
+ Default_Handler GPIO2_7_Handler ; 111
+ Default_Handler GPIO2_8_Handler ; 112
+ Default_Handler GPIO2_9_Handler ; 113
+ Default_Handler GPIO2_10_Handler ; 114
+ Default_Handler GPIO2_11_Handler ; 115
+ Default_Handler GPIO2_12_Handler ; 116
+ Default_Handler GPIO2_13_Handler ; 117
+ Default_Handler GPIO2_14_Handler ; 118
+ Default_Handler GPIO2_15_Handler ; 119
+ Default_Handler GPIO3_0_Handler ; 120 GPIO 3 has 16 individual Handlers
+ Default_Handler GPIO3_1_Handler ; 121
+ Default_Handler GPIO3_2_Handler ; 122
+ Default_Handler GPIO3_3_Handler ; 123
+
+ END
diff --git a/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_s.s b/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_s.s
new file mode 100644
index 0000000..d1043e9
--- /dev/null
+++ b/platform/ext/target/mps2/an539/device/source/iar/startup_cmsdk_an539_mps2_s.s
@@ -0,0 +1,348 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_s.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK
+ MOVS R1, #7
+ BICS R0, R1 ; Make sure that the SP address is aligned to 8
+ MOV SP, R0 ; Initialise PSP
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ PUBWEAK TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; - 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 51 SPI 0 Handler
+ PUBWEAK SPI1_Handler ; 52 SPI 1 Handler
+ PUBWEAK SPI2_Handler ; 53 SPI 2 Handler
+ PUBWEAK SPI3_Handler ; 54 SPI 3 Handler
+ PUBWEAK SPI4_Handler ; 55 SPI 4 Handler
+ PUBWEAK DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ PUBWEAK DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ PUBWEAK DMA0_Handler ; 58 DMA 0 Combined Handler
+ PUBWEAK DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ PUBWEAK DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ PUBWEAK DMA1_Handler ; 61 DMA 1 Combined Handler
+ PUBWEAK DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ PUBWEAK DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ PUBWEAK DMA2_Handler ; 64 DMA 2 Combined Handler
+ PUBWEAK DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ PUBWEAK DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ PUBWEAK DMA3_Handler ; 67 DMA 3 Combined Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO 1 has 16 individual Handlers
+ PUBWEAK GPIO0_1_Handler ; 73
+ PUBWEAK GPIO0_2_Handler ; 74
+ PUBWEAK GPIO0_3_Handler ; 75
+ PUBWEAK GPIO0_4_Handler ; 76
+ PUBWEAK GPIO0_5_Handler ; 77
+ PUBWEAK GPIO0_6_Handler ; 78
+ PUBWEAK GPIO0_7_Handler ; 79
+ PUBWEAK GPIO0_8_Handler ; 80
+ PUBWEAK GPIO0_9_Handler ; 81
+ PUBWEAK GPIO0_10_Handler ; 82
+ PUBWEAK GPIO0_11_Handler ; 83
+ PUBWEAK GPIO0_12_Handler ; 84
+ PUBWEAK GPIO0_13_Handler ; 85
+ PUBWEAK GPIO0_14_Handler ; 86
+ PUBWEAK GPIO0_15_Handler ; 87
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+ PUBWEAK GPIO1_1_Handler ; 89
+ PUBWEAK GPIO1_2_Handler ; 90
+ PUBWEAK GPIO1_3_Handler ; 91
+ PUBWEAK GPIO1_4_Handler ; 92
+ PUBWEAK GPIO1_5_Handler ; 93
+ PUBWEAK GPIO1_6_Handler ; 94
+ PUBWEAK GPIO1_7_Handler ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ END
diff --git a/platform/ext/target/mps3/an524/device/source/iar/mps3_an524_bl2.icf b/platform/ext/target/mps3/an524/device/source/iar/mps3_an524_bl2.icf
new file mode 100644
index 0000000..20be720
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/iar/mps3_an524_bl2.icf
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps3_an524_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region BL2_CODE_region = mem:[from BL2_CODE_START size BL2_CODE_SIZE];
+
+define region BL2_RAM_region = mem:[from BL2_DATA_START size BL2_DATA_SIZE];
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+keep {block TFM_SHARED_DATA};
+
+define block ER_DATA with maximum size = BL2_DATA_SIZE, alignment = 32 {readwrite};
+ /* MSP */
+
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block TFM_SHARED_DATA,
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in BL2_CODE_region { block LR_CODE };
+place in BL2_RAM_region { block DATA};
diff --git a/platform/ext/target/mps3/an524/device/source/iar/mps3_an524_ns.icf b/platform/ext/target/mps3/an524/device/source/iar/mps3_an524_ns.icf
new file mode 100644
index 0000000..598d74b
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/iar/mps3_an524_ns.icf
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps3_an524_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+define block ARM_LIB_STACK_MSP with alignment = 8, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 8, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+
+define block ER_DATA with alignment = 8 {readwrite};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in NS_CODE_region { block LR_CODE };
+place in NS_RAM_region { block DATA };
diff --git a/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_bl2.s b/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_bl2.s
new file mode 100644
index 0000000..164161c
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_bl2.s
@@ -0,0 +1,451 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps3_an524_bl2.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ DATA
+
+
+__vector_table
+ DCD sfe(ARM_LIB_STACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; 2 S32K Timer Handler
+ DCD TIMER0_Handler ; 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; 5 Dual Timer Handler
+ DCD 0 ; 6 Reserved
+ DCD 0 ; 7 Reserved
+ DCD 0 ; 8 Reserved
+ DCD MPC_Handler ; 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure)
+ ; Handler
+ DCD 0 ; 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD 0 ; 15 Reserved
+ DCD 0 ; 16 Reserved
+ DCD 0 ; 17 Reserved
+ DCD 0 ; 18 Reserved
+ DCD 0 ; 19 Reserved
+ DCD 0 ; 20 Reserved
+ DCD 0 ; 21 Reserved
+ DCD 0 ; 22 Reserved
+ DCD 0 ; 23 Reserved
+ DCD 0 ; 24 Reserved
+ DCD 0 ; 25 Reserved
+ DCD 0 ; 26 Reserved
+ DCD 0 ; 27 Reserved
+ DCD CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ DCD CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ DCD 0 ; 30 Reserved
+ DCD 0 ; 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD 0 ; 51 Reserved
+ DCD SPI0_Handler ; 52 SPI ADC Handler
+ DCD SPI1_Handler ; 53 SPI (Shield 0) Handler
+ DCD SPI2_Handler ; 54 SPI (Shield 1) Handler
+ DCD 0 ; 55 Reserved
+ DCD 0 ; 56 Reserved
+ DCD 0 ; 57 Reserved
+ DCD 0 ; 58 Reserved
+ DCD 0 ; 59 Reserved
+ DCD 0 ; 60 Reserved
+ DCD 0 ; 61 Reserved
+ DCD 0 ; 62 Reserved
+ DCD 0 ; 63 Reserved
+ DCD 0 ; 64 Reserved
+ DCD 0 ; 65 Reserved
+ DCD 0 ; 66 Reserved
+ DCD 0 ; 67 Reserved
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 GPIO0_0 Handler
+ DCD GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ DCD GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ DCD GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ DCD GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ DCD GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ DCD GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ DCD GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ DCD GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ DCD GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ DCD GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ DCD GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ DCD GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ DCD GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ DCD GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ DCD GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ DCD GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ DCD GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ DCD GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ DCD GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ DCD GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ DCD GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ DCD GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ DCD GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ DCD GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ DCD GPIO1_9_Handler ; 97 GPIO1_0 Handler
+ DCD GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ DCD GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ DCD GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ DCD GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ DCD GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ DCD GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ DCD GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ DCD GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ DCD GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ DCD GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ DCD GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ DCD GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ DCD GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ DCD GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ DCD GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ DCD GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ DCD GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ DCD GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ DCD GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ DCD GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ DCD GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ DCD GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ DCD GPIO3_0_Handler ; 120 GPIO2_16 Handler
+ DCD GPIO3_1_Handler ; 121 GPIO3_0 Handler
+ DCD GPIO3_2_Handler ; 122 GPIO3_1 Handler
+ DCD GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ DCD UARTRX5_Handler ; 124 UART 5 RX Handler
+ DCD UARTTX5_Handler ; 125 UART 5 TX Handler
+ DCD UART5_Handler ; 126 UART 5 combined Handler
+ DCD HDLCD_Handler ; 127 HDCLCD interrupt
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SecureFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+ ; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog
+ ; Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; 2 S32K Timer Handler
+ PUBWEAK TIMER0_Handler ; 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; 5 Dual Timer Handler
+ PUBWEAK MHU0_Handler ; 6 Message Handling Unit 0
+ PUBWEAK MHU1_Handler ; 7 Message Handling Unit 1
+
+ PUBWEAK MSC_Handler ; 11 MSC Combined (Secure)
+ ; Handler
+ PUBWEAK BRIDGE_ERROR_Handler ; 12 Bridge Error Combined
+ ; (Secure) Handler
+ PUBWEAK INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache
+ ; Invalidation Handler
+ PUBWEAK SYS_PPU_Handler ; 15 SYS PPU Handler
+ PUBWEAK CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+ PUBWEAK CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+ PUBWEAK CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+ PUBWEAK CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+ PUBWEAK CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+ PUBWEAK CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+ PUBWEAK RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+ PUBWEAK RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+ PUBWEAK RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+ PUBWEAK RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+ PUBWEAK CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ PUBWEAK CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ ; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 52 SPI ADC Handler
+ PUBWEAK SPI1_Handler ; 53 SPI (Shield 0) Handler
+ PUBWEAK SPI2_Handler ; 54 SPI (Shield 1) Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO0_0 Handlers
+ PUBWEAK GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ PUBWEAK GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ PUBWEAK GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ PUBWEAK GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ PUBWEAK GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ PUBWEAK GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ PUBWEAK GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ PUBWEAK GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ PUBWEAK GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ PUBWEAK GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ PUBWEAK GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ PUBWEAK GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ PUBWEAK GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ PUBWEAK GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ PUBWEAK GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ PUBWEAK GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ PUBWEAK GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ PUBWEAK GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ PUBWEAK GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ PUBWEAK GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ PUBWEAK GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ PUBWEAK GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ PUBWEAK GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ PUBWEAK GPIO1_9_Handler ; 97 GPIO1_9 Handler
+ PUBWEAK GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ PUBWEAK GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ PUBWEAK GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ PUBWEAK GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ PUBWEAK GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ PUBWEAK GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ PUBWEAK GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ PUBWEAK GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ PUBWEAK GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ PUBWEAK GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ PUBWEAK GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ PUBWEAK GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ PUBWEAK GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ PUBWEAK GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ PUBWEAK GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ PUBWEAK GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ PUBWEAK GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ PUBWEAK GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ PUBWEAK GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ PUBWEAK GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ PUBWEAK GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ PUBWEAK GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ PUBWEAK GPIO3_0_Handler ; 120 GPIO3_0 Handler
+ PUBWEAK GPIO3_1_Handler ; 121 GPIO3_1 Handler
+ PUBWEAK GPIO3_2_Handler ; 122 GPIO3_2 Handler
+ PUBWEAK GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ PUBWEAK UARTRX5_Handler ; 124 UART 5 RX Handler
+ PUBWEAK UARTTX5_Handler ; 125 UART 5 TX Handler
+ PUBWEAK UART5_Handler ; 126 UART 5 combined Handler
+ PUBWEAK HDLCD_Handler ; 127 HDCLCD interrupt
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; 2 S32K Timer Handler
+TIMER0_Handler ; 3 TIMER 0 Handler
+TIMER1_Handler ; 4 TIMER 1 Handler
+DUALTIMER_Handler ; 5 Dual Timer Handler
+MHU0_Handler ; 6 Message Handling Unit 0
+MHU1_Handler ; 7 Message Handling Unit 1
+MSC_Handler ; 11 MSC Combined (Secure) Handler
+BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure) Handler
+INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache Invalidation Handler
+SYS_PPU_Handler ; 15 SYS PPU Handler
+CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 52 SPI ADC Handler
+SPI1_Handler ; 53 SPI (Shield 0) Handler
+SPI2_Handler ; 54 SPI (Shield 1) Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO0_0 Handler
+GPIO0_1_Handler ; 73 GPIO0_1 Handler
+GPIO0_2_Handler ; 74 GPIO0_2 Handler
+GPIO0_3_Handler ; 75 GPIO0_3 Handler
+GPIO0_4_Handler ; 76 GPIO0_4 Handler
+GPIO0_5_Handler ; 77 GPIO0_5 Handler
+GPIO0_6_Handler ; 78 GPIO0_6 Handler
+GPIO0_7_Handler ; 79 GPIO0_7 Handler
+GPIO0_8_Handler ; 80 GPIO0_8 Handler
+GPIO0_9_Handler ; 81 GPIO0_9 Handler
+GPIO0_10_Handler ; 82 GPIO0_10 Handler
+GPIO0_11_Handler ; 83 GPIO0_11 Handler
+GPIO0_12_Handler ; 84 GPIO0_12 Handler
+GPIO0_13_Handler ; 85 GPIO0_13 Handler
+GPIO0_14_Handler ; 86 GPIO0_14 Handler
+GPIO0_15_Handler ; 87 GPIO0_15 Handler
+GPIO1_0_Handler ; 88 GPIO1_0 Handler
+GPIO1_1_Handler ; 89 GPIO1_1 Handler
+GPIO1_2_Handler ; 90 GPIO1_2 Handler
+GPIO1_3_Handler ; 91 GPIO1_3 Handler
+GPIO1_4_Handler ; 92 GPIO1_4 Handler
+GPIO1_5_Handler ; 93 GPIO1_5 Handler
+GPIO1_6_Handler ; 94 GPIO1_6 Handler
+GPIO1_7_Handler ; 95 GPIO1_7 Handler
+GPIO1_8_Handler ; 96 GPIO1_8 Handler
+GPIO1_9_Handler ; 97 GPIO1_9 Handler
+GPIO1_10_Handler ; 98 GPIO1_10 Handler
+GPIO1_11_Handler ; 99 GPIO1_11 Handler
+GPIO1_12_Handler ; 100 GPIO1_12 Handler
+GPIO1_13_Handler ; 101 GPIO1_13 Handler
+GPIO1_14_Handler ; 102 GPIO1_14 Handler
+GPIO1_15_Handler ; 103 GPIO1_15 Handler
+GPIO2_0_Handler ; 104 GPIO2_0 Handler
+GPIO2_1_Handler ; 105 GPIO2_1 Handler
+GPIO2_2_Handler ; 106 GPIO2_2 Handler
+GPIO2_3_Handler ; 107 GPIO2_3 Handler
+GPIO2_4_Handler ; 108 GPIO2_4 Handler
+GPIO2_5_Handler ; 109 GPIO2_5 Handler
+GPIO2_6_Handler ; 110 GPIO2_6 Handler
+GPIO2_7_Handler ; 111 GPIO2_7 Handler
+GPIO2_8_Handler ; 112 GPIO2_8 Handler
+GPIO2_9_Handler ; 113 GPIO2_9 Handler
+GPIO2_10_Handler ; 114 GPIO2_10 Handler
+GPIO2_11_Handler ; 115 GPIO2_11 Handler
+GPIO2_12_Handler ; 116 GPIO2_12 Handler
+GPIO2_13_Handler ; 117 GPIO2_13 Handler
+GPIO2_14_Handler ; 118 GPIO2_14 Handler
+GPIO2_15_Handler ; 119 GPIO2_15 Handler
+GPIO3_0_Handler ; 120 GPIO3_0 Handler
+GPIO3_1_Handler ; 121 GPIO2_1 Handler
+GPIO3_2_Handler ; 122 GPIO2_2 Handler
+GPIO3_3_Handler ; 123 GPIO2_3 Handler
+UARTRX5_Handler ; 124 UART 5 RX Handler
+UARTTX5_Handler ; 125 UART 5 TX Handler
+UART5_Handler ; 125 UART 5 combined Handler
+HDLCD_Handler ; 127 HDCLCD interrupt Handler
+ B .
+ END
diff --git a/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_ns.s b/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_ns.s
new file mode 100644
index 0000000..66f060d
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_ns.s
@@ -0,0 +1,446 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_ns.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD 0 ; 51 Reserved
+ DCD SPI0_Handler ; 52 SPI ADC Handler
+ DCD SPI1_Handler ; 53 SPI (Shield 0) Handler
+ DCD SPI2_Handler ; 54 SPI (Shield 1) Handler
+ DCD 0 ; 55 Reserved
+ DCD 0 ; 56 Reserved
+ DCD 0 ; 57 Reserved
+ DCD 0 ; 58 Reserved
+ DCD 0 ; 59 Reserved
+ DCD 0 ; 60 Reserved
+ DCD 0 ; 61 Reserved
+ DCD 0 ; 62 Reserved
+ DCD 0 ; 63 Reserved
+ DCD 0 ; 64 Reserved
+ DCD 0 ; 65 Reserved
+ DCD 0 ; 66 Reserved
+ DCD 0 ; 67 Reserved
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 GPIO0_0 Handler
+ DCD GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ DCD GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ DCD GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ DCD GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ DCD GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ DCD GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ DCD GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ DCD GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ DCD GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ DCD GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ DCD GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ DCD GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ DCD GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ DCD GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ DCD GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ DCD GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ DCD GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ DCD GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ DCD GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ DCD GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ DCD GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ DCD GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ DCD GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ DCD GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ DCD GPIO1_9_Handler ; 97 GPIO1_0 Handler
+ DCD GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ DCD GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ DCD GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ DCD GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ DCD GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ DCD GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ DCD GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ DCD GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ DCD GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ DCD GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ DCD GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ DCD GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ DCD GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ DCD GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ DCD GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ DCD GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ DCD GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ DCD GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ DCD GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ DCD GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ DCD GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ DCD GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ DCD GPIO3_0_Handler ; 120 GPIO2_16 Handler
+ DCD GPIO3_1_Handler ; 121 GPIO3_0 Handler
+ DCD GPIO3_2_Handler ; 122 GPIO3_1 Handler
+ DCD GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ DCD UARTRX5_Handler ; 124 UART 5 RX Handler
+ DCD UARTTX5_Handler ; 125 UART 5 TX Handler
+ DCD UART5_Handler ; 126 UART 5 combined Handler
+ DCD HDLCD_Handler ; 127 HDCLCD interrupt
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+Reset_Handler
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of ARM_LIB_STACK
+ MSR PSP, R0
+ MRS R0, CONTROL ; Get control value
+ ORR R0, R0, #1 ; Select switch to non privileged mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR CONTROL, R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+
+Default_Handler
+ ; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog
+ ; Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; 2 S32K Timer Handler
+ PUBWEAK TIMER0_Handler ; 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; 5 Dual Timer Handler
+ PUBWEAK MHU0_Handler ; 6 Message Handling Unit 0
+ PUBWEAK MHU1_Handler ; 7 Message Handling Unit 1
+ PUBWEAK INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache
+ ; Invalidation Handler
+ PUBWEAK SYS_PPU_Handler ; 15 SYS PPU Handler
+ PUBWEAK CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+ PUBWEAK CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+ PUBWEAK CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+ PUBWEAK CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+ PUBWEAK CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+ PUBWEAK CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+ PUBWEAK RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+ PUBWEAK RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+ PUBWEAK RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+ PUBWEAK RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+ PUBWEAK CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ PUBWEAK CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ ; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 52 SPI ADC Handler
+ PUBWEAK SPI1_Handler ; 53 SPI (Shield 0) Handler
+ PUBWEAK SPI2_Handler ; 54 SPI (Shield 1) Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO0_0 Handlers
+ PUBWEAK GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ PUBWEAK GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ PUBWEAK GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ PUBWEAK GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ PUBWEAK GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ PUBWEAK GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ PUBWEAK GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ PUBWEAK GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ PUBWEAK GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ PUBWEAK GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ PUBWEAK GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ PUBWEAK GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ PUBWEAK GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ PUBWEAK GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ PUBWEAK GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ PUBWEAK GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ PUBWEAK GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ PUBWEAK GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ PUBWEAK GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ PUBWEAK GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ PUBWEAK GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ PUBWEAK GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ PUBWEAK GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ PUBWEAK GPIO1_9_Handler ; 97 GPIO1_9 Handler
+ PUBWEAK GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ PUBWEAK GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ PUBWEAK GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ PUBWEAK GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ PUBWEAK GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ PUBWEAK GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ PUBWEAK GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ PUBWEAK GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ PUBWEAK GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ PUBWEAK GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ PUBWEAK GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ PUBWEAK GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ PUBWEAK GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ PUBWEAK GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ PUBWEAK GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ PUBWEAK GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ PUBWEAK GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ PUBWEAK GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ PUBWEAK GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ PUBWEAK GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ PUBWEAK GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ PUBWEAK GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ PUBWEAK GPIO3_0_Handler ; 120 GPIO3_0 Handler
+ PUBWEAK GPIO3_1_Handler ; 121 GPIO3_1 Handler
+ PUBWEAK GPIO3_2_Handler ; 122 GPIO3_2 Handler
+ PUBWEAK GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ PUBWEAK UARTRX5_Handler ; 124 UART 5 RX Handler
+ PUBWEAK UARTTX5_Handler ; 125 UART 5 TX Handler
+ PUBWEAK UART5_Handler ; 126 UART 5 combined Handler
+ PUBWEAK HDLCD_Handler ; 127 HDCLCD interrupt
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; 2 S32K Timer Handler
+TIMER0_Handler ; 3 TIMER 0 Handler
+TIMER1_Handler ; 4 TIMER 1 Handler
+DUALTIMER_Handler ; 5 Dual Timer Handler
+MHU0_Handler ; 6 Message Handling Unit 0
+MHU1_Handler ; 7 Message Handling Unit 1
+INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache Invalidation Handler
+SYS_PPU_Handler ; 15 SYS PPU Handler
+CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 52 SPI ADC Handler
+SPI1_Handler ; 53 SPI (Shield 0) Handler
+SPI2_Handler ; 54 SPI (Shield 1) Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO0_0 Handler
+GPIO0_1_Handler ; 73 GPIO0_1 Handler
+GPIO0_2_Handler ; 74 GPIO0_2 Handler
+GPIO0_3_Handler ; 75 GPIO0_3 Handler
+GPIO0_4_Handler ; 76 GPIO0_4 Handler
+GPIO0_5_Handler ; 77 GPIO0_5 Handler
+GPIO0_6_Handler ; 78 GPIO0_6 Handler
+GPIO0_7_Handler ; 79 GPIO0_7 Handler
+GPIO0_8_Handler ; 80 GPIO0_8 Handler
+GPIO0_9_Handler ; 81 GPIO0_9 Handler
+GPIO0_10_Handler ; 82 GPIO0_10 Handler
+GPIO0_11_Handler ; 83 GPIO0_11 Handler
+GPIO0_12_Handler ; 84 GPIO0_12 Handler
+GPIO0_13_Handler ; 85 GPIO0_13 Handler
+GPIO0_14_Handler ; 86 GPIO0_14 Handler
+GPIO0_15_Handler ; 87 GPIO0_15 Handler
+GPIO1_0_Handler ; 88 GPIO1_0 Handler
+GPIO1_1_Handler ; 89 GPIO1_1 Handler
+GPIO1_2_Handler ; 90 GPIO1_2 Handler
+GPIO1_3_Handler ; 91 GPIO1_3 Handler
+GPIO1_4_Handler ; 92 GPIO1_4 Handler
+GPIO1_5_Handler ; 93 GPIO1_5 Handler
+GPIO1_6_Handler ; 94 GPIO1_6 Handler
+GPIO1_7_Handler ; 95 GPIO1_7 Handler
+GPIO1_8_Handler ; 96 GPIO1_8 Handler
+GPIO1_9_Handler ; 97 GPIO1_9 Handler
+GPIO1_10_Handler ; 98 GPIO1_10 Handler
+GPIO1_11_Handler ; 99 GPIO1_11 Handler
+GPIO1_12_Handler ; 100 GPIO1_12 Handler
+GPIO1_13_Handler ; 101 GPIO1_13 Handler
+GPIO1_14_Handler ; 102 GPIO1_14 Handler
+GPIO1_15_Handler ; 103 GPIO1_15 Handler
+GPIO2_0_Handler ; 104 GPIO2_0 Handler
+GPIO2_1_Handler ; 105 GPIO2_1 Handler
+GPIO2_2_Handler ; 106 GPIO2_2 Handler
+GPIO2_3_Handler ; 107 GPIO2_3 Handler
+GPIO2_4_Handler ; 108 GPIO2_4 Handler
+GPIO2_5_Handler ; 109 GPIO2_5 Handler
+GPIO2_6_Handler ; 110 GPIO2_6 Handler
+GPIO2_7_Handler ; 111 GPIO2_7 Handler
+GPIO2_8_Handler ; 112 GPIO2_8 Handler
+GPIO2_9_Handler ; 113 GPIO2_9 Handler
+GPIO2_10_Handler ; 114 GPIO2_10 Handler
+GPIO2_11_Handler ; 115 GPIO2_11 Handler
+GPIO2_12_Handler ; 116 GPIO2_12 Handler
+GPIO2_13_Handler ; 117 GPIO2_13 Handler
+GPIO2_14_Handler ; 118 GPIO2_14 Handler
+GPIO2_15_Handler ; 119 GPIO2_15 Handler
+GPIO3_0_Handler ; 120 GPIO3_0 Handler
+GPIO3_1_Handler ; 121 GPIO2_1 Handler
+GPIO3_2_Handler ; 122 GPIO2_2 Handler
+GPIO3_3_Handler ; 123 GPIO2_3 Handler
+UARTRX5_Handler ; 124 UART 5 RX Handler
+UARTTX5_Handler ; 125 UART 5 TX Handler
+UART5_Handler ; 125 UART 5 combined Handler
+HDLCD_Handler ; 127 HDCLCD interrupt Handler
+ B .
+
+ END
diff --git a/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s b/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s
new file mode 100644
index 0000000..855a7af
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/iar/startup_cmsdk_mps3_an524_s.s
@@ -0,0 +1,459 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_s.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; 2 S32K Timer Handler
+ DCD TFM_TIMER0_IRQ_Handler ; 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; 5 Dual Timer Handler
+ DCD 0 ; 6 Reserved
+ DCD 0 ; 7 Reserved
+ DCD 0 ; 8 Reserved
+ DCD MPC_Handler ; 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure)
+ ; Handler
+ DCD 0 ; 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD 0 ; 15 Reserved
+ DCD 0 ; 16 Reserved
+ DCD 0 ; 17 Reserved
+ DCD 0 ; 18 Reserved
+ DCD 0 ; 19 Reserved
+ DCD 0 ; 20 Reserved
+ DCD 0 ; 21 Reserved
+ DCD 0 ; 22 Reserved
+ DCD 0 ; 23 Reserved
+ DCD 0 ; 24 Reserved
+ DCD 0 ; 25 Reserved
+ DCD 0 ; 26 Reserved
+ DCD 0 ; 27 Reserved
+ DCD CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ DCD CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ DCD 0 ; 30 Reserved
+ DCD 0 ; 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD 0 ; 51 Reserved
+ DCD SPI0_Handler ; 52 SPI ADC Handler
+ DCD SPI1_Handler ; 53 SPI (Shield 0) Handler
+ DCD SPI2_Handler ; 54 SPI (Shield 1) Handler
+ DCD 0 ; 55 Reserved
+ DCD 0 ; 56 Reserved
+ DCD 0 ; 57 Reserved
+ DCD 0 ; 58 Reserved
+ DCD 0 ; 59 Reserved
+ DCD 0 ; 60 Reserved
+ DCD 0 ; 61 Reserved
+ DCD 0 ; 62 Reserved
+ DCD 0 ; 63 Reserved
+ DCD 0 ; 64 Reserved
+ DCD 0 ; 65 Reserved
+ DCD 0 ; 66 Reserved
+ DCD 0 ; 67 Reserved
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 GPIO0_0 Handler
+ DCD GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ DCD GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ DCD GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ DCD GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ DCD GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ DCD GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ DCD GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ DCD GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ DCD GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ DCD GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ DCD GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ DCD GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ DCD GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ DCD GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ DCD GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ DCD GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ DCD GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ DCD GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ DCD GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ DCD GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ DCD GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ DCD GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ DCD GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ DCD GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ DCD GPIO1_9_Handler ; 97 GPIO1_0 Handler
+ DCD GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ DCD GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ DCD GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ DCD GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ DCD GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ DCD GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ DCD GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ DCD GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ DCD GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ DCD GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ DCD GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ DCD GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ DCD GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ DCD GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ DCD GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ DCD GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ DCD GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ DCD GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ DCD GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ DCD GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ DCD GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ DCD GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ DCD GPIO3_0_Handler ; 120 GPIO2_16 Handler
+ DCD GPIO3_1_Handler ; 121 GPIO3_0 Handler
+ DCD GPIO3_2_Handler ; 122 GPIO3_1 Handler
+ DCD GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ DCD UARTRX5_Handler ; 124 UART 5 RX Handler
+ DCD UARTTX5_Handler ; 125 UART 5 TX Handler
+ DCD UART5_Handler ; 126 UART 5 combined Handler
+ DCD HDLCD_Handler ; 127 HDCLCD interrupt
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =sfe(ARM_LIB_STACK) ; End of PROC_STACK
+ MSR PSP, R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler2 MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler2 NMI_Handler
+ Default_Handler2 HardFault_Handler
+ Default_Handler2 MemManage_Handler
+ Default_Handler2 BusFault_Handler
+ Default_Handler2 UsageFault_Handler
+ Default_Handler2 SecureFault_Handler
+ Default_Handler2 SVC_Handler
+ Default_Handler2 DebugMon_Handler
+ Default_Handler2 PendSV_Handler
+ Default_Handler2 SysTick_Handler
+ Default_Handler2 MPC_Handler
+ Default_Handler2 PPC_Handler
+
+Default_Handler
+; Core IoT Interrupts
+ PUBWEAK NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog
+ ; Reset Handler
+ PUBWEAK NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ PUBWEAK S32K_TIMER_Handler ; 2 S32K Timer Handler
+ PUBWEAK TFM_TIMER0_IRQ_Handler ; 3 TIMER 0 Handler
+ PUBWEAK TIMER1_Handler ; 4 TIMER 1 Handler
+ PUBWEAK DUALTIMER_Handler ; 5 Dual Timer Handler
+ PUBWEAK MHU0_Handler ; 6 Message Handling Unit 0
+ PUBWEAK MHU1_Handler ; 7 Message Handling Unit 1
+ PUBWEAK MSC_Handler ; 11 MSC Combined (Secure)
+ ; Handler
+ PUBWEAK BRIDGE_ERROR_Handler ; 12 Bridge Error Combined
+ ; (Secure) Handler
+ PUBWEAK INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache
+ ; Invalidation Handler
+ PUBWEAK SYS_PPU_Handler ; 15 SYS PPU Handler
+ PUBWEAK CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+ PUBWEAK CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+ PUBWEAK CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+ PUBWEAK CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+ PUBWEAK CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+ PUBWEAK CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+ PUBWEAK RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+ PUBWEAK RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+ PUBWEAK RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+ PUBWEAK RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+ PUBWEAK CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ PUBWEAK CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ ; External Interrupts
+ PUBWEAK UARTRX0_Handler ; 32 UART 0 RX Handler
+ PUBWEAK UARTTX0_Handler ; 33 UART 0 TX Handler
+ PUBWEAK UARTRX1_Handler ; 34 UART 1 RX Handler
+ PUBWEAK UARTTX1_Handler ; 35 UART 1 TX Handler
+ PUBWEAK UARTRX2_Handler ; 36 UART 2 RX Handler
+ PUBWEAK UARTTX2_Handler ; 37 UART 2 TX Handler
+ PUBWEAK UARTRX3_Handler ; 38 UART 3 RX Handler
+ PUBWEAK UARTTX3_Handler ; 39 UART 3 TX Handler
+ PUBWEAK UARTRX4_Handler ; 40 UART 4 RX Handler
+ PUBWEAK UARTTX4_Handler ; 41 UART 4 TX Handler
+ PUBWEAK UART0_Handler ; 42 UART 0 combined Handler
+ PUBWEAK UART1_Handler ; 43 UART 1 combined Handler
+ PUBWEAK UART2_Handler ; 44 UART 2 combined Handler
+ PUBWEAK UART3_Handler ; 45 UART 3 combined Handler
+ PUBWEAK UART4_Handler ; 46 UART 4 combined Handler
+ PUBWEAK UARTOVF_Handler ; 47 UART Overflow Handler
+ PUBWEAK ETHERNET_Handler ; 48 Ethernet Handler
+ PUBWEAK I2S_Handler ; 49 I2S Handler
+ PUBWEAK TSC_Handler ; 50 Touch Screen Handler
+ PUBWEAK SPI0_Handler ; 52 SPI ADC Handler
+ PUBWEAK SPI1_Handler ; 53 SPI (Shield 0) Handler
+ PUBWEAK SPI2_Handler ; 54 SPI (Shield 1) Handler
+ PUBWEAK GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ PUBWEAK GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ PUBWEAK GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ PUBWEAK GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ PUBWEAK GPIO0_0_Handler ; 72 GPIO0_0 Handlers
+ PUBWEAK GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ PUBWEAK GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ PUBWEAK GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ PUBWEAK GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ PUBWEAK GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ PUBWEAK GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ PUBWEAK GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ PUBWEAK GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ PUBWEAK GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ PUBWEAK GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ PUBWEAK GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ PUBWEAK GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ PUBWEAK GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ PUBWEAK GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ PUBWEAK GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ PUBWEAK GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ PUBWEAK GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ PUBWEAK GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ PUBWEAK GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ PUBWEAK GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ PUBWEAK GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ PUBWEAK GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ PUBWEAK GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ PUBWEAK GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ PUBWEAK GPIO1_9_Handler ; 97 GPIO1_9 Handler
+ PUBWEAK GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ PUBWEAK GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ PUBWEAK GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ PUBWEAK GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ PUBWEAK GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ PUBWEAK GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ PUBWEAK GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ PUBWEAK GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ PUBWEAK GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ PUBWEAK GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ PUBWEAK GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ PUBWEAK GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ PUBWEAK GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ PUBWEAK GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ PUBWEAK GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ PUBWEAK GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ PUBWEAK GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ PUBWEAK GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ PUBWEAK GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ PUBWEAK GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ PUBWEAK GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ PUBWEAK GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ PUBWEAK GPIO3_0_Handler ; 120 GPIO3_0 Handler
+ PUBWEAK GPIO3_1_Handler ; 121 GPIO3_1 Handler
+ PUBWEAK GPIO3_2_Handler ; 122 GPIO3_2 Handler
+ PUBWEAK GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ PUBWEAK UARTRX5_Handler ; 124 UART 5 RX Handler
+ PUBWEAK UARTTX5_Handler ; 125 UART 5 TX Handler
+ PUBWEAK UART5_Handler ; 126 UART 5 combined Handler
+ PUBWEAK HDLCD_Handler ; 127 HDCLCD interrupt
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; 2 S32K Timer Handler
+TFM_TIMER0_IRQ_Handler ; 3 TIMER 0 Handler
+TIMER1_Handler ; 4 TIMER 1 Handler
+DUALTIMER_Handler ; 5 Dual Timer Handler
+MHU0_Handler ; 6 Message Handling Unit 0
+MHU1_Handler ; 7 Message Handling Unit 1
+MSC_Handler ; 11 MSC Combined (Secure) Handler
+BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure) Handler
+INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache Invalidation Handler
+SYS_PPU_Handler ; 15 SYS PPU Handler
+CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 52 SPI ADC Handler
+SPI1_Handler ; 53 SPI (Shield 0) Handler
+SPI2_Handler ; 54 SPI (Shield 1) Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO0_0 Handler
+GPIO0_1_Handler ; 73 GPIO0_1 Handler
+GPIO0_2_Handler ; 74 GPIO0_2 Handler
+GPIO0_3_Handler ; 75 GPIO0_3 Handler
+GPIO0_4_Handler ; 76 GPIO0_4 Handler
+GPIO0_5_Handler ; 77 GPIO0_5 Handler
+GPIO0_6_Handler ; 78 GPIO0_6 Handler
+GPIO0_7_Handler ; 79 GPIO0_7 Handler
+GPIO0_8_Handler ; 80 GPIO0_8 Handler
+GPIO0_9_Handler ; 81 GPIO0_9 Handler
+GPIO0_10_Handler ; 82 GPIO0_10 Handler
+GPIO0_11_Handler ; 83 GPIO0_11 Handler
+GPIO0_12_Handler ; 84 GPIO0_12 Handler
+GPIO0_13_Handler ; 85 GPIO0_13 Handler
+GPIO0_14_Handler ; 86 GPIO0_14 Handler
+GPIO0_15_Handler ; 87 GPIO0_15 Handler
+GPIO1_0_Handler ; 88 GPIO1_0 Handler
+GPIO1_1_Handler ; 89 GPIO1_1 Handler
+GPIO1_2_Handler ; 90 GPIO1_2 Handler
+GPIO1_3_Handler ; 91 GPIO1_3 Handler
+GPIO1_4_Handler ; 92 GPIO1_4 Handler
+GPIO1_5_Handler ; 93 GPIO1_5 Handler
+GPIO1_6_Handler ; 94 GPIO1_6 Handler
+GPIO1_7_Handler ; 95 GPIO1_7 Handler
+GPIO1_8_Handler ; 96 GPIO1_8 Handler
+GPIO1_9_Handler ; 97 GPIO1_9 Handler
+GPIO1_10_Handler ; 98 GPIO1_10 Handler
+GPIO1_11_Handler ; 99 GPIO1_11 Handler
+GPIO1_12_Handler ; 100 GPIO1_12 Handler
+GPIO1_13_Handler ; 101 GPIO1_13 Handler
+GPIO1_14_Handler ; 102 GPIO1_14 Handler
+GPIO1_15_Handler ; 103 GPIO1_15 Handler
+GPIO2_0_Handler ; 104 GPIO2_0 Handler
+GPIO2_1_Handler ; 105 GPIO2_1 Handler
+GPIO2_2_Handler ; 106 GPIO2_2 Handler
+GPIO2_3_Handler ; 107 GPIO2_3 Handler
+GPIO2_4_Handler ; 108 GPIO2_4 Handler
+GPIO2_5_Handler ; 109 GPIO2_5 Handler
+GPIO2_6_Handler ; 110 GPIO2_6 Handler
+GPIO2_7_Handler ; 111 GPIO2_7 Handler
+GPIO2_8_Handler ; 112 GPIO2_8 Handler
+GPIO2_9_Handler ; 113 GPIO2_9 Handler
+GPIO2_10_Handler ; 114 GPIO2_10 Handler
+GPIO2_11_Handler ; 115 GPIO2_11 Handler
+GPIO2_12_Handler ; 116 GPIO2_12 Handler
+GPIO2_13_Handler ; 117 GPIO2_13 Handler
+GPIO2_14_Handler ; 118 GPIO2_14 Handler
+GPIO2_15_Handler ; 119 GPIO2_15 Handler
+GPIO3_0_Handler ; 120 GPIO3_0 Handler
+GPIO3_1_Handler ; 121 GPIO2_1 Handler
+GPIO3_2_Handler ; 122 GPIO2_2 Handler
+GPIO3_3_Handler ; 123 GPIO2_3 Handler
+UARTRX5_Handler ; 124 UART 5 RX Handler
+UARTTX5_Handler ; 125 UART 5 TX Handler
+UART5_Handler ; 125 UART 5 combined Handler
+HDLCD_Handler ; 127 HDCLCD interrupt Handler
+ B .
+
+ END
diff --git a/platform/ext/target/sse-200_aws/iar/sse-200_aws_bl2.icf b/platform/ext/target/sse-200_aws/iar/sse-200_aws_bl2.icf
new file mode 100644
index 0000000..97ce6e7
--- /dev/null
+++ b/platform/ext/target/sse-200_aws/iar/sse-200_aws_bl2.icf
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/sse-200_aws_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region BL2_CODE_region = mem:[from BL2_CODE_START size BL2_CODE_SIZE];
+
+define region BL2_RAM_region = mem:[from BL2_DATA_START size BL2_DATA_SIZE];
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+keep {block TFM_SHARED_DATA};
+
+define block ER_DATA with maximum size = BL2_DATA_SIZE, alignment = 32 {readwrite};
+ /* MSP */
+
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block TFM_SHARED_DATA,
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in BL2_CODE_region { block LR_CODE };
+place in BL2_RAM_region { block DATA};
diff --git a/platform/ext/target/sse-200_aws/iar/sse-200_aws_ns.icf b/platform/ext/target/sse-200_aws/iar/sse-200_aws_ns.icf
new file mode 100644
index 0000000..8989d44
--- /dev/null
+++ b/platform/ext/target/sse-200_aws/iar/sse-200_aws_ns.icf
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/sse-200_aws_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define memory mem with size = 4G;
+
+define region NS_CODE_region = mem:[from NS_CODE_START size NS_CODE_SIZE];
+
+define region NS_RAM_region = mem:[from NS_DATA_START size NS_DATA_SIZE];
+
+define block ARM_LIB_STACK_MSP with alignment = 8, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 8, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+
+define block ER_DATA with alignment = 8 {readwrite};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block LR_CODE with fixed order {block ER_CODE};
+define block DATA with fixed order {block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL};
+
+place in NS_CODE_region { block LR_CODE };
+place in NS_RAM_region { block DATA };
diff --git a/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s b/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s
new file mode 100644
index 0000000..60d68b4
--- /dev/null
+++ b/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s
@@ -0,0 +1,229 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an519_bl2.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+ DATA
+
+
+__vector_table DCD sfe(ARM_LIB_STACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD MHU0_Handler ; - 6 Message Handling Unit 0
+ DCD MHU1_Handler ; - 7 Message Handling Unit 1
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD 0 ; 34 Reserved
+ DCD 0 ; 35 Reserved
+ DCD 0 ; 36 Reserved
+ DCD 0 ; 37 Reserved
+ DCD 0 ; 38 Reserved
+ DCD 0 ; 39 Reserved
+ DCD 0 ; 40 Reserved
+ DCD 0 ; 41 Reserved
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD 0 ; 43 Reserved
+ DCD 0 ; 44 Reserved
+ DCD 0 ; 45 Reserved
+ DCD 0 ; 46 Reserved
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD 0 ; 48 Reserved
+ DCD 0 ; 49 Reserved
+ DCD 0 ; 50 Reserved
+ DCD 0 ; 51 Reserved
+ DCD 0 ; 52 Reserved
+ DCD 0 ; 53 Reserved
+ DCD 0 ; 54 Reserved
+ DCD 0 ; 55 Reserved
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD 0 ; 68 Reserved
+ DCD 0 ; 69 Reserved
+ DCD 0 ; 70 Reserved
+ DCD 0 ; 71 Reserved
+ DCD 0 ; 72 Reserved
+ DCD 0 ; 73 Reserved
+ DCD 0 ; 74 Reserved
+ DCD 0 ; 75 Reserved
+ DCD 0 ; 76 Reserved
+ DCD 0 ; 77 Reserved
+ DCD 0 ; 78 Reserved
+ DCD 0 ; 79 Reserved
+ DCD 0 ; 80 Reserved
+ DCD 0 ; 81 Reserved
+ DCD 0 ; 82 Reserved
+ DCD 0 ; 83 Reserved
+ DCD 0 ; 84 Reserved
+ DCD 0 ; 85 Reserved
+ DCD 0 ; 86 Reserved
+ DCD 0 ; 87 Reserved
+ DCD 0 ; 88 Reserved
+ DCD 0 ; 89 Reserved
+ DCD 0 ; 90 Reserved
+ DCD 0 ; 91 Reserved
+ DCD 0 ; 92 Reserved
+ DCD 0 ; 93 Reserved
+ DCD 0 ; 94 Reserved
+ DCD 0 ; 95 Reserved
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ ; Only run on core 0
+ MOV r0, #0x50000000
+ ADD r0, #0x0001F000
+ LDR r0, [r0]
+ CMP r0,#0
+not_the_core_to_run_on
+ BNE not_the_core_to_run_on
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+; Core IoT Interrupts
+ Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ Default_Handler TIMER0_Handler ; - 3 TIMER 0 Handler
+ Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler
+ Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler
+ Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0
+ Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1
+ Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+; External Interrupts
+ Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler
+ Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler
+ Default_Handler UART0_Handler ; 42 UART 0 combined Handler
+ Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler
+ Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler
+ Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler
+ Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler
+ Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler
+
+ END
diff --git a/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s b/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s
new file mode 100644
index 0000000..64b48d0
--- /dev/null
+++ b/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s
@@ -0,0 +1,222 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_ns.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD MHU0_Handler ; - 6 Message Handling Unit 0
+ DCD MHU1_Handler ; - 7 Message Handling Unit 1
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD 0 ; 34 Reserved
+ DCD 0 ; 35 Reserved
+ DCD 0 ; 36 Reserved
+ DCD 0 ; 37 Reserved
+ DCD 0 ; 38 Reserved
+ DCD 0 ; 39 Reserved
+ DCD 0 ; 40 Reserved
+ DCD 0 ; 41 Reserved
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD 0 ; 43 Reserved
+ DCD 0 ; 44 Reserved
+ DCD 0 ; 45 Reserved
+ DCD 0 ; 46 Reserved
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD 0 ; 48 Reserved
+ DCD 0 ; 49 Reserved
+ DCD 0 ; 50 Reserved
+ DCD 0 ; 51 Reserved
+ DCD 0 ; 52 Reserved
+ DCD 0 ; 53 Reserved
+ DCD 0 ; 54 Reserved
+ DCD 0 ; 55 Reserved
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD 0 ; 68 Reserved
+ DCD 0 ; 69 Reserved
+ DCD 0 ; 70 Reserved
+ DCD 0 ; 71 Reserved
+ DCD 0 ; 72 Reserved
+ DCD 0 ; 73 Reserved
+ DCD 0 ; 74 Reserved
+ DCD 0 ; 75 Reserved
+ DCD 0 ; 76 Reserved
+ DCD 0 ; 77 Reserved
+ DCD 0 ; 78 Reserved
+ DCD 0 ; 79 Reserved
+ DCD 0 ; 80 Reserved
+ DCD 0 ; 81 Reserved
+ DCD 0 ; 82 Reserved
+ DCD 0 ; 83 Reserved
+ DCD 0 ; 84 Reserved
+ DCD 0 ; 85 Reserved
+ DCD 0 ; 86 Reserved
+ DCD 0 ; 87 Reserved
+ DCD 0 ; 88 Reserved
+ DCD 0 ; 89 Reserved
+ DCD 0 ; 90 Reserved
+ DCD 0 ; 91 Reserved
+ DCD 0 ; 92 Reserved
+ DCD 0 ; 93 Reserved
+ DCD 0 ; 94 Reserved
+ DCD 0 ; 95 Reserved
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+Reset_Handler
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+; Core IoT Interrupts
+ Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ Default_Handler TIMER0_Handler ; - 3 TIMER 0 Handler
+ Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler
+ Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler
+ Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0
+ Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1
+ Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+; External Interrupts
+ Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler
+ Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler
+ Default_Handler UART0_Handler ; 42 UART 0 combined Handler
+ Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler
+ Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler
+ Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler
+ Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler
+ Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler
+
+ END
diff --git a/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s b/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s
new file mode 100644
index 0000000..76e131f
--- /dev/null
+++ b/platform/ext/target/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s
@@ -0,0 +1,228 @@
+;/*
+; * Copyright (c) 2016-2020 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_s.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table ;Core Interrupts
+ DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD MHU0_Handler ; - 6 Message Handling Unit 0
+ DCD MHU1_Handler ; - 7 Message Handling Unit 1
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD 0 ; 34 Reserved
+ DCD 0 ; 35 Reserved
+ DCD 0 ; 36 Reserved
+ DCD 0 ; 37 Reserved
+ DCD 0 ; 38 Reserved
+ DCD 0 ; 39 Reserved
+ DCD 0 ; 40 Reserved
+ DCD 0 ; 41 Reserved
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD 0 ; 43 Reserved
+ DCD 0 ; 44 Reserved
+ DCD 0 ; 45 Reserved
+ DCD 0 ; 46 Reserved
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD 0 ; 48 Reserved
+ DCD 0 ; 49 Reserved
+ DCD 0 ; 50 Reserved
+ DCD 0 ; 51 Reserved
+ DCD 0 ; 52 Reserved
+ DCD 0 ; 53 Reserved
+ DCD 0 ; 54 Reserved
+ DCD 0 ; 55 Reserved
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD 0 ; 68 Reserved
+ DCD 0 ; 69 Reserved
+ DCD 0 ; 70 Reserved
+ DCD 0 ; 71 Reserved
+ DCD 0 ; 72 Reserved
+ DCD 0 ; 73 Reserved
+ DCD 0 ; 74 Reserved
+ DCD 0 ; 75 Reserved
+ DCD 0 ; 76 Reserved
+ DCD 0 ; 77 Reserved
+ DCD 0 ; 78 Reserved
+ DCD 0 ; 79 Reserved
+ DCD 0 ; 80 Reserved
+ DCD 0 ; 81 Reserved
+ DCD 0 ; 82 Reserved
+ DCD 0 ; 83 Reserved
+ DCD 0 ; 84 Reserved
+ DCD 0 ; 85 Reserved
+ DCD 0 ; 86 Reserved
+ DCD 0 ; 87 Reserved
+ DCD 0 ; 88 Reserved
+ DCD 0 ; 89 Reserved
+ DCD 0 ; 90 Reserved
+ DCD 0 ; 91 Reserved
+ DCD 0 ; 92 Reserved
+ DCD 0 ; 93 Reserved
+ DCD 0 ; 94 Reserved
+ DCD 0 ; 95 Reserved
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+Default_Handler MACRO handler_name
+ PUBWEAK handler_name
+handler_name
+ B .
+ ENDM
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+; Core IoT Interrupts
+ Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ Default_Handler TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler
+ Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler
+ Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler
+ Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0
+ Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1
+ Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler
+ Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler
+; External Interrupts
+ Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler
+ Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler
+ Default_Handler UART0_Handler ; 42 UART 0 combined Handler
+ Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler
+ Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler
+ Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler
+ Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler
+ Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler
+
+ END
diff --git a/secure_fw/core/arch/tfm_arch_v8m_base.c b/secure_fw/core/arch/tfm_arch_v8m_base.c
index 3a64f82..eefdaaf 100644
--- a/secure_fw/core/arch/tfm_arch_v8m_base.c
+++ b/secure_fw/core/arch/tfm_arch_v8m_base.c
@@ -47,6 +47,10 @@
* thread SP/SP_LIMIT. R2 holds dummy data due to stack operation is 8 bytes
* aligned.
*/
+#if defined(__ICCARM__)
+#pragma required = tfm_pendsv_do_schedule
+#endif
+
__attribute__((naked)) void PendSV_Handler(void)
{
__ASM volatile(
@@ -87,7 +91,6 @@
int32_t tfm_core_sfn_request(const struct tfm_sfn_req_s *desc_ptr)
{
__ASM volatile(
- ".syntax unified \n"
"PUSH {lr} \n"
"PUSH {r4-r7} \n"
"MOV r4, r8 \n"
@@ -187,10 +190,14 @@
}
}
+#if defined(__ICCARM__)
+uint32_t tfm_core_svc_handler(uint32_t *svc_args, uint32_t exc_return);
+#pragma required = tfm_core_svc_handler
+#endif
+
__attribute__((naked)) void SVC_Handler(void)
{
__ASM volatile(
- ".syntax unified \n"
"MRS r2, MSP \n"
"MOVS r1, #4 \n"
"MOV r3, lr \n"