Platform: Add Musca test chip support
1) Files derived from the following keil packs
keil-pack-musca-a1 release_v1.0.1
keil-pack-sse-200 release_v1.0.3
2) Add Musca target configuration and partition files
3) Add Musca platform support in cmake files
4) Enable BL2 with Musca test chip
5) Create signed binary with correct size for MPS2 platforms
Change-Id: I0ab913110b0817b7e8d7424812b978526487a3d0
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
diff --git a/CommonConfig.cmake b/CommonConfig.cmake
old mode 100644
new mode 100755
index 2ffe115..37368e3
--- a/CommonConfig.cmake
+++ b/CommonConfig.cmake
@@ -54,6 +54,8 @@
if(${TARGET_PLATFORM} STREQUAL "AN521" OR ${TARGET_PLATFORM} STREQUAL "AN519")
set (REFERENCE_PLATFORM ON)
+elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
+ add_definitions(-DTARGET_MUSCA_A)
endif()
if (REGRESSION)
diff --git a/ConfigDefault.cmake b/ConfigDefault.cmake
old mode 100644
new mode 100755
index c9dbf2f..fb5f516
--- a/ConfigDefault.cmake
+++ b/ConfigDefault.cmake
@@ -15,6 +15,8 @@
set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set (PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
+ set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/musca_a.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/ConfigRegression.cmake b/ConfigRegression.cmake
old mode 100644
new mode 100755
index 2a50771..c557ef8
--- a/ConfigRegression.cmake
+++ b/ConfigRegression.cmake
@@ -15,6 +15,8 @@
set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set (PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
+ set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/musca_a.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/app/CMakeLists.txt b/app/CMakeLists.txt
old mode 100644
new mode 100755
index 52e3a19..e849ebe
--- a/app/CMakeLists.txt
+++ b/app/CMakeLists.txt
@@ -93,7 +93,7 @@
find_package(PythonInterp 3)
if (NOT PYTHONINTERP_FOUND)
- message(FATAL_ERROR "Failed to find Python3.x interpreter. Pyhton3 must be installed an available on the PATH.")
+ message(FATAL_ERROR "Failed to find Python3.x interpreter. Python3 must be installed and available on the PATH.")
endif()
set(MCUBOOT_DIR ${TFM_ROOT_DIR}/bl2/ext/mcuboot)
@@ -119,7 +119,7 @@
--align 1
-v 1.0
-H 0x400
- --pad 0x100000
+ --pad ${SIGN_BIN_SIZE}
${CMAKE_BINARY_DIR}/tfm_full.bin
${CMAKE_BINARY_DIR}/tfm_sign.bin
)
diff --git a/platform/ext/Mps2AN519.cmake b/platform/ext/Mps2AN519.cmake
old mode 100644
new mode 100755
index 2a62c6b..257d5fc
--- a/platform/ext/Mps2AN519.cmake
+++ b/platform/ext/Mps2AN519.cmake
@@ -17,6 +17,7 @@
set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/armclang/mps2_an519_s.sct")
set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/armclang/mps2_an519_ns.sct")
set (FLASH_LAYOUT "${PLATFORM_DIR}/target/mps2/an519/partition/flash_layout.h")
+set (SIGN_BIN_SIZE 0x100000)
if (DEFINED CMSIS_5_DIR)
# not all project defines CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib")
diff --git a/platform/ext/Mps2AN521.cmake b/platform/ext/Mps2AN521.cmake
old mode 100644
new mode 100755
index b63e9db..68beb5d
--- a/platform/ext/Mps2AN521.cmake
+++ b/platform/ext/Mps2AN521.cmake
@@ -17,6 +17,7 @@
set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an521/armclang/mps2_an521_s.sct")
set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an521/armclang/mps2_an521_ns.sct")
set (FLASH_LAYOUT "${PLATFORM_DIR}/target/mps2/an521/partition/flash_layout.h")
+set (SIGN_BIN_SIZE 0x100000)
if (DEFINED CMSIS_5_DIR)
# not all project defines CMSIS_5_DIR, only the ones that use it.
set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
diff --git a/platform/ext/common/uart_stdout.c b/platform/ext/common/uart_stdout.c
old mode 100644
new mode 100755
index 3dd3b02..cb5466d
--- a/platform/ext/common/uart_stdout.c
+++ b/platform/ext/common/uart_stdout.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017-2018 ARM Limited
*
* Licensed under the Apace License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -19,7 +19,11 @@
#include <assert.h>
#include <stdio.h>
#include <string.h>
+#ifdef TARGET_MUSCA_A
+#include "uart_pl011_drv.h"
+#else
#include "arm_uart_drv.h"
+#endif
#include "Driver_USART.h"
#define ASSERT_HIGH(X) assert(X == ARM_DRIVER_OK)
@@ -40,8 +44,13 @@
return ch;
}
+#ifdef TARGET_MUSCA_A
+extern struct uart_pl011_dev_t UART0_DEV_S, UART0_DEV_NS;
+extern struct uart_pl011_dev_t UART1_DEV_S, UART1_DEV_NS;
+#else
extern struct arm_uart_dev_t ARM_UART0_DEV_S, ARM_UART0_DEV_NS;
extern struct arm_uart_dev_t ARM_UART1_DEV_S, ARM_UART1_DEV_NS;
+#endif
/* Generic driver to be configured and used */
ARM_DRIVER_USART *Driver_USART = NULL;
@@ -58,7 +67,11 @@
* to use UART1 only from S side as it's a secure peripheral, but for
* simplicity, leave the option to use UART0 and use a workaround
*/
+#ifdef TARGET_MUSCA_A
+ memcpy(&UART0_DEV_S, &UART0_DEV_NS, sizeof(struct uart_pl011_dev_t));
+#else
memcpy(&ARM_UART0_DEV_S, &ARM_UART0_DEV_NS, sizeof(struct arm_uart_dev_t));
+#endif
Driver_USART = &Driver_USART0;
break;
case UART1_CHANNEL:
diff --git a/platform/ext/driver/Driver_MPC.h b/platform/ext/driver/Driver_MPC.h
old mode 100644
new mode 100755
index c4fe825..994dfda
--- a/platform/ext/driver/Driver_MPC.h
+++ b/platform/ext/driver/Driver_MPC.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -27,6 +27,7 @@
#define ARM_MPC_ERR_NOT_ALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Address is not aligned on the block size of this MPC */
#define ARM_MPC_ERR_INVALID_RANGE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given address range to configure is invalid
#define ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< The given range cannot be accessed with the wanted security attributes */
+#define ARM_MPC_ERR_UNSPECIFIED (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Unspecified error */
/* Security attribute used in various place of the API */
typedef enum _ARM_MPC_SEC_ATTR {
diff --git a/platform/ext/musca_a.cmake b/platform/ext/musca_a.cmake
new file mode 100755
index 0000000..17b3141
--- /dev/null
+++ b/platform/ext/musca_a.cmake
@@ -0,0 +1,116 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file gathers all musca specific files in the application.
+
+#MUSCA-A has a Cortex M33 CPU.
+include("Common/CpuM33")
+
+set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+#Specify the location of platform specific build dependencies.
+set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_bl2.sct")
+set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_s.sct")
+set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/musca_ns.sct")
+set (FLASH_LAYOUT "${PLATFORM_DIR}/target/musca_a/partition/flash_layout.h")
+set (SIGN_BIN_SIZE 0x30000)
+if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
+endif()
+
+if (BL2)
+ set (BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
+endif()
+
+embedded_include_directories(PATH "${PLATFORM_DIR}/cmsis" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Config" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/Device/Config" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/Device/Include" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/Native_Driver" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/partition" ABSOLUTE)
+
+#Gather all source files we need.
+if (NOT DEFINED BUILD_CMSIS_CORE)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_CORE (true|false) is undefined!")
+elseif(BUILD_CMSIS_CORE)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Device/Source/system_cmsdk_musca.c")
+endif()
+
+if (NOT DEFINED BUILD_RETARGET)
+ message(FATAL_ERROR "Configuration variable BUILD_RETARGET (true|false) is undefined!")
+elseif(BUILD_RETARGET)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Device/Source/platform_retarget_dev.c")
+endif()
+
+if (NOT DEFINED BUILD_UART_STDOUT)
+ message(FATAL_ERROR "Configuration variable BUILD_UART_STDOUT (true|false) is undefined!")
+elseif(BUILD_UART_STDOUT)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/uart_stdout.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+ set(BUILD_NATIVE_DRIVERS true)
+ set(BUILD_CMSIS_DRIVERS true)
+endif()
+
+if (NOT DEFINED BUILD_NATIVE_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_NATIVE_DRIVERS (true|false) is undefined!")
+elseif(BUILD_NATIVE_DRIVERS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Native_Driver/uart_pl011_drv.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Native_Driver/arm_scc_drv.c")
+
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/musca_a/Native_Driver/mpc_sie200_drv.c"
+ "${PLATFORM_DIR}/target/musca_a/Native_Driver/ppc_sse200_drv.c")
+endif()
+
+if (NOT DEFINED BUILD_TIME)
+ message(FATAL_ERROR "Configuration variable BUILD_TIME (true|false) is undefined!")
+elseif(BUILD_TIME)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/Native_Driver/timer_cmsdk.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/Native_Driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_STARTUP)
+ message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
+elseif(BUILD_STARTUP)
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s")
+ else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TARGET_CFG)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_CFG (true|false) is undefined!")
+elseif(BUILD_TARGET_CFG)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/target_cfg.c")
+endif()
+
+if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/dummy_crypto_keys.c")
+endif()
+
+if (NOT DEFINED BUILD_CMSIS_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_DRIVERS (true|false) is undefined!")
+elseif(BUILD_CMSIS_DRIVERS)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Driver_MPC.c"
+ "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Driver_PPC.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver/Driver_USART.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/musca_a/CMSIS_Driver" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_FLASH)
+ message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
+elseif(BUILD_FLASH)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/flash_memory_mapped.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+endif()
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h b/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
new file mode 100755
index 0000000..7235c79
--- /dev/null
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Config/RTE_Device.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
+#define RTE_ISRAM0_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <i> Configuration settings for Driver_SRAM1_MPC in component ::Drivers:MPC
+#define RTE_ISRAM1_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+// <i> Configuration settings for Driver_ISRAM2_MPC in component ::Drivers:MPC
+#define RTE_ISRAM2_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+// <i> Configuration settings for Driver_SRAM2_MPC in component ::Drivers:MPC
+#define RTE_ISRAM3_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM3_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+// <i> Configuration settings for Driver_SRAM1_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM1_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
+#define RTE_QSPI_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_USART0 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_USART1 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPC0]
+// <i> Configuration settings for Driver_AHB_PPC0 in component ::Drivers:PPC
+#define RTE_AHB_PPC0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPC0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+// <i> Configuration settings for Driver_AHB_PPCEXP0 in component ::Drivers:PPC
+#define RTE_AHB_PPCEXP0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1]
+// <i> Configuration settings for Driver_AHB_PPCEXP1 in component ::Drivers:PPC
+#define RTE_AHB_PPCEXP1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2]
+// <i> Configuration settings for Driver_AHB_PPCEXP2 in component ::Drivers:PPC
+#define RTE_AHB_PPCEXP2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3]
+// <i> Configuration settings for Driver_AHB_PPCEXP3 in component ::Drivers:PPC
+#define RTE_AHB_PPCEXP3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+// <i> Configuration settings for Driver_APB_PPC0 in component ::Drivers:PPC
+#define RTE_APB_PPC0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+// <i> Configuration settings for Driver_APB_PPC1 in component ::Drivers:PPC
+#define RTE_APB_PPC1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+// <i> Configuration settings for Driver_APB_PPCEXP0 in component ::Drivers:PPC
+#define RTE_APB_PPCEXP0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+// <i> Configuration settings for Driver_APB_PPCEXP1 in component ::Drivers:PPC
+#define RTE_APB_PPCEXP1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+// <i> Configuration settings for Driver_APB_PPCEXP2 in component ::Drivers:PPC
+#define RTE_APB_PPCEXP2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+// <i> Configuration settings for Driver_APB_PPCEXP3 in component ::Drivers:PPC
+#define RTE_APB_PPCEXP3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+
+#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c
new file mode 100644
index 0000000..c76558c
--- /dev/null
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_MPC.c
@@ -0,0 +1,879 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Driver_MPC.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+/* driver version */
+#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_MPC_API_VERSION,
+ ARM_MPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+/*
+ * \brief Translates error codes from native API to CMSIS API.
+ *
+ * \param[in] err Error code to translate (\ref mpc_sie200_error_t).
+ *
+ * \return Returns CMSIS error code.
+ */
+static int32_t error_trans(enum mpc_sie200_error_t err)
+{
+ switch(err) {
+ case MPC_SIE200_ERR_NONE:
+ return ARM_DRIVER_OK;
+ case MPC_SIE200_INVALID_ARG:
+ return ARM_DRIVER_ERROR_PARAMETER;
+ case MPC_SIE200_NOT_INIT:
+ return ARM_MPC_ERR_NOT_INIT;
+ case MPC_SIE200_ERR_NOT_IN_RANGE:
+ return ARM_MPC_ERR_NOT_IN_RANGE;
+ case MPC_SIE200_ERR_NOT_ALIGNED:
+ return ARM_MPC_ERR_NOT_ALIGNED;
+ case MPC_SIE200_ERR_INVALID_RANGE:
+ return ARM_MPC_ERR_INVALID_RANGE;
+ case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE:
+ return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ default:
+ return ARM_MPC_ERR_UNSPECIFIED;
+ }
+}
+
+#if (RTE_ISRAM0_MPC)
+/* Ranges controlled by this ISRAM0_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_S = {
+ .base = MPC_ISRAM0_RANGE_BASE_S,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_NS = {
+ .base = MPC_ISRAM0_RANGE_BASE_NS,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM0_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN]=
+ {&MPC_ISRAM0_RANGE_S, &MPC_ISRAM0_RANGE_NS};
+
+/* ISRAM0_MPC Driver wrapper functions */
+static int32_t ISRAM0_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM0_DEV_S,
+ MPC_ISRAM0_RANGE_LIST,
+ MPC_ISRAM0_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM0_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM0_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM0_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM0_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM0_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM0_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM0_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM0_DEV_S);
+}
+
+
+static void ISRAM0_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM0_DEV_S);
+}
+
+static uint32_t ISRAM0_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM0_DEV_S);
+}
+
+static int32_t ISRAM0_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM0_DEV_S);
+}
+
+/* ISRAM0_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
+ARM_DRIVER_MPC Driver_ISRAM0_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM0_MPC_Initialize,
+ .Uninitialize = ISRAM0_MPC_Uninitialize,
+ .GetBlockSize = ISRAM0_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM0_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM0_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM0_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM0_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM0_MPC_ClearInterrupt,
+ .InterruptState = ISRAM0_MPC_InterruptState,
+ .LockDown = ISRAM0_MPC_LockDown,
+};
+#endif /* RTE_ISRAM0_MPC */
+
+#if (RTE_ISRAM1_MPC)
+/* Ranges controlled by this ISRAM1_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_S = {
+ .base = MPC_ISRAM1_RANGE_BASE_S,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_NS = {
+ .base = MPC_ISRAM1_RANGE_BASE_NS,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN]=
+ {&MPC_ISRAM1_RANGE_S, &MPC_ISRAM1_RANGE_NS};
+
+/* ISRAM1_MPC Driver wrapper functions */
+static int32_t ISRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM1_DEV_S,
+ MPC_ISRAM1_RANGE_LIST,
+ MPC_ISRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM1_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM1_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM1_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM1_DEV_S);
+}
+
+
+static void ISRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM1_DEV_S);
+}
+
+static uint32_t ISRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM1_DEV_S);
+}
+
+static int32_t ISRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM1_DEV_S);
+}
+
+/* ISRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
+ARM_DRIVER_MPC Driver_ISRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM1_MPC_Initialize,
+ .Uninitialize = ISRAM1_MPC_Uninitialize,
+ .GetBlockSize = ISRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM1_MPC_ClearInterrupt,
+ .InterruptState = ISRAM1_MPC_InterruptState,
+ .LockDown = ISRAM1_MPC_LockDown,
+};
+#endif /* RTE_ISRAM1_MPC */
+
+#if (RTE_ISRAM2_MPC)
+/* Ranges controlled by this ISRAM2_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_S = {
+ .base = MPC_ISRAM2_RANGE_BASE_S,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_NS = {
+ .base = MPC_ISRAM2_RANGE_BASE_NS,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN]=
+ {&MPC_ISRAM2_RANGE_S, &MPC_ISRAM2_RANGE_NS};
+
+/* ISRAM2_MPC Driver wrapper functions */
+static int32_t ISRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM2_DEV_S,
+ MPC_ISRAM2_RANGE_LIST,
+ MPC_ISRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM2_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM2_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM2_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM2_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM2_DEV_S);
+}
+
+static void ISRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM2_DEV_S);
+}
+
+static uint32_t ISRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM2_DEV_S);
+}
+
+static int32_t ISRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM2_DEV_S);
+}
+
+/* ISRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
+ARM_DRIVER_MPC Driver_ISRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM2_MPC_Initialize,
+ .Uninitialize = ISRAM2_MPC_Uninitialize,
+ .GetBlockSize = ISRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM2_MPC_ClearInterrupt,
+ .InterruptState = ISRAM2_MPC_InterruptState,
+ .LockDown = ISRAM2_MPC_LockDown,
+};
+#endif /* RTE_ISRAM2_MPC */
+
+#if (RTE_ISRAM3_MPC)
+/* Ranges controlled by this ISRAM3_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_S = {
+ .base = MPC_ISRAM3_RANGE_BASE_S,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_NS = {
+ .base = MPC_ISRAM3_RANGE_BASE_NS,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN]=
+ {&MPC_ISRAM3_RANGE_S, &MPC_ISRAM3_RANGE_NS};
+
+/* ISRAM3_MPC Driver wrapper functions */
+static int32_t ISRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM3_DEV_S,
+ MPC_ISRAM3_RANGE_LIST,
+ MPC_ISRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM3_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM3_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM3_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM3_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM3_DEV_S);
+}
+
+
+static void ISRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM3_DEV_S);
+}
+
+static uint32_t ISRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM3_DEV_S);
+}
+
+static int32_t ISRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM3_DEV_S);
+}
+
+/* ISRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
+ARM_DRIVER_MPC Driver_ISRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM3_MPC_Initialize,
+ .Uninitialize = ISRAM3_MPC_Uninitialize,
+ .GetBlockSize = ISRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM3_MPC_ClearInterrupt,
+ .InterruptState = ISRAM3_MPC_InterruptState,
+ .LockDown = ISRAM3_MPC_LockDown,
+};
+#endif /* RTE_ISRAM3_MPC */
+
+#if (RTE_CODE_SRAM1_MPC)
+/* Ranges controlled by this SRAM1_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM1_RANGE_S = {
+ .base = MPC_CODE_SRAM1_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM1_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM1_RANGE_NS = {
+ .base = MPC_CODE_SRAM1_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM1_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM1_RANGE_LIST[MPC_CODE_SRAM1_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM1_RANGE_S, &MPC_CODE_SRAM1_RANGE_NS};
+
+/* SRAM1_MPC Driver wrapper functions */
+static int32_t SRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM1_DEV_S,
+ MPC_CODE_SRAM1_RANGE_LIST,
+ MPC_CODE_SRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM1_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM1_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM1_DEV_S);
+}
+
+
+static void SRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM1_DEV_S);
+}
+
+static uint32_t SRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM1_DEV_S);
+}
+
+static int32_t SRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM1_DEV_S);
+}
+
+/* SRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+ARM_DRIVER_MPC Driver_SRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM1_MPC_Initialize,
+ .Uninitialize = SRAM1_MPC_Uninitialize,
+ .GetBlockSize = SRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM1_MPC_ClearInterrupt,
+ .InterruptState = SRAM1_MPC_InterruptState,
+ .LockDown = SRAM1_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM1_MPC */
+
+#if (RTE_QSPI_MPC)
+/* Ranges controlled by this QSPI_MPC */
+static struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_S = {
+ .base = MPC_QSPI_RANGE_BASE_S,
+ .limit = MPC_QSPI_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_NS = {
+ .base = MPC_QSPI_RANGE_BASE_NS,
+ .limit = MPC_QSPI_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_QSPI_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_QSPI_RANGE_LIST[MPC_QSPI_RANGE_LIST_LEN]=
+ {&MPC_QSPI_RANGE_S, &MPC_QSPI_RANGE_NS};
+
+/* QSPI_MPC Driver wrapper functions */
+static int32_t QSPI_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_QSPI_DEV_S,
+ MPC_QSPI_RANGE_LIST,
+ MPC_QSPI_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t QSPI_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_QSPI_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_QSPI_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_QSPI_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_QSPI_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_QSPI_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_QSPI_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void QSPI_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_QSPI_DEV_S);
+}
+
+
+static void QSPI_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_QSPI_DEV_S);
+}
+
+static uint32_t QSPI_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_QSPI_DEV_S);
+}
+
+static int32_t QSPI_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_QSPI_DEV_S);
+}
+
+/* QSPI1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_QSPI_MPC;
+ARM_DRIVER_MPC Driver_QSPI_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = QSPI_MPC_Initialize,
+ .Uninitialize = QSPI_MPC_Uninitialize,
+ .GetBlockSize = QSPI_MPC_GetBlockSize,
+ .GetCtrlConfig = QSPI_MPC_GetCtrlConfig,
+ .SetCtrlConfig = QSPI_MPC_SetCtrlConfig,
+ .ConfigRegion = QSPI_MPC_ConfigRegion,
+ .GetRegionConfig = QSPI_MPC_GetRegionConfig,
+ .EnableInterrupt = QSPI_MPC_EnableInterrupt,
+ .DisableInterrupt = QSPI_MPC_DisableInterrupt,
+ .ClearInterrupt = QSPI_MPC_ClearInterrupt,
+ .InterruptState = QSPI_MPC_InterruptState,
+ .LockDown = QSPI_MPC_LockDown,
+};
+#endif /* RTE_QSPI_MPC */
+
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c
new file mode 100755
index 0000000..04587ef
--- /dev/null
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_PPC.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_PPC.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+/* Driver version */
+#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_PPC_API_VERSION,
+ ARM_PPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+#if (RTE_AHB_PPC0)
+/* AHB PPC0 Driver wrapper functions */
+static int32_t AHB_PPC0_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPC0_DEV_S, AHB_PPC0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPC0_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPC0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPC0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPC0_DEV_S, periph);
+}
+
+static uint32_t AHB_PPC0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPC0_DEV_S, periph);
+}
+
+static int32_t AHB_PPC0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPC0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPC0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPC0_DEV_S);
+}
+
+static void AHB_PPC0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPC0_DEV_S);
+}
+
+static uint32_t AHB_PPC0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPC0_DEV_S);
+}
+
+/* AHB PPC0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPC0;
+ARM_DRIVER_PPC Driver_AHB_PPC0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPC0_Initialize,
+ .Uninitialize = AHB_PPC0_Uninitialize,
+ .ConfigPeriph = AHB_PPC0_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPC0_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPC0_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPC0_EnableInterrupt,
+ .DisableInterrupt = AHB_PPC0_DisableInterrupt,
+ .ClearInterrupt = AHB_PPC0_ClearInterrupt,
+ .InterruptState = AHB_PPC0_InterruptState
+};
+#endif /* RTE_AHB_PPC0 */
+
+#if (RTE_AHB_PPCEXP0)
+/* AHB PPCEXP0 Driver wrapper functions */
+static int32_t AHB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP0_DEV_S, AHB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP0_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP0_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP0_DEV_S);
+}
+
+static void AHB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP0_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP0_DEV_S);
+}
+
+/* AHB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP0_Initialize,
+ .Uninitialize = AHB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP0_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP0_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP0 */
+
+#if (RTE_AHB_PPCEXP1)
+/* AHB PPCEXP1 Driver wrapper functions */
+static int32_t AHB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP1_DEV_S, AHB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP1_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP1_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP1_DEV_S);
+}
+
+static void AHB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP1_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP1_DEV_S);
+}
+
+/* AHB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP1;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP1_Initialize,
+ .Uninitialize = AHB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP1_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP1_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP1 */
+
+#if (RTE_AHB_PPCEXP2)
+/* AHB PPCEXP2 Driver wrapper functions */
+static int32_t AHB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP2_DEV_S, AHB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP2_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP2_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP2_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP2_DEV_S);
+}
+
+static void AHB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP2_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP2_DEV_S);
+}
+
+/* AHB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP2;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP2_Initialize,
+ .Uninitialize = AHB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP2_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP2_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP2 */
+
+#if (RTE_AHB_PPCEXP3)
+/* AHB PPCEXP3 Driver wrapper functions */
+static int32_t AHB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP3_DEV_S, AHB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP3_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP3_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP3_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP3_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP3_DEV_S);
+}
+
+static void AHB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP3_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP3_DEV_S);
+}
+
+/* AHB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP3;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP3_Initialize,
+ .Uninitialize = AHB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP3_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP3_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP3 */
+
+#if (RTE_APB_PPC0)
+/* APB PPC0 Driver wrapper functions */
+static int32_t APB_PPC0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC0_DEV_S, APB_PPC0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC0_DEV_S, periph);
+}
+
+static uint32_t APB_PPC0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC0_DEV_S, periph);
+}
+
+static int32_t APB_PPC0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC0_DEV_S);
+}
+
+static void APB_PPC0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC0_DEV_S);
+}
+
+static uint32_t APB_PPC0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC0_DEV_S);
+}
+
+/* APB PPC0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC0;
+ARM_DRIVER_PPC Driver_APB_PPC0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC0_Initialize,
+ .Uninitialize = APB_PPC0_Uninitialize,
+ .ConfigPeriph = APB_PPC0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC0_EnableInterrupt,
+ .DisableInterrupt = APB_PPC0_DisableInterrupt,
+ .ClearInterrupt = APB_PPC0_ClearInterrupt,
+ .InterruptState = APB_PPC0_InterruptState
+};
+#endif /* RTE_APB_PPC0 */
+
+#if (RTE_APB_PPC1)
+/* APB PPC1 Driver wrapper functions */
+static int32_t APB_PPC1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC1_DEV_S, APB_PPC1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC1_DEV_S, periph);
+}
+
+static uint32_t APB_PPC1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC1_DEV_S, periph);
+}
+static int32_t APB_PPC1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC1_DEV_S);
+}
+
+static void APB_PPC1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC1_DEV_S);
+}
+
+static uint32_t APB_PPC1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC1_DEV_S);
+}
+
+/* APB PPC1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC1;
+ARM_DRIVER_PPC Driver_APB_PPC1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC1_Initialize,
+ .Uninitialize = APB_PPC1_Uninitialize,
+ .ConfigPeriph = APB_PPC1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC1_EnableInterrupt,
+ .DisableInterrupt = APB_PPC1_DisableInterrupt,
+ .ClearInterrupt = APB_PPC1_ClearInterrupt,
+ .InterruptState = APB_PPC1_InterruptState
+};
+#endif /* RTE_APB_PPC1 */
+
+#if (RTE_APB_PPCEXP0)
+/* APB PPCEXP0 Driver wrapper functions */
+static int32_t APB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP0_DEV_S, APB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP0_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP0_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP0_DEV_S);
+}
+
+static void APB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP0_DEV_S);
+}
+
+static uint32_t APB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP0_DEV_S);
+}
+
+/* APB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP0;
+ARM_DRIVER_PPC Driver_APB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP0_Initialize,
+ .Uninitialize = APB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP0_ClearInterrupt,
+ .InterruptState = APB_PPCEXP0_InterruptState
+};
+#endif /* RTE_APB_PPCEXP0 */
+
+#if (RTE_APB_PPCEXP1)
+/* APB PPCEXP1 Driver wrapper functions */
+static int32_t APB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP1_DEV_S, APB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP1_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP1_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP1_DEV_S);
+}
+
+static void APB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP1_DEV_S);
+}
+
+static uint32_t APB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP1_DEV_S);
+}
+
+/* APB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP1;
+ARM_DRIVER_PPC Driver_APB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP1_Initialize,
+ .Uninitialize = APB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP1_ClearInterrupt,
+ .InterruptState = APB_PPCEXP1_InterruptState
+};
+#endif /* RTE_APB_PPCEXP1 */
+
+#if (RTE_APB_PPCEXP2)
+/* APB PPCEXP2 Driver wrapper functions */
+static int32_t APB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP2_DEV_S, APB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP2_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP2_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP2_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP2_DEV_S);
+}
+
+static void APB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP2_DEV_S);
+}
+
+static uint32_t APB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP2_DEV_S);
+}
+
+/* APB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP2;
+ARM_DRIVER_PPC Driver_APB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP2_Initialize,
+ .Uninitialize = APB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP2_ClearInterrupt,
+ .InterruptState = APB_PPCEXP2_InterruptState
+};
+#endif /* RTE_APB_PPCEXP2 */
+
+#if (RTE_APB_PPCEXP3)
+/* APB PPCEXP3 Driver wrapper functions */
+static int32_t APB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP3_DEV_S, APB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP3_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP3_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP3_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP3_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP3_DEV_S);
+}
+
+static void APB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP3_DEV_S);
+}
+
+static uint32_t APB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP3_DEV_S);
+}
+
+/* APB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP3;
+ARM_DRIVER_PPC Driver_APB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP3_Initialize,
+ .Uninitialize = APB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP3_ClearInterrupt,
+ .InterruptState = APB_PPCEXP3_InterruptState
+};
+#endif /* RTE_APB_PPCEXP3 */
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c
new file mode 100755
index 0000000..90a25e6
--- /dev/null
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_USART.c
@@ -0,0 +1,424 @@
+/*
+ * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_USART.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) (void)arg
+#endif
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_USART_API_VERSION,
+ ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+ 1, /* supports UART (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports UART Single-wire mode */
+ 0, /* supports UART IrDA mode */
+ 0, /* supports UART Smart Card mode */
+ 0, /* Smart Card Clock generator available */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+ 0 /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+typedef struct {
+ struct uart_pl011_dev_t* dev; /* UART device structure */
+ uint32_t tx_nbr_bytes; /* Number of bytes transfered */
+ uint32_t rx_nbr_bytes; /* Number of bytes recevied */
+ ARM_USART_SignalEvent_t cb_event; /* Callback function for events */
+} UARTx_Resources;
+
+static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev)
+{
+ /* Initializes generic UART driver */
+ uart_pl011_init(uart_dev->dev, PeripheralClock);
+
+ uart_pl011_enable(uart_dev->dev);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev,
+ ARM_POWER_STATE state)
+{
+ ARG_UNUSED(uart_dev);
+
+ switch (state) {
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *data,
+ uint32_t num)
+{
+ const uint8_t* p_data = (const uint8_t*)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ /* Invalid parameters */
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous TX counter */
+ uart_dev->tx_nbr_bytes = 0;
+
+ while(uart_dev->tx_nbr_bytes != num) {
+ /* Waits until UART is ready to transmit */
+ while(!uart_pl011_is_writable(uart_dev->dev)) {};
+
+ /* As UART is ready to transmit at this point, the write function can
+ * not return any transmit error */
+ (void)uart_pl011_write(uart_dev->dev, *p_data);
+
+ uart_dev->tx_nbr_bytes++;
+ p_data++;
+ }
+
+ /* Waits until character is transmited */
+ while (!uart_pl011_is_writable(uart_dev->dev)){};
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev,
+ void *data, uint32_t num)
+{
+ uint8_t* p_data = (uint8_t*)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ // Invalid parameters
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous RX counter */
+ uart_dev->rx_nbr_bytes = 0;
+
+ while(uart_dev->rx_nbr_bytes != num) {
+ /* Waits until one character is received */
+ while (!uart_pl011_is_readable(uart_dev->dev)){};
+
+ /* As UART has received one byte, the read can not
+ * return any receive error at this point */
+ (void)uart_pl011_read(uart_dev->dev, p_data);
+
+ uart_dev->rx_nbr_bytes++;
+ p_data++;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->tx_nbr_bytes;
+}
+
+static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->rx_nbr_bytes;
+}
+
+static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control,
+ uint32_t arg)
+{
+ switch (control & ARM_USART_CONTROL_Msk) {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ if(uart_pl011_set_baudrate(uart_dev->dev, arg) !=
+ UART_PL011_ERR_NONE) {
+ return ARM_USART_ERROR_BAUDRATE;
+ }
+ break;
+ /* Unsupported command */
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Data bits */
+ if(control & ARM_USART_DATA_BITS_Msk) {
+ /* Data bit is not configurable */
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Parity */
+ if(control & ARM_USART_PARITY_Msk) {
+ /* Parity is not configurable */
+ return ARM_USART_ERROR_PARITY;
+ }
+
+ /* USART Stop bits */
+ if(control & ARM_USART_STOP_BITS_Msk) {
+ /* Stop bit is not configurable */
+ return ARM_USART_ERROR_STOP_BITS;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+#if (RTE_USART0)
+/* USART0 Driver wrapper functions */
+static UARTx_Resources USART0_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &UART0_DEV_NS,
+#else
+ .dev = &UART0_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART0_DEV.cb_event = cb_event;
+
+#if (__DOMAIN_NS == 1)
+ arm_scc_set_alt_func(&ARM_SCC_DEV_NS, GPIO_ALTFUNC_1, 1<<AHB_GPIO0_0);
+ arm_scc_set_alt_func(&ARM_SCC_DEV_NS, GPIO_ALTFUNC_1, 1<<AHB_GPIO0_1);
+#else
+ arm_scc_set_alt_func(&ARM_SCC_DEV_S, GPIO_ALTFUNC_1, 1<<AHB_GPIO0_0);
+ arm_scc_set_alt_func(&ARM_SCC_DEV_S, GPIO_ALTFUNC_1, 1<<AHB_GPIO0_1);
+#endif
+
+ return ARM_USARTx_Initialize(&USART0_DEV);
+}
+
+static int32_t ARM_USART0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART0_DEV, state);
+}
+
+static int32_t ARM_USART0_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART0_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART0_DEV);
+}
+
+static uint32_t ARM_USART0_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART0_DEV);
+}
+static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART0_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART0_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART0;
+ARM_DRIVER_USART Driver_USART0 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART0_Initialize,
+ ARM_USART0_Uninitialize,
+ ARM_USART0_PowerControl,
+ ARM_USART0_Send,
+ ARM_USART0_Receive,
+ ARM_USART0_Transfer,
+ ARM_USART0_GetTxCount,
+ ARM_USART0_GetRxCount,
+ ARM_USART0_Control,
+ ARM_USART0_GetStatus,
+ ARM_USART0_SetModemControl,
+ ARM_USART0_GetModemStatus
+};
+#endif /* RTE_USART0 */
+
+#if (RTE_USART1)
+/* USART1 Driver wrapper functions */
+static UARTx_Resources USART1_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &UART1_DEV_NS,
+#else
+ .dev = &UART1_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART1_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART1_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART1_DEV);
+}
+
+static int32_t ARM_USART1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART1_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART1_DEV, state);
+}
+
+static int32_t ARM_USART1_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART1_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART1_DEV);
+}
+
+static uint32_t ARM_USART1_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART1_DEV);
+}
+static int32_t ARM_USART1_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART1_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART1_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART1_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART1_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART1;
+ARM_DRIVER_USART Driver_USART1 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART1_Initialize,
+ ARM_USART1_Uninitialize,
+ ARM_USART1_PowerControl,
+ ARM_USART1_Send,
+ ARM_USART1_Receive,
+ ARM_USART1_Transfer,
+ ARM_USART1_GetTxCount,
+ ARM_USART1_GetRxCount,
+ ARM_USART1_Control,
+ ARM_USART1_GetStatus,
+ ARM_USART1_SetModemControl,
+ ARM_USART1_GetModemStatus
+};
+#endif /* RTE_USART1 */
diff --git a/platform/ext/target/musca_a/Device/Config/device_cfg.h b/platform/ext/target/musca_a/Device/Config/device_cfg.h
new file mode 100755
index 0000000..c12bcef
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Config/device_cfg.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief
+ * This is the default device configuration file with all peripherals
+ * defined and configured to be use via the non-secure base address.
+ * This file is an example of how to define your own configuration file
+ * with the peripherals required for your application.
+ */
+
+/* ARM SCC */
+#define ARM_SCC_S
+#define ARM_SCC_NS
+
+/* ARM GPIO */
+#define ARM_GPIO0_S
+#define ARM_GPIO0_NS
+
+/* ARM Memory Protection Controller (MPC) SIE 200 */
+#define MPC_ISRAM0_S
+#define MPC_ISRAM1_S
+#define MPC_ISRAM2_S
+#define MPC_ISRAM3_S
+#define MPC_CODE_SRAM1_S
+#define MPC_CODE_SRAM1_NS
+#define MPC_QSPI_S
+#define MPC_QSPI_NS
+
+/* ARM Peripheral Protection Controllers (PPC) */
+#define AHB_PPC0_S
+#define AHB_PPCEXP0_S
+#define AHB_PPCEXP1_S
+#define AHB_PPCEXP2_S
+#define AHB_PPCEXP3_S
+#define APB_PPC0_S
+#define APB_PPC1_S
+#define APB_PPCEXP0_S
+#define APB_PPCEXP1_S
+#define APB_PPCEXP2_S
+#define APB_PPCEXP3_S
+
+/*ARM UART Controller PL011*/
+#define UART0_PL011_S
+#define UART0_PL011_NS
+#define UART1_PL011_S
+#define UART1_PL011_NS
+
+/* CMSDK Timers */
+#define CMSDK_TIMER0_S
+#define CMSDK_TIMER0_NS
+#define CMSDK_TIMER1_S
+#define CMSDK_TIMER1_NS
+
+#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/cmsis.h b/platform/ext/target/musca_a/Device/Include/cmsis.h
new file mode 100644
index 0000000..b23b8a1
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/cmsis.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MUSCA_CMSIS_H__
+#define __MUSCA_CMSIS_H__
+
+/* CMSIS wrapper for Musca board */
+
+#include "system_cmsdk_musca.h"
+#include "platform_regs.h" /* Platform registers */
+#include "platform_retarget.h" /* Peripherals base addresses */
+
+#endif /*__MUSCA_CMSIS_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/cmsis_cpu.h b/platform/ext/target/musca_a/Device/Include/cmsis_cpu.h
new file mode 100755
index 0000000..b65df25
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/cmsis_cpu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_CPU_H__
+#define __CMSIS_CPU_H__
+
+#include "system_core_musca.h"
+#include "core_cm33.h"
+
+#endif /* __CMSIS_CPU_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_regs.h b/platform/ext/target/musca_a/Device/Include/platform_regs.h
new file mode 100644
index 0000000..219f38c
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/platform_regs.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_MUSCA_REGS_H__
+#define __ARM_LTD_MUSCA_REGS_H__
+
+#include <stdint.h>
+#include "platform_retarget.h"
+
+/* sysinfo memory mapped register access structure */
+struct sysinfo_t {
+ volatile uint32_t sysversion; /* (R/ ) System version */
+ volatile uint32_t sysconfig; /* (R/ ) System configuration */
+ volatile uint32_t reserved0[1008];
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved1[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* sysctrl memory mapped register access structure */
+struct sysctrl_t {
+ volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
+ * Status Register*/
+ volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
+ * Set Register */
+ volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
+ * Clear Register */
+ volatile uint32_t scsecctrl; /* (R/W) System Control Security
+ * Control Register */
+ volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
+ * Configuration Register */
+ volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
+ * Configuration Register */
+ volatile uint32_t clockforce; /* (R/W) Clock Forces */
+ volatile uint32_t reserved0[57];
+ volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
+ volatile uint32_t resetmask; /* (R/W) Reset MASK */
+ volatile uint32_t swreset; /* ( /W) Software Reset */
+ volatile uint32_t gretreg; /* (R/W) General Purpose Retention
+ * Register */
+ volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector
+ * Register For CPU 0 */
+ volatile uint32_t initsvtor1; /* (R/W) Initial Secure Reset
+ * Vector Register For CPU 1*/
+ volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control
+ * after reset */
+ volatile uint32_t reserved1;
+ volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and
+ * Acknowledgement */
+ volatile uint32_t ewctrl; /* (R/W) External Wakeup Control */
+ volatile uint32_t reserved2[54];
+ volatile uint32_t pdcm_pd_sys_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SYS
+ * Power Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_cpu0core_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_CPU0CORE
+ * Power Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_cpu1core_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_CPU1CORE
+ * Power Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram0_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM0 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram1_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM1 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram2_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM2 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_sram3_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM3 Power
+ * Domain Sensitivity.*/
+ volatile uint32_t reserved3[5];
+ volatile uint32_t pdcm_pd_cc_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_CC
+ * Power Domain Sensitivity.*/
+ volatile uint32_t pdcm_pd_exp0_out_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_EXP0 Sensitivity. */
+ volatile uint32_t pdcm_pd_exp1_out_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_EXP1 Sensitivity. */
+ volatile uint32_t pdcm_pd_exp2_out_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_EXP2 Sensitivity. */
+ volatile uint32_t pdcm_pd_exp3_out_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_EXP3 Sensitivity. */
+ volatile uint32_t reserved4[864];
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved5[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* Secure Privilege Control */
+#define CMSDK_SPCTRL ((struct spctrl_def*)MUSCA_SPCTRL_S_BASE)
+
+/* SPCTRL memory mapped register access structure */
+struct spctrl_def {
+ volatile uint32_t spcsecctrl; /* (R/W) Secure Configuration Control
+ Register */
+ volatile uint32_t buswait; /* (R/W) Bus Access wait control after reset.*/
+ volatile uint32_t reserved[2];
+ volatile uint32_t secrespcfg; /* (R/W) Security Violation Response
+ * Configuration register.*/
+ volatile uint32_t nsccfg; /* (R/W) Non Secure Callable Configuration
+ * for IDAU. */
+ volatile uint32_t reserved2;
+ volatile uint32_t secmpcintstat; /* (R/W) Secure MPC Interrupt Status. */
+ volatile uint32_t secppcintstat; /* (R/W) Secure PPC Interrupt Status. */
+ volatile uint32_t secppcintclr; /* (R/W) Secure PPC Interrupt Clear. */
+ volatile uint32_t secppcinten; /* (R/W) Secure PPC Interrupt Enable. */
+ volatile uint32_t reserved3;
+ volatile uint32_t secmscintstat; /* (R/W) Secure MSC Interrupt Status. */
+ volatile uint32_t secmscintclr; /* (R/W) Secure MSC Interrupt Clear. */
+ volatile uint32_t secmscinten; /* (R/W) Secure MSC Interrupt Enable. */
+ volatile uint32_t reserved4;
+ volatile uint32_t brgintstat; /* (R/W) Bridge Buffer Error Interrupt Status. */
+ volatile uint32_t brgintclr; /* (R/W) Bridge Buffer Error Interrupt Clear. */
+ volatile uint32_t brginten; /* (R/W) Bridge Buffer Error Interrupt Enable. */
+ volatile uint32_t reserved5;
+ volatile uint32_t ahbnsppc0; /* (R/W) Non-Secure Access AHB slave Peripheral
+ * Protection Control #0 */
+ volatile uint32_t reserved6[3];
+ volatile uint32_t ahbnsppcexp0; /* (R/W) Expansion 0 Non_Secure Access AHB slave
+ * Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp1; /* (R/W) Expansion 1 Non_Secure Access AHB slave
+ * Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp2; /* (R/W) Expansion 2 Non_Secure Access AHB slave
+ * Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp3; /* (R/W) Expansion 3 Non_Secure Access AHB slave
+ * Peripheral Protection Control */
+ volatile uint32_t apbnsppc0; /* (R/W) Non-Secure Access APB slave Peripheral
+ * Protection Control #0 */
+ volatile uint32_t apbnsppc1; /* (R/W) Non-Secure Access APB slave Peripheral
+ * Protection Control #1 */
+ volatile uint32_t reserved7[2];
+ volatile uint32_t apbnsppcexp0; /* (R/W) Expansion 0 Non_Secure Access APB slave
+ * Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp1; /* (R/W) Expansion 1 Non_Secure Access APB slave
+ * Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp2; /* (R/W) Expansion 2 Non_Secure Access APB slave
+ * Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp3; /* (R/W) Expansion 3 Non_Secure Access APB slave
+ * Peripheral Protection Control */
+ volatile uint32_t ahbspppc0; /* (R/W) Secure Unprivileged Access AHB slave
+ * Peripheral Protection Control #0. */
+ volatile uint32_t reserved8[3];
+ volatile uint32_t ahbspppcexp0; /* (R/W) Expansion 0 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control. */
+ volatile uint32_t ahbspppcexp1; /* (R/W) Expansion 1 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control. */
+ volatile uint32_t ahbspppcexp2; /* (R/W) Expansion 2 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control. */
+ volatile uint32_t ahbspppcexp3; /* (R/W) Expansion 3 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control. */
+ volatile uint32_t apbspppc0; /* (R/W) Secure Unprivileged Access APB slave
+ * Peripheral Protection Control #0 */
+ volatile uint32_t apbspppc1; /* (R/W) Secure Unprivileged Access APB slave
+ * Peripheral Protection Control #1 */
+ volatile uint32_t reserved9[2];
+ volatile uint32_t apbspppcexp0; /* (R/W) Expansion 0 Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t apbspppcexp1; /* (R/W) Expansion 1 Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t apbspppcexp2; /* (R/W) Expansion 2 Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t apbspppcexp3; /* (R/W) Expansion 3 Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t nsmscexp; /* (R/W) Expansion MSC Non-Secure Configuration */
+ volatile uint32_t reserved10[959];
+ volatile uint32_t pid4; /* (R/W) Peripheral ID 4 */
+ volatile uint32_t pid5; /* (R/W) Peripheral ID 5 */
+ volatile uint32_t pid6; /* (R/W) Peripheral ID 6 */
+ volatile uint32_t pid7; /* (R/W) Peripheral ID 7 */
+ volatile uint32_t pid0; /* (R/W) Peripheral ID 0 */
+ volatile uint32_t pid1; /* (R/W) Peripheral ID 1 */
+ volatile uint32_t pid2; /* (R/W) Peripheral ID 2 */
+ volatile uint32_t pid3; /* (R/W) Peripheral ID 3 */
+ volatile uint32_t cid0; /* (R/W) Component ID 0 */
+ volatile uint32_t cid1; /* (R/W) Component ID 1 */
+ volatile uint32_t cid2; /* (R/W) Component ID 2 */
+ volatile uint32_t cid3; /* (R/W) Component ID 3 */
+};
+
+/* Non-Secure Privilege Control */
+#define CMSDK_NSPCTRL ((struct nspctrl_def*)MUSCA_NSPCTRL_NS_BASE)
+
+/* NSPCTRL memory mapped register access structure */
+struct nspctrl_def {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0; /* (R/W) Non-Secure Unprivileged Access AHB slave
+ * Peripheral Protection Control #0 */
+ volatile uint32_t reserved3[3];
+ volatile uint32_t ahbnspppcexp0; /* (R/W) Expansion 0 Non-Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control */
+ volatile uint32_t ahbnspppcexp1; /* (R/W) Expansion 1 Non-Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control */
+ volatile uint32_t ahbnspppcexp2; /* (R/W) Expansion 2 Non-Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control */
+ volatile uint32_t ahbnspppcexp3; /* (R/W) Expansion 3 Non-Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control */
+ volatile uint32_t apbnspppc0; /* (R/W) Non-Secure Unprivileged Access APB slave
+ * Peripheral Protection Control #0 */
+ volatile uint32_t apbnspppc1; /* (R/W) Non-Secure Unprivileged Access APB slave
+ * Peripheral Protection Control #1 */
+ volatile uint32_t reserved4[2];
+ volatile uint32_t apbnspppcexp0; /* (R/W) Expansion 0 Non-Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t apbnspppcexp1; /* (R/W) Expansion 1 Non-Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t apbnspppcexp2; /* (R/W) Expansion 2 Non-Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t apbnspppcexp3; /* (R/W) Expansion 3 Non-Secure Unprivileged Access
+ * APB slave Peripheral Protection Control */
+ volatile uint32_t reserved5[960];
+ volatile uint32_t pidr4; /* (R/W) Peripheral ID 3 */
+ volatile uint32_t reserved7;
+ volatile uint32_t reserved8;
+ volatile uint32_t reserved9;
+ volatile uint32_t pidr0; /* (R/W) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/W) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/W) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/W) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/W) Component ID 0 */
+ volatile uint32_t cidr2; /* (R/W) Component ID 1 */
+ volatile uint32_t cidr1; /* (R/W) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/W) Component ID 3 */
+};
+
+#endif /* __ARM_LTD_MUSCA_REGS_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget.h b/platform/ext/target/musca_a/Device/Include/platform_retarget.h
new file mode 100755
index 0000000..2580aae
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/platform_retarget.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget.h
+ * \brief This file defines all the peripheral base addresses for Musca platform.
+ */
+
+#ifndef __ARM_LTD_MUSCA_RETARGET_H__
+#define __ARM_LTD_MUSCA_RETARGET_H__
+
+#include "platform_regs.h" /* Platform registers */
+#include "platform_retarget_pins.h" /* Platform pin names */
+#include "system_cmsdk_musca.h"
+
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
+#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
+#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
+#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
+
+#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000
+#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF
+#define MPC_ISRAM1_RANGE_BASE_S 0x30008000
+#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF
+
+#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000
+#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF
+#define MPC_ISRAM2_RANGE_BASE_S 0x30010000
+#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF
+
+#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000
+#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF
+#define MPC_ISRAM3_RANGE_BASE_S 0x30018000
+#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF
+
+/* Code SRAM memory */
+#define MPC_CODE_SRAM1_RANGE_BASE_NS (0x00000000)
+#define MPC_CODE_SRAM1_RANGE_LIMIT_NS (0x00200000)
+#define MPC_CODE_SRAM1_RANGE_BASE_S (0x10000000)
+#define MPC_CODE_SRAM1_RANGE_LIMIT_S (0x10200000)
+
+/* QSPI Flash memory */
+#define MPC_QSPI_RANGE_BASE_NS (0x00200000)
+#define MPC_QSPI_RANGE_LIMIT_NS (0x00240000)
+#define MPC_QSPI_RANGE_BASE_S (0x10200000)
+#define MPC_QSPI_RANGE_LIMIT_S (0x10240000)
+
+#endif /* __ARM_LTD_MUSCA_RETARGET_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget_dev.h b/platform/ext/target/musca_a/Device/Include/platform_retarget_dev.h
new file mode 100755
index 0000000..d645e4c
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/platform_retarget_dev.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_dev.h
+ * \brief The structure definitions in this file are exported based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#ifndef __ARM_LTD_MUSCA_RETARGET_DEV_H__
+#define __ARM_LTD_MUSCA_RETARGET_DEV_H__
+
+#include "device_cfg.h"
+
+/* ======= Includes generic driver headers ======= */
+#include "mpc_sie200_drv.h"
+#include "ppc_sse200_drv.h"
+#include "arm_gpio_drv.h"
+#include "timer_cmsdk.h"
+#include "uart_pl011_drv.h"
+
+/* ======= Peripheral configuration structure declarations ======= */
+/* ARM SCC driver structures */
+#ifdef ARM_SCC_S
+extern struct arm_scc_dev_t ARM_SCC_DEV_S;
+#endif
+#ifdef ARM_SCC_NS
+extern struct arm_scc_dev_t ARM_SCC_DEV_NS;
+#endif
+
+/* ARM GPIO driver structures */
+#ifdef ARM_GPIO0_S
+extern struct arm_gpio_dev_t ARM_GPIO0_DEV_S;
+#endif
+#ifdef ARM_GPIO0_NS
+extern struct arm_gpio_dev_t ARM_GPIO0_DEV_NS;
+#endif
+
+/* ARM MPC SIE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+extern struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S;
+#endif
+#ifdef MPC_ISRAM1_S
+extern struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S;
+#endif
+#ifdef MPC_ISRAM2_S
+extern struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S;
+#endif
+#ifdef MPC_ISRAM3_S
+extern struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S;
+#endif
+#ifdef MPC_CODE_SRAM1_S
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_S;
+#endif
+#ifdef MPC_CODE_SRAM1_NS
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_NS;
+#endif
+#ifdef MPC_QSPI_S
+extern struct mpc_sie200_dev_t MPC_QSPI_DEV_S;
+#endif
+#ifdef MPC_QSPI_NS
+extern struct mpc_sie200_dev_t MPC_QSPI_DEV_NS;
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+extern struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_S;
+#endif
+#ifdef CMSDK_TIMER0_NS
+extern struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_NS;
+#endif
+
+#ifdef CMSDK_TIMER1_S
+extern struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_S;
+#endif
+#ifdef CMSDK_TIMER1_NS
+extern struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_NS;
+#endif
+
+/* ARM UART PL011 driver structures */
+#ifdef UART0_PL011_S
+extern struct uart_pl011_dev_t UART0_DEV_S;
+#endif
+#ifdef UART0_PL011_NS
+extern struct uart_pl011_dev_t UART0_DEV_NS;
+#endif
+#ifdef UART1_PL011_S
+extern struct uart_pl011_dev_t UART1_DEV_S;
+#endif
+#ifdef UART1_PL011_NS
+extern struct uart_pl011_dev_t UART1_DEV_NS;
+#endif
+
+/* ARM PPC driver structures */
+#ifdef AHB_PPC0_S
+extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP0_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP1_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP2_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP3_S
+extern struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S;
+#endif
+
+#ifdef APB_PPC0_S
+extern struct ppc_sse200_dev_t APB_PPC0_DEV_S;
+#endif
+
+#ifdef APB_PPC1_S
+extern struct ppc_sse200_dev_t APB_PPC1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP0_S
+extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP1_S
+extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP2_S
+extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP3_S
+extern struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S;
+#endif
+
+#endif /* __ARM_LTD_MUSCA_RETARGET_DEV_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/platform_retarget_pins.h b/platform/ext/target/musca_a/Device/Include/platform_retarget_pins.h
new file mode 100644
index 0000000..fed5d66
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/platform_retarget_pins.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __ARM_LTD_MUSCA_RETARGET_PINS_H__
+#define __ARM_LTD_MUSCA_RETARGET_PINS_H__
+
+/* AHB GPIO pin names */
+enum arm_gpio_pin_name_t {
+ AHB_GPIO0_0 = 0U,
+ AHB_GPIO0_1,
+ AHB_GPIO0_2,
+ AHB_GPIO0_3,
+ AHB_GPIO0_4,
+ AHB_GPIO0_5,
+ AHB_GPIO0_6,
+ AHB_GPIO0_7,
+ AHB_GPIO0_8,
+ AHB_GPIO0_9,
+ AHB_GPIO0_10,
+ AHB_GPIO0_11,
+ AHB_GPIO0_12,
+ AHB_GPIO0_13,
+ AHB_GPIO0_14,
+ AHB_GPIO0_15,
+};
+
+#endif /* __ARM_LTD_MUSCA_RETARGET_PINS_H__ */
diff --git a/platform/ext/target/musca_a/Device/Include/system_cmsdk_musca.h b/platform/ext/target/musca_a/Device/Include/system_cmsdk_musca.h
new file mode 100755
index 0000000..1b8c529
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/system_cmsdk_musca.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h
+ */
+
+#ifndef SYSTEM_CMSDK_MUSCA_H
+#define SYSTEM_CMSDK_MUSCA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum IRQn
+{
+/* =========================================== Core Specific Interrupt Numbers ============================================= */
+ NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* -13 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* -5 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* -2 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* -1 System Tick Interrupt */
+
+/* ======================================== Musca Specific SSE-200 Interrupt Numbers ====================================== */
+ NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request Interrupt */
+ NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
+ S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
+ TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */
+ TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */
+ DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */
+ MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */
+ MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */
+ CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */
+ MPC_IRQn = 9, /* Secure Combined MPC Interrupt */
+ PPC_IRQn = 10, /* Secure Combined PPC Interrupt */
+ S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */
+ S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined Interrupt */
+ I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation Interrupt */
+ /* Reserved = 14, Reserved */
+ SYS_PPU_IRQn = 15, /* System PPU Interrupt */
+ CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */
+ CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */
+ CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */
+ CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */
+ CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */
+ /* Reserved = 21, Reserved */
+ RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */
+ RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */
+ RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */
+ RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */
+ DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */
+ /* Reserved = 27, Reserved */
+ CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */
+ CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */
+ /* Reserved = 30, Reserved */
+ /* Reserved = 31, Reserved */
+/* ========================================== Musca Specific Expansion Interrupt Numbers =================================== */
+ /* None = 32, Not used. Tied to 0 */
+ GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */
+ I2C0_IRQn = 34, /* I2C0 Interrupt */
+ I2C1_IRQn = 35, /* I2C1 Interrupt */
+ I2S_IRQn = 36, /* I2S Interrupt */
+ SPI_IRQn = 37, /* SPI Interrupt */
+ QSPI_IRQn = 38, /* QSPI Interrupt */
+ UARTRX0_IRQn = 39, /* UART0 receive FIFO interrupt */
+ UARTTX0_IRQn = 40, /* UART0 transmit FIFO interrupt */
+ UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */
+ UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */
+ UART0_Error_IRQn = 43, /* UART0 error interrupt */
+ UART0_IRQn = 44, /* UART0 interrupt */
+ UARTRX1_IRQn = 45, /* UART1 receive FIFO interrupt */
+ UARTTX1_IRQn = 46, /* UART1 transmit FIFO interrupt */
+ UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */
+ UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */
+ UART1_Error_IRQn = 49, /* UART1 error interrupt */
+ UART1_IRQn = 50, /* UART1 interrupt */
+ GPIO_0_IRQn = 51, /* GPIO 0 interrupt */
+ GPIO_1_IRQn = 52, /* GPIO 1 interrupt */
+ GPIO_2_IRQn = 53, /* GPIO 2 interrupt */
+ GPIO_3_IRQn = 54, /* GPIO 3 interrupt */
+ GPIO_4_IRQn = 55, /* GPIO 4 interrupt */
+ GPIO_5_IRQn = 56, /* GPIO 5 interrupt */
+ GPIO_6_IRQn = 57, /* GPIO 6 interrupt */
+ GPIO_7_IRQn = 58, /* GPIO 7 interrupt */
+ GPIO_8_IRQn = 59, /* GPIO 8 interrupt */
+ GPIO_9_IRQn = 60, /* GPIO 9 interrupt */
+ GPIO_10_IRQn = 61, /* GPIO 10 interrupt */
+ GPIO_11_IRQn = 62, /* GPIO 11 interrupt */
+ GPIO_12_IRQn = 63, /* GPIO 12 interrupt */
+ GPIO_13_IRQn = 64, /* GPIO 13 interrupt */
+ GPIO_14_IRQn = 65, /* GPIO 14 interrupt */
+ GPIO_15_IRQn = 66, /* GPIO 15 interrupt */
+ Combined_IRQn = 67, /* Combined interrupt */
+ PVT_IRQn = 68, /* PVT sensor interrupt */
+ /* Reserved = 69, Reserved */
+ PWM_0_IRQn = 70, /* PWM0 interrupt */
+ RTC_IRQn = 71, /* RTC interrupt */
+ GpTimer0_IRQn = 72, /* General Purpose Timer0 Interrupt */
+ GpTimer1_IRQn = 73, /* General Purpose Timer1 Interrupt */
+ PWM_1_IRQn = 74, /* PWM1 interrupt */
+ PWM_2_IRQn = 75, /* PWM2 interrupt */
+ IOMUX_IRQn = 76, /* IOMUX interrupt */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+#include "system_core_musca.h"
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+
+#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
+#include "system_musca.h" /*!< Musca System */
+
+
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+/* Non-Secure Peripheral and SRAM base address */
+#define MUSCA_CODE_SRAM_NS_BASE (0x00000000UL) /*!< (Non-Secure Code SRAM ) Base Address */
+#define MUSCA_QSPI_FLASH_NS_BASE (0x00200000UL) /*!< (Non-Secure QSPI FLASH ) Base Address */
+#define MUSCA_OTP_NS_BASE (0x0E000000UL) /*!< (Non-Secure OTP ) Base Address */
+#define MUSCA_SRAM_NS_BASE (0x20000000UL) /*!< (Non-Secure Internal SRAM ) Base Address */
+#define MUSCA_BASE_ELEMENT_NS_BASE (0x40000000UL) /*!< (Non-Secure Base Peripherals ) Base Address */
+#define MUSCA_CMSDK_TIMER0_NS_BASE (0x40000000UL) /*!< (Non-Secure CMSDK Timer0 ) Base Address */
+#define MUSCA_CMSDK_TIMER1_NS_BASE (0x40001000UL) /*!< (Non-Secure CMSDK Timer1 ) Base Address */
+#define MUSCA_CMSDK_DUALTIMER_NS_BASE (0x40002000UL) /*!< (Non-Secure CMSDK Dual Timer ) Base Address */
+#define MUSCA_MHU0_NS_BASE (0x40003000UL) /*!< (Non-Secure MHU0 ) Base Address */
+#define MUSCA_MHU1_NS_BASE (0x40004000UL) /*!< (Non-Secure MHU1 ) Base Address */
+#define MUSCA_CPU_ELEMENT_NS_BASE (0x40010000UL) /*!< (Non-Secure CPU Peripherals ) Base Address */
+#define MUSCA_SYSTEM_INFO_NS_BASE (0x40020000UL) /*!< (Non-Secure System Info ) Base Address */
+#define MUSCA_CMSDK_S32KTIMER_NS_BASE (0x4002F000UL) /*!< (Non-Secure CMSDK S32K Timer ) Base Address */
+#define MUSCA_NSPCTRL_NS_BASE (0x40080000UL) /*!< (Non-Secure Privilege Ctrl Blk) Base Address */
+#define MUSCA_CMSDK_WATCHDOG_NS_BASE (0x40081000UL) /*!< (Non-Secure CMSDK Watchdog ) Base Address */
+#define MUSCA_UART0_NS_BASE (0x40101000UL) /*!< (Non-Secure UART0 ) Base Address */
+#define MUSCA_UART1_NS_BASE (0x40102000UL) /*!< (Non-Secure UART1 ) Base Address */
+#define MUSCA_SPI0_NS_BASE (0x40103000UL) /*!< (Non-Secure SPI0 ) Base Address */
+#define MUSCA_I2C0_NS_BASE (0x40104000UL) /*!< (Non-Secure I2C0 ) Base Address */
+#define MUSCA_I2C1_NS_BASE (0x40105000UL) /*!< (Non-Secure I2C1 ) Base Address */
+#define MUSCA_I2S_NS_BASE (0x40106000UL) /*!< (Non-Secure I2S ) Base Address */
+#define MUSCA_PWM0_NS_BASE (0x40107000UL) /*!< (Non-Secure PWM0 ) Base Address */
+#define MUSCA_RTC_NS_BASE (0x40108000UL) /*!< (Non-Secure RTC ) Base Address */
+#define MUSCA_PVT_NS_BASE (0x40109000UL) /*!< (Non-Secure PVT sensors ) Base Address */
+#define MUSCA_QSPI_REG_NS_BASE (0x4010A000UL) /*!< (Non-Secure QSPI registers ) Base Address */
+#define MUSCA_TIMER_NS_BASE (0x4010B000UL) /*!< (Non-Secure Timer ) Base Address */
+#define MUSCA_SCC_NS_BASE (0x4010C000UL) /*!< (Non-Secure SCC ) Base Address */
+#define MUSCA_PWM1_NS_BASE (0x4010E000UL) /*!< (Non-Secure PWM1 ) Base Address */
+#define MUSCA_PWM2_NS_BASE (0x4010F000UL) /*!< (Non-Secure PWM2 ) Base Address */
+#define MUSCA_GPIO_NS_BASE (0x40110000UL) /*!< (Non-Secure GPIO ) Base Address */
+#define MUSCA_QSPI_MPC_NS_BASE (0x40120000UL) /*!< (Non-Secure QSPI MPC ) Base Address */
+#define MUSCA_CODE_SRAM_MPC_NS_BASE (0x40130000UL) /*!< (Non-Secure Code SRAM MPC ) Base Address */
+#define MUSCA_DEFAULT_SLAVE_NS_BASE (0x60000000UL) /*!< (Non-Secure Unused AHB ) Base Address */
+/* Secure Peripheral and SRAM base address */
+#define MUSCA_CODE_SRAM_S_BASE (0x10000000UL) /*!< (Secure Code SRAM ) Base Address */
+#define MUSCA_QSPI_FLASH_S_BASE (0x10200000UL) /*!< (Secure QSPI FLASH ) Base Address */
+#define MUSCA_OTP_S_BASE (0x1E000000UL) /*!< (Secure OTP ) Base Address */
+#define MUSCA_SRAM_S_BASE (0x30000000UL) /*!< (Secure Internal SRAM ) Base Address */
+#define MUSCA_BASE_ELEMENT_S_BASE (0x50000000UL) /*!< (Secure Base Peripherals ) Base Address */
+#define MUSCA_MHU0_S_BASE (0x50003000UL) /*!< (Secure MHU0 ) Base Address */
+#define MUSCA_MHU1_S_BASE (0x50004000UL) /*!< (Secure MHU1 ) Base Address */
+#define MUSCA_CPU_ELEMENT_S_BASE (0x50010000UL) /*!< (Secure CPU Peripherals ) Base Address */
+#define MUSCA_SYSTEM_INFO_S_BASE (0x50020000UL) /*!< (Secure System Info ) Base Address */
+#define MUSCA_SYSTEM_CTRL_S_BASE (0x50021000UL) /*!< (Secure System Control ) Base Address */
+#define MUSCA_CMSDK_S32KTIMER_S_BASE (0x5002F000UL) /*!< (Secure CMSDK S32K Timer ) Base Address */
+#define MUSCA_CMSDK_TIMER0_S_BASE (0x50000000UL) /*!< (Secure CMSDK Timer0 ) Base Address */
+#define MUSCA_CMSDK_TIMER1_S_BASE (0x50001000UL) /*!< (Secure CMSDK Timer1 ) Base Address */
+#define MUSCA_CMSDK_DUALTIMER_S_BASE (0x50002000UL) /*!< (Secure CMSDK Dual Timer ) Base Address */
+#define MUSCA_SPCTRL_S_BASE (0x50080000UL) /*!< (Secure Privilege Ctrl Blk) Base Address */
+#define MUSCA_CMSDK_WATCHDOG_S_BASE (0x50081000UL) /*!< (Secure CMSDK Watchdog ) Base Address */
+#define MUSCA_MPC_SRAM0_S_BASE (0x50083000UL) /*!< (Secure MPC SRAM Bank 0 ) Base Address */
+#define MUSCA_MPC_SRAM1_S_BASE (0x50084000UL) /*!< (Secure MPC SRAM Bank 1 ) Base Address */
+#define MUSCA_MPC_SRAM2_S_BASE (0x50085000UL) /*!< (Secure MPC SRAM Bank 2 ) Base Address */
+#define MUSCA_MPC_SRAM3_S_BASE (0x50086000UL) /*!< (Secure MPC SRAM Bank 3 ) Base Address */
+#define MUSCA_UART0_S_BASE (0x50101000UL) /*!< (Secure UART0 ) Base Address */
+#define MUSCA_UART1_S_BASE (0x50102000UL) /*!< (Secure UART1 ) Base Address */
+#define MUSCA_SPI0_S_BASE (0x50103000UL) /*!< (Secure SPI0 ) Base Address */
+#define MUSCA_I2C0_S_BASE (0x50104000UL) /*!< (Secure I2C0 ) Base Address */
+#define MUSCA_I2C1_S_BASE (0x50105000UL) /*!< (Secure I2C1 ) Base Address */
+#define MUSCA_I2S_S_BASE (0x50106000UL) /*!< (Secure I2S ) Base Address */
+#define MUSCA_PWM0_S_BASE (0x50107000UL) /*!< (Secure PWM0 ) Base Address */
+#define MUSCA_RTC_S_BASE (0x50108000UL) /*!< (Secure RTC ) Base Address */
+#define MUSCA_PVT_S_BASE (0x50109000UL) /*!< (Secure PVT sensors ) Base Address */
+#define MUSCA_QSPI_REG_S_BASE (0x5010A000UL) /*!< (Secure QSPI registers ) Base Address */
+#define MUSCA_TIMER_S_BASE (0x5010B000UL) /*!< (Secure Timer ) Base Address */
+#define MUSCA_SCC_S_BASE (0x5010C000UL) /*!< (Secure SCC ) Base Address */
+#define MUSCA_PWM1_S_BASE (0x5010E000UL) /*!< (Secure PWM1 ) Base Address */
+#define MUSCA_PWM2_S_BASE (0x5010F000UL) /*!< (Secure PWM2 ) Base Address */
+#define MUSCA_GPIO_S_BASE (0x50110000UL) /*!< (Secure GPIO ) Base Address */
+#define MUSCA_QSPI_MPC_S_BASE (0x50120000UL) /*!< (Secure QSPI MPC ) Base Address */
+#define MUSCA_CODE_SRAM_MPC_S_BASE (0x50130000UL) /*!< (Secure Code SRAM MPC ) Base Address */
+#define MUSCA_DEFAULT_SLAVE_S_BASE (0x70000000UL) /*!< (Secure Unused AHB ) Base Address */
+
+#define CMSDK_SYSCTRL_BASE_S MUSCA_SYSTEM_CTRL_S_BASE /*!< Secure System Control Alias */
+
+/* PPC interrupt position mask */
+#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0)
+#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1)
+#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+#define CMSDK_AHB_PPC0_INT_POS_MASK (1UL << 16)
+#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+
+/* Non-Secure Access slave PPCs register addresses */
+#define CMSDK_SPCTRL_AHB_NS_PPC0 (MUSCA_SPCTRL_S_BASE + 0x050)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP0 (MUSCA_SPCTRL_S_BASE + 0x060)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP1 (MUSCA_SPCTRL_S_BASE + 0x064)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP2 (MUSCA_SPCTRL_S_BASE + 0x068)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP3 (MUSCA_SPCTRL_S_BASE + 0x06C)
+#define CMSDK_SPCTRL_APB_NS_PPC0 (MUSCA_SPCTRL_S_BASE + 0x070)
+#define CMSDK_SPCTRL_APB_NS_PPC1 (MUSCA_SPCTRL_S_BASE + 0x074)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP0 (MUSCA_SPCTRL_S_BASE + 0x080)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP1 (MUSCA_SPCTRL_S_BASE + 0x084)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP2 (MUSCA_SPCTRL_S_BASE + 0x088)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP3 (MUSCA_SPCTRL_S_BASE + 0x08C)
+
+/* Secure Unprivileged (SP) Access slave PPCs register addresses */
+#define CMSDK_SPCTRL_AHB_PPC0_SP (MUSCA_SPCTRL_S_BASE + 0x090)
+#define CMSDK_SPCTRL_AHB_PPCEXP0_SP (MUSCA_SPCTRL_S_BASE + 0x0A0)
+#define CMSDK_SPCTRL_AHB_PPCEXP1_SP (MUSCA_SPCTRL_S_BASE + 0x0A4)
+#define CMSDK_SPCTRL_AHB_PPCEXP2_SP (MUSCA_SPCTRL_S_BASE + 0x0A8)
+#define CMSDK_SPCTRL_AHB_PPCEXP3_SP (MUSCA_SPCTRL_S_BASE + 0x0AC)
+#define CMSDK_SPCTRL_APB_PPC0_SP (MUSCA_SPCTRL_S_BASE + 0x0B0)
+#define CMSDK_SPCTRL_APB_PPC1_SP (MUSCA_SPCTRL_S_BASE + 0x0B4)
+#define CMSDK_SPCTRL_APB_PPCEXP0_SP (MUSCA_SPCTRL_S_BASE + 0x0C0)
+#define CMSDK_SPCTRL_APB_PPCEXP1_SP (MUSCA_SPCTRL_S_BASE + 0x0C4)
+#define CMSDK_SPCTRL_APB_PPCEXP2_SP (MUSCA_SPCTRL_S_BASE + 0x0C8)
+#define CMSDK_SPCTRL_APB_PPCEXP3_SP (MUSCA_SPCTRL_S_BASE + 0x0CC)
+
+/* Non-Secure Unprivileged Access (NSP) Access slave PPCs register addresses */
+#define CMSDK_NSPCTRL_AHB_PPC0_NSP (MUSCA_NSPCTRL_NS_BASE + 0x090)
+#define CMSDK_NSPCTRL_AHB_PPCEXP0_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0A0)
+#define CMSDK_NSPCTRL_AHB_PPCEXP1_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0A4)
+#define CMSDK_NSPCTRL_AHB_PPCEXP2_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0A8)
+#define CMSDK_NSPCTRL_AHB_PPCEXP3_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0AC)
+#define CMSDK_NSPCTRL_APB_PPC0_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0B0)
+#define CMSDK_NSPCTRL_APB_PPC1_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0B4)
+#define CMSDK_NSPCTRL_APB_PPCEXP0_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0C0)
+#define CMSDK_NSPCTRL_APB_PPCEXP1_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0C4)
+#define CMSDK_NSPCTRL_APB_PPCEXP2_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0C8)
+#define CMSDK_NSPCTRL_APB_PPCEXP3_NSP (MUSCA_NSPCTRL_NS_BASE + 0x0CC)
+
+/* ARM APB PPC0 peripherals definition */
+#define CMSDK_TIMER0_APB_PPC_POS 0U
+#define CMSDK_TIMER1_APB_PPC_POS 1U
+#define CMSDK_DTIMER_APB_PPC_POS 2U
+#define CMSDK_MHU0_APB_PPC_POS 3U
+#define CMSDK_MHU1_APB_PPC_POS 4U
+/* The bits 31:5 are reserved */
+/* End ARM APB PPC0 peripherals definition */
+
+/* ARM APB PPC1 peripherals definition */
+#define CMSDK_S32K_TIMER_PPC_POS 0U
+/* The bits 31:1 are reserved */
+/* End ARM APB PPC1 peripherals definition */
+
+/* ARM AHB PPC0 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPC0 peripherals definition */
+
+/* ARM AHB PPCEXP0 peripherals definition */
+#define MUSCA_PERIPHS_AHB_PPC_POS 0U
+/* The bits 31:1 are reserved */
+/* End of ARM AHB PPCEXP0 peripherals definition */
+
+/* ARM AHB PPCEXP1 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP1 peripherals definition */
+
+/* ARM AHB PPCEXP2 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP2 peripherals definition */
+
+/* ARM AHB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+
+/* End of ARM AHB PPCEXP3 peripherals definition */
+
+/* Peripheral memory map */
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_CMSDK_MUSCA_H */
diff --git a/platform/ext/target/musca_a/Device/Include/system_core_musca.h b/platform/ext/target/musca_a/Device/Include/system_core_musca.h
new file mode 100644
index 0000000..aac5b0d
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/system_core_musca.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_CORE_MUSCA_H
+#define SYSTEM_CORE_MUSCA_H
+
+#ifdef DUAL_CORE
+/* Both cores are used */
+/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+#define __CM33_REV 0x0001U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+
+#if defined CORE0
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+#elif defined CORE1
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+#else
+#error "Either CORE0 or CORE1 must be defined"
+#endif /* CORE0/1 */
+
+#else /* DUAL_CORE */
+
+/* Single core is used */
+/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
+#define __CM33_REV 0x0000U /* Core revision r0p1 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+#endif /* DUAL_CORE */
+
+#endif /* SYSTEM_CORE_MUSCA_H */
+
diff --git a/platform/ext/target/musca_a/Device/Include/system_musca.h b/platform/ext/target/musca_a/Device/Include/system_musca.h
new file mode 100644
index 0000000..8a6802a
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Include/system_musca.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Include\system_ARMCM33.h
+ * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+ *
+ */
+
+#ifndef SYSTEM_MUSCA_H
+#define SYSTEM_MUSCA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
+extern uint32_t RefClock; /*!< External Reference Clock Frequency */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ It should be called from Reset Handler within the first few steps.
+ The minimal feature set should be initialised for successful exit
+ from Reset Handler to main entry point.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_MUSCA_H */
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct
new file mode 100755
index 0000000..1eb12f6
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct
@@ -0,0 +1,30 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2018 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../../../partition/region_defs.h"
+
+LR_CODE BL2_CODE_START {
+ ER_CODE BL2_CODE_START BL2_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA BL2_DATA_START BL2_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+}
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct
new file mode 100644
index 0000000..8e678d8
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct
@@ -0,0 +1,31 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../../../partition/region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA NS_DATA_START NS_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+}
+
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
new file mode 100755
index 0000000..6d8ecb2
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct
@@ -0,0 +1,127 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../../../partition/region_defs.h"
+
+LR_CODE S_CODE_START {
+
+ /**** This initial section contains common code for TEE */
+ ER_TFM_CODE S_CODE_START S_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+#if TFM_LVL == 1
+
+ ER_TFM_DATA S_DATA_START S_DATA_SIZE {
+ .ANY (+RW +ZI)
+ }
+
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x4000 {
+ }
+
+ TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
+ }
+
+#else /* TFM_LVL == 1 */
+
+ /**** Unprivileged Secure code start here */
+ TFM_UNPRIV_CODE +0 ALIGN 32 {
+ tfm_unpriv_api.o (+RO)
+ platform_retarget_dev.o (+RO)
+ *(SFN)
+ }
+
+ TFM_SP_STORAGE +0 ALIGN 32 {
+ *tfm_storage* (+RO)
+ }
+
+#ifdef TFM_PARTITION_TEST_CORE
+ TFM_SP_CORE_TEST +0 ALIGN 32 {
+ *tfm_ss_core_test.* (+RO)
+ }
+
+ TFM_SP_CORE_TEST_2 +0 ALIGN 32 {
+ *tfm_ss_core_test_2.* (+RO)
+ }
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_SST
+ TFM_SP_SST_TEST_PARTITION +0 ALIGN 32 {
+ *sst_test_service.* (+RO)
+ }
+#endif /* TFM_PARTITION_TEST_SST */
+
+ ER_TFM_DATA S_DATA_START S_DATA_SIZE {
+ .ANY (+RW +ZI)
+ }
+
+ TFM_UNPRIV_RO_DATA +0 ALIGN 32 {
+ tfm_unpriv_api.o (+RW +ZI)
+ platform_retarget_dev.o (+RW +ZI)
+ }
+
+ TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
+ }
+
+ TFM_SP_STORAGE_DATA +0 ALIGN 32 {
+ *tfm_storage* (+RW +ZI)
+ }
+
+ TFM_SP_STORAGE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+
+#ifdef TFM_PARTITION_TEST_CORE
+ TFM_SP_CORE_TEST_DATA +0 ALIGN 32 {
+ tfm_ss_core_test.o (+RW +ZI)
+ }
+
+ TFM_SP_CORE_TEST_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+
+ TFM_SP_CORE_TEST_2_DATA +0 ALIGN 32 {
+ tfm_ss_core_test_2.o (+RW +ZI)
+ }
+
+ TFM_SP_CORE_TEST_2_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_PARTITION_TEST_CORE */
+
+#ifdef TFM_PARTITION_TEST_SST
+ TFM_SP_SST_TEST_PARTITION_DATA +0 ALIGN 32 {
+ sst_test_service.o (+RW +ZI)
+ }
+
+ TFM_SP_SST_TEST_PARTITION_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* TFM_PARTITION_TEST_SST */
+
+#endif /* TFM_LVL == 1 */
+
+}
+
+LR_VENEER CMSE_VENEER_REGION_START {
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+ ER_CODE_CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s
new file mode 100755
index 0000000..d26e329
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s
@@ -0,0 +1,290 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+Heap_Size EQU 0x00010000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
+ DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
+ DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
+ DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler MPC_Handler
+ Default_Handler PPC_Handler
+ Default_Handler S_MSC_COMBINED_IRQHandler
+ Default_Handler S_BRIDGE_ERR_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ENDIF
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s
new file mode 100755
index 0000000..6d1e8f9
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s
@@ -0,0 +1,286 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+Heap_Size EQU 0x00001000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD 0 ; 9: Reserved
+ DCD 0 ; 10: Reserved
+ DCD 0 ; 11: Reserved
+ DCD 0 ; 12: Reserved
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ENDIF
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
new file mode 100755
index 0000000..b375d36
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s
@@ -0,0 +1,293 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
+; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+Heap_Size EQU 0x00001000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors ;Core Interrupts
+ DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ;SSE-200 Interrupts
+ DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
+ DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
+ DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
+ DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
+ DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
+ DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
+ DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
+ DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
+ DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
+ DCD MPC_Handler ; 9: Secure Combined MPC Interrupt
+ DCD PPC_Handler ; 10: Secure Combined PPC Interrupt
+ DCD S_MSC_COMBINED_IRQHandler ; 11: Secure Combined MSC Interrupt
+ DCD S_BRIDGE_ERR_IRQHandler ; 12: Secure Bridge Error Combined Interrupt
+ DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
+ DCD 0 ; 14: Reserved
+ DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
+ DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
+ DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
+ DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
+ DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
+ DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
+ DCD 0 ; 21: Reserved
+ DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
+ DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
+ DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
+ DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
+ DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
+ DCD 0 ; 27: Reserved
+ DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
+ DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
+ DCD 0 ; 30: Reserved
+ DCD 0 ; 31: Reserved
+ ;Expansion Interrupts
+ DCD 0 ; 32: Reserved
+ DCD GpTimer_IRQHandler ; 33: General Purpose Timer
+ DCD I2C0_IRQHandler ; 34: I2C0
+ DCD I2C1_IRQHandler ; 35: I2C1
+ DCD I2S_IRQHandler ; 36: I2S
+ DCD SPI_IRQHandler ; 37: SPI
+ DCD QSPI_IRQHandler ; 38: QSPI
+ DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
+ DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
+ DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
+ DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
+ DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
+ DCD UART0_IRQHandler ; 44: UART0 interrupt
+ DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
+ DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
+ DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
+ DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
+ DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
+ DCD UART1_IRQHandler ; 50: UART0 interrupt
+ DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
+ DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
+ DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
+ DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
+ DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
+ DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
+ DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
+ DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
+ DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
+ DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
+ DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
+ DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
+ DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
+ DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
+ DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
+ DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
+ DCD Combined_IRQHandler ; 67: Combined interrupt
+ DCD PVT_IRQHandler ; 68: PVT sensor interrupt
+ DCD 0 ; 69: Reserved
+ DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
+ DCD RTC_IRQHandler ; 71: RTC interrupt
+ DCD GpTimer0_IRQHandler ; 72: General Purpose Timer0
+ DCD GpTimer1_IRQHandler ; 73: General Purpose Timer1
+ DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
+ DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
+ DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; Reset Handler
+ AREA |.text|, CODE, READONLY
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+End_Of_Main
+ B .
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+ MACRO
+ Default_Handler $handler_name
+$handler_name PROC
+ EXPORT $handler_name [WEAK]
+ B .
+ ENDP
+ MEND
+
+ Default_Handler NMI_Handler
+ Default_Handler HardFault_Handler
+ Default_Handler MemManage_Handler
+ Default_Handler BusFault_Handler
+ Default_Handler UsageFault_Handler
+ Default_Handler SecureFault_Handler
+ Default_Handler SVC_Handler
+ Default_Handler DebugMon_Handler
+ Default_Handler PendSV_Handler
+ Default_Handler SysTick_Handler
+
+ Default_Handler NS_WATCHDOG_RESET_IRQHandler
+ Default_Handler NS_WATCHDOG_IRQHandler
+ Default_Handler S32K_TIMER_IRQHandler
+ Default_Handler TIMER0_IRQHandler
+ Default_Handler TIMER1_IRQHandler
+ Default_Handler DUALTIMER_IRQHandler
+ Default_Handler MHU0_IRQHandler
+ Default_Handler MHU1_IRQHandler
+ Default_Handler CRYPTOCELL_IRQHandler
+ Default_Handler MPC_Handler
+ Default_Handler PPC_Handler
+ Default_Handler S_MSC_COMBINED_IRQHandler
+ Default_Handler S_BRIDGE_ERR_IRQHandler
+ Default_Handler I_CACHE_INV_ERR_IRQHandler
+ Default_Handler SYS_PPU_IRQHandler
+ Default_Handler CPU0_PPU_IRQHandler
+ Default_Handler CPU1_PPU_IRQHandler
+ Default_Handler CPU0_DGB_PPU_IRQHandler
+ Default_Handler CPU1_DGB_PPU_IRQHandler
+ Default_Handler CRYPTOCELL_PPU_IRQHandler
+ Default_Handler RAM0_PPU_IRQHandler
+ Default_Handler RAM1_PPU_IRQHandler
+ Default_Handler RAM2_PPU_IRQHandler
+ Default_Handler RAM3_PPU_IRQHandler
+ Default_Handler DEBUG_PPU_IRQHandler
+ Default_Handler CPU0_CTI_IRQHandler
+ Default_Handler CPU1_CTI_IRQHandler
+
+ Default_Handler GpTimer_IRQHandler
+ Default_Handler I2C0_IRQHandler
+ Default_Handler I2C1_IRQHandler
+ Default_Handler I2S_IRQHandler
+ Default_Handler SPI_IRQHandler
+ Default_Handler QSPI_IRQHandler
+ Default_Handler UARTRX0_Handler
+ Default_Handler UARTTX0_Handler
+ Default_Handler UART0_RxTimeout_IRQHandler
+ Default_Handler UART0_ModemStatus_IRQHandler
+ Default_Handler UART0_Error_IRQHandler
+ Default_Handler UART0_IRQHandler
+ Default_Handler UARTRX1_Handler
+ Default_Handler UARTTX1_Handler
+ Default_Handler UART1_RxTimeout_IRQHandler
+ Default_Handler UART1_ModemStatus_IRQHandler
+ Default_Handler UART1_Error_IRQHandler
+ Default_Handler UART1_IRQHandler
+ Default_Handler GPIO_0_IRQHandler
+ Default_Handler GPIO_1_IRQHandler
+ Default_Handler GPIO_2_IRQHandler
+ Default_Handler GPIO_3_IRQHandler
+ Default_Handler GPIO_4_IRQHandler
+ Default_Handler GPIO_5_IRQHandler
+ Default_Handler GPIO_6_IRQHandler
+ Default_Handler GPIO_7_IRQHandler
+ Default_Handler GPIO_8_IRQHandler
+ Default_Handler GPIO_9_IRQHandler
+ Default_Handler GPIO_10_IRQHandler
+ Default_Handler GPIO_11_IRQHandler
+ Default_Handler GPIO_12_IRQHandler
+ Default_Handler GPIO_13_IRQHandler
+ Default_Handler GPIO_14_IRQHandler
+ Default_Handler GPIO_15_IRQHandler
+ Default_Handler Combined_IRQHandler
+ Default_Handler PVT_IRQHandler
+ Default_Handler PWM_0_IRQHandler
+ Default_Handler RTC_IRQHandler
+ Default_Handler GpTimer0_IRQHandler
+ Default_Handler GpTimer1_IRQHandler
+ Default_Handler PWM_1_IRQHandler
+ Default_Handler PWM_2_IRQHandler
+ Default_Handler IOMUX_IRQHandler
+
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ENDIF
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/musca_a/Device/Source/platform_retarget_dev.c b/platform/ext/target/musca_a/Device/Source/platform_retarget_dev.c
new file mode 100755
index 0000000..c9e7d32
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/platform_retarget_dev.c
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_dev.c
+ * \brief This file defines exports the structures based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#include "platform_retarget_dev.h"
+#include "platform_retarget.h"
+#include "system_cmsdk_musca.h"
+
+/* ======= Peripheral configuration structure definitions ======= */
+/* ARM SCC driver structures */
+#ifdef ARM_SCC_S
+static const struct arm_scc_dev_cfg_t ARM_SCC_DEV_CFG_S = {
+ .base = MUSCA_SCC_S_BASE};
+struct arm_scc_dev_t ARM_SCC_DEV_S = {&(ARM_SCC_DEV_CFG_S)};
+#endif
+#ifdef ARM_SCC_NS
+static const struct arm_scc_dev_cfg_t ARM_SCC_DEV_CFG_NS = {
+ .base = MUSCA_SCC_NS_BASE};
+struct arm_scc_dev_t ARM_SCC_DEV_NS = {&(ARM_SCC_DEV_CFG_NS)};
+#endif
+
+/* ARM GPIO driver structures */
+#ifdef ARM_GPIO0_S
+#ifndef ARM_SCC_S
+#error "SCC is needed for GPIO"
+#endif
+static const struct arm_gpio_dev_cfg_t ARM_GPIO0_DEV_CFG_S = {
+ .base = MUSCA_GPIO_S_BASE,
+ .scc_dev = (uint32_t)&ARM_SCC_DEV_S};
+static struct arm_gpio_dev_data_t ARM_GPIO0_DEV_DATA_S = {
+ .state = ARM_GPIO_UNINITIALIZED,
+ .port_mask = DEFAULT_PORT_MASK};
+struct arm_gpio_dev_t ARM_GPIO0_DEV_S = {&(ARM_GPIO0_DEV_CFG_S),
+ &(ARM_GPIO0_DEV_DATA_S)};
+#endif
+#ifdef ARM_GPIO0_NS
+#ifndef ARM_SCC_NS
+#error "SCC is needed for GPIO"
+#endif
+static const struct arm_gpio_dev_cfg_t ARM_GPIO0_DEV_CFG_NS = {
+ .base = MUSCA_GPIO_NS_BASE,
+ .scc_dev = (uint32_t)&ARM_SCC_DEV_NS};
+static struct arm_gpio_dev_data_t ARM_GPIO0_DEV_DATA_NS = {
+ .state = ARM_GPIO_UNINITIALIZED,
+ .port_mask = DEFAULT_PORT_MASK};
+struct arm_gpio_dev_t ARM_GPIO0_DEV_NS = {&(ARM_GPIO0_DEV_CFG_NS),
+ &(ARM_GPIO0_DEV_DATA_NS)};
+#endif
+
+/* ARM PPC SSE 200 driver structures */
+#ifdef AHB_PPC0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPC0_DEV_S = {
+ &AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = {
+ &AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP1_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP1_DEV_S = {
+ &AHB_PPCEXP1_DEV_CFG_S, &AHB_PPCEXP1_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP2_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S = {
+ &AHB_PPCEXP2_DEV_CFG_S, &AHB_PPCEXP2_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP3_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP3_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP3_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S = {
+ &AHB_PPCEXP3_DEV_CFG_S, &AHB_PPCEXP3_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPC0_S
+static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPC0_DEV_S = {
+ &APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPC1_S
+static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPC1_DEV_S = {
+ &APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S};
+#endif
+
+#ifdef APB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = {
+ &APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = {
+ &APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = {
+ &APB_PPCEXP2_DEV_CFG, &APB_PPCEXP2_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP3_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP3_DEV_CFG = {
+ .spctrl_base = MUSCA_SPCTRL_S_BASE,
+ .nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
+static struct ppc_sse200_dev_data_t APB_PPCEXP3_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S = {
+ &APB_PPCEXP3_DEV_CFG, &APB_PPCEXP3_DEV_DATA_S };
+#endif
+
+/* ARM MPC SIE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = {
+ .base = MUSCA_MPC_SRAM0_S_BASE};
+static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = {
+ &(MPC_ISRAM0_DEV_CFG_S),
+ &(MPC_ISRAM0_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = {
+ .base = MUSCA_MPC_SRAM1_S_BASE};
+static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = {
+ &(MPC_ISRAM1_DEV_CFG_S),
+ &(MPC_ISRAM1_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM2_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = {
+ .base = MUSCA_MPC_SRAM2_S_BASE};
+static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = {
+ &(MPC_ISRAM2_DEV_CFG_S),
+ &(MPC_ISRAM2_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM3_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = {
+ .base = MUSCA_MPC_SRAM3_S_BASE};
+static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = {
+ &(MPC_ISRAM3_DEV_CFG_S),
+ &(MPC_ISRAM3_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM1_NS
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM1_DEV_CFG_NS = {
+ .base = MUSCA_CODE_SRAM_MPC_NS_BASE};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM1_DEV_DATA_NS = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_NS = {
+ &(MPC_CODE_SRAM1_DEV_CFG_NS),
+ &(MPC_CODE_SRAM1_DEV_DATA_NS)};
+#endif
+
+#ifdef MPC_CODE_SRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM1_DEV_CFG_S = {
+ .base = MUSCA_CODE_SRAM_MPC_S_BASE};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_S = {
+ &(MPC_CODE_SRAM1_DEV_CFG_S),
+ &(MPC_CODE_SRAM1_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_QSPI_S
+static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_S = {
+ .base = MUSCA_QSPI_MPC_S_BASE};
+static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_QSPI_DEV_S = {
+ &(MPC_QSPI_DEV_CFG_S),
+ &(MPC_QSPI_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_QSPI_NS
+static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_NS = {
+ .base = MUSCA_QSPI_MPC_NS_BASE};
+static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_NS = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_QSPI_DEV_NS = {
+ &(MPC_QSPI_DEV_CFG_NS),
+ &(MPC_QSPI_DEV_DATA_NS)};
+#endif
+
+/* CMSDK Timers driver structures */
+#ifdef CMSDK_TIMER0_S
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
+ .base = MUSCA_CMSDK_TIMER0_S_BASE};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
+ &(CMSDK_TIMER0_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER0_NS
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
+ .base = MUSCA_CMSDK_TIMER0_NS_BASE};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
+ &(CMSDK_TIMER0_DEV_DATA_NS)};
+#endif
+
+#ifdef CMSDK_TIMER1_S
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
+ .base = MUSCA_CMSDK_TIMER1_S_BASE};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
+ &(CMSDK_TIMER1_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER1_NS
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
+ .base = MUSCA_CMSDK_TIMER1_NS_BASE};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
+ &(CMSDK_TIMER1_DEV_DATA_NS)};
+#endif
+
+/* ARM UART PL011 driver structures */
+#ifdef UART0_PL011_S
+static const struct uart_pl011_dev_cfg_t UART0_DEV_CFG_S = {
+ .base = MUSCA_UART0_S_BASE,
+ .def_baudrate = 115200,
+ .def_wlen = UART_PL011_WLEN_8,
+ .def_parity = UART_PL011_PARITY_DISABLED,
+ .def_stopbit = UART_PL011_STOPBIT_1};
+static struct uart_pl011_dev_data_t UART0_DEV_DATA_S = {
+ .state = 0,
+ .uart_clk = 0,
+ .baudrate = 0};
+struct uart_pl011_dev_t UART0_DEV_S = {&(UART0_DEV_CFG_S),
+ &(UART0_DEV_DATA_S)};
+#endif
+
+#ifdef UART0_PL011_NS
+static const struct uart_pl011_dev_cfg_t UART0_DEV_CFG_NS = {
+ .base = MUSCA_UART0_NS_BASE,
+ .def_baudrate = 115200,
+ .def_wlen = UART_PL011_WLEN_8,
+ .def_parity = UART_PL011_PARITY_DISABLED,
+ .def_stopbit = UART_PL011_STOPBIT_1};
+static struct uart_pl011_dev_data_t UART0_DEV_DATA_NS = {
+ .state = 0,
+ .uart_clk = 0,
+ .baudrate = 0};
+struct uart_pl011_dev_t UART0_DEV_NS = {&(UART0_DEV_CFG_NS),
+ &(UART0_DEV_DATA_NS)};
+#endif
+
+#ifdef UART1_PL011_S
+static const struct uart_pl011_dev_cfg_t UART1_DEV_CFG_S = {
+ .base = MUSCA_UART1_S_BASE,
+ .def_baudrate = 115200,
+ .def_wlen = UART_PL011_WLEN_8,
+ .def_parity = UART_PL011_PARITY_DISABLED,
+ .def_stopbit = UART_PL011_STOPBIT_1};
+static struct uart_pl011_dev_data_t UART1_DEV_DATA_S = {
+ .state = 0,
+ .uart_clk = 0,
+ .baudrate = 0};
+struct uart_pl011_dev_t UART1_DEV_S = {&(UART1_DEV_CFG_S),
+ &(UART1_DEV_DATA_S)};
+#endif
+
+#ifdef UART1_PL011_NS
+static const struct uart_pl011_dev_cfg_t UART1_DEV_CFG_NS = {
+ .base = MUSCA_UART1_NS_BASE,
+ .def_baudrate = 115200,
+ .def_wlen = UART_PL011_WLEN_8,
+ .def_parity = UART_PL011_PARITY_DISABLED,
+ .def_stopbit = UART_PL011_STOPBIT_1};
+static struct uart_pl011_dev_data_t UART1_DEV_DATA_NS = {
+ .state = 0,
+ .uart_clk = 0,
+ .baudrate = 0};
+struct uart_pl011_dev_t UART1_DEV_NS = {&(UART1_DEV_CFG_NS),
+ &(UART1_DEV_DATA_NS)};
+#endif
diff --git a/platform/ext/target/musca_a/Device/Source/system_cmsdk_musca.c b/platform/ext/target/musca_a/Device/Source/system_cmsdk_musca.c
new file mode 100644
index 0000000..4ad7770
--- /dev/null
+++ b/platform/ext/target/musca_a/Device/Source/system_cmsdk_musca.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Source\system_ARMCM33.c
+ */
+
+#include "system_cmsdk_musca.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL)
+#define SYSTEM_CLOCK (XTAL)
+#define SYSTEM_REFCLK (32768UL)
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t PeripheralClock = SYSTEM_CLOCK;
+uint32_t RefClock = SYSTEM_REFCLK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+ PeripheralClock = SYSTEM_CLOCK;
+ RefClock = SYSTEM_REFCLK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
+ (3U << 11U*2U) ); /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/platform/ext/target/musca_a/Native_Driver/arm_gpio_drv.c b/platform/ext/target/musca_a/Native_Driver/arm_gpio_drv.c
new file mode 100644
index 0000000..cf5988e
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/arm_gpio_drv.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_gpio_drv.h"
+#include "arm_scc_drv.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+
+/* Valid return values of the CLZ instruction are 0-31 */
+#define ERROR_BIT_NUMBER 32
+
+/* GPIO register map structure */
+struct arm_gpio_reg_map_t {
+ volatile uint32_t data; /* Offset: 0x000 (R/W) Data register */
+ volatile uint32_t dataout; /* Offset: 0x004 (R/W) Data output
+ * latch register */
+ volatile uint32_t reserved0[2];
+ volatile uint32_t outenableset; /* Offset: 0x010 (R/W) Output enable
+ * set register */
+ volatile uint32_t outenableclr; /* Offset: 0x014 (R/W) Output enable
+ * clear register */
+ volatile uint32_t altfuncset; /* Offset: 0x018 (R/W) Alternate function
+ * set register */
+ volatile uint32_t altfuncclr; /* Offset: 0x01C (R/W) Alternate function
+ * clear register */
+ volatile uint32_t intenset; /* Offset: 0x020 (R/W) Interrupt enable
+ * set register */
+ volatile uint32_t intenclr; /* Offset: 0x024 (R/W) Interrupt enable
+ * clear register */
+ volatile uint32_t inttypeset; /* Offset: 0x028 (R/W) Interrupt type
+ * set register */
+ volatile uint32_t inttypeclr; /* Offset: 0x02C (R/W) Interrupt type
+ * clear register */
+ volatile uint32_t intpolset; /* Offset: 0x030 (R/W) Interrupt polarity
+ * set register */
+ volatile uint32_t intpolclr; /* Offset: 0x034 (R/W) Interrupt polarity
+ * clear register */
+ union {
+ volatile uint32_t intstatus; /* Offset: 0x038 (R/ ) Interrupt status
+ * register */
+ volatile uint32_t intclear; /* Offset: 0x038 ( /W) Interrupt clear
+ * register */
+ }intreg;
+ volatile uint32_t reserved1[241];
+ volatile uint32_t lb_masked[256]; /* Offset: 0x400 - 0x7FC (R/W)
+ * Lower byte masked access register */
+ volatile uint32_t ub_masked[256]; /* Offset: 0x800 - 0xBFC (R/W)
+ * Upper byte masked access register */
+};
+
+/**
+ * \brief Find the bit number of the lowest significant bit set to 1
+ *
+ * \param[in] value Input bitmask value
+ *
+ * \return Bit number of the lowest significatn bit or ERROR_BIT_NUMBER
+ */
+static uint32_t get_first_set_bit(uint32_t value)
+{
+ if (value == 0) {
+ return ERROR_BIT_NUMBER;
+ }
+ value = __RBIT(value);
+ value = __CLZ(value);
+
+ return value;
+}
+
+/*
+ * \brief Selects whether to set alt func through GPIO or SCC
+ *
+ * \param[in] p_gpio_port GPIO port to configure \ref ahbarm_gpio_reg_map_t
+ * \param[in] scc_base SCC registers base address \ref arm_scc_reg_map_t
+ * \param[in] mask GPIO pin bit mask
+ * \param[in] flags GPIO pin flags \ref gpio_flags_t
+ *
+ * \details GPIO has only one bit to store the alternate function so if there
+ * are more then one alternate functions they will be selected through
+ * the SCC
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ */
+static enum arm_gpio_error_t
+set_alt_func(struct arm_gpio_reg_map_t* p_gpio_port,
+ struct arm_scc_dev_t* scc_dev, uint32_t mask,
+ enum gpio_flags_t flags)
+{
+ /* If SCC device is defined then alt functions are selected through SCC */
+ if (scc_dev) {
+ /* If many alternate functions are set */
+ /* then only the first will be selected */
+ flags = get_first_set_bit(flags);
+ arm_scc_set_alt_func(scc_dev, (enum gpio_altfunc_t) flags, mask);
+ } else if (flags & ARM_GPIO_ENABLE) {
+ p_gpio_port->altfuncclr = mask;
+ } else if (flags & ARM_GPIO_PIN_DISABLE){
+ p_gpio_port->altfuncset = mask;
+ } else {
+ return ARM_GPIO_ERR_INVALID_ARG;
+ }
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+/*
+ * \brief Configures the pin or port.
+ *
+ * \param[in] p_gpio_port GPIO port to configure \ref ahbarm_gpio_reg_map_t
+ * \param[in] scc_base SCC registers base address \ref arm_scc_reg_map_t
+ * \param[in] mask GPIO pin bit mask
+ * \param[in] flags GPIO pin flags
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ */
+static enum arm_gpio_error_t
+set_port_config(struct arm_gpio_reg_map_t* p_gpio_port,
+ struct arm_scc_dev_t* scc_dev, uint32_t mask,
+ enum gpio_flags_t flags)
+{
+ if(flags & ARM_GPIO_PIN_DISABLE) {
+ return(set_alt_func(p_gpio_port, scc_dev, mask, flags));
+ }
+
+ if(flags & ARM_GPIO_OUTPUT) {
+ p_gpio_port->outenableset = mask;
+ } else if(flags & ARM_GPIO_INPUT) {
+ p_gpio_port->outenableclr = mask;
+ }
+
+ /* Sets interrupt configuration */
+ if(flags & ARM_GPIO_IRQ) {
+ /* Interrupt type: EDGE = 1 - LEVEL = 0 */
+ if(flags & ARM_GPIO_IRQ_EDGE) {
+ p_gpio_port->inttypeset = mask;
+ } else if(flags & ARM_GPIO_IRQ_LEVEL) {
+ p_gpio_port->inttypeclr = mask;
+ }
+
+ /* Interrupt polarity */
+ if(flags & ARM_GPIO_IRQ_ACTIVE_LOW) {
+ p_gpio_port->intpolclr = mask;
+ } else if(flags & ARM_GPIO_IRQ_ACTIVE_HIGH) {
+ p_gpio_port->intpolset = mask;
+ }
+ }
+
+ if(flags & ARM_GPIO_PIN_ENABLE) {
+ return(set_alt_func(p_gpio_port, scc_dev, mask, flags));
+ }
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+void arm_gpio_init(struct arm_gpio_dev_t* dev)
+{
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+ struct arm_scc_dev_t* scc_dev = (struct arm_scc_dev_t*)dev->cfg->scc_dev;
+
+ if(dev->data->state != ARM_GPIO_INITIALIZED) {
+ /* Disables all pins in this port */
+ set_port_config(p_gpio_port, scc_dev,
+ DEFAULT_PORT_MASK, ARM_GPIO_PIN_DISABLE);
+
+ dev->data->port_mask = DEFAULT_PORT_MASK;
+ dev->data->state = ARM_GPIO_INITIALIZED;
+ }
+}
+
+enum arm_gpio_error_t arm_gpio_config(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ enum gpio_flags_t flags)
+{
+ uint32_t pin_mask;
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+ struct arm_scc_dev_t* scc_dev = (struct arm_scc_dev_t*)dev->cfg->scc_dev;
+
+ if(dev->data->state != ARM_GPIO_INITIALIZED) {
+ return ARM_GPIO_ERR_PORT_NOT_INIT;
+ }
+
+ if(pin_num >= MAX_PIN_NBR) {
+ return ARM_GPIO_ERR_INVALID_ARG;
+ }
+
+ switch(access) {
+ case ARM_GPIO_ACCESS_PIN:
+ pin_mask = (1UL << pin_num);
+ return(set_port_config(p_gpio_port, scc_dev, pin_mask, flags));
+ case ARM_GPIO_ACCESS_PORT:
+ return(set_port_config(p_gpio_port, scc_dev,
+ dev->data->port_mask, flags));
+ default:
+ break;
+ }
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+enum arm_gpio_error_t arm_gpio_write(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ uint32_t value)
+{
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+ if(pin_num >= MAX_PIN_NBR) {
+ return ARM_GPIO_ERR_INVALID_ARG;
+ }
+
+ /* As ARM is a read-modify-write architecture, before set a
+ * value on a GPIO register it is required to disable the
+ * interrupts to prevent problems in a multitasking
+ * environment */
+ switch(access) {
+ case ARM_GPIO_ACCESS_PIN:
+ if(value) {
+ /* Sets the pin */
+ p_gpio_port->dataout |= (1UL << pin_num);
+ } else {
+ /* Clears the pin */
+ p_gpio_port->dataout &= ~(1UL << pin_num);
+ }
+ break;
+ case ARM_GPIO_ACCESS_PORT:
+ if(value) {
+ /* Sets masked pins */
+ p_gpio_port->dataout |= dev->data->port_mask;
+ } else {
+ /* Clears masked pins */
+ p_gpio_port->dataout &= ~(dev->data->port_mask);
+ }
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch. */
+ }
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+int32_t arm_gpio_read(struct arm_gpio_dev_t* dev, enum arm_gpio_access_t access,
+ uint8_t pin_num)
+{
+ uint32_t value;
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+ value = p_gpio_port->data;
+
+ if(access == ARM_GPIO_ACCESS_PIN) {
+ if(pin_num >= MAX_PIN_NBR) {
+ return -1;
+ }
+ value = ((value >> pin_num) & 1UL);
+ } else {
+ value &= dev->data->port_mask;
+ }
+
+ return (int32_t)value;
+}
+
+enum arm_gpio_error_t arm_gpio_set_interrupt(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ enum arm_gpio_irq_status_t status)
+{
+ uint32_t mask = 0;
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state != ARM_GPIO_INITIALIZED) {
+ return ARM_GPIO_ERR_PORT_NOT_INIT;
+ }
+
+ if(pin_num >= MAX_PIN_NBR) {
+ return ARM_GPIO_ERR_INVALID_ARG;
+ }
+
+ switch(access) {
+ case ARM_GPIO_ACCESS_PIN:
+ mask = (1UL << pin_num);
+ break;
+ case ARM_GPIO_ACCESS_PORT:
+ mask = dev->data->port_mask;
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+
+ if(status == ARM_GPIO_IRQ_ENABLE) {
+ p_gpio_port->intenset = mask;
+ } else {
+ p_gpio_port->intenclr = mask;
+ }
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+enum arm_gpio_error_t arm_gpio_get_irq_status(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ uint32_t* status)
+{
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state != ARM_GPIO_INITIALIZED) {
+ return ARM_GPIO_ERR_PORT_NOT_INIT;
+ }
+
+ if(pin_num >= MAX_PIN_NBR) {
+ return ARM_GPIO_ERR_INVALID_ARG;
+ }
+
+ *status = p_gpio_port->intreg.intstatus;
+
+ if(access == ARM_GPIO_ACCESS_PIN) {
+ *status = ((*status >> pin_num) & 1UL);
+ } else {
+ *status &= dev->data->port_mask;
+ }
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+enum arm_gpio_error_t arm_gpio_clear_interrupt(struct arm_gpio_dev_t* dev,
+ uint8_t pin_num)
+{
+ struct arm_gpio_reg_map_t* p_gpio_port =
+ (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state != ARM_GPIO_INITIALIZED) {
+ return ARM_GPIO_ERR_PORT_NOT_INIT;
+ }
+
+ if(pin_num >= MAX_PIN_NBR) {
+ return ARM_GPIO_ERR_INVALID_ARG;
+ }
+
+ p_gpio_port->intreg.intstatus = (1UL << pin_num);
+
+ return ARM_GPIO_ERR_NONE;
+}
+
+void arm_gpio_set_port_mask(struct arm_gpio_dev_t* dev, uint32_t port_mask)
+{
+ dev->data->port_mask = (port_mask & DEFAULT_PORT_MASK);
+}
+
+uint32_t arm_gpio_get_port_mask(struct arm_gpio_dev_t* dev)
+{
+ if(dev->data->state != ARM_GPIO_INITIALIZED) {
+ return 0;
+ }
+
+ return (dev->data->port_mask & DEFAULT_PORT_MASK);
+}
diff --git a/platform/ext/target/musca_a/Native_Driver/arm_gpio_drv.h b/platform/ext/target/musca_a/Native_Driver/arm_gpio_drv.h
new file mode 100644
index 0000000..0ee9663
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/arm_gpio_drv.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_gpio_drv.h
+ * \brief Generic driver for ARM GPIO.
+ */
+
+#ifndef __ARM_GPIO_DRV_H__
+#define __ARM_GPIO_DRV_H__
+
+#include <stdint.h>
+#include "arm_scc_drv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_PIN_NBR 16
+#define DEFAULT_PORT_MASK 0xFFFF /* Default port mask */
+
+enum gpio_flags_t {
+ ARM_GPIO_FLAG_NONE = (GPIO_ALTFUNC_NONE),
+ ARM_GPIO_MAIN_FUNC_EN = (1UL << GPIO_MAIN_FUNC),
+ ARM_GPIO_ALTFUNC1_EN = (1UL << GPIO_ALTFUNC_1),
+ ARM_GPIO_ALTFUNC2_EN = (1UL << GPIO_ALTFUNC_2),
+ ARM_GPIO_ALTFUNC3_EN = (1UL << GPIO_ALTFUNC_3),
+ ARM_GPIO_PIN_DISABLE = (1ul << GPIO_ALTFUNC_MAX),
+ ARM_GPIO_ENABLE = (1ul << (GPIO_ALTFUNC_MAX + 1)),
+ ARM_GPIO_OUTPUT = (1ul << (GPIO_ALTFUNC_MAX + 2)),
+ ARM_GPIO_INPUT = (1ul << (GPIO_ALTFUNC_MAX + 3)),
+ ARM_GPIO_IRQ = (1ul << (GPIO_ALTFUNC_MAX + 4)),
+ ARM_GPIO_IRQ_EDGE = (1ul << (GPIO_ALTFUNC_MAX + 5)),
+ ARM_GPIO_IRQ_LEVEL = (1ul << (GPIO_ALTFUNC_MAX + 6)),
+ ARM_GPIO_IRQ_ACTIVE_LOW = (1ul << (GPIO_ALTFUNC_MAX + 7)),
+ ARM_GPIO_IRQ_ACTIVE_HIGH = (1ul << (GPIO_ALTFUNC_MAX + 8))
+};
+
+/* If GPIO is enabled it means the main alternate function */
+/* These two have to be selected together */
+#define ARM_GPIO_PIN_ENABLE (ARM_GPIO_ENABLE | ARM_GPIO_MAIN_FUNC_EN)
+
+/* ARM GPIO enumeration types */
+enum arm_gpio_access_t {
+ ARM_GPIO_ACCESS_PIN = 0, /*!< Pin access to GPIO */
+ ARM_GPIO_ACCESS_PORT /*!< Port access to GPIO */
+};
+
+enum arm_gpio_irq_status_t {
+ ARM_GPIO_IRQ_DISABLE = 0, /*!< Disable interruptions */
+ ARM_GPIO_IRQ_ENABLE /*!< Enable interruptions */
+};
+
+enum arm_gpio_state_t {
+ ARM_GPIO_UNINITIALIZED = 0, /*!< GPIO is not initialized */
+ ARM_GPIO_INITIALIZED /*!< GPIO is initialized */
+};
+
+enum arm_gpio_error_t {
+ ARM_GPIO_ERR_NONE = 0, /*!< No error */
+ ARM_GPIO_ERR_INVALID_ARG, /*!< Error invalid input argument */
+ ARM_GPIO_ERR_PORT_NOT_INIT /*!< Error GPIO port not initialized */
+};
+
+/* ARM GPIO device configuration structure */
+struct arm_gpio_dev_cfg_t {
+ const uint32_t base; /*!< GPIO base address */
+ const uint32_t scc_dev; /*!< SCC device address */
+};
+
+/* ARM GPIO device data structure */
+struct arm_gpio_dev_data_t {
+ enum arm_gpio_state_t state; /*!< Indicates if the gpio driver
+ is initialized and enabled */
+ uint32_t port_mask; /*!< Port mask used for any port access */
+};
+
+/* ARM GPIO device structure */
+struct arm_gpio_dev_t {
+ const struct arm_gpio_dev_cfg_t* const cfg; /*!< GPIO configuration */
+ struct arm_gpio_dev_data_t* const data; /*!< GPIO data */
+};
+
+/* ARM GPIO pin structure */
+struct arm_gpio_pin_t {
+ uint32_t number; /*!< Pin number */
+ enum arm_gpio_access_t access_type; /*!< Type of access in the
+ GPIO block */
+};
+
+/**
+ * \brief Initializes GPIO port.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_gpio_init(struct arm_gpio_dev_t* dev);
+
+/**
+ * \brief Configurates pin or port.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access Access type \ref arm_gpio_access_t
+ * \param[in] pin_num Pin number.
+ * \param[in] flags Pin flags \ref arm_gpio_flags_t
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_config(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ enum gpio_flags_t flags);
+
+/**
+ * \brief Writes to output pin or port.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access Access type \ref arm_gpio_access_t
+ * \param[in] pin_num Pin number.
+ * \param[in] value Value(s) to set.
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ * \note As ARM is a read-modify-write architecture, before writing a
+ * value on a GPIO pin it is required to disable the
+ * interrupts to prevent problems in a multitasking
+ * environment.
+ */
+enum arm_gpio_error_t arm_gpio_write(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ uint32_t value);
+
+/**
+ * \brief Reads the pin or port status.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access Access type \ref arm_gpio_access_t
+ * \param[in] pin_num Pin number.
+ * \param[in] value Value of input pin(s).
+ *
+ * \return Returns bit value for Pin access or port value for port access.
+ * Negative value for error.
+ * \note This function doesn't check if dev is NULL.
+ */
+int32_t arm_gpio_read(struct arm_gpio_dev_t* dev, enum arm_gpio_access_t access,
+ uint8_t pin_num);
+
+/**
+ * \brief Sets interrupt status for the given pin or port.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access Access type \ref arm_gpio_access_t
+ * \param[in] pin_num Pin number.
+ * \param[in] status Interrupt status \ref arm_gpio_irq_status
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_set_interrupt(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ enum arm_gpio_irq_status_t status);
+
+/**
+ * \brief Gets interrupt status for the given pin or port.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access Access type \ref arm_gpio_access_t
+ * \param[in] pin_num Pin number.
+ * \param[out] status Interrupt status values. If the access is by pin, then
+ * the status will be 0 or 1.
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_get_irq_status(struct arm_gpio_dev_t* dev,
+ enum arm_gpio_access_t access,
+ uint8_t pin_num,
+ uint32_t* status);
+
+/**
+ * \brief Clears gpio interrupt.
+ *
+ * \param[in] dev GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] pin_num Pin number.
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_clear_interrupt(struct arm_gpio_dev_t* dev,
+ uint8_t pin_num);
+
+/**
+ * \brief Sets gpio mask for port access.
+ *
+ * \param[in] dev GPIO port \ref arm_gpio_dev_t
+ * \param[in] port_mask New port mask to set, only the 16 LSb are taken into
+ * account
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_gpio_set_port_mask(struct arm_gpio_dev_t* dev, uint32_t port_mask);
+
+/**
+ * \brief Gets gpio mask for port access.
+ *
+ * \param[in] dev GPIO port \ref arm_gpio_dev_t
+ *
+ * \return Returns the current port mask
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_gpio_get_port_mask(struct arm_gpio_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ARM_GPIO_DRV_H__ */
diff --git a/platform/ext/target/musca_a/Native_Driver/arm_scc_drv.c b/platform/ext/target/musca_a/Native_Driver/arm_scc_drv.c
new file mode 100644
index 0000000..ce16dc6
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/arm_scc_drv.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_scc_drv.h"
+
+struct arm_scc_reg_map_t {
+ volatile uint32_t reset_ctrl; /* 0x00 RW Reset Control Register */
+ volatile uint32_t clk_ctrl; /* 0x04 RW Clock Control Register*/
+ volatile uint32_t pwr_ctrl; /* 0x08 RW Power Control Register*/
+ volatile uint32_t pll_ctrl; /* 0x0C RW Power Control Register */
+ volatile uint32_t dbg_ctrl; /* 0x10 RW Debug Control Register */
+ volatile uint32_t sram_ctrl; /* 0x14 RW SRAM Control Register */
+ volatile uint32_t intr_ctrl; /* 0x18 RW Interupt Control Register */
+ volatile uint32_t reserved1; /* 0x1C RW reserved */
+ volatile uint32_t cpu0_vtor_sram; /* 0x20 RW Reset vector for CPU0 Secure Mode */
+ volatile uint32_t cpu0_vtor_flash; /* 0x24 RW Reset vector for CPU0 Secure Mode */
+ volatile uint32_t cpu1_vtor_sram; /* 0x28 RW Reset vector for CPU1 Secure Mode */
+ volatile uint32_t cpu1_vtor_flash; /* 0x2C RW Reset vector for CPU0 Secure Mode */
+ volatile uint32_t iomux_main_insel; /* 0x30 RW Main function in data select */
+ volatile uint32_t iomux_main_outse; /* 0x34 RW Main function out data select */
+ volatile uint32_t iomux_main_oense; /* 0x38 RW Main function out enable select */
+ volatile uint32_t iomux_main_default_in; /* 0x3C RW Main function default in select */
+ volatile uint32_t iomux_altf1_insel; /* 0x40 RW Alt function 1 in data select */
+ volatile uint32_t iomux_altf1_outse; /* 0x44 RW Alt function 1 out data select */
+ volatile uint32_t iomux_altf1_oense; /* 0x48 RW Alt function 1 out enable select */
+ volatile uint32_t iomux_altf1_default_in; /* 0x4C RW Alt function 1 default in select */
+ volatile uint32_t iomux_altf2_insel; /* 0x50 RW Alt function 2 in data select */
+ volatile uint32_t iomux_altf2_outse; /* 0x54 RW Alt function 2 out data select */
+ volatile uint32_t iomux_altf2_oense; /* 0x58 RW Alt function 2 out enable select */
+ volatile uint32_t iomux_altf2_default_in; /* 0x5C RW Alt function 2 default in select */
+ volatile uint32_t pvt_ctrl; /* 0x60 RW PVT control register */
+ volatile uint32_t spare0; /* 0x64 RW reserved */
+ volatile uint32_t iopad_ds0; /* 0x68 RW Drive Select 0 */
+ volatile uint32_t iopad_ds1; /* 0x6C RW Drive Select 1 */
+ volatile uint32_t iopad_pe; /* 0x70 RW Pull Enable */
+ volatile uint32_t iopad_ps; /* 0x74 RW Pull Select */
+ volatile uint32_t iopad_sr; /* 0x78 RW Slew Select */
+ volatile uint32_t iopad_is; /* 0x7C RW Input Select */
+ volatile uint32_t sram_rw_margine; /* 0x80 RW reserved */
+ volatile uint32_t static_conf_sig0; /* 0x84 RW Static configuration */
+ volatile uint32_t static_conf_sig1; /* 0x88 RW Static configuration */
+ volatile uint32_t req_set; /* 0x8C RW External Event Enable */
+ volatile uint32_t req_clear; /* 0x90 RW External Event Clear */
+ volatile uint32_t iomux_altf3_insel; /* 0x94 RW Alt function 3 in data select */
+ volatile uint32_t iomux_altf3_outse; /* 0x98 RW Alt function 3 out data select */
+ volatile uint32_t iomux_altf3_oense; /* 0x9C RW Alt function 3 out enable select */
+ volatile uint32_t iomux_altf3_default_in; /* 0xA0 RW Alt function 3 default in select */
+ volatile uint32_t pcsm_ctrl_override; /* 0xA4 RW Q-Channels QACTIVE Override */
+ volatile uint32_t pd_cpu0_iso_override; /* 0xA8 RW CPU0 Isolation Override */
+ volatile uint32_t pd_cpu1_iso_override; /* 0xAC RW CPU1 Isolation Override */
+ volatile uint32_t sys_sram_rw_assist0; /* 0xB0 RW CPU0 icache sram ldata */
+ volatile uint32_t sys_sram_rw_assist1; /* 0xB4 RW CPU0 icache sram tag */
+ volatile uint32_t sys_sram_rw_assist2; /* 0xB8 RW CPU1 icache sram ldata */
+ volatile uint32_t sys_sram_rw_assist3; /* 0xBC RW CPU1 icache sram tag */
+ volatile uint32_t sys_sram_rw_assist4; /* 0xC0 RW System sram */
+ volatile uint32_t sys_sram_rw_assist5; /* 0xC4 RW System sram */
+ volatile uint32_t reserved2[3]; /* reserved */
+ volatile uint32_t crypto_sram_rw_assist0; /* 0xD4 RW Crypto ram */
+ volatile uint32_t crypto_sram_rw_assist1; /* 0xD8 RW Crypto sec sram */
+ volatile uint32_t crypto_sram_rw_assist2; /* 0xDC RW Reserved */
+ volatile uint32_t req_edge_sel; /* 0xC0 RW Power clock request edge select */
+ volatile uint32_t req_enable; /* 0xC4 RW Power clock request enable */
+ volatile uint32_t reserved3[28]; /* reserved */
+ volatile uint32_t chip_id; /* 0x100 RO Chip ID 0x0797_0477 */
+ volatile uint32_t clock_status; /* 0x104 RO Clock status */
+ volatile uint32_t io_in_status; /* 0x108 RO I/O in status */
+};
+
+/**
+ * \brief Clears selected alternate functions for selected pins
+ *
+ * \param[in] dev SCC registers base address \ref arm_scc_reg_map_t
+ * \param[in] func_mask Bitmask of alternate functions to clear
+ * \ref gpio_altfunc_mask_t
+ * \param[in] pin_mask Pin mask for the alternate functions
+ */
+static void scc_clear_alt_func(struct arm_scc_reg_map_t* scc_regs,
+ enum gpio_altfunc_mask_t func_mask,
+ uint32_t pin_mask)
+{
+ if (func_mask & GPIO_MAIN_FUNC_MASK) {
+ scc_regs->iomux_main_insel &= ~pin_mask;
+ scc_regs->iomux_main_outse &= ~pin_mask;
+ scc_regs->iomux_main_oense &= ~pin_mask;
+ }
+ if (func_mask & GPIO_ALTFUNC_1_MASK) {
+ scc_regs->iomux_altf1_insel &= ~pin_mask;
+ scc_regs->iomux_altf1_outse &= ~pin_mask;
+ scc_regs->iomux_altf1_oense &= ~pin_mask;
+ }
+ if (func_mask & GPIO_ALTFUNC_2_MASK) {
+ scc_regs->iomux_altf2_insel &= ~pin_mask;
+ scc_regs->iomux_altf2_outse &= ~pin_mask;
+ scc_regs->iomux_altf2_oense &= ~pin_mask;
+ }
+ if (func_mask & GPIO_ALTFUNC_3_MASK) {
+ scc_regs->iomux_altf3_insel &= ~pin_mask;
+ scc_regs->iomux_altf3_outse &= ~pin_mask;
+ scc_regs->iomux_altf3_oense &= ~pin_mask;
+ }
+}
+
+void arm_scc_set_alt_func(struct arm_scc_dev_t* dev,
+ enum gpio_altfunc_t altfunc, uint32_t pin_mask)
+{
+ struct arm_scc_reg_map_t* scc_regs =
+ (struct arm_scc_reg_map_t*) dev->cfg->base;
+ enum gpio_altfunc_mask_t altfunc_to_clear = GPIO_ALTFUNC_NONE;
+ volatile uint32_t *insel = NULL;
+ volatile uint32_t *outse = NULL;
+ volatile uint32_t *oense = NULL;
+
+ if (altfunc >= GPIO_ALTFUNC_MAX) {
+ /* If no altfunction is selected, then nothing to do.
+ * This is possible during init and we do not
+ * want to change the reset values set by the HW
+ */
+ return;
+ }
+
+ switch (altfunc) {
+ case GPIO_MAIN_FUNC:
+ insel = &scc_regs->iomux_main_insel;
+ outse = &scc_regs->iomux_main_outse;
+ oense = &scc_regs->iomux_main_oense;
+ altfunc_to_clear = GPIO_MAIN_FUNC_NEG_MASK;
+ break;
+
+ case GPIO_ALTFUNC_1:
+ insel = &scc_regs->iomux_altf1_insel;
+ outse = &scc_regs->iomux_altf1_outse;
+ oense = &scc_regs->iomux_altf1_oense;
+ altfunc_to_clear = GPIO_ALTFUNC_1_NEG_MASK;
+ break;
+
+ case GPIO_ALTFUNC_2:
+ insel = &scc_regs->iomux_altf2_insel;
+ outse = &scc_regs->iomux_altf2_outse;
+ oense = &scc_regs->iomux_altf2_oense;
+ altfunc_to_clear = GPIO_ALTFUNC_2_NEG_MASK;
+ break;
+
+ case GPIO_ALTFUNC_3:
+ insel = &scc_regs->iomux_altf3_insel;
+ outse = &scc_regs->iomux_altf3_outse;
+ oense = &scc_regs->iomux_altf3_oense;
+ altfunc_to_clear = GPIO_ALTFUNC_3_NEG_MASK;
+ break;
+ default:
+ break;
+ }
+
+ /* Select the wanted function's output enable bit first.
+ * This way the output won't be disabled which is desired
+ * if we switch from output to output function
+ */
+ *oense |= pin_mask;
+
+ /* Clear all alternate function registers which are not selected */
+ scc_clear_alt_func(scc_regs, altfunc_to_clear, pin_mask);
+
+ /* Enable input and output data line */
+ *insel |= pin_mask;
+ *outse |= pin_mask;
+}
+
+void arm_scc_set_pinmode(struct arm_scc_dev_t* dev, uint32_t pin_mask,
+ enum pinmode_select_t mode)
+{
+ struct arm_scc_reg_map_t* scc_regs =
+ (struct arm_scc_reg_map_t*) dev->cfg->base;
+
+ switch (mode) {
+ case PINMODE_NONE:
+ scc_regs->iopad_pe &= ~pin_mask;
+ break;
+ case PINMODE_PULL_DOWN:
+ /* If the pull select bit is set to 0 it means pull down */
+ scc_regs->iopad_ps &= ~pin_mask;
+ scc_regs->iopad_pe |= pin_mask;
+ break;
+ case PINMODE_PULL_UP:
+ /* If the pull select bit is set to 1 it means pull up */
+ scc_regs->iopad_ps |= pin_mask;
+ scc_regs->iopad_pe |= pin_mask;
+ break;
+ default:
+ break;
+ }
+}
+
diff --git a/platform/ext/target/musca_a/Native_Driver/arm_scc_drv.h b/platform/ext/target/musca_a/Native_Driver/arm_scc_drv.h
new file mode 100644
index 0000000..f8402d0
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/arm_scc_drv.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __ARM_SCC_DRV_H__
+#define __ARM_SCC_DRV_H__
+
+#include <stdint.h>
+#include <stddef.h>
+
+/**
+ * \brief Enum to store alternate function values.
+ * They are used as shift operand, must be unsigned.
+ */
+enum gpio_altfunc_t {
+ GPIO_MAIN_FUNC = 0UL,
+ GPIO_ALTFUNC_1,
+ GPIO_ALTFUNC_2,
+ GPIO_ALTFUNC_3,
+ GPIO_ALTFUNC_MAX
+};
+
+#define GPIO_ALTFUNC_ALL_MASK ((1U << GPIO_ALTFUNC_MAX) - 1)
+
+/**
+* \brief Enum to store alternate function mask values.
+*/
+enum gpio_altfunc_mask_t {
+ GPIO_ALTFUNC_NONE = 0,
+ GPIO_MAIN_FUNC_MASK = (1UL << GPIO_MAIN_FUNC),
+ GPIO_ALTFUNC_1_MASK = (1UL << GPIO_ALTFUNC_1),
+ GPIO_ALTFUNC_2_MASK = (1UL << GPIO_ALTFUNC_2),
+ GPIO_ALTFUNC_3_MASK = (1UL << GPIO_ALTFUNC_3),
+ GPIO_MAIN_FUNC_NEG_MASK = (~GPIO_MAIN_FUNC_MASK & GPIO_ALTFUNC_ALL_MASK),
+ GPIO_ALTFUNC_1_NEG_MASK = (~GPIO_ALTFUNC_1_MASK & GPIO_ALTFUNC_ALL_MASK),
+ GPIO_ALTFUNC_2_NEG_MASK = (~GPIO_ALTFUNC_2_MASK & GPIO_ALTFUNC_ALL_MASK),
+ GPIO_ALTFUNC_3_NEG_MASK = (~GPIO_ALTFUNC_3_MASK & GPIO_ALTFUNC_ALL_MASK)
+};
+
+enum pinmode_select_t {
+ PINMODE_NONE,
+ PINMODE_PULL_DOWN,
+ PINMODE_PULL_UP
+};
+
+/* ARM SCC device configuration structure */
+struct arm_scc_dev_cfg_t {
+ const uint32_t base; /*!< SCC base address */
+};
+
+/* ARM SCC device structure */
+struct arm_scc_dev_t {
+ const struct arm_scc_dev_cfg_t* const cfg; /*!< SCC configuration */
+};
+
+/**
+ * \brief Sets selected alternate functions for selected pins
+ *
+ * \param[in] dev SCC device pointer \ref arm_scc_dev_t
+ * \param[in] altfunc Alternate function to set \ref gpio_altfunc_t
+ * \param[in] pin_mask Pin mask for the alternate functions
+ *
+ * \note This function doesn't check if scc_base is NULL.
+ * \note If no alternate function is selected then the function won't do anything
+ */
+void arm_scc_set_alt_func(struct arm_scc_dev_t* dev,
+ enum gpio_altfunc_t altfunc, uint32_t pin_mask);
+
+/**
+ * \brief Sets pinmode for the given pins
+ *
+ * \param[in] dev SCC device pointer \ref arm_scc_dev_t
+ * \param[in] pin_mask Pin mask for the alternate functions
+ * \param[in] mode Pin mode to set \ref pinmode_select_t
+ *
+ * \note This function doesn't check if scc_base is NULL.
+ */
+void arm_scc_set_pinmode(struct arm_scc_dev_t* dev, uint32_t pin_mask,
+ enum pinmode_select_t mode);
+
+#endif /* __ARM_SCC_DRV_H__ */
diff --git a/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c b/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c
new file mode 100644
index 0000000..e842681
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.c
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mpc_sie200_drv.h"
+
+#include <stddef.h>
+
+#include "cmsis.h"
+
+#define MPC_SIE200_BLK_CFG_OFFSET 5U
+
+#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a
+ * bus error */
+#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */
+#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */
+
+/* ARM MPC interrupt */
+#define MPC_SIE200_INT_EN 1UL
+#define MPC_SIE200_INT_STAT 1UL
+
+/* ARM MPC state definitions */
+#define MPC_SIE200_INITIALIZED (1 << 0)
+
+/* Error code returned by the internal driver functions */
+enum mpc_sie200_intern_error_t{
+ MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE,
+ MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE,
+ MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED,
+ MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE,
+ MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE =
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE,
+ /* Calculated block index
+ is higher than the maximum allowed by the MPC. It should never
+ happen unless the controlled ranges of the MPC are misconfigured
+ in the driver or if the IP has not enough LUTs to cover the
+ range, due to wrong reported block size for example.
+ */
+ MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1,
+
+};
+
+/* ARM MPC memory mapped register access structure */
+struct mpc_sie200_reg_map_t {
+ volatile uint32_t ctrl; /* (R/W) MPC Control */
+ volatile uint32_t reserved[3];/* Reserved */
+ volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */
+ volatile uint32_t blk_cfg; /* (R/ ) Block configuration */
+ volatile uint32_t blk_idx; /* (R/W) Index value for accessing block
+ * based look up table */
+ volatile uint32_t blk_lutn; /* (R/W) Block based gating
+ * Look Up Table (LUT) */
+ volatile uint32_t int_stat; /* (R/ ) Interrupt state */
+ volatile uint32_t int_clear; /* ( /W) Interrupt clear */
+ volatile uint32_t int_en; /* (R/W) Interrupt enable */
+ volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */
+ volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */
+ volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */
+ volatile uint32_t reserved2[997]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */
+ volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */
+ volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/*
+ * Checks if the address is controlled by the MPC and returns
+ * the range index in which it is contained.
+ *
+ * \param[in] dev MPC device to initalize \ref mpc_sie200_dev_t
+ * \param[in] addr Address to check if it is controlled by MPC.
+ * \param[out] addr_range Range index in which it is contained.
+ *
+ * \return True if the base is controller by the range list, false otherwise.
+ */
+static uint32_t is_ctrl_by_range_list(struct mpc_sie200_dev_t* dev, uint32_t addr,
+ const struct mpc_sie200_memory_range_t** addr_range)
+{
+ uint32_t i;
+ const struct mpc_sie200_memory_range_t* range;
+
+ for(i = 0; i < dev->data->nbr_of_ranges; i++) {
+ range = dev->data->range_list[i];
+ if(addr >= range->base && addr <= range->limit) {
+ *addr_range = range;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Gets the masks selecting the bits in the LUT of the MPC corresponding
+ * to the base address (included) up to the limit address (included)
+ *
+ * \param[in] mpc_dev The MPC device.
+ * \param[in] base Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[in] limit Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[out] range Memory range in which the base address and
+ * limit are.
+ * \param[out] first_word_idx Index of the first touched word in the LUT.
+ * \param[out] nr_words Number of words used in the LUT. If 1, only
+ * first_word_mask is valid and limit_word_mask
+ * must not be used.
+ * \param[out] first_word_mask First word mask in the LUT will be stored here.
+ * \param[out] limit_word_mask Limit word mask in the LUT will be stored here.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_intern_error_t
+ */
+static enum mpc_sie200_intern_error_t get_lut_masks(
+ struct mpc_sie200_dev_t* dev,
+ const uint32_t base, const uint32_t limit,
+ const struct mpc_sie200_memory_range_t** range,
+ uint32_t *first_word_idx,
+ uint32_t *nr_words,
+ uint32_t *first_word_mask,
+ uint32_t *limit_word_mask)
+{
+ const struct mpc_sie200_memory_range_t* base_range;
+ uint32_t block_size;
+ uint32_t base_block_idx;
+ uint32_t base_word_idx;
+ uint32_t blk_max;
+ const struct mpc_sie200_memory_range_t* limit_range;
+ uint32_t limit_block_idx;
+ uint32_t limit_word_idx;
+ uint32_t mask;
+ uint32_t norm_base;
+ uint32_t norm_limit;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ /*
+ * Check that the addresses are within the controlled regions
+ * of this MPC
+ */
+ if(!is_ctrl_by_range_list(dev, base, &base_range) ||
+ !is_ctrl_by_range_list(dev, limit, &limit_range)) {
+ return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE;
+ }
+
+ /* Base and limit should be part of the same range */
+ if(base_range != limit_range) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+ *range = base_range;
+
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ /* Base and limit+1 addresses must be aligned on the MPC block size */
+ if(base % block_size || (limit+1) % block_size) {
+ return MPC_SIE200_INTERN_ERR_NOT_ALIGNED;
+ }
+
+ /*
+ * Get a normalized address that is an offset from the beginning
+ * of the lowest range controlled by the MPC
+ */
+ norm_base = (base - base_range->base);
+ norm_limit = (limit - base_range->base);
+
+ /*
+ * Calculate block index and to which 32 bits word it belongs
+ */
+ limit_block_idx = norm_limit/block_size;
+ limit_word_idx = limit_block_idx/32;
+
+ base_block_idx = norm_base/block_size;
+ base_word_idx = base_block_idx/32;
+
+ if(base_block_idx > limit_block_idx) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+
+ /* Transmit the information to the caller */
+ *nr_words = limit_word_idx - base_word_idx + 1;
+ *first_word_idx = base_word_idx;
+
+ /* Limit to the highest block that can be configured */
+ blk_max = p_mpc->blk_max;
+
+ if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) {
+ return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH;
+ }
+
+ /*
+ * Create the mask for the first word to only select the limit N bits
+ */
+ *first_word_mask = ~((1 << (base_block_idx % 32)) - 1);
+
+ /*
+ * Create the mask for the limit word to select only the first M bits.
+ */
+ *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1;
+ /*
+ * If limit_word_mask is 0, it means that the limit touched block index is
+ * the limit in its word, so the limit word mask has all its bits selected
+ */
+ if(*limit_word_mask == 0) {
+ *limit_word_mask = 0xFFFFFFFF;
+ }
+
+ /*
+ * If the blocks to configure are all packed in one word, only
+ * touch this word.
+ * Code using the computed masks should test if this mask
+ * is non-zero, and if so, only use this one instead of the limit_word_mask
+ * and first_word_mask.
+ * As the only bits that are the same in both masks are the 1 that we want
+ * to select, just use XOR to extract them.
+ */
+ if(base_word_idx == limit_word_idx) {
+ mask = ~(*first_word_mask ^ *limit_word_mask);
+ *first_word_mask = mask;
+ *limit_word_mask = mask;
+ }
+
+ return MPC_SIE200_INTERN_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges)
+{
+ if((range_list == NULL) || (nbr_of_ranges == 0)) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ dev->data->range_list = range_list;
+ dev->data->nbr_of_ranges = nbr_of_ranges;
+ dev->data->state = MPC_SIE200_INITIALIZED;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(blk_size == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /* Calculate the block size in byte according to the manual */
+ *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr)
+{
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_mask;
+ uint32_t limit_word_idx;
+ uint32_t nr_words;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ /* Sanity check to make sure the given range is within this MPCs range */
+ if ((dev->data->range_list[attr]->base > base) ||
+ (dev->data->range_list[attr]->limit < limit) ) {
+ return MPC_SIE200_ERR_NOT_IN_RANGE;
+ }
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx + nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to a generic errpr */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /*
+ * The memory range should allow accesses in with the wanted security
+ * attribute if it requires special attribute for successfull accesses
+ */
+ if(range->attr != attr) {
+ return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ }
+
+ /*
+ * Starts changing actual configuration so issue DMB to ensure every
+ * transaction has completed by now
+ */
+ __DMB();
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* First word */
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ /* Partially configure the first word */
+ p_mpc->blk_lutn = word_value;
+
+ /* Fully configure the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ p_mpc->blk_lutn = 0xFFFFFFFF;
+ } else {
+ p_mpc->blk_lutn = 0x00000000;
+ }
+ }
+
+ /* Partially configure the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= limit_word_mask;
+ } else {
+ word_value &= ~limit_word_mask;
+ }
+ p_mpc->blk_idx = limit_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base, uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr)
+{
+ enum mpc_sie200_sec_attr_t attr_prev;
+ uint32_t block_size;
+ uint32_t block_size_mask;
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_idx;
+ uint32_t limit_word_mask;
+ uint32_t nr_words;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(attr == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /*
+ * Initialize the security attribute to mixed in case of early
+ * termination of this function. A caller that does not check the
+ * returned error will act as if it does not know anything about the
+ * region queried, which is the safest bet
+ */
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+
+ /*
+ * If the base and limit are not aligned, align them and make sure
+ * that the resulting region fully includes the original region
+ */
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ block_size_mask = block_size - 1;
+ base &= ~(block_size_mask);
+ limit &= ~(block_size_mask);
+ limit += block_size - 1; /* Round to the upper block address,
+ * and then remove one to get the preceding
+ * address.
+ */
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx+nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to generic error */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ word_value &= first_word_mask;
+ if(word_value == 0) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ /*
+ * If there are differences between the mask and the word value,
+ * it means that the security attributes of blocks are mixed
+ */
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* Get the partial configuration of the first word */
+ word_value = p_mpc->blk_lutn & first_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ /*
+ * Bail out as the security attribute will be the same regardless
+ * of the configuration of other blocks
+ */
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ /*
+ * Store the current found attribute, to check that all the blocks indeed
+ * have the same security attribute.
+ */
+ attr_prev = *attr;
+
+ /* Get the configuration of the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ word_value = p_mpc->blk_lutn;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value == 0xFFFFFFFF) {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* If the attribute is different than the one found before, bail out */
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+ attr_prev = *attr;
+ }
+
+ /* Get the partial configuration of the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn & limit_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(ctrl_val == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ *ctrl_val = p_mpc->ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl = mpc_ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(sec_rep == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) {
+ *sec_rep = MPC_SIE200_RESP_BUS_ERROR;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ *sec_rep = MPC_SIE200_RESP_RAZ_WI;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->int_en |= MPC_SIE200_INT_EN;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_en &= ~MPC_SIE200_INT_EN;
+}
+
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_clear = MPC_SIE200_INT_EN;
+}
+
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ return (p_mpc->int_stat & MPC_SIE200_INT_STAT);
+}
+
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT
+ | MPC_SIE200_CTRL_SEC_LOCK_DOWN);
+
+ return MPC_SIE200_ERR_NONE;
+}
diff --git a/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.h b/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.h
new file mode 100644
index 0000000..02bd1d9
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/mpc_sie200_drv.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file mpc_sie200_drv.h
+ * \brief Generic driver for ARM SIE 200 Memory Protection
+ * Controllers (MPC).
+ */
+
+#ifndef __MPC_SIE_200_DRV_H__
+#define __MPC_SIE_200_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Error code returned by the driver functions */
+enum mpc_sie200_error_t {
+ MPC_SIE200_ERR_NONE, /*!< No error */
+ MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */
+ MPC_SIE200_NOT_INIT, /*!< MPC not initialized */
+ MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range
+ * controlled by the MPC */
+ MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size
+ * of this MPC */
+ MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure
+ * is invalid. This could be because:
+ * - The base and limit swapped
+ * - The base and limit addresses
+ * are in different ranges */
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be
+ * accessed with the wanted
+ * security attributes */
+};
+
+/* Security attribute used in various place of the API */
+enum mpc_sie200_sec_attr_t {
+ MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */
+ MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */
+ /*!< Used when getting the configuration of a memory range and some blocks
+ * are secure whereas some other are non secure */
+ MPC_SIE200_SEC_ATTR_MIXED,
+};
+
+/* What can happen when trying to do an illegal memory access */
+enum mpc_sie200_sec_resp_t {
+ MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */
+ MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */
+};
+
+/* Description of a memory range controlled by the MPC */
+struct mpc_sie200_memory_range_t {
+ const uint32_t base; /*!< Base address (included in the range) */
+ const uint32_t limit; /*!< Limit address (excluded in the range) */
+ const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute
+ needed to be matched when
+ accessing this range.
+ For example, the non-secure
+ alias of a memory region can not
+ be accessed using secure access,
+ and configuring the MPC to
+ secure using that range will not
+ be permitted by the driver. */
+};
+
+/* ARM MPC SIE 200 device configuration structure */
+struct mpc_sie200_dev_cfg_t {
+ const uint32_t base; /*!< MPC base address */
+};
+
+/* ARM MPC SIE 200 device data structure */
+struct mpc_sie200_dev_data_t {
+ const struct mpc_sie200_memory_range_t** range_list; /*!< Array of pointers
+ to memory ranges
+ controlled by
+ the MPC */
+ uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */
+ uint8_t state; /*!< Indicates if the MPC driver
+ is initialized and enabled */
+ uint16_t reserved; /*!< 32 bits alignment */
+};
+
+/* ARM MPC SIE 200 device structure */
+struct mpc_sie200_dev_t {
+ const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */
+ struct mpc_sie200_dev_data_t* const data; /*!< MPC data */
+};
+
+/**
+ * \brief Initializes a MPC device.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] range_list List of memory ranges controller by the MPC
+ * (\ref mpc_sie200_memory_range_t). This list can not
+ * freed after the initializations.
+ * \param[in] nbr_of_ranges Number of memory ranges
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges);
+
+/**
+ * \brief Gets MPC block size. All regions must be aligned on this block
+ * size (base address and limit+1 address).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] blk_size MPC block size
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size);
+
+/**
+ * \brief Configures a memory region (base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to poll. This bound is
+ * included. It does not need to be aligned in any way.
+ *
+ * \param[in] limit Limit address of the region to poll. This bound is
+ * included. (limit+1) does not need to be aligned
+ * in any way.
+ * \param[in] attr Security attribute of the region. If the region has mixed
+ * secure/non-secure, a special value is returned
+ * (\ref mpc_sie200_sec_attr_t).
+ *
+ * In case base and limit+1 addresses are not aligned on
+ * the block size, the enclosing region with base and
+ * limit+1 aligned on block size will be queried.
+ * In case of early termination of the function (error), the
+ * security attribute will be set to MPC_SIE200_ATTR_MIXED.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr);
+
+/**
+ * \brief Gets a memory region configuration(base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to get the configuration.
+ * \param[in] limit Limit address of the region to get the configuration.
+ * \param[out] attr Security attribute of the region
+ * \ref mpc_sie200_sec_attr_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base,
+ uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr);
+
+/**
+ * \brief Gets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] ctrl_val Current MPC control value.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val);
+
+/**
+ * \brief Sets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] mpc_ctrl New MPC control value
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl);
+
+/**
+ * \brief Gets the configured secure response.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t).
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep);
+
+/**
+ * \brief Enables MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Disables MPC interrupt
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Clears MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Returns the MPC interrupt state.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Locks down the MPC configuration.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MPC_SIE_200_DRV_H__ */
diff --git a/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.c b/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.c
new file mode 100644
index 0000000..8db96e2
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ppc_sse200_drv.h"
+
+/* SPCTRL PPCs control memory mapped registers access structure */
+struct arm_spctrl_ppc_sse200_t {
+ volatile uint32_t reserved[8];
+ volatile uint32_t secppcintstat; /* Secure PPC Interrupt Status */
+ volatile uint32_t secppcintclr; /* Secure PPC Interrupt Clear */
+ volatile uint32_t secppcinten; /* Secure PPC Interrupt Enable */
+ volatile uint32_t reserved1[9];
+ volatile uint32_t ahbnsppc0; /* Non-Secure Access AHB slave Peripheral
+ Protection Control #0 */
+ volatile uint32_t reserved2[3]; /* Reserved for Future Non-secure Access
+ AHB Slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbnsppcexp0; /* Expansion 0 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp1; /* Expansion 1 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp2; /* Expansion 2 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp3; /* Expansion 3 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppc0; /* Non-Secure Access APB slave Peripheral
+ Protection Control 0 */
+ volatile uint32_t apbnsppc1; /* Non-Secure Access APB slave Peripheral
+ Protection Control 1 */
+ volatile uint32_t reserved3[2]; /* Non-Secure Access APB slave Peripheral
+ Protection Control [3:1] */
+ volatile uint32_t apbnsppcexp0; /* Expansion 0 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp1; /* Expansion 1 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp2; /* Expansion 2 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp3; /* Expansion 3 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbspppc0; /* Secure Unprivileged Access AHB slave
+ Peripheral Protection Control 0 */
+ volatile uint32_t reserved4[3]; /* Reserved for Future Secure Unprivileged
+ Access AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppc0; /* Secure Unprivileged Access APB slave
+ Peripheral 0 */
+ volatile uint32_t apbspppc1; /* Secure Unprivileged Access APB slave
+ Peripheral 1 */
+ volatile uint32_t reserved5[2]; /* Reserved for Future Secure Unprivileged
+ Access APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+};
+
+/* NSPCTRL PPCs memory mapped register access structure */
+struct arm_nspctrl_ppc_sse200_t {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved1[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved2[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+};
+
+/* PPC interrupt position mask */
+#define APB_PPC0_INT_POS_MASK (1UL << 0)
+#define APB_PPC1_INT_POS_MASK (1UL << 1)
+/* Reseved bits 2:3 */
+#define APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+/* Reseved bits 8:15 */
+#define AHB_PPC0_INT_POS_MASK (1UL << 16)
+/* Reseved bits 17:19 */
+#define AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+/* Reseved bits 24:31 */
+
+/* ARM PPC state definitions */
+#define PPC_SSE200_INITIALIZED (1 << 0)
+
+/* Default peripheral states */
+#define SECURE_AS_DEFAULT_PERIPHERAL_STATE 1
+#define PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE 1
+
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+ struct arm_nspctrl_ppc_sse200_t* p_nspctrl =
+ (struct arm_nspctrl_ppc_sse200_t*)dev->cfg->nspctrl_base;
+
+ switch(ppc_name) {
+ case AHB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppc0;
+ dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp0;
+ dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp1;
+ dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp2;
+ dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp3;
+ dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK;
+ break;
+ case APB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc0;
+ dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK;
+ break;
+ case APB_PPC1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc1;
+ dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp0;
+ dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp1;
+ dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp2;
+ dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp3;
+ dev->data->int_bit_mask = APB_PPCEXP3_INT_POS_MASK;
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+
+ dev->data->state = PPC_SSE200_INITIALIZED;
+}
+
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ if(sec_attr == PPC_SSE200_SECURE_ONLY) {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) &= ~(1U << periph);
+
+ /* Uses secure unprivileged access address (SPCTRL) to set privilege
+ * attribute */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_sp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_sp_ppc) |= (1U << periph);
+ }
+ } else {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) |= (1U << periph);
+
+ /* Uses non-secure unprivileged access address (NSPCTRL) to set
+ * privilege attribute */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_nsp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_nsp_ppc) |= (1U << periph);
+ }
+ }
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return SECURE_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ return ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0);
+}
+
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ if ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0) {
+ /* Returns secure unprivileged access address (SPCTRL) */
+ return ((*(dev->data->p_sp_ppc) & (1U << periph)) == 0);
+ } else {
+ /* Returns non-secure unprivileged access address (NSPCTRL) */
+ return ((*(dev->data->p_nsp_ppc) & (1U << periph)) == 0);
+ }
+}
+
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ p_spctrl->secppcinten |= dev->data->int_bit_mask;
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcinten &= ~(dev->data->int_bit_mask);
+ }
+}
+
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcintclr = dev->data->int_bit_mask;
+ }
+}
+
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return 0;
+ }
+
+ return ((p_spctrl->secppcintstat & dev->data->int_bit_mask) != 0);
+}
diff --git a/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h b/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h
new file mode 100644
index 0000000..4ac0afa
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/ppc_sse200_drv.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file ppc_sse200_drv.h
+ * \brief Generic driver for ARM SEE 200 Peripheral Protection
+ * Controllers (PPC).
+ */
+
+#ifndef __PPC_SSE_200_DRV_H__
+#define __PPC_SSE_200_DRV_H__
+
+#include <stdint.h>
+
+/* Secure Privilege Control Block aka SPCTRL */
+/* Non-Secure Privilege Control Block aka NSPCTRL */
+
+/* ARM TrustZone PPC device configuration structure */
+struct ppc_sse200_dev_cfg_t {
+ uint32_t const spctrl_base; /*!< SPCTRL base address */
+ uint32_t const nspctrl_base; /*!< NSPCTRL base address */
+};
+
+/* ARM TrustZone PPC device data structure */
+struct ppc_sse200_dev_data_t {
+ volatile uint32_t* p_ns_ppc; /*!< Pointer to non-secure register */
+ volatile uint32_t* p_sp_ppc; /*!< Pointer to secure unprivileged
+ register */
+ volatile uint32_t* p_nsp_ppc; /*!< Pointer to non-secure unprivileged
+ register */
+ uint32_t int_bit_mask; /*!< Interrupt bit mask */
+ uint8_t state; /*!< Indicates if the PPC driver
+ is initialized */
+ uint8_t reserved[3]; /*!< 32 bits alignment */
+};
+
+/* ARM PPC device structure */
+struct ppc_sse200_dev_t {
+ const struct ppc_sse200_dev_cfg_t* const cfg; /*!< PPC configuration */
+ struct ppc_sse200_dev_data_t* const data; /*!< PPC data */
+};
+
+/* Security attribute used to configure the peripheral */
+enum ppc_sse200_sec_attr_t {
+ PPC_SSE200_SECURE_ONLY, /*! Secure access */
+ PPC_SSE200_NONSECURE_ONLY, /*! Non-secure access */
+};
+
+/* Privilege attribute used to configure the peripheral */
+enum ppc_sse200_priv_attr_t {
+ PPC_SSE200_PRIV_AND_NONPRIV, /*! Privilege and non-Privilege access */
+ PPC_SSE200_PRIV_ONLY, /*! Privilege only access */
+};
+
+/* ARM PPC error codes */
+enum ppc_sse200_error_t {
+ PPC_SSE200_ERR_NONE = 0, /*!< No error */
+ PPC_SSE200_NOT_INIT, /*!< PPC not initialized */
+};
+
+/* ARM PPC names */
+enum ppc_sse200_name_t {
+ AHB_PPC0 = 0, /*!< AHB PPC0 */
+ AHB_PPC_EXP0, /*!< Expansion 0 AHB PPC */
+ AHB_PPC_EXP1, /*!< Expansion 1 AHB PPC */
+ AHB_PPC_EXP2, /*!< Expansion 2 AHB PPC */
+ AHB_PPC_EXP3, /*!< Expansion 3 AHB PPC */
+ APB_PPC0, /*!< APB PPC0 */
+ APB_PPC1, /*!< APB PPC1 */
+ APB_PPC_EXP0, /*!< Expansion 0 AHB PPC */
+ APB_PPC_EXP1, /*!< Expansion 1 AHB PPC */
+ APB_PPC_EXP2, /*!< Expansion 2 AHB PPC */
+ APB_PPC_EXP3 /*!< Expansion 3 AHB PPC */
+};
+
+/**
+ * \brief Initialize the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] ppc_name PPC name \ref ppc_sse200_name_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name);
+
+/**
+ * \brief Configures the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ * \param[in] sec_attr Secure attribute value.
+ * \param[in] priv_attr Privilege attribute value.
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr);
+/**
+ * \brief Checks if the peripheral is configured as secure or non-secure.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for secure and 0 for non-secure.
+ * If the driver is not initalized the return value is 1 (secure) as
+ * it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+
+/**
+ * \brief Checks if the peripheral is configured as Privilege only or
+ * Privilege and non-Privilege access mode.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for Privilege only configuration and 0 for Privilege and
+ * non-Privilege access.
+ * If the driver is not initalized the return of this function is
+ * 1 (Privilege only) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+/**
+ * \brief Enables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Disables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Clears PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Returns the PPC interrupt state.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active and otherwise 0.
+ * If the driver is not initalized the return of this function is
+ * 0 (not active) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev);
+
+#endif /* __PPC_SSE_200_DRV_H__ */
diff --git a/platform/ext/target/musca_a/Native_Driver/timer_cmsdk.c b/platform/ext/target/musca_a/Native_Driver/timer_cmsdk.c
new file mode 100644
index 0000000..1037f2d
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/timer_cmsdk.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk.c
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#include "timer_cmsdk.h"
+
+/** Setter bit manipulation macro */
+#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
+/** Clearing bit manipulation macro */
+#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
+/** Getter bit manipulation macro */
+#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
+
+/**
+ * \brief Timer register map structure
+ *
+ */
+struct cmsdk_timer_reg_map_t {
+ volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */
+ volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */
+ volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */
+ union {
+ volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt
+ * status register */
+ volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt
+ * clear register */
+ }intreg;
+};
+
+/**
+ * \brief CTRL register bit definitions
+ *
+ */
+enum ctrl_reg_bits_t{
+ CTRL_REG_ENUM_ENABLE_INDEX = 0,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2,
+ CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3
+};
+
+/**
+ * \brief INTSTATUS/INTCLEAR register bit definitions
+ *
+ */
+enum interrupt_reg_bits_t{
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0
+};
+
+void cmsdk_timer_init(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+
+ if (dev->data->is_initialized == 0) {
+ register_map->ctrl = 0;
+ register_map->reload = CMSDK_TIMER_DEFAULT_RELOAD;
+ dev->data->is_initialized = 1;
+ }
+}
+
+bool cmsdk_timer_is_initialized(const struct cmsdk_timer_dev_t* dev)
+{
+ return dev->data->is_initialized;
+}
+
+void cmsdk_timer_enable_external_input(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable_external_input(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_external_input_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void cmsdk_timer_set_clock_to_internal(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void cmsdk_timer_set_clock_to_external(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+bool cmsdk_timer_is_clock_external(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void cmsdk_timer_enable(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void cmsdk_timer_enable_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_interrupt_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_interrupt_active(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->intreg.intstatus,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+void cmsdk_timer_clear_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->intreg.intclear,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+uint32_t cmsdk_timer_get_current_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->value;
+}
+
+void cmsdk_timer_set_reload_value(const struct cmsdk_timer_dev_t* dev,
+ uint32_t reload)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ register_map->reload = reload;
+}
+
+void cmsdk_timer_reset(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ register_map->value = register_map->reload;
+}
+
+uint32_t cmsdk_timer_get_reload_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->reload;
+}
+
+uint32_t cmsdk_timer_get_elapsed_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->reload - register_map->value;
+}
diff --git a/platform/ext/target/musca_a/Native_Driver/timer_cmsdk.h b/platform/ext/target/musca_a/Native_Driver/timer_cmsdk.h
new file mode 100644
index 0000000..52d9d5c
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/timer_cmsdk.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk.h
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#ifndef __CMSDK_TIMER_DRV_H__
+#define __CMSDK_TIMER_DRV_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Maximum reload value */
+#define CMSDK_TIMER_MAX_RELOAD INT32_MAX /* max of 32-bit */
+#define CMSDK_TIMER_DEFAULT_RELOAD CMSDK_TIMER_MAX_RELOAD
+
+/** CMSDK timer device configuration structure */
+struct cmsdk_timer_dev_cfg_t {
+ const uintptr_t base; /*!< Timer base address */
+};
+
+/** CMSDK timer device data structure */
+struct cmsdk_timer_dev_data_t {
+ bool is_initialized; /*!< Indicates if the timer is initialized */
+};
+
+/* CMSDK timer device structure */
+struct cmsdk_timer_dev_t {
+ const struct cmsdk_timer_dev_cfg_t* const cfg; /*!< Timer configuration */
+ struct cmsdk_timer_dev_data_t* const data; /*!< Timer data */
+};
+
+/**
+ * \brief Initializes timer to a known default state, which is:
+ * - timer disabled
+ * - timer interrupt disabled
+ * - clock source set to internal
+ * - external input disabled
+ * - reload value maxed out
+ * Init should be called prior to any other process and
+ * it's the caller's responsibility to follow proper call order.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_init(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is initialized.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if initialized, false otherwise
+ */
+bool cmsdk_timer_is_initialized(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables external input, which could be used as clock source
+ * by calling \ref cmsdk_timer_set_clock_to_external.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable_external_input(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables external input.
+ * Make sure if the timer is explicitly wanted to be stopped or set
+ * the clock source to internal by \ref cmsdk_timer_set_clock_to_internal.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable_external_input(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if external input is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_external_input_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to internal.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_set_clock_to_internal(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to external.
+ * Make sure external input is enabled correspondingly
+ * by \ref cmsdk_timer_enable_external_input.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_set_clock_to_external(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if clock source is external input.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if external, false if internal
+ */
+bool cmsdk_timer_is_clock_external(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables timer operation.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables the given hardware timer.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer interrupt is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_interrupt_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Gets timer interrupt status
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * * \return true if active, false otherwise
+ */
+bool cmsdk_timer_is_interrupt_active(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Clears timer interrupt
+ * The interrupt request is held until it is cleared.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_clear_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Reads timer current value.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Timer value
+ */
+uint32_t cmsdk_timer_get_current_value(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the reload value of the selected timer.
+ *
+ * New reload value takes effect when:
+ * - timer is restarted
+ * - on timer underflow
+ * - when cmsdk_timer_reset is called
+ *
+ * \note In r1p0 technical reference manual it's incorrectly stated
+ * writing the reload value automatically sets the current value also.
+ * r1p1 technical reference manual includes the fix.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ * \param[in] reload Timer reload value to set.
+ * This is the start value of the 32-bit down counter,
+ * which automatically reloaded if 0 is reached.
+ */
+void cmsdk_timer_set_reload_value(const struct cmsdk_timer_dev_t* dev,
+ uint32_t reload);
+
+/**
+ * \brief Resets the timer counter to the reload value instantly
+ * (i.e. without waiting for underflow).
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_reset(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Gets the reload value of the selected timer.
+ * This is the start value of the 32-bit down counter,
+ * which is automatically reloaded if 0 is reached by the counter.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Reload value of the selected timer.
+ */
+uint32_t cmsdk_timer_get_reload_value(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Reads the number of ticks elapsed in the current cycle.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Get elapsed number of ticks since last reload was set.
+ * Elapsed = (Reload value - Current value)
+ */
+uint32_t cmsdk_timer_get_elapsed_value(const struct cmsdk_timer_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CMSDK_TIMER_DRV_H__ */
diff --git a/platform/ext/target/musca_a/Native_Driver/uart_pl011_drv.c b/platform/ext/target/musca_a/Native_Driver/uart_pl011_drv.c
new file mode 100755
index 0000000..71dcab0
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/uart_pl011_drv.c
@@ -0,0 +1,977 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "uart_pl011_drv.h"
+
+#include <stddef.h>
+#include <cmsis.h>
+
+#define FREQ_IRLPBAUD16_MIN (1420000u) /* 1.42 MHz */
+#define FREQ_IRLPBAUD16_MAX (2120000u) /* 2.12 MHz */
+#define SAMPLING_FACTOR (16u)
+#define UART_PL011_FBRD_WIDTH (6u)
+
+/**
+ * \brief UART PL011 register map structure
+ */
+struct _uart_pl011_reg_map_t {
+ volatile uint32_t uartdr; /*!< Offset: 0x000 (R/W) Data register */
+ union {
+ volatile uint32_t uartrsr;
+ /*!< Offset: 0x004 (R/ ) Receive status register */
+ volatile uint32_t uartecr;
+ /*!< Offset: 0x004 ( /W) Error clear register */
+ };
+ volatile uint32_t reserved_0[4]; /*!< Offset: 0x008-0x014 Reserved */
+ volatile uint32_t uartfr; /*!< Offset: 0x018 (R/ ) Flag register */
+ volatile uint32_t reserved_1; /*!< Offset: 0x01C Reserved */
+ volatile uint32_t uartilpr;
+ /*!< Offset: 0x020 (R/W) IrDA low-power counter register */
+ volatile uint32_t uartibrd;
+ /*!< Offset: 0x024 (R/W) Integer baud rate register */
+ volatile uint32_t uartfbrd;
+ /*!< Offset: 0x028 (R/W) Fractional baud rate register */
+ volatile uint32_t uartlcr_h;
+ /*!< Offset: 0x02C (R/W) Line control register */
+ volatile uint32_t uartcr;
+ /*!< Offset: 0x030 (R/W) Control register */
+ volatile uint32_t uartifls;
+ /*!< Offset: 0x034 (R/W) Interrupt FIFO level select register */
+ volatile uint32_t uartimsc;
+ /*!< Offset: 0x038 (R/W) Interrupt mask set/clear register */
+ volatile uint32_t uartris;
+ /*!< Offset: 0x03C (R/ ) Raw interrupt status register */
+ volatile uint32_t uartmis;
+ /*!< Offset: 0x040 (R/ ) Masked interrupt status register */
+ volatile uint32_t uarticr;
+ /*!< Offset: 0x044 ( /W) Interrupt clear register */
+ volatile uint32_t uartdmacr;
+ /*!< Offset: 0x048 (R/W) DMA control register */
+ volatile uint32_t reserved_2[13]; /*!< Offset: 0x04C-0x07C Reserved */
+ volatile uint32_t reserved_3[4];
+ /*!< Offset: 0x080-0x08C Reserved for test purposes */
+ volatile uint32_t reserved_4[976]; /*!< Offset: 0x090-0xFCC Reserved */
+ volatile uint32_t reserved_5[4];
+ /*!< Offset: 0xFD0-0xFDC Reserved for future ID expansion */
+ volatile uint32_t uartperiphid0;
+ /*!< Offset: 0xFE0 (R/ ) UARTPeriphID0 register */
+ volatile uint32_t uartperiphid1;
+ /*!< Offset: 0xFE4 (R/ ) UARTPeriphID1 register */
+ volatile uint32_t uartperiphid2;
+ /*!< Offset: 0xFE8 (R/ ) UARTPeriphID2 register */
+ volatile uint32_t uartperiphid3;
+ /*!< Offset: 0xFEC (R/ ) UARTPeriphID3 register */
+ volatile uint32_t uartpcellid0;
+ /*!< Offset: 0xFF0 (R/ ) UARTPCellID0 register */
+ volatile uint32_t uartpcellid1;
+ /*!< Offset: 0xFF4 (R/ ) UARTPCellID1 register */
+ volatile uint32_t uartpcellid2;
+ /*!< Offset: 0xFF8 (R/ ) UARTPCellID2 register */
+ volatile uint32_t uartpcellid3;
+ /*!< Offset: 0xFFC (R/ ) UARTPCellID3 register */
+};
+
+#define UART_PL011_UARTFR_CTS_MASK ( \
+ 0x1u<<UART_PL011_UARTFR_CTS_OFF)
+#define UART_PL011_UARTFR_DSR_MASK ( \
+ 0x1u<<UART_PL011_UARTFR_DSR_OFF)
+#define UART_PL011_UARTFR_DCD_MASK ( \
+ 0x1u<<UART_PL011_UARTFR_DCD_OFF)
+#define UART_PL011_UARTFR_BUSYBIT ( \
+ 0x1u<<UART_PL011_UARTFR_BUSYBIT_OFF)
+#define UART_PL011_UARTFR_RX_FIFO_EMPTY ( \
+ 0x1u<<UART_PL011_UARTFR_RX_FIFO_EMPTY_OFF)
+#define UART_PL011_UARTFR_TX_FIFO_FULL ( \
+ 0x1u<<UART_PL011_UARTFR_TX_FIFO_FULL_OFF)
+#define UART_PL011_UARTFR_RI_MASK ( \
+ 0x1u<<UART_PL011_UARTFR_RI_OFF)
+
+#define UART_PL011_UARTLCR_H_BRK_MASK ( \
+ 0x1u<<UART_PL011_UARTLCR_H_BRK_OFF)
+#define UART_PL011_UARTLCR_H_PARITY_MASK ( \
+ 0x1u<<UART_PL011_UARTLCR_H_PEN_OFF \
+ | 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF \
+ | 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF)
+#define UART_PL011_UARTLCR_H_STOPBIT_MASK ( \
+ 0x1u<<UART_PL011_UARTLCR_H_STP2_OFF)
+#define UART_PL011_UARTLCR_H_FEN_MASK ( \
+ 0x1u<<UART_PL011_UARTLCR_H_FEN_OFF)
+#define UART_PL011_UARTLCR_H_WLEN_MASK ( \
+ 0x3u<<UART_PL011_UARTLCR_H_WLEN_OFF)
+#define UART_PL011_FORMAT_MASK ( \
+ UART_PL011_UARTLCR_H_PARITY_MASK \
+ | UART_PL011_UARTLCR_H_STOPBIT_MASK \
+ | UART_PL011_UARTLCR_H_WLEN_MASK)
+
+#define UART_PL011_UARTCR_EN_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_UARTEN_OFF)
+#define UART_PL011_UARTCR_SIREN_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_SIREN_OFF)
+#define UART_PL011_UARTCR_SIRLP_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_SIRLP_OFF)
+#define UART_PL011_UARTCR_LBE_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_LBE_OFF)
+#define UART_PL011_UARTCR_TX_EN_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_TXE_OFF)
+#define UART_PL011_UARTCR_RX_EN_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_RXE_OFF)
+#define UART_PL011_UARTCR_DTR_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_DTR_OFF)
+#define UART_PL011_UARTCR_RTS_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_RTS_OFF)
+#define UART_PL011_UARTCR_OUT1_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_OUT1_OFF)
+#define UART_PL011_UARTCR_OUT2_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_OUT2_OFF)
+#define UART_PL011_UARTCR_RTSE_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_RTSE_OFF)
+#define UART_PL011_UARTCR_CTSE_MASK ( \
+ 0x1u<<UART_PL011_UARTCR_CTSE_OFF)
+
+#define UART_PL011_UARTIFLS_TX_FIFO_LVL_MASK ( \
+ 0x7u<<UART_PL011_UARTIFLS_TX_OFF)
+#define UART_PL011_UARTIFLS_RX_FIFO_LVL_MASK ( \
+ 0x7u<<UART_PL011_UARTIFLS_RX_OFF)
+
+#define UART_PL011_UARTDMACR_RX_MASK ( \
+ 0x1u<<UART_PL011_UARTDMACR_RXEN_OFF \
+ | 0x1u<<UART_PL011_UARTDMACR_ON_ERR_OFF)
+#define UART_PL011_UARTDMACR_TX_MASK ( \
+ 0x1u<<UART_PL011_UARTDMACR_TXEN_OFF)
+
+static void _uart_pl011_enable(struct _uart_pl011_reg_map_t* p_uart)
+{
+ p_uart->uartcr |= UART_PL011_UARTCR_EN_MASK;
+}
+
+static void _uart_pl011_disable(struct _uart_pl011_reg_map_t* p_uart)
+{
+ p_uart->uartcr &= ~UART_PL011_UARTCR_EN_MASK;
+}
+
+static bool _uart_pl011_is_enabled(struct _uart_pl011_reg_map_t* p_uart)
+{
+ return (bool)(p_uart->uartcr & UART_PL011_UARTCR_EN_MASK);
+}
+
+static void _uart_pl011_enable_fifo(struct _uart_pl011_reg_map_t* p_uart)
+{
+ p_uart->uartlcr_h |= UART_PL011_UARTLCR_H_FEN_MASK;
+}
+
+static void _uart_pl011_disable_fifo(struct _uart_pl011_reg_map_t* p_uart)
+{
+ p_uart->uartlcr_h &= ~UART_PL011_UARTLCR_H_FEN_MASK;
+}
+
+static bool _uart_pl011_is_fifo_enabled(struct _uart_pl011_reg_map_t* p_uart)
+{
+ return (bool)(p_uart->uartlcr_h & UART_PL011_UARTLCR_H_FEN_MASK);
+}
+
+static enum uart_pl011_error_t _uart_pl011_set_baudrate(
+ struct _uart_pl011_reg_map_t* p_uart,
+ uint32_t clk, uint32_t baudrate)
+{
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+ uint64_t bauddiv = (((uint64_t)clk)<<UART_PL011_FBRD_WIDTH)
+ /(SAMPLING_FACTOR*baudrate);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+ if((bauddiv < (1u<<UART_PL011_FBRD_WIDTH))
+ || (bauddiv > (65535u<<UART_PL011_FBRD_WIDTH))) {
+ return UART_PL011_ERR_INVALID_BAUD;
+ }
+
+ p_uart->uartibrd = (uint32_t)(bauddiv >> UART_PL011_FBRD_WIDTH);
+ p_uart->uartfbrd = (uint32_t)(bauddiv &
+ ((1u << UART_PL011_FBRD_WIDTH) - 1u));
+
+ __DMB();
+
+ /* In order to internally update the contents of uartibrd or uartfbrd, a
+ * uartlcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+ p_uart->uartlcr_h = p_uart->uartlcr_h;
+
+ return UART_PL011_ERR_NONE;
+}
+
+static void _uart_pl011_set_format(struct _uart_pl011_reg_map_t* p_uart,
+ enum uart_pl011_wlen_t word_len,
+ enum uart_pl011_parity_t parity,
+ enum uart_pl011_stopbit_t stop_bits)
+{
+ uint32_t ctrl_reg = p_uart->uartlcr_h & ~(UART_PL011_FORMAT_MASK);
+
+ /* Making sure other bit are not changed */
+ word_len &= UART_PL011_UARTLCR_H_WLEN_MASK;
+ parity &= UART_PL011_UARTLCR_H_PARITY_MASK;
+ stop_bits &= UART_PL011_UARTLCR_H_STOPBIT_MASK;
+
+ p_uart->uartlcr_h = ctrl_reg | word_len | parity | stop_bits;
+
+}
+
+static void _uart_pl011_set_cr_bit(struct _uart_pl011_reg_map_t* p_uart,
+ uint32_t mask)
+{
+ bool uart_enabled = _uart_pl011_is_enabled(p_uart);
+ bool fifo_enabled = _uart_pl011_is_fifo_enabled(p_uart);
+
+ /* UART must be disabled before any Control Register or
+ * Line Control Register are reprogrammed */
+ _uart_pl011_disable(p_uart);
+
+ /* Flush the transmit FIFO by disabling bit 4 (FEN) in
+ * the line control register (UARTCLR_H) */
+ _uart_pl011_disable_fifo(p_uart);
+
+ p_uart->uartcr |= (mask);
+
+ /* Enabling the FIFOs if previously enabled */
+ if(fifo_enabled) {
+ _uart_pl011_enable_fifo(p_uart);
+ }
+
+ /* Enabling the UART if previously enabled */
+ if(uart_enabled) {
+ _uart_pl011_enable(p_uart);
+ }
+}
+
+static void _uart_pl011_clear_cr_bit(struct _uart_pl011_reg_map_t* p_uart,
+ uint32_t mask)
+{
+ bool uart_enabled = _uart_pl011_is_enabled(p_uart);
+ bool fifo_enabled = _uart_pl011_is_fifo_enabled(p_uart);
+
+ /* UART must be disabled before any Control Register or
+ * Line Control Register are reprogrammed */
+ _uart_pl011_disable(p_uart);
+
+ /* Flush the transmit FIFO by disabling bit 4 (FEN) in
+ * the line control register (UARTCLR_H) */
+ _uart_pl011_disable_fifo(p_uart);
+
+ p_uart->uartcr &= ~(mask);
+
+ /* Enabling the FIFOs if previously enabled */
+ if(fifo_enabled) {
+ _uart_pl011_enable_fifo(p_uart);
+ }
+
+ /* Enabling the UART if previously enabled */
+ if(uart_enabled) {
+ _uart_pl011_enable(p_uart);
+ }
+}
+
+static void _uart_pl011_set_lcr_h_bit(struct _uart_pl011_reg_map_t* p_uart,
+ uint32_t mask)
+{
+ bool uart_enabled = _uart_pl011_is_enabled(p_uart);
+
+ /* UART must be disabled before any Control Register or
+ * Line Control Register are reprogrammed */
+ _uart_pl011_disable(p_uart);
+
+ p_uart->uartlcr_h |= (mask);
+
+ /* Enabling the UART if previously enabled */
+ if(uart_enabled) {
+ _uart_pl011_enable(p_uart);
+ }
+}
+
+static void _uart_pl011_clear_lcr_h_bit(struct _uart_pl011_reg_map_t* p_uart,
+ uint32_t mask)
+{
+ bool uart_enabled = _uart_pl011_is_enabled(p_uart);
+
+ /* UART must be disabled before any Control Register or
+ * Line Control Register are reprogrammed */
+ _uart_pl011_disable(p_uart);
+
+ p_uart->uartlcr_h &= ~(mask);
+
+ /* Enabling the UART if previously enabled */
+ if(uart_enabled) {
+ _uart_pl011_enable(p_uart);
+ }
+}
+
+enum uart_pl011_error_t uart_pl011_init(struct uart_pl011_dev_t* dev,
+ uint32_t uart_clk)
+{
+ enum uart_pl011_error_t err;
+
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ uint32_t def_baud = dev->cfg->def_baudrate;
+
+ if(uart_clk == 0) {
+ return UART_PL011_ERR_INVALID_ARG;
+ }
+
+ if(def_baud == 0) {
+ return UART_PL011_ERR_INVALID_BAUD;
+ }
+
+ /* Updating the system clock */
+ dev->data->uart_clk = uart_clk;
+
+ /* Setting the default baudrate */
+ err = _uart_pl011_set_baudrate(p_uart, uart_clk, def_baud);
+
+ if(err != UART_PL011_ERR_NONE) {
+ return err;
+ }
+
+ /* Setting the default character format */
+ _uart_pl011_set_format(p_uart, dev->cfg->def_wlen,
+ dev->cfg->def_parity,
+ dev->cfg->def_stopbit);
+
+ /* Enabling the FIFOs */
+ _uart_pl011_enable_fifo(p_uart);
+
+ dev->data->state = UART_PL011_INITIALIZED;
+
+ return UART_PL011_ERR_NONE;
+}
+
+void uart_pl011_uninit(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_disable(p_uart);
+
+ dev->data->state = UART_PL011_UNINITIALIZED;
+
+ return;
+}
+
+enum uart_pl011_state_t uart_pl011_get_state(struct uart_pl011_dev_t* dev)
+{
+ return dev->data->state;
+}
+
+enum uart_pl011_error_t uart_pl011_set_baudrate(
+ struct uart_pl011_dev_t* dev, uint32_t baudrate)
+{
+ enum uart_pl011_error_t err = UART_PL011_ERR_NONE;
+
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ bool uart_enabled = _uart_pl011_is_enabled(p_uart);
+
+ if(uart_pl011_get_state(dev) != UART_PL011_INITIALIZED) {
+ return UART_PL011_ERR_NOT_INIT;
+ }
+
+ if(baudrate == 0) {
+ return UART_PL011_ERR_INVALID_BAUD;
+ }
+
+ /* UART must be disabled before any Control Register or
+ * Line Control Register are reprogrammed */
+ _uart_pl011_disable(p_uart);
+
+ /* If baudrate is not valid ie UART_PL011_ERR_NONE is not returned then
+ * the UART will continue to function at the old baudrate */
+ err = _uart_pl011_set_baudrate(p_uart, dev->data->uart_clk, baudrate);
+
+ if(err == UART_PL011_ERR_NONE) {
+ dev->data->baudrate = baudrate;
+ }
+
+ if(uart_enabled) {
+ _uart_pl011_enable(p_uart);
+ }
+
+ return err;
+}
+
+uint32_t uart_pl011_get_baudrate(struct uart_pl011_dev_t* dev)
+{
+ return dev->data->baudrate;
+}
+
+void uart_pl011_enable_intr(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_intr_t mask)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ p_uart->uartimsc |= (uint32_t)(mask);
+
+ return;
+}
+
+void uart_pl011_disable_intr(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_intr_t mask)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ p_uart->uartimsc &= (uint32_t)(~mask);
+
+ return;
+}
+
+void uart_pl011_clear_intr(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_intr_t mask)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ p_uart->uarticr = (uint32_t)mask;
+
+ return;
+}
+
+
+enum uart_pl011_intr_t uart_pl011_get_masked_intr_status(
+ struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ return (enum uart_pl011_intr_t)(p_uart->uartmis);
+
+}
+
+enum uart_pl011_intr_t uart_pl011_get_raw_intr_status(
+ struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ return (enum uart_pl011_intr_t)(p_uart->uartris);
+}
+
+void uart_pl011_set_rx_fifo_lvl(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_rx_fifo_lvl_t rx_lvl)
+{
+ uint32_t fifo_lvl;
+
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ /* Check if rx_lvl have valid values */
+ rx_lvl &= UART_PL011_UARTIFLS_RX_FIFO_LVL_MASK;
+
+ fifo_lvl = p_uart->uartifls
+ & ~(UART_PL011_UARTIFLS_RX_FIFO_LVL_MASK);
+ p_uart->uartifls = fifo_lvl | rx_lvl;
+
+ return;
+}
+
+void uart_pl011_set_tx_fifo_lvl(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_tx_fifo_lvl_t tx_lvl)
+{
+ uint32_t fifo_lvl;
+
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+ /* Check if tx_lvl have valid values */
+ tx_lvl &= UART_PL011_UARTIFLS_TX_FIFO_LVL_MASK;
+
+ fifo_lvl = p_uart->uartifls
+ & ~(UART_PL011_UARTIFLS_TX_FIFO_LVL_MASK);
+ p_uart->uartifls = fifo_lvl | tx_lvl;
+
+ return;
+}
+
+void uart_pl011_set_tx_dma(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_tx_dma_t enable)
+{
+ uint32_t dma_cr;
+
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ enable &= UART_PL011_UARTDMACR_TX_MASK;
+
+ dma_cr = p_uart->uartdmacr
+ & ~(UART_PL011_UARTDMACR_TX_MASK);
+
+ p_uart->uartdmacr = dma_cr | enable;
+
+ return;
+}
+
+void uart_pl011_set_rx_dma(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_rx_dma_t enable)
+{
+ uint32_t dma_cr;
+
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ enable &= UART_PL011_UARTDMACR_RX_MASK;
+
+ dma_cr = p_uart->uartdmacr
+ & ~(UART_PL011_UARTDMACR_RX_MASK);
+
+ p_uart->uartdmacr = dma_cr | enable;
+
+ return;
+}
+
+bool uart_pl011_is_readable(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ if( (uart_pl011_get_state(dev) == UART_PL011_INITIALIZED) &&
+ /* UART is initialized */
+ (p_uart->uartcr & UART_PL011_UARTCR_EN_MASK) &&
+ /* UART is enabled */
+ (p_uart->uartcr & UART_PL011_UARTCR_RX_EN_MASK) &&
+ /* Receive is enabled */
+ ((p_uart->uartfr & UART_PL011_UARTFR_RX_FIFO_EMPTY) == 0)) {
+ /* Receive Fifo is not empty */
+ return true;
+ }
+
+ return false;
+
+}
+
+enum uart_pl011_error_t uart_pl011_read(
+ struct uart_pl011_dev_t* dev, uint8_t* byte)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ *byte = p_uart->uartdr;
+
+ return (enum uart_pl011_error_t)(p_uart->uartrsr
+ & UART_PL011_RX_ERR_MASK);
+}
+
+bool uart_pl011_is_writable(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ if( (uart_pl011_get_state(dev) == UART_PL011_INITIALIZED) &&
+ /* UART is initialized */
+ (p_uart->uartcr & UART_PL011_UARTCR_EN_MASK) &&
+ /* UART is enabled */
+ (p_uart->uartcr & UART_PL011_UARTCR_TX_EN_MASK) &&
+ /* Transmit is enabled */
+ ((p_uart->uartfr & UART_PL011_UARTFR_TX_FIFO_FULL) == 0)) {
+ /* Transmit Fifo is not full */
+ return true;
+ }
+ return false;
+
+}
+
+void uart_pl011_write(struct uart_pl011_dev_t* dev, uint8_t byte)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ p_uart->uartdr = byte;
+
+ return;
+}
+
+enum uart_pl011_error_t uart_pl011_set_format(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_wlen_t word_len,
+ enum uart_pl011_parity_t parity,
+ enum uart_pl011_stopbit_t stop_bits)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ bool uart_enabled = _uart_pl011_is_enabled(p_uart);
+
+ if(uart_pl011_get_state(dev) != UART_PL011_INITIALIZED) {
+ return UART_PL011_ERR_NOT_INIT;
+ }
+
+ /* UART must be disabled before any Control Register or
+ * Line Control Register are reprogrammed */
+ _uart_pl011_disable(p_uart);
+
+ _uart_pl011_set_format(p_uart, word_len, parity, stop_bits);
+
+ /* Enabling the UART if previously enabled */
+ if(uart_enabled) {
+ _uart_pl011_enable(p_uart);
+ }
+
+ return UART_PL011_ERR_NONE;
+}
+
+void uart_pl011_enable_fifo(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_FEN_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_fifo(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_FEN_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_break(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_BRK_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_break(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_lcr_h_bit(p_uart, UART_PL011_UARTLCR_H_BRK_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_cts_flowcontrol(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_CTSE_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_cts_flowcontrol(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_CTSE_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_rts_flowcontrol(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_RTSE_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_rts_flowcontrol(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_RTSE_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_ri(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_OUT2_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_ri(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_OUT2_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_dcd(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_OUT1_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_dcd(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_OUT1_MASK);
+
+ return;
+}
+
+void uart_pl011_set_rts(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_RTS_MASK);
+
+ return;
+}
+
+void uart_pl011_clear_rts(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_RTS_MASK);
+
+ return;
+}
+
+void uart_pl011_set_dtr(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_DTR_MASK);
+
+ return;
+}
+
+void uart_pl011_clear_dtr(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_DTR_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_receive(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_RX_EN_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_receive(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_RX_EN_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_transmit(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_TX_EN_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_transmit(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_TX_EN_MASK);
+
+ return;
+}
+
+void uart_pl011_set_loopback(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_LBE_MASK);
+
+ return;
+}
+
+void uart_pl011_clear_loopback(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_LBE_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_sirlp(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart,
+ UART_PL011_UARTCR_SIREN_MASK | UART_PL011_UARTCR_SIRLP_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_sirlp(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart,
+ UART_PL011_UARTCR_SIREN_MASK | UART_PL011_UARTCR_SIRLP_MASK);
+
+ return;
+}
+
+void uart_pl011_enable_sir(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_set_cr_bit(p_uart, UART_PL011_UARTCR_SIREN_MASK);
+
+ return;
+}
+
+void uart_pl011_disable_sir(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_clear_cr_bit(p_uart, UART_PL011_UARTCR_SIREN_MASK);
+
+ return;
+}
+
+void uart_pl011_enable(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_enable(p_uart);
+
+ return;
+}
+
+void uart_pl011_disable(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ _uart_pl011_disable(p_uart);
+
+ return;
+}
+
+bool uart_pl011_get_cts_status(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+ return (bool)(p_uart->uartfr & UART_PL011_UARTFR_CTS_MASK);
+
+}
+
+bool uart_pl011_get_dsr_status(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+ return (bool)(p_uart->uartfr & UART_PL011_UARTFR_DSR_MASK);
+
+}
+
+bool uart_pl011_get_dcd_status(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+ return (bool)(p_uart->uartfr & UART_PL011_UARTFR_DCD_MASK);
+
+}
+
+bool uart_pl011_get_ri_status(struct uart_pl011_dev_t* dev)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+ return (bool)(p_uart->uartfr & UART_PL011_UARTFR_RI_MASK);
+
+}
+
+enum uart_pl011_error_t uart_pl011_set_sirlp_divisor(
+ struct uart_pl011_dev_t* dev, uint32_t value)
+{
+ struct _uart_pl011_reg_map_t* p_uart =
+ (struct _uart_pl011_reg_map_t*)dev->cfg->base;
+
+ uint32_t irlp_baud16_clk;
+
+ if(uart_pl011_get_state(dev) != UART_PL011_INITIALIZED) {
+ return UART_PL011_ERR_NOT_INIT;
+ }
+
+ if(value == 0) {
+ return UART_PL011_ERR_INVALID_ARG;
+ }
+
+ irlp_baud16_clk = dev->data->uart_clk/value;
+
+ /* Chose the divisor so that 1.42MHz < FIrLPBaud16 < 2.12MHz, that
+ * results in a low-power pulse duration of 1.41–2.11μs (three times
+ * the period of IrLPBaud16). ARM DDI0183F Pg 3-9 */
+ if(irlp_baud16_clk < FREQ_IRLPBAUD16_MIN ||
+ irlp_baud16_clk > FREQ_IRLPBAUD16_MAX) {
+ return UART_PL011_ERR_INVALID_ARG;
+ }
+
+ p_uart->uartilpr = value;
+
+ return UART_PL011_ERR_NONE;
+}
diff --git a/platform/ext/target/musca_a/Native_Driver/uart_pl011_drv.h b/platform/ext/target/musca_a/Native_Driver/uart_pl011_drv.h
new file mode 100755
index 0000000..31bf99c
--- /dev/null
+++ b/platform/ext/target/musca_a/Native_Driver/uart_pl011_drv.h
@@ -0,0 +1,852 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file uart_pl011_drv.h
+ * \brief Driver for ARM UART PL011.
+ */
+
+#ifndef __UART_PL011_DRV_H__
+#define __UART_PL011_DRV_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ARM UART PL011 state types
+ */
+enum uart_pl011_state_t {
+ UART_PL011_UNINITIALIZED = 0x0u,
+ UART_PL011_INITIALIZED = 0x1u,
+};
+
+#define UART_PL011_UARTRSR_FE_ERR_OFF 0x0u
+ /*!< Receive Status Register Frame Error bit field offset */
+#define UART_PL011_UARTRSR_PE_ERR_OFF 0x1u
+ /*!< Receive Status Register Parity Error bit field offset */
+#define UART_PL011_UARTRSR_BE_ERR_OFF 0x2u
+ /*!< Receive Status Register Break Error bit field offset */
+#define UART_PL011_UARTRSR_OE_ERR_OFF 0x3u
+ /*!< Receive Status Register Overrun Error bit field offset */
+
+#define UART_PL011_RX_ERR_MASK ( \
+ 0x1u<<UART_PL011_UARTRSR_FE_ERR_OFF \
+ | 0x1u<<UART_PL011_UARTRSR_PE_ERR_OFF \
+ | 0x1u<<UART_PL011_UARTRSR_BE_ERR_OFF \
+ | 0x1u<<UART_PL011_UARTRSR_OE_ERR_OFF)
+ /*!< Receive Status Register Error Mask */
+
+#define UART_PL011_UARTFR_CTS_OFF 0x0u
+ /*!< Flag Register Clear to send bit field offset */
+#define UART_PL011_UARTFR_DSR_OFF 0x1u
+ /*!< Flag Register Data set ready bit field offset */
+#define UART_PL011_UARTFR_DCD_OFF 0x2u
+ /*!< Flag Register Data carrier detect bit field offset */
+#define UART_PL011_UARTFR_BUSYBIT_OFF 0x3u
+ /*!< Flag Register Busy bit field offset */
+#define UART_PL011_UARTFR_RX_FIFO_EMPTY_OFF 0x4u
+ /*!< Flag Register Receive fifo empty bit field offset */
+#define UART_PL011_UARTFR_TX_FIFO_FULL_OFF 0x5u
+ /*!< Flag Register Transmit fifo full bit field offset */
+#define UART_PL011_UARTFR_RX_FIFO_FULL_OFF 0x6u
+ /*!< Flag Register Receive fifo full bit field offset */
+#define UART_PL011_UARTFR_TX_FIFO_EMPTY_OFF 0x7u
+ /*!< Flag Register Transmit fifo empty bit field offset */
+#define UART_PL011_UARTFR_RI_OFF 0x8u
+ /*!< Flag Register Ring indicator bit field offset */
+
+#define UART_PL011_UARTLCR_H_BRK_OFF 0x0u
+ /*!< Line Control Register Break bit field offset */
+#define UART_PL011_UARTLCR_H_PEN_OFF 0x1u
+ /*!< Line Control Register Parity enable bit field offset */
+#define UART_PL011_UARTLCR_H_EPS_OFF 0x2u
+ /*!< Line Control Register Even parity select bit field offset */
+#define UART_PL011_UARTLCR_H_STP2_OFF 0x3u
+ /*!< Line Control Register 2 stop bit select bit field offset */
+#define UART_PL011_UARTLCR_H_FEN_OFF 0x4u
+ /*!< Line Control Register Fifo enable bit field offset */
+#define UART_PL011_UARTLCR_H_WLEN_OFF 0x5u
+ /*!< Line Control Register Word length bit field offset */
+#define UART_PL011_UARTLCR_H_SPS_OFF 0x7u
+ /*!< Line Control Register Stick parity select bit field offset */
+
+/**
+ * \brief Allowed word length options UART PL011
+ */
+enum uart_pl011_wlen_t {
+ UART_PL011_WLEN_5 = (0x0u<<UART_PL011_UARTLCR_H_WLEN_OFF),
+ UART_PL011_WLEN_6 = (0x1u<<UART_PL011_UARTLCR_H_WLEN_OFF),
+ UART_PL011_WLEN_7 = (0x2u<<UART_PL011_UARTLCR_H_WLEN_OFF),
+ UART_PL011_WLEN_8 = (0x3u<<UART_PL011_UARTLCR_H_WLEN_OFF),
+};
+
+/**
+ * \brief Allowed parity options UART PL011
+ */
+enum uart_pl011_parity_t {
+ UART_PL011_PARITY_DISABLED = (0x0u<<UART_PL011_UARTLCR_H_PEN_OFF),
+ UART_PL011_PARITY_ODD = (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
+ | 0x0u<<UART_PL011_UARTLCR_H_EPS_OFF
+ | 0x0u<<UART_PL011_UARTLCR_H_SPS_OFF),
+ UART_PL011_PARITY_EVEN = (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
+ | 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF
+ | 0x0u<<UART_PL011_UARTLCR_H_SPS_OFF),
+ UART_PL011_PARITY_STICKY_ONE= (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
+ | 0x0u<<UART_PL011_UARTLCR_H_EPS_OFF
+ | 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF),
+ UART_PL011_PARITY_STICKY_ZERO= (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
+ | 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF
+ | 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF),
+};
+
+/**
+ * \brief Allowed stop bits options UART PL011
+ */
+enum uart_pl011_stopbit_t {
+ UART_PL011_STOPBIT_1 = (0x0u<<UART_PL011_UARTLCR_H_STP2_OFF),
+ UART_PL011_STOPBIT_2 = (0x1u<<UART_PL011_UARTLCR_H_STP2_OFF),
+};
+
+#define UART_PL011_UARTCR_UARTEN_OFF 0x0u
+ /*!< Control Register Uart enable bit field offset */
+#define UART_PL011_UARTCR_SIREN_OFF 0x1u
+ /*!< Control Register Sir enable bit field offset */
+#define UART_PL011_UARTCR_SIRLP_OFF 0x2u
+ /*!< Control Register Sir low power bit field offset */
+#define UART_PL011_UARTCR_LBE_OFF 0x7u
+ /*!< Control Register Loop back enable bit field offset */
+#define UART_PL011_UARTCR_TXE_OFF 0x8u
+ /*!< Control Register Transmit enable bit field offset */
+#define UART_PL011_UARTCR_RXE_OFF 0x9u
+ /*!< Control Register Receive enable bit field offset */
+#define UART_PL011_UARTCR_DTR_OFF 0xAu
+ /*!< Control Register Data transmit ready bit field offset */
+#define UART_PL011_UARTCR_RTS_OFF 0xBu
+ /*!< Control Register Request to send bit field offset */
+#define UART_PL011_UARTCR_OUT1_OFF 0xCu
+ /*!< Control Register Out1 bit field offset */
+#define UART_PL011_UARTCR_OUT2_OFF 0xDu
+ /*!< Control Register Out2 bit field offset */
+#define UART_PL011_UARTCR_RTSE_OFF 0xEu
+ /*!< Control Register RTS hardware flow control enable bit field offset */
+#define UART_PL011_UARTCR_CTSE_OFF 0xFu
+ /*!< Control Register CTS hardware flow control enable bit field offset */
+
+#define UART_PL011_UARTIFLS_TX_OFF 0x0u
+ /*!< Interrupt FIFO Level Select Register Transmit bit field offset */
+#define UART_PL011_UARTIFLS_RX_OFF 0x3u
+ /*!< Interrupt FIFO Level Select Register Receive bit field offset */
+
+/**
+ * \brief UART Receive fifo levels
+ */
+enum uart_pl011_rx_fifo_lvl_t {
+ UART_PL011_RX_FIFO_LVL_1_8 = (0x0u<<UART_PL011_UARTIFLS_RX_OFF),
+ UART_PL011_RX_FIFO_LVL_1_4 = (0x1u<<UART_PL011_UARTIFLS_RX_OFF),
+ UART_PL011_RX_FIFO_LVL_1_2 = (0x2u<<UART_PL011_UARTIFLS_RX_OFF),
+ UART_PL011_RX_FIFO_LVL_3_4 = (0x3u<<UART_PL011_UARTIFLS_RX_OFF),
+ UART_PL011_RX_FIFO_LVL_7_8 = (0x4u<<UART_PL011_UARTIFLS_RX_OFF),
+};
+
+/**
+ * \brief UART Transmit fifo levels
+ */
+enum uart_pl011_tx_fifo_lvl_t {
+ UART_PL011_TX_FIFO_LVL_1_8 = (0x0u<<UART_PL011_UARTIFLS_TX_OFF),
+ UART_PL011_TX_FIFO_LVL_1_4 = (0x1u<<UART_PL011_UARTIFLS_TX_OFF),
+ UART_PL011_TX_FIFO_LVL_1_2 = (0x2u<<UART_PL011_UARTIFLS_TX_OFF),
+ UART_PL011_TX_FIFO_LVL_3_4 = (0x3u<<UART_PL011_UARTIFLS_TX_OFF),
+ UART_PL011_TX_FIFO_LVL_7_8 = (0x4u<<UART_PL011_UARTIFLS_TX_OFF),
+};
+
+#define UART_PL011_UARTDMACR_RXEN_OFF 0x0u
+ /*!< DMA Control Register Receive DMA enable bit field offset */
+#define UART_PL011_UARTDMACR_TXEN_OFF 0x1u
+ /*!< DMA Control Register Transmit DMA enable bit field offset */
+#define UART_PL011_UARTDMACR_ON_ERR_OFF 0x2u
+ /*!< DMA Control Register DMA on error bit field offset */
+
+/**
+ * \brief Transmit DMA Enable
+ */
+enum uart_pl011_tx_dma_t {
+ UART_PL011_TX_DMA_DISABLE = (0x0u<<UART_PL011_UARTDMACR_TXEN_OFF),
+ UART_PL011_TX_DMA_ENABLE = (0x1u<<UART_PL011_UARTDMACR_TXEN_OFF),
+};
+
+/**
+ * \brief Receive DMA Enable
+ */
+enum uart_pl011_rx_dma_t {
+ UART_PL011_RX_DMA_DISABLE = (0x0u<<UART_PL011_UARTDMACR_RXEN_OFF),
+ UART_PL011_RX_DMA_ENABLE = (0x1u<<UART_PL011_UARTDMACR_RXEN_OFF),
+ UART_PL011_RX_DMA_ON_ERR_EN= (0x1u<<UART_PL011_UARTDMACR_RXEN_OFF
+ | 0x1u<<UART_PL011_UARTDMACR_ON_ERR_OFF),
+};
+
+#define UART_PL011_INTR_RI_OFF 0x0u
+ /*!< Ring indicator interrupt bit field offset */
+#define UART_PL011_INTR_CTS_OFF 0x1u
+ /*!< Clear to send interrupt bit field offset */
+#define UART_PL011_INTR_DCD_OFF 0x2u
+ /*!< Data carrier detect interrupt bit field offset */
+#define UART_PL011_INTR_DSR_OFF 0x3u
+ /*!< Data set ready interrupt bit field offset */
+#define UART_PL011_INTR_RX_OFF 0x4u
+ /*!< Receive interrupt bit field offset */
+#define UART_PL011_INTR_TX_OFF 0x5u
+ /*!< Transmit interrupt bit field offset */
+#define UART_PL011_INTR_RT_OFF 0x6u
+ /*!< Receive timeout interrupt bit field offset */
+#define UART_PL011_INTR_FE_OFF 0x7u
+ /*!< Frame error interrupt bit field offset */
+#define UART_PL011_INTR_PE_OFF 0x8u
+ /*!< Parity error interrupt bit field offset */
+#define UART_PL011_INTR_BE_OFF 0x9u
+ /*!< Break error interrupt bit field offset */
+#define UART_PL011_INTR_OE_OFF 0xAu
+ /*!< Overrun error interrupt bit field offset */
+
+/**
+ * \brief ARM UART PL011 Interrupt data structure
+ */
+enum uart_pl011_intr_t {
+ UART_PL011_RI_INTR_MASK = (0x1u<<UART_PL011_INTR_RI_OFF),
+ UART_PL011_CTS_INTR_MASK = (0x1u<<UART_PL011_INTR_CTS_OFF),
+ UART_PL011_DCD_INTR_MASK = (0x1u<<UART_PL011_INTR_DCD_OFF),
+ UART_PL011_DSR_INTR_MASK = (0x1u<<UART_PL011_INTR_DSR_OFF),
+ UART_PL011_RX_INTR_MASK = (0x1u<<UART_PL011_INTR_RX_OFF),
+ UART_PL011_TX_INTR_MASK = (0x1u<<UART_PL011_INTR_TX_OFF),
+ UART_PL011_RT_INTR_MASK = (0x1u<<UART_PL011_INTR_RT_OFF),
+ UART_PL011_FE_INTR_MASK = (0x1u<<UART_PL011_INTR_FE_OFF),
+ UART_PL011_PE_INTR_MASK = (0x1u<<UART_PL011_INTR_PE_OFF),
+ UART_PL011_BE_INTR_MASK = (0x1u<<UART_PL011_INTR_BE_OFF),
+ UART_PL011_OE_INTR_MASK = (0x1u<<UART_PL011_INTR_OE_OFF),
+};
+
+/**
+ * \brief ARM UART PL011 error enumeration types
+ */
+enum uart_pl011_error_t {
+ UART_PL011_ERR_NONE = (0x0u),
+ UART_PL011_ERR_RX_FRAME = (0x1u<<UART_PL011_UARTRSR_FE_ERR_OFF),
+ UART_PL011_ERR_RX_PARITY = (0x1u<<UART_PL011_UARTRSR_PE_ERR_OFF),
+ UART_PL011_ERR_RX_BREAK = (0x1u<<UART_PL011_UARTRSR_BE_ERR_OFF),
+ UART_PL011_ERR_RX_OVERFLOW = (0x1u<<UART_PL011_UARTRSR_OE_ERR_OFF),
+ UART_PL011_ERR_INVALID_ARG = (UART_PL011_RX_ERR_MASK + 1),
+ UART_PL011_ERR_NOT_READY,
+ UART_PL011_ERR_INVALID_BAUD,
+ UART_PL011_ERR_NOT_INIT,
+};
+
+/**
+ * \brief ARM UART PL011 device configuration structure
+ */
+struct uart_pl011_dev_cfg_t {
+ const uint32_t base; /*!< UART PL011 base address */
+ const uint32_t def_baudrate; /*!< Default baudrate */
+ const enum uart_pl011_wlen_t def_wlen; /*!< Default word length */
+ const enum uart_pl011_parity_t def_parity; /*!< Default parity */
+ const enum uart_pl011_stopbit_t def_stopbit; /*!< Default stop bits */
+};
+
+/**
+ * \brief ARM UART PL011 device data structure
+ */
+struct uart_pl011_dev_data_t {
+ enum uart_pl011_state_t state; /*!< UART State */
+ uint32_t uart_clk; /*!< UART clock */
+ uint32_t baudrate; /*!< Baudrate */
+};
+
+/**
+ * \brief ARM UART PL011 device structure
+ */
+struct uart_pl011_dev_t {
+ const struct uart_pl011_dev_cfg_t* const cfg;
+ /*!< UART PL011 configuration */
+ struct uart_pl011_dev_data_t* const data;
+ /*!< UART PL011 data */
+};
+
+/**
+ * \brief Initializes UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ * \param[in] uart_clk UART clock used by the device.
+ *
+ * It uses the default baudrate to configure UART.
+ *
+ * \return Returns error code as specified in \ref uart_pl011_error_t
+ *
+ * \note This API should be called before calling any of the below UART APIs.
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_pl011_error_t uart_pl011_init(struct uart_pl011_dev_t* dev,
+ uint32_t uart_clk);
+
+/**
+ * \brief Uninitializes UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_uninit(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Returns the UART PL011 operational state.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns the UART operational state
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_pl011_state_t uart_pl011_get_state(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Sets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] baudrate New baudrate.
+ *
+ * \return Returns error code as specified in \ref uart_pl011_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_pl011_error_t uart_pl011_set_baudrate(
+ struct uart_pl011_dev_t* dev, uint32_t baudrate);
+
+/**
+ * \brief Gets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns the UART baudrate.
+ *
+ * \note The UART should be in valid state before calling this API
+ * \ref uart_pl011_get_state should return UART_PL011_INITIALIZED
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t uart_pl011_get_baudrate(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables UART interrupts
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] mask Bit mask for enabling/disabling interrupts
+ * \ref uart_pl011_intr_t
+ *
+ * \note User is responsible to configure the interrupt vector and
+ * the interrupt controller.
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_intr(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_intr_t mask);
+
+/**
+ * \brief Disables UART interrupts
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] mask Bit mask for enabling/disabling interrupts
+ * \ref uart_pl011_intr_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_intr(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_intr_t mask);
+
+/**
+ * \brief Clears UART Interrupt
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] mask Bit mask for clearing interrupts \ref uart_pl011_intr_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_clear_intr(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_intr_t mask);
+
+/**
+ * \brief Returns the UART Masked interrupt status
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \return Masked interrupt status \ref uart_pl011_intr_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_pl011_intr_t uart_pl011_get_masked_intr_status(
+ struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Returns the UART Raw interrupt status
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \return Raw interrupt status \ref uart_pl011_intr_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_pl011_intr_t uart_pl011_get_raw_intr_status(
+ struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Sets receive fifo levels
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] rx_lvl Receive fifo levels \ref uart_pl011_rx_fifo_lvl_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_set_rx_fifo_lvl(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_rx_fifo_lvl_t rx_lvl);
+
+/**
+ * \brief Sets transmit fifo levels
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] tx_lvl Transmit fifo levels \ref uart_pl011_tx_fifo_lvl_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_set_tx_fifo_lvl(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_tx_fifo_lvl_t tx_lvl);
+
+/**
+ * \brief Enables/Disables transmit UART DMA
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] enable To enable/disable the UART transmit DMA
+ * \ref uart_pl011_tx_dma_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_set_tx_dma(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_tx_dma_t enable);
+
+/**
+ * \brief Enables/Disables receive UART DMA
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] enable To enable/disable the UART receive DMA
+ * \ref uart_pl011_rx_dma_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_set_rx_dma(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_rx_dma_t enable);
+
+/**
+ * \brief Check if the UART dev is readable
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns bool, true if UART is readable, false otherwise
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+bool uart_pl011_is_readable(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Reads one byte from UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[out] byte Pointer to byte that is populated with the data to be read
+ *
+ * \return Error status (if any) as specified in
+ * \ref uart_pl011_error_t
+ *
+ * \note This API should only be called when the device is readable
+ * \ref uart_pl011_is_readable
+ * \note For better performance, this function doesn't check if dev and byte
+ * pointer are NULL, and if the driver is initialized.
+ */
+enum uart_pl011_error_t uart_pl011_read(struct uart_pl011_dev_t* dev,
+ uint8_t* byte);
+
+/**
+ * \brief Check if the UART dev is writable
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns bool, true if UART is writable, false otherwise
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+bool uart_pl011_is_writable(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Writes a byte to UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] byte One byte to write.
+ *
+ * \note This API should only be called when the device is writable
+ * \ref uart_pl011_is_writable
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_write(struct uart_pl011_dev_t* dev, uint8_t byte);
+
+/**
+ * \brief Sets the UART format.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] word_len UART word length \ref uart_pl011_wlen_t
+ * \param[in] parity UART parity \ref uart_pl011_parity_t
+ * \param[in] stop_bits UART stop bits \ref uart_pl011_stopbit_t
+ *
+ * \return Returns error code as specified in \ref uart_pl011_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_pl011_error_t uart_pl011_set_format(struct uart_pl011_dev_t* dev,
+ enum uart_pl011_wlen_t word_len,
+ enum uart_pl011_parity_t parity,
+ enum uart_pl011_stopbit_t stop_bits);
+
+/**
+ * \brief Enables the UART fifo.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_fifo(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables the UART fifo.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_fifo(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables break transmission from UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_enable_break(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables break transmission from UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_disable_break(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables CTS flow control in UART PL011
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_cts_flowcontrol(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables CTS flow control in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_cts_flowcontrol(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables RTS flow control in UART PL011
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_rts_flowcontrol(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables RTS flow control in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_rts_flowcontrol(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables Data carrier detect in UART PL011
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \note For DTE nUARTOut1 can be used as Data carrier detect (DCD).
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_dcd(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables Data carrier detect in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \note For DTE nUARTOut1 can be used as Data carrier detect (DCD).
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_dcd(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables RTS signal for UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_set_rts(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables RTS signal for UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_clear_rts(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables DTR signal for UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_set_dtr(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables DTR signal for UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_clear_dtr(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables reception in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_receive(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables reception in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_receive(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables transmission in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable_transmit(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables transmission in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable_transmit(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables loopback in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_set_loopback(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables loopback in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_clear_loopback(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables IrDA Sir low power mode in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_enable_sirlp(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables IrDA Sir in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_disable_sirlp(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables IrDA Sir in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_enable_sir(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables IrDA Sir in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+void uart_pl011_disable_sir(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Enables in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_enable(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Disables in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_pl011_disable(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Gets the Clear to send status in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns bool, true when the modem status input is 0, false otherwise
+ *
+ * \note This bit is the complement of the UART clear to send (nUARTCTS) modem
+ * status input.
+ * \note This function doesn't check if dev is NULL.
+ */
+bool uart_pl011_get_cts_status(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Gets the Data set ready status in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns bool, true when the modem status input is 0, false otherwise
+ *
+ * \note This bit is the complement of the UART UART data set ready (nUARTDSR)
+ * modem status input.
+ * \note This function doesn't check if dev is NULL.
+ */
+bool uart_pl011_get_dsr_status(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Gets the Data carrier detect status in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns bool, true when the modem status input is 0, false otherwise
+ *
+ * \note This bit is the complement of the UART data carrier detect (nUARTDCD)
+ * modem status input.
+ * \note This function doesn't check if dev is NULL.
+ */
+bool uart_pl011_get_dcd_status(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Gets the Ring indicator status in UART PL011.
+ *
+ * \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
+ *
+ * \return Returns bool, true when the modem status input is 0, false otherwise
+ *
+ * \note This bit is the complement of the UART ring indicator (nUARTRI) modem
+ * status input.
+ * \note This function doesn't check if dev is NULL.
+ */
+bool uart_pl011_get_ri_status(struct uart_pl011_dev_t* dev);
+
+/**
+ * \brief Sets the Low power Divisor in UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_pl011_dev_t
+ * \param[in] value Low power divisor value to be set
+ *
+ * \return Returns error code as specified in \ref uart_pl011_error_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL
+ */
+enum uart_pl011_error_t uart_pl011_set_sirlp_divisor(
+ struct uart_pl011_dev_t* dev, uint32_t value);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __UART_PL011_DRV_H__ */
diff --git a/platform/ext/target/musca_a/dummy_crypto_keys.c b/platform/ext/target/musca_a/dummy_crypto_keys.c
new file mode 100644
index 0000000..80a8f28
--- /dev/null
+++ b/platform/ext/target/musca_a/dummy_crypto_keys.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/plat_crypto_keys.h"
+
+#define TFM_KEY_LEN_BYTES 16
+
+static uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] =
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
+enum tfm_plat_errno_t plat_get_crypto_huk(uint8_t* key, uint32_t size)
+{
+ /* FIXME: this function should be implemented by platform vendor. For the
+ * security of the storage system, it is critical to use a hardware unique
+ * key.
+ *
+ * SSE-200 does not have any available hardware unique key engine, so a
+ * software stub has been implemented in this case.
+ */
+ uint32_t i;
+ uint8_t* p_dst = key;
+ uint8_t* p_huk = sample_tfm_key;
+
+ if(size > TFM_KEY_LEN_BYTES) {
+ return TFM_PLAT_ERRNO_SYSTEM_ERR;
+ }
+
+ for (i = size; i > 0; i--) {
+ *((uint8_t*)p_dst) = *((uint8_t*)p_huk);
+ p_huk++;
+ p_dst++;
+ }
+
+ return TFM_PLAT_ERRNO_SUCCESS;
+}
+
diff --git a/platform/ext/target/musca_a/partition/flash_layout.h b/platform/ext/target/musca_a/partition/flash_layout.h
new file mode 100755
index 0000000..12c5638
--- /dev/null
+++ b/platform/ext/target/musca_a/partition/flash_layout.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/* Flash layout on Musca with BL2:
+ * 0x0020_0000 BL2 - MCUBoot
+ * 0x0021_0000 Flash_area_image_0:
+ * 0x0021_0000 Secure image primary
+ * 0x0023_0000 Non-secure image primary
+ * 0x0024_0000 Flash_area_image_1:
+ * 0x0024_0000 Secure image secondary
+ * 0x0026_0000 Non-secure image secondary
+ * 0x0027_0000 Scratch area
+ */
+#define FLASH_BASE_ADDRESS (0x00200000)
+
+#define FLASH_ALIGN (1)
+#define FLASH_PARTITION_SIZE (0x20000) /* 128KB */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000)
+
+
+#define FLASH_AREA_BL2_OFFSET (0x0)
+#ifdef BL2
+#define FLASH_AREA_BL2_SIZE (0x10000) /* 64KB */
+#else
+#define FLASH_AREA_BL2_SIZE (0x0)
+#endif
+#define FLASH_AREA_IMAGE_SIZE ((2 * FLASH_PARTITION_SIZE) -\
+ FLASH_AREA_BL2_SIZE)
+
+#define FLASH_AREA_IMAGE_0_OFFSET (FLASH_AREA_BL2_OFFSET + \
+ FLASH_AREA_BL2_SIZE)
+#define FLASH_AREA_IMAGE_0_SIZE (FLASH_AREA_IMAGE_SIZE)
+
+#define FLASH_AREA_IMAGE_1_OFFSET (FLASH_AREA_IMAGE_0_OFFSET + \
+ FLASH_AREA_IMAGE_0_SIZE)
+#define FLASH_AREA_IMAGE_1_SIZE (FLASH_AREA_IMAGE_SIZE)
+
+#define FLASH_AREA_IMAGE_SCRATCH_OFFSET (FLASH_AREA_IMAGE_1_OFFSET + \
+ FLASH_AREA_IMAGE_1_SIZE)
+#define FLASH_AREA_IMAGE_SCRATCH_SIZE (FLASH_AREA_IMAGE_SIZE)
+
+/* Offset and size definition in flash area, used by assemble.py */
+#define SECURE_IMAGE_OFFSET 0x0
+#define SECURE_IMAGE_MAX_SIZE 0x20000
+
+#define NON_SECURE_IMAGE_OFFSET 0x20000
+#define NON_SECURE_IMAGE_MAX_SIZE 0x20000
+
+#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/musca_a/partition/region_defs.h b/platform/ext/target/musca_a/partition/region_defs.h
new file mode 100755
index 0000000..47b2fcb
--- /dev/null
+++ b/platform/ext/target/musca_a/partition/region_defs.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "flash_layout.h"
+
+#define TOTAL_ROM_SIZE (0x00040000) /* 256KB */
+#define TOTAL_RAM_SIZE (0x00020000) /* 128KB */
+
+/*
+ * MPC granularity is 128 KB on Musca. Alignment
+ * of partitions is defined in accordance with this constraint.
+ */
+
+/*Flash partitions on Musca with BL2:
+ * 0x0020_0000 BL2 - MCUBoot
+ * 0x0021_0000 Flash_area_image_0:
+ * 0x0021_0000 Secure image primary
+ * 0x0023_0000 Non-secure image primary
+ * 0x0024_0000 Flash_area_image_1:
+ * 0x0024_0000 Secure image secondary
+ * 0x0026_0000 Non-secure image secondary
+ * 0x0027_0000 Scratch area
+
+ *
+ * Flash partitions on bare metal, if BL2 not defined:
+ * 0x0020_0000 Secure image
+ * 0x0022_0000 Non-secure image
+ */
+
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET)
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + \
+ FLASH_PARTITION_SIZE)
+
+/*
+ * Boot partition structure if MCUBoot is used:
+ * 0x0_0000 Bootloader header
+ * 0x0_0200 Image area
+ * 0x7_0000 Trailer
+ */
+/* IMAGE_CODE_SIZE is the space available for the software binary image.
+ * It is less than the FLASH_PARTITION_SIZE because we reserve space
+ * for the image header and trailer introduced by the bootloader.
+ */
+#ifdef BL2
+#define BL2_HEADER_SIZE (0x400)
+#define BL2_TRAILER_SIZE (0x400)
+#else
+/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */
+#define BL2_HEADER_SIZE (0x0)
+#define BL2_TRAILER_SIZE (0x800)
+#endif /* BL2 */
+
+#define IMAGE_CODE_SIZE \
+ (FLASH_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+
+#define CMSE_VENEER_REGION_SIZE (0x00000080)
+
+/* Use QSPI Flash memory to store Code data */
+#define S_ROM_ALIAS_BASE (0x10200000)
+#define NS_ROM_ALIAS_BASE (0x00200000)
+
+#define S_RAM_ALIAS_BASE (0x30000000)
+#define NS_RAM_ALIAS_BASE (0x20000000)
+
+/* Alias definitions for secure and non-secure areas*/
+#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + x)
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + x)
+
+#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + x)
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + x)
+
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET \
+ (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
+#define S_CODE_SIZE (IMAGE_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+
+#define S_DATA_START (S_RAM_ALIAS(0x0))
+#define S_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
+
+/* CMSE Veneers region */
+#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+#define CMSE_VENEER_REGION_LIMIT (CMSE_VENEER_REGION_START + \
+ CMSE_VENEER_REGION_SIZE - 1)
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET \
+ (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
+#define NS_CODE_SIZE (IMAGE_CODE_SIZE - FLASH_AREA_BL2_SIZE)
+#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
+
+/* NS partition information is used for MPC configuration */
+#define NS_PARTITION_START \
+ (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+
+/* Code SRAM area */
+#define TOTAL_CODE_SRAM_SIZE (TOTAL_ROM_SIZE)
+#define S_CODE_SRAM_ALIAS_BASE (0x10000000)
+#define NS_CODE_SRAM_ALIAS_BASE (0x00000000)
+
+#define BL2_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
+#define S_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
+#define S_CODE_SRAM_EXEC_LIMIT (S_CODE_SRAM_EXEC_BASE + \
+ (TOTAL_CODE_SRAM_SIZE/2) - 1)
+#define NS_CODE_SRAM_EXEC_BASE (NS_CODE_SRAM_ALIAS_BASE + \
+ (TOTAL_CODE_SRAM_SIZE/2))
+#define NS_CODE_SRAM_EXEC_LIMIT (NS_CODE_SRAM_EXEC_BASE + \
+ (TOTAL_CODE_SRAM_SIZE/2) - 1)
+
+#define NS_PARTITION_LIMIT \
+ (NS_PARTITION_START + FLASH_PARTITION_SIZE \
+ - FLASH_AREA_BL2_SIZE - 1)
+
+#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE -1)
+
+#ifdef BL2
+/* Bootloader regions */
+#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
+#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
+#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
+
+#define BL2_DATA_START (S_RAM_ALIAS(0x0))
+#define BL2_DATA_SIZE (TOTAL_RAM_SIZE)
+#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
+#endif /* BL2 */
+
+#endif /* __REGION_DEFS_H__ */
+
diff --git a/platform/ext/target/musca_a/target_cfg.c b/platform/ext/target/musca_a/target_cfg.c
new file mode 100755
index 0000000..c80bc86
--- /dev/null
+++ b/platform/ext/target/musca_a/target_cfg.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arm_cmse.h>
+
+#include "cmsis.h"
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "platform_retarget_dev.h"
+#include "region_defs.h"
+#include "tfm_secure_api.h"
+
+/*
+ * This function pointer is meant to only hold non-secure function pointers.
+ * It will be turned into a non-secure one (LSB cleared) before being called
+ * whatever happens anyway (unless cast to another function pointer type).
+ * Registers will be cleared before branching so that no information leaks
+ * from secure to non-secure world.
+ */
+typedef void __attribute__((cmse_nonsecure_call)) (*nsfptr_t) (void);
+
+/* Allows software, via SAU, to define the code region as a NSC */
+#define NSCCFG_CODENSC 1
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC, Driver_QSPI_MPC;
+extern ARM_DRIVER_MPC Driver_ISRAM0_MPC, Driver_ISRAM1_MPC;
+extern ARM_DRIVER_MPC Driver_ISRAM2_MPC, Driver_ISRAM3_MPC;
+
+/* Define Peripherals NS address range for the platform */
+#define PERIPHERALS_BASE_NS_START (0x40000000)
+#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF)
+
+void configure_ns_code()
+{
+ /* SCB_NS.VTOR points to the Non-secure vector table base address */
+ SCB_NS->VTOR = (NS_CODE_START);
+
+ /* Setups Main stack pointer of the non-secure code */
+ uint32_t ns_msp = *((uint32_t*)(NS_CODE_START));
+ __TZ_set_MSP_NS(ns_msp);
+}
+
+void jump_to_ns_code()
+{
+ /* The entry contains address of the Reset_handler (CMSIS-CORE) function */
+ uint32_t entry_ptr = *((uint32_t*)(NS_CODE_START + 4));
+
+ /* Clears LSB of the function address to indicate the function-call
+ will perform the switch from secure to non-secure */
+ nsfptr_t ns_entry = (nsfptr_t) cmse_nsfptr_create(entry_ptr);
+
+ /* All changes made to memory will be effective after this point */
+ __DSB();
+ __ISB();
+
+ /* Calls the non-secure Reset_Handler to jump to the non-secure binary */
+ ns_entry();
+}
+
+void enable_fault_handlers(void)
+{
+ /* Enables BUS, MEM, USG and Secure faults */
+ SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
+ | SCB_SHCSR_BUSFAULTENA_Msk
+ | SCB_SHCSR_MEMFAULTENA_Msk
+ | SCB_SHCSR_SECUREFAULTENA_Msk;
+}
+
+/*----------------- NVIC interrupt target state to NS configuration ----------*/
+void nvic_interrupt_target_state_cfg()
+{
+ /* Target every interrupt to NS; unimplemented interrupts will be WI */
+ for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) {
+ NVIC->ITNS[i] = 0xFFFFFFFF;
+ }
+
+ /* Make sure that MPC and PPC are targeted to S state */
+ NVIC_ClearTargetState(MPC_IRQn);
+ NVIC_ClearTargetState(PPC_IRQn);
+
+ /* UART1 is a secure peripheral, so its IRQs have to target S state */
+ NVIC_ClearTargetState(UARTRX1_IRQn);
+ NVIC_ClearTargetState(UARTTX1_IRQn);
+ NVIC_ClearTargetState(UART1_IRQn);
+}
+
+/*----------------- NVIC interrupt enabling for S peripherals ----------------*/
+void nvic_interrupt_enable()
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+
+ /* MPC interrupt enabling */
+ Driver_QSPI_MPC.EnableInterrupt();
+ Driver_SRAM1_MPC.EnableInterrupt();
+ NVIC_EnableIRQ(MPC_IRQn);
+
+ /* PPC interrupt enabling */
+ /* Clear pending PPC interrupts */
+ /* In the PPC configuration function, we have used the Non-Secure
+ * Privilege Control Block to grant unprivilged NS access to some
+ * peripherals used by NS. That triggers a PPC0 exception as that
+ * register is meant for NS privileged access only. Clear it here
+ */
+ spctrl->secppcintclr = CMSDK_APB_PPC0_INT_POS_MASK;
+
+ /* Enable PPC interrupts for APB PPC */
+ spctrl->secppcinten |= CMSDK_APB_PPC0_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPC1_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP0_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP1_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP2_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP3_INT_POS_MASK;
+ NVIC_EnableIRQ(PPC_IRQn);
+}
+
+/*------------------- SAU/IDAU configuration functions -----------------------*/
+
+void sau_and_idau_cfg(void)
+{
+ /* Enables SAU */
+ TZ_SAU_Enable();
+
+ /* Configures SAU regions to be non-secure */
+ SAU->RNR = TFM_NS_REGION_CODE;
+ SAU->RBAR = (NS_PARTITION_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_PARTITION_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+/*
+ * If __USE_BOTH_CODE_MEMORY is defined the code is copied from QSPI flash to
+ * CODE SRAM before executing, SAU needs to be configured accordingly.
+ * If __USE_BOTH_CODE_MEMORY is undefined then the code will be executed from
+ * QSPI flash directly, no such configuration is needed for CODE SRAM
+ */
+#ifdef __USE_BOTH_CODE_MEMORY
+ SAU->RNR = TFM_NS_REGION_CODE_SRAM;
+ SAU->RBAR = (NS_CODE_SRAM_EXEC_BASE & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_CODE_SRAM_EXEC_LIMIT & SAU_RLAR_LADDR_Msk) |
+ SAU_RLAR_ENABLE_Msk;
+#endif
+
+ SAU->RNR = TFM_NS_REGION_DATA;
+ SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ /* Configures veneers region to be non-secure callable */
+ SAU->RNR = TFM_NS_REGION_VENEER;
+ SAU->RBAR = (CMSE_VENEER_REGION_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (CMSE_VENEER_REGION_LIMIT & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk
+ | SAU_RLAR_NSC_Msk;
+
+ /* Configure the peripherals space */
+ SAU->RNR = TFM_NS_REGION_PERIPH_1;
+ SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk;
+
+ /* Allows SAU to define the code region as a NSC */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ spctrl->nsccfg |= NSCCFG_CODENSC;
+}
+
+/*------------------- Memory configuration functions -------------------------*/
+
+void mpc_init_cfg(void)
+{
+ ARM_DRIVER_MPC* mpc_data_region0 = &Driver_ISRAM0_MPC;
+ ARM_DRIVER_MPC* mpc_data_region1 = &Driver_ISRAM1_MPC;
+ ARM_DRIVER_MPC* mpc_data_region2 = &Driver_ISRAM2_MPC;
+ ARM_DRIVER_MPC* mpc_data_region3 = &Driver_ISRAM3_MPC;
+
+ Driver_QSPI_MPC.Initialize();
+ Driver_QSPI_MPC.ConfigRegion(NS_PARTITION_START,
+ NS_PARTITION_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+
+ Driver_SRAM1_MPC.Initialize();
+/*
+ * If __USE_BOTH_CODE_MEMORY is defined the code is copied from QSPI flash to
+ * CODE SRAM before executing, MPC needs to be configured accordingly.
+ * If __USE_BOTH_CODE_MEMORY is undefined then the code will be executed from
+ * QSPI flash directly
+ */
+#ifdef __USE_BOTH_CODE_MEMORY
+ Driver_SRAM1_MPC.ConfigRegion(NS_CODE_SRAM_EXEC_BASE,
+ NS_CODE_SRAM_EXEC_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+#else
+ Driver_SRAM1_MPC.ConfigRegion(NS_PARTITION_START,
+ NS_PARTITION_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+#endif
+
+ mpc_data_region0->Initialize();
+ mpc_data_region0->ConfigRegion(MPC_ISRAM0_RANGE_BASE_S,
+ MPC_ISRAM0_RANGE_LIMIT_S,
+ ARM_MPC_ATTR_SECURE);
+
+ mpc_data_region1->Initialize();
+ mpc_data_region1->ConfigRegion(MPC_ISRAM1_RANGE_BASE_S,
+ MPC_ISRAM1_RANGE_LIMIT_S,
+ ARM_MPC_ATTR_SECURE);
+
+ mpc_data_region2->Initialize();
+ mpc_data_region2->ConfigRegion(MPC_ISRAM2_RANGE_BASE_NS,
+ MPC_ISRAM2_RANGE_LIMIT_NS,
+ ARM_MPC_ATTR_NONSECURE);
+
+ mpc_data_region3->Initialize();
+ mpc_data_region3->ConfigRegion(MPC_ISRAM3_RANGE_BASE_NS,
+ MPC_ISRAM3_RANGE_LIMIT_NS,
+ ARM_MPC_ATTR_NONSECURE);
+
+ /* Lock down the MPC configuration */
+ Driver_QSPI_MPC.LockDown();
+ Driver_SRAM1_MPC.LockDown();
+ mpc_data_region0->LockDown();
+ mpc_data_region1->LockDown();
+ mpc_data_region2->LockDown();
+ mpc_data_region3->LockDown();
+
+ /* Add barriers to assure the MPC configuration is done before continue
+ * the execution. */
+ __DSB();
+ __ISB();
+}
+
+/*------------------- PPC configuration functions -------------------------*/
+
+void ppc_init_cfg(void)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ struct nspctrl_def* nspctrl = CMSDK_NSPCTRL;
+
+ /* Grant non-secure access to peripherals in the PPC0
+ * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1) */
+ spctrl->apbnsppc0 |= (1U << CMSDK_TIMER0_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_TIMER1_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_DTIMER_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_MHU0_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_MHU1_APB_PPC_POS);
+ /* Grant non-secure access to S32K Timer in PPC1*/
+ spctrl->apbnsppc1 |= (1U << CMSDK_S32K_TIMER_PPC_POS);
+
+ /* Grant non-secure access for AHB peripherals on EXP0 */
+ spctrl->ahbnsppcexp0 = (1U << MUSCA_PERIPHS_AHB_PPC_POS);
+
+ /* in NS, grant un-privileged for AHB peripherals on EXP0 */
+ nspctrl->ahbnspppcexp0 = (1U << MUSCA_PERIPHS_AHB_PPC_POS);
+
+ /* Configure the response to a security violation as a
+ * bus error instead of RAZ/WI */
+ spctrl->secrespcfg |= 1U;
+}
+
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t pos)
+{
+ /* Setting NS flag for peripheral to enable NS access */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbnsppc0))[bank] |= (1U << pos);
+}
+
+void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t pos)
+{
+ /* Clear NS flag for peripheral to prevent NS access */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbnsppc0))[bank] &= ~(1U << pos);
+}
+
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbspppc0))[bank] |= (1U << pos);
+}
+
+void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbspppc0))[bank] &= ~(1U << pos);
+}
+
+void ppc_clear_irq(void)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ /* Clear APB PPC EXP2 IRQ */
+ spctrl->secppcintclr = CMSDK_APB_PPCEXP2_INT_POS_MASK;
+}
diff --git a/platform/ext/target/musca_a/target_cfg.h b/platform/ext/target/musca_a/target_cfg.h
new file mode 100755
index 0000000..c3a8a55
--- /dev/null
+++ b/platform/ext/target/musca_a/target_cfg.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __TARGET_CFG_H__
+#define __TARGET_CFG_H__
+
+enum ppc_bank_e
+{
+ PPC_SP_AHB_PPC0 = 0,
+ PPC_SP_RES0,
+ PPC_SP_RES1,
+ PPC_SP_RES2,
+ PPC_SP_AHB_PPC_EXP0,
+ PPC_SP_AHB_PPC_EXP1,
+ PPC_SP_AHB_PPC_EXP2,
+ PPC_SP_AHB_PPC_EXP3,
+ PPC_SP_APB_PPC0,
+ PPC_SP_APB_PPC1,
+ PPC_SP_RES3,
+ PPC_SP_RES4,
+ PPC_SP_APB_PPC_EXP0,
+ PPC_SP_APB_PPC_EXP1,
+ PPC_SP_APB_PPC_EXP2,
+ PPC_SP_APB_PPC_EXP3,
+};
+
+/**
+ * \brief Configures non-secure code.
+ */
+void configure_ns_code(void);
+
+/**
+ * \brief Jumps to non-secure code.
+ */
+void jump_to_ns_code(void);
+
+/**
+ * \brief Enables the fault handlers BusFault, UsageFault,
+ * MemManageFault and SecureFault.
+ */
+void enable_fault_handlers(void);
+
+/**
+ * \brief Configures all external interrupts to target the
+ * NS state, apart for the ones associated to secure
+ * peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_target_state_cfg();
+
+/**
+ * \brief This function enables the interrupts associated
+ * to the secure peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_enable();
+
+/**
+ * \brief Configures the Memory Protection Controller.
+ */
+void mpc_init_cfg(void);
+
+/**
+ * \brief Configures the Peripheral Protection Controller.
+ */
+void ppc_init_cfg(void);
+
+/**
+ * \brief Restict access to peripheral to secure
+ */
+void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Allow non-secure access to peripheral
+ */
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Enable secure unprivileged access to peripheral
+ */
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clear secure unprivileged access to peripheral
+ */
+void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clears PPC interrupt.
+ */
+void ppc_clear_irq(void);
+
+/**
+ * \brief Configures SAU and IDAU.
+ */
+void sau_and_idau_cfg(void);
+
+
+#endif /* __TARGET_CFG_H__ */