diff --git a/lib/ext/CMSIS_5/CMakeLists.txt b/lib/ext/CMSIS_5/CMakeLists.txt
index 818b09d..b25811a 100644
--- a/lib/ext/CMSIS_5/CMakeLists.txt
+++ b/lib/ext/CMSIS_5/CMakeLists.txt
@@ -18,9 +18,15 @@
     set_target_properties(CMSIS_5_RTX_V8MBN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib)
     set_target_properties(CMSIS_5_RTX_CM3   PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/ARM/RTX_CM3.lib)
 elseif("${CMAKE_C_COMPILER_ID}" STREQUAL IAR)
+    add_library(CMSIS_5_RTX_V81MMN STATIC IMPORTED GLOBAL)
     set_target_properties(CMSIS_5_RTX_V8MMN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V8MMN.a)
+    set_target_properties(CMSIS_5_RTX_V81MMN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V81MMN.a)
     set_target_properties(CMSIS_5_RTX_V8MBN PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_V8MBN.a)
     set_target_properties(CMSIS_5_RTX_CM3   PROPERTIES IMPORTED_LOCATION ${CMSIS_5_PATH}/RTOS2/RTX/Library/IAR/RTX_CM3.a)
+    target_link_libraries(CMSIS_5_RTX_V81MMN
+        INTERFACE
+            tfm_s_veneers
+    )
 else()
     message(FATAL_ERROR "${CMAKE_C_COMPILER_ID} does not have CMSIS RTX static libraries set up")
 endif()
diff --git a/lib/ext/tf-m-tests/repo_config_default.cmake b/lib/ext/tf-m-tests/repo_config_default.cmake
index 10e6c11..56df5e2 100644
--- a/lib/ext/tf-m-tests/repo_config_default.cmake
+++ b/lib/ext/tf-m-tests/repo_config_default.cmake
@@ -8,5 +8,5 @@
 # Default configs of tf-m-tests repo
 
 set(TFM_TEST_REPO_PATH                  "DOWNLOAD"  CACHE PATH      "Path to TFM-TEST repo (or DOWNLOAD to fetch automatically")
-set(TFM_TEST_REPO_VERSION               "db22c68"   CACHE STRING    "The version of tf-m-tests to use")
+set(TFM_TEST_REPO_VERSION               "429be9e"   CACHE STRING    "The version of tf-m-tests to use")
 set(CMSIS_5_PATH                        "DOWNLOAD"  CACHE PATH      "Path to CMSIS_5 (or DOWNLOAD to fetch automatically")
diff --git a/platform/ext/target/arm/mps3/an547/CMakeLists.txt b/platform/ext/target/arm/mps3/an547/CMakeLists.txt
index 7284e25..9d74ce8 100644
--- a/platform/ext/target/arm/mps3/an547/CMakeLists.txt
+++ b/platform/ext/target/arm/mps3/an547/CMakeLists.txt
@@ -17,10 +17,6 @@
 
 #========================= Platform common defs ===============================#
 
-if (${CMAKE_C_COMPILER_ID} STREQUAL IAR)
-    message(FATAL_ERROR "IAR is currently not supported on the mps3/an547 due to a lack of scatter files")
-endif()
-
 if (${CMAKE_C_COMPILER_ID} STREQUAL ARMClang)
     if (${CMAKE_C_COMPILER_VERSION} VERSION_LESS "6.14")
         message(FATAL_ERROR "CPU (Cortex-M55) is only supported in ARMCLANG version 6.14 or newer.")
@@ -35,6 +31,7 @@
 target_add_scatter_file(tfm_s
     $<$<C_COMPILER_ID:ARMClang>:${CMAKE_SOURCE_DIR}/platform/ext/common/armclang/tfm_common_s.sct>
     $<$<C_COMPILER_ID:GNU>:${CMAKE_SOURCE_DIR}/platform/ext/common/gcc/tfm_common_s.ld>
+    $<$<C_COMPILER_ID:IAR>:${CMAKE_SOURCE_DIR}/platform/ext/common/iar/tfm_common_s.icf>
 )
 
 if(NS)
@@ -45,10 +42,13 @@
     target_add_scatter_file(tfm_ns
         $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/an547_ns.sct>
         $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/gcc/an547_ns.ld>
+        $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/iar/an547_ns.icf>
     )
     target_link_libraries(CMSIS_5_tfm_ns
         INTERFACE
-            CMSIS_5_RTX_V8MMN
+            $<$<C_COMPILER_ID:ARMClang>:CMSIS_5_RTX_V8MMN>
+            $<$<C_COMPILER_ID:GNU>:CMSIS_5_RTX_V8MMN>
+            $<$<C_COMPILER_ID:IAR>:CMSIS_5_RTX_V81MMN>
     )
 endif()
 
@@ -60,6 +60,7 @@
     target_add_scatter_file(bl2
             $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/an547_bl2.sct>
             $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/gcc/an547_bl2.ld>
+            $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/iar/an547_bl2.icf>
     )
 endif()
 
diff --git a/platform/ext/target/arm/mps3/an547/device/source/iar/an547_bl2.icf b/platform/ext/target/arm/mps3/an547/device/source/iar/an547_bl2.icf
new file mode 100644
index 0000000..391ef17
--- /dev/null
+++ b/platform/ext/target/arm/mps3/an547/device/source/iar/an547_bl2.icf
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ * Copyright (c) 2021 IAR Systems AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps3_an524_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE        with fixed order, alignment = 8 {
+       section .intvec,
+       readonly
+       };
+define block LR_CODE with fixed order, maximum size = BL2_CODE_SIZE {block ER_CODE};
+place at address BL2_CODE_START {block LR_CODE};
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block ER_DATA         with alignment = 32 {readwrite};
+define block ARM_LIB_STACK   with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP            with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP    {block HEAP};
+keep {block TFM_SHARED_DATA, block ER_DATA, block ARM_LIB_STACK,
+      block HEAP, block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block DATA with fixed order, maximum size = BL2_DATA_SIZE {
+       block TFM_SHARED_DATA,
+       block ER_DATA,
+       block ARM_LIB_STACK,
+       block ARM_LIB_HEAP
+};
+place at address BOOT_TFM_SHARED_DATA_BASE {block DATA};
diff --git a/platform/ext/target/arm/mps3/an547/device/source/iar/an547_ns.icf b/platform/ext/target/arm/mps3/an547/device/source/iar/an547_ns.icf
new file mode 100644
index 0000000..9b344ec
--- /dev/null
+++ b/platform/ext/target/arm/mps3/an547/device/source/iar/an547_ns.icf
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ * Copyright (c) 2021 IAR Systems AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps3_an524_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define block ER_CODE            with fixed order, alignment = 8 {
+       section .intvec,
+       readonly};
+define block LR_CODE with fixed order {block ER_CODE};
+place at address NS_CODE_START {block LR_CODE};
+
+define block ER_DATA	        with alignment = 8 {readwrite};
+define block ARM_LIB_STACK_MSP  with alignment = 32, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK      with alignment = 32, size = NS_PSP_STACK_SIZE { };
+define block HEAP               with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP       {block HEAP};
+keep {block ARM_LIB_STACK_MSP, block ARM_LIB_STACK,
+      block HEAP, block ARM_LIB_HEAP};
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block DATA with fixed order, maximum size = NS_DATA_SIZE  {
+       block ER_DATA,
+       block ARM_LIB_STACK_MSP,
+       block ARM_LIB_STACK,
+       block ARM_LIB_HEAP
+};
+place at address NS_DATA_START {block DATA};
diff --git a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
index 72691ec..db4061a 100644
--- a/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
+++ b/platform/ext/target/arm/mps3/an547/device/source/startup_an547_ns.c
@@ -346,6 +346,10 @@
 void Reset_Handler(void)
 {
   __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
+#ifdef __ICCARM__
+  __set_PSP((uint32_t)(&__INITIAL_SP));
+  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+#endif
 
   SystemInit();                             /* CMSIS System Initialization */
   __ASM volatile("MRS     R0, control\n"    /* Get control value */
diff --git a/platform/ext/target/arm/mps3/an552/CMakeLists.txt b/platform/ext/target/arm/mps3/an552/CMakeLists.txt
index 90b5b23..7a888e6 100644
--- a/platform/ext/target/arm/mps3/an552/CMakeLists.txt
+++ b/platform/ext/target/arm/mps3/an552/CMakeLists.txt
@@ -17,10 +17,6 @@
 
 #========================= Platform common defs ===============================#
 
-if (${CMAKE_C_COMPILER_ID} STREQUAL IAR)
-    message(FATAL_ERROR "IAR is currently not supported on the mps3/an552 due to a lack of scatter files")
-endif()
-
 if (${CMAKE_C_COMPILER_ID} STREQUAL ARMClang)
     if (${CMAKE_C_COMPILER_VERSION} VERSION_LESS "6.14")
         message(FATAL_ERROR "CPU (Cortex-M55) is only supported in ARMCLANG version 6.14 or newer.")
@@ -35,6 +31,7 @@
 target_add_scatter_file(tfm_s
     $<$<C_COMPILER_ID:ARMClang>:${CMAKE_SOURCE_DIR}/platform/ext/common/armclang/tfm_common_s.sct>
     $<$<C_COMPILER_ID:GNU>:${CMAKE_SOURCE_DIR}/platform/ext/common/gcc/tfm_common_s.ld>
+    $<$<C_COMPILER_ID:IAR>:${CMAKE_SOURCE_DIR}/platform/ext/common/iar/tfm_common_s.icf>
 )
 
 if(NS)
@@ -45,10 +42,13 @@
     target_add_scatter_file(tfm_ns
         $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/an552_ns.sct>
         $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/gcc/an552_ns.ld>
+        $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/iar/an552_ns.icf>
     )
     target_link_libraries(CMSIS_5_tfm_ns
         INTERFACE
-            CMSIS_5_RTX_V8MMN
+            $<$<C_COMPILER_ID:ARMClang>:CMSIS_5_RTX_V8MMN>
+            $<$<C_COMPILER_ID:GNU>:CMSIS_5_RTX_V8MMN>
+            $<$<C_COMPILER_ID:IAR>:CMSIS_5_RTX_V81MMN>
     )
 endif()
 
@@ -60,6 +60,7 @@
     target_add_scatter_file(bl2
             $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/an552_bl2.sct>
             $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/gcc/an552_bl2.ld>
+            $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/iar/an552_bl2.icf>
     )
 endif()
 
diff --git a/platform/ext/target/arm/mps3/an552/device/source/iar/an552_bl2.icf b/platform/ext/target/arm/mps3/an552/device/source/iar/an552_bl2.icf
new file mode 100644
index 0000000..ffa32fd
--- /dev/null
+++ b/platform/ext/target/arm/mps3/an552/device/source/iar/an552_bl2.icf
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ * Copyright (c) 2021 IAR Systems AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps3_an524_bl2.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+
+define block ER_CODE        with fixed order, alignment = 8 {
+       section .intvec,
+       readonly
+       };
+define block LR_CODE with fixed order, maximum size = BL2_CODE_SIZE {block ER_CODE};
+place at address BL2_CODE_START {block LR_CODE};
+
+define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { };
+define block ER_DATA         with alignment = 32 {readwrite};
+define block ARM_LIB_STACK   with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP            with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP    with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL      {block HEAP};
+define overlay HEAP_OVL      {block ARM_LIB_HEAP};
+keep {block TFM_SHARED_DATA, block ER_DATA, block ARM_LIB_STACK,
+      block HEAP, block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block DATA with fixed order, maximum size = BL2_DATA_SIZE {
+       block TFM_SHARED_DATA,
+       block ER_DATA,
+       block ARM_LIB_STACK,
+       overlay HEAP_OVL
+};
+place at address BOOT_TFM_SHARED_DATA_BASE {block DATA};
diff --git a/platform/ext/target/arm/mps3/an552/device/source/iar/an552_ns.icf b/platform/ext/target/arm/mps3/an552/device/source/iar/an552_ns.icf
new file mode 100644
index 0000000..9256048
--- /dev/null
+++ b/platform/ext/target/arm/mps3/an552/device/source/iar/an552_ns.icf
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020 Arm Limited
+ * Copyright (c) 2021 IAR Systems AB
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *
+ * This file is derivative of ../armclang/mps3_an524_ns.sct
+ */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+define block ER_CODE            with fixed order, alignment = 8 {
+       section .intvec,
+       readonly};
+define block LR_CODE with fixed order {block ER_CODE};
+place at address NS_CODE_START {block LR_CODE};
+
+define block ER_DATA	        with alignment = 8 {readwrite};
+define block ARM_LIB_STACK_MSP  with alignment = 32, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK      with alignment = 32, size = NS_PSP_STACK_SIZE { };
+define block HEAP               with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP       with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL         {block HEAP};
+define overlay HEAP_OVL         {block ARM_LIB_HEAP};
+keep {block ARM_LIB_STACK_MSP, block ARM_LIB_STACK,
+      block HEAP, block ARM_LIB_HEAP};
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block DATA with fixed order, maximum size = NS_DATA_SIZE  {
+       block ER_DATA,
+       block ARM_LIB_STACK_MSP,
+       block ARM_LIB_STACK,
+       overlay HEAP_OVL
+};
+place at address NS_DATA_START {block DATA};
diff --git a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c
index 72691ec..db4061a 100644
--- a/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c
+++ b/platform/ext/target/arm/mps3/an552/device/source/startup_an552_ns.c
@@ -346,6 +346,10 @@
 void Reset_Handler(void)
 {
   __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
+#ifdef __ICCARM__
+  __set_PSP((uint32_t)(&__INITIAL_SP));
+  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+#endif
 
   SystemInit();                             /* CMSIS System Initialization */
   __ASM volatile("MRS     R0, control\n"    /* Get control value */
diff --git a/toolchain_IARARM.cmake b/toolchain_IARARM.cmake
index af65fc7..89d7ce9 100644
--- a/toolchain_IARARM.cmake
+++ b/toolchain_IARARM.cmake
@@ -49,6 +49,7 @@
         $<$<COMPILE_LANGUAGE:C,CXX>:-DNO_TYPEOF>
         $<$<COMPILE_LANGUAGE:C,CXX>:-D_NO_DEFINITIONS_IN_HEADER_FILES>
         $<$<COMPILE_LANGUAGE:C,CXX>:--diag_suppress=Pe546,Pe940,Pa082,Pa084>
+        $<$<AND:$<COMPILE_LANGUAGE:C,CXX,ASM>,$<NOT:$<BOOL:${TFM_SYSTEM_FP}>>>:--fpu=none>
         $<$<AND:$<COMPILE_LANGUAGE:C,CXX,ASM>,$<BOOL:${TFM_DEBUG_SYMBOLS}>,$<CONFIG:Release,MinSizeRel>>:-r>
     )
 endmacro()
@@ -60,6 +61,7 @@
       --silent
       --semihosting
       --redirect __write=__write_buffered
+      $<$<NOT:$<BOOL:${TFM_SYSTEM_FP}>>:--fpu=none>
     )
 endmacro()