RSS: Use host flash driver
Change-Id: I4d149104e2b9b1560fba7bfd1d2cd32576bedd72
Signed-off-by: Raef Coles <raef.coles@arm.com>
diff --git a/docs/platform/arm/rss/readme.rst b/docs/platform/arm/rss/readme.rst
index cbb2ca9..d36e6ea 100644
--- a/docs/platform/arm/rss/readme.rst
+++ b/docs/platform/arm/rss/readme.rst
@@ -88,23 +88,33 @@
srec_cat \
bl2_signed.bin -Binary -offset 0x0 \
- bl2_signed.bin -Binary -offset 0x20000 \
- tfm_s_ns_signed.bin -Binary -offset 0x40000 \
- tfm_s_ns_signed.bin -Binary -offset 0x140000 \
- <Host AP BL1 image> -Binary -offset 0x240000 \
- <SCP BL1 image> -Binary -offset 0x2C0000 \
- <Host AP BL1 image> -Binary -offset 0x340000 \
- <SCP BL1 image> -Binary -offset 0x3C0000 \
+ bl2_signed.bin -Binary -offset 0x10000 \
+ tfm_s_ns_signed.bin -Binary -offset 0x020000 \
+ tfm_s_ns_signed.bin -Binary -offset 0x0E0000 \
+ <Host AP BL1 image> -Binary -offset 0x1A0000 \
+ <SCP BL1 image> -Binary -offset 0x220000 \
+ <Host AP BL1 image> -Binary -offset 0x2A0000 \
+ <SCP BL1 image> -Binary -offset 0x320000 \
-o flash.bin -Binary
+
+Once the flash image is created, it can be combined with the host FIP to create
+a combined host flash image::
+
+ srec_cat \
+ fip-tc.bin -Binary -offset 0x0\
+ flash.bin -Binary -offset 0x00400000 \
+ -o host_flash.bin -Binary
+
For development purposes, the OTP image is included as a provisioning bundle in
the ROM image and provisioned into OTP by BL1_1. The flash image should include
the signed host images from the previous section. For each boot image, there is
a primary and secondary image; if these are different then BL2 will load the one
with the higher version number.
-The ROM binary should be placed in RSS ROM at ``0x11000000`` and the flash
-binary should be placed at ``0x31000000``.
+The ROM binary should be placed in RSS ROM at ``0x11000000`` and the host flash
+binary should be placed at the base of the host flash. For the TC platform,
+this is at ``0x84000000``.
--------------
diff --git a/platform/ext/target/arm/rss/common/bl1/boot_hal_bl1.c b/platform/ext/target/arm/rss/common/bl1/boot_hal_bl1.c
index 93d8e62..0d9d535 100644
--- a/platform/ext/target/arm/rss/common/bl1/boot_hal_bl1.c
+++ b/platform/ext/target/arm/rss/common/bl1/boot_hal_bl1.c
@@ -50,6 +50,26 @@
return 1;
}
+ /* Initialize BL2 slot 0 region */
+ err = atu_initialize_region(&ATU_DEV_S,
+ 0,
+ HOST_FLASH0_BASE_S + FLASH_AREA_0_OFFSET,
+ HOST_FLASH0_BASE + FLASH_AREA_0_OFFSET,
+ FLASH_AREA_0_SIZE);
+ if (err != ATU_ERR_NONE) {
+ return 1;
+ }
+
+ /* Initialize BL2 slot 1 region */
+ err = atu_initialize_region(&ATU_DEV_S,
+ 1,
+ HOST_FLASH0_BASE_S + FLASH_AREA_1_OFFSET,
+ HOST_FLASH0_BASE + FLASH_AREA_1_OFFSET,
+ FLASH_AREA_1_SIZE);
+ if (err != ATU_ERR_NONE) {
+ return 1;
+ }
+
return 0;
}
diff --git a/platform/ext/target/arm/rss/common/partition/platform_base_address.h b/platform/ext/target/arm/rss/common/partition/platform_base_address.h
index d7e1466..d49ff8c 100644
--- a/platform/ext/target/arm/rss/common/partition/platform_base_address.h
+++ b/platform/ext/target/arm/rss/common/partition/platform_base_address.h
@@ -124,16 +124,22 @@
#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */
#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */
#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */
+
/* Secure Host region */
#define HOST_ACCESS_BASE_S 0x70000000 /* Can access the Host region based on ATU config */
#define HOST_ACCESS_LIMIT_S (HOST_ACCESS_BASE_S + HOST_ACCESS_SIZE - 1)
+
/* ATU regions open in bootloader and runtime */
#define UART0_BASE_S (HOST_ACCESS_BASE_S + 0xFF00000) /* UART 0 Secure base address */
+/* ATU regions open in BL1 */
+#define HOST_FLASH0_BASE_S (HOST_ACCESS_BASE_S + 0x200000) /* Host flash 0 address */
/* ATU regions open in BL2 */
-#define HOST_BOOT0_LOAD_BASE_S HOST_ACCESS_BASE_S /* Host boot image 0 base address */
-#define HOST_BOOT1_LOAD_BASE_S (HOST_ACCESS_BASE_S + 0x100000) /* Host boot image 1 base address */
-/* Regions open at runtime */
-#define HOST_COMMS_MAPPABLE_BASE_S HOST_ACCESS_BASE_S
+#define HOST_BOOT_IMAGE0_LOAD_BASE_S (HOST_ACCESS_BASE_S + 0x000000) /* Host boot image 0 output address */
+#define HOST_BOOT_IMAGE1_LOAD_BASE_S (HOST_ACCESS_BASE_S + 0x100000) /* Host boot image 1 output address */
+#define HOST_FLASH0_BASE_S (HOST_ACCESS_BASE_S + 0x200000) /* Host flash 0 address */
+/* ATU regions open at runtime */
+#define FWU_HOST_IMAGE_BASE_S (HOST_ACCESS_BASE_S + 0x000000) /* Region to allow writing new RSS FW images */
+#define HOST_COMMS_MAPPABLE_BASE_S (HOST_ACCESS_BASE_S + 0x100000) /* Region into which to map host comms pointers */
/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
#define RSS_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller
diff --git a/platform/ext/target/arm/rss/tc/CMakeLists.txt b/platform/ext/target/arm/rss/tc/CMakeLists.txt
index c2dcaa2..5b6cb5f 100644
--- a/platform/ext/target/arm/rss/tc/CMakeLists.txt
+++ b/platform/ext/target/arm/rss/tc/CMakeLists.txt
@@ -23,6 +23,7 @@
PRIVATE
bl2/boot_hal_bl2.c
bl2/flash_map_bl2.c
+ bl2/host_flash_atu.c
)
target_compile_definitions(platform_bl2
diff --git a/platform/ext/target/arm/rss/tc/bl2/boot_hal_bl2.c b/platform/ext/target/arm/rss/tc/bl2/boot_hal_bl2.c
index e71dabd..026ca93 100644
--- a/platform/ext/target/arm/rss/tc/bl2/boot_hal_bl2.c
+++ b/platform/ext/target/arm/rss/tc/bl2/boot_hal_bl2.c
@@ -12,6 +12,7 @@
#ifdef PLATFORM_HAS_BOOT_DMA
#include "boot_dma.h"
#endif /* PLATFORM_HAS_BOOT_DMA */
+#include "flash_layout.h"
#include "bootutil/bootutil_log.h"
#include "device_definition.h"
#include "host_base_address.h"
@@ -24,6 +25,7 @@
#endif /* CRYPTO_HW_ACCELERATOR */
#include "bl2_image_id.h"
#include "Driver_Flash.h"
+#include "host_flash_atu.h"
#ifdef FLASH_DEV_NAME
extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
@@ -75,26 +77,7 @@
int boot_platform_pre_load(uint32_t image_id)
{
- enum atu_error_t err;
-
- if (image_id == RSS_BL2_IMAGE_SCP) {
- /* Initialize SCP ATU region */
- err = atu_initialize_region(&ATU_DEV_S, 0, HOST_BOOT1_LOAD_BASE_S,
- SCP_BL1_SRAM_BASE, SCP_BL1_SIZE);
- if (err != ATU_ERR_NONE) {
- return 1;
- }
-
- } else if (image_id == RSS_BL2_IMAGE_AP) {
- /* Initialize AP ATU region */
- err = atu_initialize_region(&ATU_DEV_S, 0, HOST_BOOT0_LOAD_BASE_S,
- AP_BL1_SRAM_BASE, AP_BL1_SIZE);
- if (err != ATU_ERR_NONE) {
- return 1;
- }
- }
-
- return 0;
+ return host_flash_atu_pre_load(image_id);
}
int boot_platform_post_load(uint32_t image_id)
@@ -109,19 +92,13 @@
/* Remove the image header and move the image to the start of SCP memory
* FIXME: Would be better to set SCP VTOR, but not currently possible
*/
- memmove((void *)HOST_BOOT1_LOAD_BASE_S,
- (void *)(HOST_BOOT1_LOAD_BASE_S + BL2_HEADER_SIZE),
- SCP_BL1_SIZE - BL2_HEADER_SIZE);
+ memmove((void *)HOST_BOOT_IMAGE1_LOAD_BASE_S,
+ (void *)(HOST_BOOT_IMAGE1_LOAD_BASE_S + 0x1000),
+ SCP_BL1_SIZE - 0x1000);
/* Release SCP CPU from wait */
sysctrl->gretreg = 0x1;
- /* Close SCP ATU region */
- err = atu_uninitialize_region(&ATU_DEV_S, 0);
- if (err != ATU_ERR_NONE) {
- return 1;
- }
-
/* Wait for SCP to finish its startup */
BOOT_LOG_INF("Waiting for SCP BL1 started event");
while (channel_stat == 0) {
@@ -130,17 +107,16 @@
BOOT_LOG_INF("Got SCP BL1 started event");
} else if (image_id == RSS_BL2_IMAGE_AP) {
- /* Close AP ATU region */
- err = atu_uninitialize_region(&ATU_DEV_S, 0);
- if (err != ATU_ERR_NONE) {
- return 1;
- }
-
BOOT_LOG_INF("Telling SCP to start AP cores");
mhu_v2_x_initiate_transfer(&MHU_RSS_TO_SCP_DEV);
/* Slot 0 is used in the SCP protocol */
mhu_v2_x_channel_send(&MHU_RSS_TO_SCP_DEV, 0, 1);
}
+ err = host_flash_atu_post_load(image_id);
+ if (err) {
+ return err;
+ }
+
return 0;
}
diff --git a/platform/ext/target/arm/rss/tc/bl2/flash_map_bl2.c b/platform/ext/target/arm/rss/tc/bl2/flash_map_bl2.c
index fc8a9dc..2f7850b 100644
--- a/platform/ext/target/arm/rss/tc/bl2/flash_map_bl2.c
+++ b/platform/ext/target/arm/rss/tc/bl2/flash_map_bl2.c
@@ -98,11 +98,11 @@
*exec_ram_size = NON_SECURE_IMAGE_MAX_SIZE;
rc = 0;
} else if (image_id == RSS_BL2_IMAGE_AP) {
- *exec_ram_start = HOST_BOOT0_LOAD_BASE_S;
+ *exec_ram_start = HOST_BOOT_IMAGE0_LOAD_BASE_S;
*exec_ram_size = AP_BL1_SIZE;
rc = 0;
} else if (image_id == RSS_BL2_IMAGE_SCP) {
- *exec_ram_start = HOST_BOOT1_LOAD_BASE_S;
+ *exec_ram_start = HOST_BOOT_IMAGE1_LOAD_BASE_S;
*exec_ram_size = SCP_BL1_SIZE;
rc = 0;
}
diff --git a/platform/ext/target/arm/rss/tc/bl2/host_flash_atu.c b/platform/ext/target/arm/rss/tc/bl2/host_flash_atu.c
new file mode 100644
index 0000000..d51b701
--- /dev/null
+++ b/platform/ext/target/arm/rss/tc/bl2/host_flash_atu.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "host_flash_atu.h"
+
+#include "bl2_image_id.h"
+#include "flash_layout.h"
+#include "device_definition.h"
+#include "flash_map/flash_map.h"
+
+#define RSS_ATU_REGION_INPUT_IMAGE_SLOT_0 0
+#define RSS_ATU_REGION_INPUT_IMAGE_SLOT_1 1
+#define RSS_ATU_REGION_OUTPUT_IMAGE_SLOT 2
+
+#define HOST_BOOT_AP_LOAD_BASE_S HOST_BOOT_IMAGE0_LOAD_BASE_S
+#define HOST_BOOT_SCP_LOAD_BASE_S HOST_BOOT_IMAGE1_LOAD_BASE_S
+
+extern struct flash_area flash_map[];
+extern int flash_map_entry_num;
+
+static struct flash_area *flash_map_slot_from_flash_area_id(uint32_t area_id)
+{
+ uint32_t idx;
+
+ for (idx = 0; idx < flash_map_entry_num; idx++) {
+ if (area_id == flash_map[idx].fa_id) {
+ return &flash_map[idx];
+ }
+ }
+
+ return NULL;
+}
+
+static int setup_image_input_slots(uint32_t image_id)
+{
+ enum atu_error_t err;
+ struct flash_area *flash_area_primary =
+ flash_map_slot_from_flash_area_id(FLASH_AREA_IMAGE_PRIMARY(image_id));
+ struct flash_area *flash_area_secondary =
+ flash_map_slot_from_flash_area_id(FLASH_AREA_IMAGE_SECONDARY(image_id));
+
+ if (flash_area_primary == NULL || flash_area_secondary == NULL) {
+ return 1;
+ }
+
+ /* Initialize primary input region */
+ err = atu_initialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_INPUT_IMAGE_SLOT_0,
+ HOST_FLASH0_BASE_S + flash_area_primary->fa_off,
+ HOST_FLASH0_BASE + flash_area_primary->fa_off,
+ flash_area_primary->fa_size);
+ if (err != ATU_ERR_NONE) {
+ return 1;
+ }
+
+ /* Initialize secondary input region */
+ err = atu_initialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_INPUT_IMAGE_SLOT_1,
+ HOST_FLASH0_BASE_S + flash_area_secondary->fa_off,
+ HOST_FLASH0_BASE + flash_area_secondary->fa_off,
+ flash_area_secondary->fa_size);
+ if (err != ATU_ERR_NONE) {
+ return 1;
+ }
+
+ return 0;
+}
+
+int host_flash_atu_pre_load(uint32_t image_id)
+{
+ int err;
+ enum atu_error_t atu_err;
+
+ err = setup_image_input_slots(image_id);
+ if (err != 0) {
+ return err;
+ }
+
+ switch (image_id) {
+ case RSS_BL2_IMAGE_SCP:
+ /* Initialize SCP ATU output region */
+ atu_err = atu_initialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_OUTPUT_IMAGE_SLOT,
+ HOST_BOOT_SCP_LOAD_BASE_S,
+ SCP_BL1_SRAM_BASE, SCP_BL1_SIZE);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+ break;
+ case RSS_BL2_IMAGE_AP:
+ /* Initialize AP ATU region */
+ atu_err = atu_initialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_OUTPUT_IMAGE_SLOT,
+ HOST_BOOT_AP_LOAD_BASE_S,
+ AP_BL1_SRAM_BASE, AP_BL1_SIZE);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+ break;
+ case RSS_BL2_IMAGE_NS:
+#ifndef RSS_XIP
+ /* Initialize AP ATU region */
+ atu_err = atu_initialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_OUTPUT_IMAGE_SLOT,
+ HOST_BOOT_AP_LOAD_BASE_S,
+ AP_BL1_SRAM_BASE, AP_BL1_SIZE);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+#endif /* !RSS_XIP */
+ break;
+ case RSS_BL2_IMAGE_S:
+#ifndef RSS_XIP
+ /* Initialize AP ATU region */
+ atu_err = atu_initialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_OUTPUT_IMAGE_SLOT,
+ HOST_BOOT_AP_LOAD_BASE_S,
+ AP_BL1_SRAM_BASE, AP_BL1_SIZE);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+#endif /* !RSS_XIP */
+ break;
+ default:
+ return 1;
+ }
+
+ return 0;
+}
+
+int host_flash_atu_post_load(uint32_t image_id)
+{
+ enum atu_error_t atu_err;
+ (void)image_id;
+
+ atu_err = atu_uninitialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_INPUT_IMAGE_SLOT_0);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+
+ atu_err = atu_uninitialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_INPUT_IMAGE_SLOT_1);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+
+ atu_err = atu_uninitialize_region(&ATU_DEV_S,
+ RSS_ATU_REGION_OUTPUT_IMAGE_SLOT);
+ if (atu_err != ATU_ERR_NONE) {
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/platform/ext/target/arm/rss/tc/bl2/host_flash_atu.h b/platform/ext/target/arm/rss/tc/bl2/host_flash_atu.h
new file mode 100644
index 0000000..102e1b7
--- /dev/null
+++ b/platform/ext/target/arm/rss/tc/bl2/host_flash_atu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __HOST_FLASH_ATU_H__
+#define __HOST_FLASH_ATU_H__
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Performs ATU setup so that the given image can be
+ * accessed within the host flash.
+ *
+ * \param[in] image_id The image id to setup the ATU regions for.
+ *
+ * \return 0 if The regions have been setup successfully.
+ */
+int host_flash_atu_pre_load(uint32_t image_id);
+
+/**
+ * \brief Performs ATU teardown to disable the regions setup
+ * for the particular image.
+ *
+ * \param[in] image_id The image id to teardown the ATU regions for.
+ *
+ * \return 0 if The regions have been disabled successfully.
+ */
+int host_flash_atu_post_load(uint32_t image_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HOST_FLASH_ATU_H__ */
diff --git a/platform/ext/target/arm/rss/tc/flash_layout.h b/platform/ext/target/arm/rss/tc/flash_layout.h
index 25d0606..ffb9e73 100644
--- a/platform/ext/target/arm/rss/tc/flash_layout.h
+++ b/platform/ext/target/arm/rss/tc/flash_layout.h
@@ -19,19 +19,19 @@
#include "host_base_address.h"
-/* Flash layout on RSS with BL2 (multiple image boot):
+/* Flash layout on RSS with XIP mode disabled:
*
- * 0x3100_0000 BL2 - MCUBoot (128 KB)
- * 0x3102_0000 BL2 - MCUBoot (128 KB)
- * 0x3104_0000 Secure image primary slot (512 KB)
- * 0x310C_0000 Non-secure image primary slot (512 KB)
- * 0x3114_0000 Secure image secondary slot (512 KB)
- * 0x311C_0000 Non-secure image secondary slot (512 KB)
- * 0x3124_0000 AP BL1 primary slot (512 KB)
- * 0x312C_0000 SCP BL1 primary slot (512 KB)
- * 0x3134_0000 AP BL1 secondary slot (512 KB)
- * 0x313C_0000 SCP BL1 secondary slot (512 KB)
- * 0x3144_0000 Unused
+ * 0x8400_0000 BL2 - MCUBoot (128 KiB)
+ * 0x8401_0000 BL2 - MCUBoot (128 KiB)
+ * 0x8402_0000 Secure image primary slot (384 KiB)
+ * 0x8408_0000 Non-secure image primary slot (384 KiB)
+ * 0x840E_0000 Secure image secondary slot (384 KiB)
+ * 0x8414_0000 Non-secure image secondary slot (384 KiB)
+ * 0x841A_0000 AP BL1 primary slot (512 KiB)
+ * 0x8422_0000 SCP BL1 primary slot (512 KiB)
+ * 0x842A_0000 AP BL1 secondary slot (512 KiB)
+ * 0x8432_0000 SCP BL1 secondary slot (512 KiB)
+ * 0x843A_0000 Unused
*/
/* This header file is included from linker scatter file as well, where only a