Platform: Add gcc support

The current limitations are:
 - Only level TFM_LVL == 1 is supported (tested with regression test)
 - Only AN521 is supported
 - mbedcrypto.a is linked directly, not as part of secure_storage.a
 - wchar-size-warning is suppressed

Detailed changes are:
 - Work around false error on __attribute_((noreturn))
 - Add cmsis_gcc.h
 - Add linker scripts and startup assembly files for AN521
 - Format region_defs.h so that the expressions are understood by ld
 - Work around missing cmse_nsfptr_create
 - Use cmsis function instead of __arm_rsr

Change-Id: I2e2418023dc873f85dbfe0c6b825d23b018e3fcb
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
diff --git a/app/main_ns.c b/app/main_ns.c
index 13725d0..ab2175d 100644
--- a/app/main_ns.c
+++ b/app/main_ns.c
@@ -93,7 +93,9 @@
 /**
  * \brief main() function
  */
+#ifndef __GNUC__
 __attribute__((noreturn))
+#endif
 int main(void)
 {
     (void)Driver_USART0.Initialize(NULL); /* Use UART0 as stdout */
diff --git a/platform/ext/cmsis/cmsis_gcc.h b/platform/ext/cmsis/cmsis_gcc.h
new file mode 100644
index 0000000..d0526f1
--- /dev/null
+++ b/platform/ext/cmsis/cmsis_gcc.h
@@ -0,0 +1,2026 @@
+/**************************************************************************//**

+ * @file     cmsis_gcc.h

+ * @brief    CMSIS compiler GCC header file

+ * @version  V5.0.2

+ * @date     13. February 2017

+ ******************************************************************************/

+/*

+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.

+ *

+ * SPDX-License-Identifier: Apache-2.0

+ *

+ * Licensed under the Apache License, Version 2.0 (the License); you may

+ * not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ * www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT

+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+

+#ifndef __CMSIS_GCC_H

+#define __CMSIS_GCC_H

+

+/* ignore some GCC warnings */

+#pragma GCC diagnostic push

+#pragma GCC diagnostic ignored "-Wsign-conversion"

+#pragma GCC diagnostic ignored "-Wconversion"

+#pragma GCC diagnostic ignored "-Wunused-parameter"

+

+/* Fallback for __has_builtin */

+#ifndef __has_builtin

+  #define __has_builtin(x) (0)

+#endif

+

+/* CMSIS compiler specific defines */

+#ifndef   __ASM

+  #define __ASM                                  __asm

+#endif

+#ifndef   __INLINE

+  #define __INLINE                               inline

+#endif

+#ifndef   __STATIC_INLINE

+  #define __STATIC_INLINE                        static inline

+#endif

+#ifndef   __STATIC_FORCEINLINE

+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline

+#endif

+#ifndef   __NO_RETURN

+  #define __NO_RETURN                            __attribute__((noreturn))

+#endif

+#ifndef   __USED

+  #define __USED                                 __attribute__((used))

+#endif

+#ifndef   __WEAK

+  #define __WEAK                                 __attribute__((weak))

+#endif

+#ifndef   __PACKED

+  #define __PACKED                               __attribute__((packed, aligned(1)))

+#endif

+#ifndef   __PACKED_STRUCT

+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))

+#endif

+#ifndef   __PACKED_UNION

+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))

+#endif

+#ifndef   __UNALIGNED_UINT32        /* deprecated */

+  #pragma GCC diagnostic push

+  #pragma GCC diagnostic ignored "-Wpacked"

+  #pragma GCC diagnostic ignored "-Wattributes"

+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };

+  #pragma GCC diagnostic pop

+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)

+#endif

+#ifndef   __UNALIGNED_UINT16_WRITE

+  #pragma GCC diagnostic push

+  #pragma GCC diagnostic ignored "-Wpacked"

+  #pragma GCC diagnostic ignored "-Wattributes"

+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };

+  #pragma GCC diagnostic pop

+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))

+#endif

+#ifndef   __UNALIGNED_UINT16_READ

+  #pragma GCC diagnostic push

+  #pragma GCC diagnostic ignored "-Wpacked"

+  #pragma GCC diagnostic ignored "-Wattributes"

+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };

+  #pragma GCC diagnostic pop

+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)

+#endif

+#ifndef   __UNALIGNED_UINT32_WRITE

+  #pragma GCC diagnostic push

+  #pragma GCC diagnostic ignored "-Wpacked"

+  #pragma GCC diagnostic ignored "-Wattributes"

+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };

+  #pragma GCC diagnostic pop

+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))

+#endif

+#ifndef   __UNALIGNED_UINT32_READ

+  #pragma GCC diagnostic push

+  #pragma GCC diagnostic ignored "-Wpacked"

+  #pragma GCC diagnostic ignored "-Wattributes"

+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };

+  #pragma GCC diagnostic pop

+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)

+#endif

+#ifndef   __ALIGNED

+  #define __ALIGNED(x)                           __attribute__((aligned(x)))

+#endif

+#ifndef   __RESTRICT

+  #define __RESTRICT                             __restrict

+#endif

+

+

+/* ###########################  Core Function Access  ########################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

+  @{

+ */

+

+/**

+  \brief   Enable IRQ Interrupts

+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __enable_irq(void)

+{

+  __ASM volatile ("cpsie i" : : : "memory");

+}

+

+

+/**

+  \brief   Disable IRQ Interrupts

+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __disable_irq(void)

+{

+  __ASM volatile ("cpsid i" : : : "memory");

+}

+

+

+/**

+  \brief   Get Control Register

+  \details Returns the content of the Control Register.

+  \return               Control Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Control Register (non-secure)

+  \details Returns the content of the non-secure Control Register when in secure mode.

+  \return               non-secure Control Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Control Register

+  \details Writes the given value to the Control Register.

+  \param [in]    control  Control Register value to set

+ */

+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)

+{

+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Control Register (non-secure)

+  \details Writes the given value to the non-secure Control Register when in secure state.

+  \param [in]    control  Control Register value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)

+{

+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");

+}

+#endif

+

+

+/**

+  \brief   Get IPSR Register

+  \details Returns the content of the IPSR Register.

+  \return               IPSR Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Get APSR Register

+  \details Returns the content of the APSR Register.

+  \return               APSR Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_APSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Get xPSR Register

+  \details Returns the content of the xPSR Register.

+  \return               xPSR Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Get Process Stack Pointer

+  \details Returns the current value of the Process Stack Pointer (PSP).

+  \return               PSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_PSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Process Stack Pointer (non-secure)

+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

+  \return               PSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Process Stack Pointer

+  \details Assigns the given value to the Process Stack Pointer (PSP).

+  \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Process Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

+  \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );

+}

+#endif

+

+

+/**

+  \brief   Get Main Stack Pointer

+  \details Returns the current value of the Main Stack Pointer (MSP).

+  \return               MSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_MSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msp" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Main Stack Pointer (non-secure)

+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

+  \return               MSP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Main Stack Pointer

+  \details Assigns the given value to the Main Stack Pointer (MSP).

+  \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Main Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

+  \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );

+}

+#endif

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Stack Pointer (non-secure)

+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.

+  \return               SP Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );

+  return(result);

+}

+

+

+/**

+  \brief   Set Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.

+  \param [in]    topOfStack  Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)

+{

+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );

+}

+#endif

+

+

+/**

+  \brief   Get Priority Mask

+  \details Returns the current state of the priority mask bit from the Priority Mask Register.

+  \return               Priority Mask value

+ */

+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Priority Mask (non-secure)

+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.

+  \return               Priority Mask value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Priority Mask

+  \details Assigns the given value to the Priority Mask Register.

+  \param [in]    priMask  Priority Mask

+ */

+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Priority Mask (non-secure)

+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.

+  \param [in]    priMask  Priority Mask

+ */

+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");

+}

+#endif

+

+

+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Enable FIQ

+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __enable_fault_irq(void)

+{

+  __ASM volatile ("cpsie f" : : : "memory");

+}

+

+

+/**

+  \brief   Disable FIQ

+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

+           Can only be executed in Privileged modes.

+ */

+__STATIC_FORCEINLINE void __disable_fault_irq(void)

+{

+  __ASM volatile ("cpsid f" : : : "memory");

+}

+

+

+/**

+  \brief   Get Base Priority

+  \details Returns the current value of the Base Priority register.

+  \return               Base Priority register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Base Priority (non-secure)

+  \details Returns the current value of the non-secure Base Priority register when in secure state.

+  \return               Base Priority register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Base Priority

+  \details Assigns the given value to the Base Priority register.

+  \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)

+{

+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Base Priority (non-secure)

+  \details Assigns the given value to the non-secure Base Priority register when in secure state.

+  \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)

+{

+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");

+}

+#endif

+

+

+/**

+  \brief   Set Base Priority with condition

+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

+           or the new value increases the BASEPRI priority level.

+  \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)

+{

+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");

+}

+

+

+/**

+  \brief   Get Fault Mask

+  \details Returns the current value of the Fault Mask register.

+  \return               Fault Mask register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

+  return(result);

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Get Fault Mask (non-secure)

+  \details Returns the current value of the non-secure Fault Mask register when in secure state.

+  \return               Fault Mask register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Fault Mask

+  \details Assigns the given value to the Fault Mask register.

+  \param [in]    faultMask  Fault Mask value to set

+ */

+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

+}

+

+

+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))

+/**

+  \brief   Set Fault Mask (non-secure)

+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.

+  \param [in]    faultMask  Fault Mask value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");

+}

+#endif

+

+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

+

+

+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

+

+/**

+  \brief   Get Process Stack Pointer Limit

+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).

+  \return               PSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );

+  return(result);

+}

+

+

+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \

+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Get Process Stack Pointer Limit (non-secure)

+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

+  \return               PSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Process Stack Pointer Limit

+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

+ */

+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)

+{

+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));

+}

+

+

+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \

+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Set Process Stack Pointer (non-secure)

+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)

+{

+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));

+}

+#endif

+

+

+/**

+  \brief   Get Main Stack Pointer Limit

+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).

+  \return               MSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );

+

+  return(result);

+}

+

+

+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \

+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Get Main Stack Pointer Limit (non-secure)

+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

+  \return               MSPLIM Register value

+ */

+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );

+  return(result);

+}

+#endif

+

+

+/**

+  \brief   Set Main Stack Pointer Limit

+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set

+ */

+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)

+{

+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));

+}

+

+

+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \

+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Set Main Stack Pointer Limit (non-secure)

+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set

+ */

+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)

+{

+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

+}

+#endif

+

+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

+

+

+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+

+/**

+  \brief   Get FPSCR

+  \details Returns the current value of the Floating Point Status/Control register.

+  \return               Floating Point Status/Control register value

+ */

+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)

+{

+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

+  return __builtin_arm_get_fpscr();

+#else

+  uint32_t result;

+

+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

+  return(result);

+#endif

+#else

+  return(0U);

+#endif

+}

+

+

+/**

+  \brief   Set FPSCR

+  \details Assigns the given value to the Floating Point Status/Control register.

+  \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \

+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )

+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)

+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

+  __builtin_arm_set_fpscr(fpscr);

+#else

+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");

+#endif

+#else

+  (void)fpscr;

+#endif

+}

+

+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

+

+

+

+/*@} end of CMSIS_Core_RegAccFunctions */

+

+

+/* ##########################  Core Instruction Access  ######################### */

+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

+  Access to dedicated instructions

+  @{

+*/

+

+/* Define macros for porting to both thumb1 and thumb2.

+ * For thumb1, use low register (r0-r7), specified by constraint "l"

+ * Otherwise, use general registers, specified by constraint "r" */

+#if defined (__thumb__) && !defined (__thumb2__)

+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

+#define __CMSIS_GCC_RW_REG(r) "+l" (r)

+#define __CMSIS_GCC_USE_REG(r) "l" (r)

+#else

+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

+#define __CMSIS_GCC_RW_REG(r) "+r" (r)

+#define __CMSIS_GCC_USE_REG(r) "r" (r)

+#endif

+

+/**

+  \brief   No Operation

+  \details No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+#define __NOP()                             __ASM volatile ("nop")

+

+/**

+  \brief   Wait For Interrupt

+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

+ */

+#define __WFI()                             __ASM volatile ("wfi")

+

+

+/**

+  \brief   Wait For Event

+  \details Wait For Event is a hint instruction that permits the processor to enter

+           a low-power state until one of a number of events occurs.

+ */

+#define __WFE()                             __ASM volatile ("wfe")

+

+

+/**

+  \brief   Send Event

+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+#define __SEV()                             __ASM volatile ("sev")

+

+

+/**

+  \brief   Instruction Synchronization Barrier

+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,

+           so that all instructions following the ISB are fetched from cache or memory,

+           after the instruction has been completed.

+ */

+__STATIC_FORCEINLINE void __ISB(void)

+{

+  __ASM volatile ("isb 0xF":::"memory");

+}

+

+

+/**

+  \brief   Data Synchronization Barrier

+  \details Acts as a special kind of Data Memory Barrier.

+           It completes when all explicit memory accesses before this instruction complete.

+ */

+__STATIC_FORCEINLINE void __DSB(void)

+{

+  __ASM volatile ("dsb 0xF":::"memory");

+}

+

+

+/**

+  \brief   Data Memory Barrier

+  \details Ensures the apparent order of the explicit memory operations before

+           and after the instruction, without ensuring their completion.

+ */

+__STATIC_FORCEINLINE void __DMB(void)

+{

+  __ASM volatile ("dmb 0xF":::"memory");

+}

+

+

+/**

+  \brief   Reverse byte order (32 bit)

+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

+  \param [in]    value  Value to reverse

+  \return               Reversed value

+ */

+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)

+{

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

+  return __builtin_bswap32(value);

+#else

+  uint32_t result;

+

+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return result;

+#endif

+}

+

+

+/**

+  \brief   Reverse byte order (16 bit)

+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

+  \param [in]    value  Value to reverse

+  \return               Reversed value

+ */

+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return result;

+}

+

+

+/**

+  \brief   Reverse byte order (16 bit)

+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

+  \param [in]    value  Value to reverse

+  \return               Reversed value

+ */

+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)

+{

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+  return (int16_t)__builtin_bswap16(value);

+#else

+  int16_t result;

+

+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return result;

+#endif

+}

+

+

+/**

+  \brief   Rotate Right in unsigned value (32 bit)

+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

+  \param [in]    op1  Value to rotate

+  \param [in]    op2  Number of Bits to rotate

+  \return               Rotated value

+ */

+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

+{

+  op2 %= 32U;

+  if (op2 == 0U)

+  {

+    return op1;

+  }

+  return (op1 >> op2) | (op1 << (32U - op2));

+}

+

+

+/**

+  \brief   Breakpoint

+  \details Causes the processor to enter Debug state.

+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+  \param [in]    value  is ignored by the processor.

+                 If required, a debugger can use it to store additional information about the breakpoint.

+ */

+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)

+

+

+/**

+  \brief   Reverse bit order of value

+  \details Reverses the bit order of the given value.

+  \param [in]    value  Value to reverse

+  \return               Reversed value

+ */

+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)

+{

+  uint32_t result;

+

+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

+#else

+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */

+

+  result = value;                      /* r will be reversed bits of v; first get LSB of v */

+  for (value >>= 1U; value != 0U; value >>= 1U)

+  {

+    result <<= 1U;

+    result |= value & 1U;

+    s--;

+  }

+  result <<= s;                        /* shift when v's highest bits are zero */

+#endif

+  return result;

+}

+

+

+/**

+  \brief   Count leading zeros

+  \details Counts the number of leading zeros of a data value.

+  \param [in]  value  Value to count the leading zeros

+  \return             number of leading zeros in value

+ */

+#define __CLZ             __builtin_clz

+

+

+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

+/**

+  \brief   LDR Exclusive (8 bit)

+  \details Executes a exclusive LDR instruction for 8 bit value.

+  \param [in]    ptr  Pointer to data

+  \return             value of type uint8_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/**

+  \brief   LDR Exclusive (16 bit)

+  \details Executes a exclusive LDR instruction for 16 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint16_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/**

+  \brief   LDR Exclusive (32 bit)

+  \details Executes a exclusive LDR instruction for 32 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint32_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );

+   return(result);

+}

+

+

+/**

+  \brief   STR Exclusive (8 bit)

+  \details Executes a exclusive STR instruction for 8 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+  \return          0  Function succeeded

+  \return          1  Function failed

+ */

+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/**

+  \brief   STR Exclusive (16 bit)

+  \details Executes a exclusive STR instruction for 16 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+  \return          0  Function succeeded

+  \return          1  Function failed

+ */

+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/**

+  \brief   STR Exclusive (32 bit)

+  \details Executes a exclusive STR instruction for 32 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+  \return          0  Function succeeded

+  \return          1  Function failed

+ */

+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

+   return(result);

+}

+

+

+/**

+  \brief   Remove the exclusive lock

+  \details Removes the exclusive lock which is created by LDREX.

+ */

+__STATIC_FORCEINLINE void __CLREX(void)

+{

+  __ASM volatile ("clrex" ::: "memory");

+}

+

+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

+

+

+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )

+/**

+  \brief   Signed Saturate

+  \details Saturates a signed value.

+  \param [in]  ARG1  Value to be saturated

+  \param [in]  ARG2  Bit position to saturate to (1..32)

+  \return             Saturated value

+ */

+#define __SSAT(ARG1,ARG2) \

+__extension__ \

+({                          \

+  int32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/**

+  \brief   Unsigned Saturate

+  \details Saturates an unsigned value.

+  \param [in]  ARG1  Value to be saturated

+  \param [in]  ARG2  Bit position to saturate to (0..31)

+  \return             Saturated value

+ */

+#define __USAT(ARG1,ARG2) \

+ __extension__ \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/**

+  \brief   Rotate Right with Extend (32 bit)

+  \details Moves each bit of a bitstring right by one bit.

+           The carry input is shifted in at the left end of the bitstring.

+  \param [in]    value  Value to rotate

+  \return               Rotated value

+ */

+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+}

+

+

+/**

+  \brief   LDRT Unprivileged (8 bit)

+  \details Executes a Unprivileged LDRT instruction for 8 bit value.

+  \param [in]    ptr  Pointer to data

+  \return             value of type uint8_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/**

+  \brief   LDRT Unprivileged (16 bit)

+  \details Executes a Unprivileged LDRT instruction for 16 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint16_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/**

+  \brief   LDRT Unprivileged (32 bit)

+  \details Executes a Unprivileged LDRT instruction for 32 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint32_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return(result);

+}

+

+

+/**

+  \brief   STRT Unprivileged (8 bit)

+  \details Executes a Unprivileged STRT instruction for 8 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+ */

+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)

+{

+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+}

+

+

+/**

+  \brief   STRT Unprivileged (16 bit)

+  \details Executes a Unprivileged STRT instruction for 16 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+ */

+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)

+{

+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+}

+

+

+/**

+  \brief   STRT Unprivileged (32 bit)

+  \details Executes a Unprivileged STRT instruction for 32 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+ */

+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)

+{

+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );

+}

+

+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

+

+/**

+  \brief   Signed Saturate

+  \details Saturates a signed value.

+  \param [in]  value  Value to be saturated

+  \param [in]    sat  Bit position to saturate to (1..32)

+  \return             Saturated value

+ */

+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)

+{

+  if ((sat >= 1U) && (sat <= 32U))

+  {

+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);

+    const int32_t min = -1 - max ;

+    if (val > max)

+    {

+      return max;

+    }

+    else if (val < min)

+    {

+      return min;

+    }

+  }

+  return val;

+}

+

+/**

+  \brief   Unsigned Saturate

+  \details Saturates an unsigned value.

+  \param [in]  value  Value to be saturated

+  \param [in]    sat  Bit position to saturate to (0..31)

+  \return             Saturated value

+ */

+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)

+{

+  if (sat <= 31U)

+  {

+    const uint32_t max = ((1U << sat) - 1U);

+    if (val > (int32_t)max)

+    {

+      return max;

+    }

+    else if (val < 0)

+    {

+      return 0U;

+    }

+  }

+  return (uint32_t)val;

+}

+

+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \

+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \

+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */

+

+

+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )

+/**

+  \brief   Load-Acquire (8 bit)

+  \details Executes a LDAB instruction for 8 bit value.

+  \param [in]    ptr  Pointer to data

+  \return             value of type uint8_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return ((uint8_t) result);

+}

+

+

+/**

+  \brief   Load-Acquire (16 bit)

+  \details Executes a LDAH instruction for 16 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint16_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return ((uint16_t) result);

+}

+

+

+/**

+  \brief   Load-Acquire (32 bit)

+  \details Executes a LDA instruction for 32 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint32_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return(result);

+}

+

+

+/**

+  \brief   Store-Release (8 bit)

+  \details Executes a STLB instruction for 8 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+ */

+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)

+{

+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+}

+

+

+/**

+  \brief   Store-Release (16 bit)

+  \details Executes a STLH instruction for 16 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+ */

+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)

+{

+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+}

+

+

+/**

+  \brief   Store-Release (32 bit)

+  \details Executes a STL instruction for 32 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+ */

+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)

+{

+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

+}

+

+

+/**

+  \brief   Load-Acquire Exclusive (8 bit)

+  \details Executes a LDAB exclusive instruction for 8 bit value.

+  \param [in]    ptr  Pointer to data

+  \return             value of type uint8_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return ((uint8_t) result);

+}

+

+

+/**

+  \brief   Load-Acquire Exclusive (16 bit)

+  \details Executes a LDAH exclusive instruction for 16 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint16_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return ((uint16_t) result);

+}

+

+

+/**

+  \brief   Load-Acquire Exclusive (32 bit)

+  \details Executes a LDA exclusive instruction for 32 bit values.

+  \param [in]    ptr  Pointer to data

+  \return        value of type uint32_t at (*ptr)

+ */

+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );

+   return(result);

+}

+

+

+/**

+  \brief   Store-Release Exclusive (8 bit)

+  \details Executes a STLB exclusive instruction for 8 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+  \return          0  Function succeeded

+  \return          1  Function failed

+ */

+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)

+{

+   uint32_t result;

+

+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/**

+  \brief   Store-Release Exclusive (16 bit)

+  \details Executes a STLH exclusive instruction for 16 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+  \return          0  Function succeeded

+  \return          1  Function failed

+ */

+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)

+{

+   uint32_t result;

+

+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/**

+  \brief   Store-Release Exclusive (32 bit)

+  \details Executes a STL exclusive instruction for 32 bit values.

+  \param [in]  value  Value to store

+  \param [in]    ptr  Pointer to location

+  \return          0  Function succeeded

+  \return          1  Function failed

+ */

+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)

+{

+   uint32_t result;

+

+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \

+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */

+

+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

+

+

+/* ###################  Compiler specific Intrinsics  ########################### */

+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

+  Access to dedicated SIMD instructions

+  @{

+*/

+

+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */

+

+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+

+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+

+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+#define __SSAT16(ARG1,ARG2) \

+({                          \

+  int32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+#define __USAT16(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)

+{

+  uint32_t result;

+

+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)

+{

+  uint32_t result;

+

+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   /* Little endian */

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               /* Big endian */

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   /* Little endian */

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               /* Big endian */

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   /* Little endian */

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               /* Big endian */

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   /* Little endian */

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               /* Big endian */

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)

+{

+  int32_t result;

+

+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)

+{

+  int32_t result;

+

+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+#if 0

+#define __PKHBT(ARG1,ARG2,ARG3) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

+  __RES; \

+ })

+

+#define __PKHTB(ARG1,ARG2,ARG3) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

+  if (ARG3 == 0) \

+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

+  else \

+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

+  __RES; \

+ })

+#endif

+

+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

+

+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

+

+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

+{

+ int32_t result;

+

+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

+ return(result);

+}

+

+#endif /* (__ARM_FEATURE_DSP == 1) */

+/*@} end of group CMSIS_SIMD_intrinsics */

+

+

+#pragma GCC diagnostic pop

+

+#endif /* __CMSIS_GCC_H */

diff --git a/platform/ext/common/uart_stdout.c b/platform/ext/common/uart_stdout.c
index cb5466d..fbf2d17 100755
--- a/platform/ext/common/uart_stdout.c
+++ b/platform/ext/common/uart_stdout.c
@@ -44,6 +44,15 @@
     return ch;

 }

 

+int _write(int fd, char * str, int len)

+{

+    for (int i = 0; i < len; i++)

+    {

+        uart_putc(str[i]);

+    }

+    return len;

+}

+

 #ifdef TARGET_MUSCA_A

 extern struct uart_pl011_dev_t UART0_DEV_S, UART0_DEV_NS;

 extern struct uart_pl011_dev_t UART1_DEV_S, UART1_DEV_NS;

diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld
new file mode 100644
index 0000000..ff2b465
--- /dev/null
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld
@@ -0,0 +1,200 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "../partition/region_defs.h"
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
+  RAM   (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
+}
+
+__heap_size__  = 0x00010000;
+__psp_stack_size__ = 0x00000800;
+__msp_stack_size__ = 0x00000800;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.vectors))
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+         *crtbegin.o(.dtors)
+         *crtbegin?.o(.dtors)
+         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+         *(SORT(.dtors.*))
+         *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * define etext2/data2_start/data2_end and
+     * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_sse_200.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (DEFINED(__etext2) ? __etext2 : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+        __copy_table_end__ = .;
+    } > FLASH
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+        LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+        __zero_table_end__ = .;
+    } > FLASH
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    bss_size = __bss_end__ - __bss_start__;
+
+    .heap (COPY):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+    } > RAM
+
+    .psp_stack :
+    {
+        . = ALIGN(8);
+        KEEP(*(.psp_stack*))
+        . += __psp_stack_size__;
+    } > RAM
+    __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+    Stack_Mem = ADDR(.psp_stack);
+
+    .msp_stack :
+    {
+        . = ALIGN(8);
+        KEEP(*(.psp_stack*))
+        . += __msp_stack_size__;
+    } > RAM
+    __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+    .heap :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        . += __heap_size__;
+        __HeapLimit = .;
+        __heap_limit = .; /* Add for _sbrk */
+    } > RAM
+}
diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld
new file mode 100644
index 0000000..61fd11e
--- /dev/null
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld
@@ -0,0 +1,202 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "../partition/region_defs.h"
+
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
+  RAM   (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
+}
+
+__heap_size__  = 0x00001000;
+__psp_stack_size__ = 0x00000C00;
+__msp_stack_size__ = 0x00000400;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.vectors))
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+         *crtbegin.o(.dtors)
+         *crtbegin?.o(.dtors)
+         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+         *(SORT(.dtors.*))
+         *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * define etext2/data2_start/data2_end and
+     * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_sse_200.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (DEFINED(__etext2) ? __etext2 : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+        __copy_table_end__ = .;
+    } > FLASH
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+        LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+        __zero_table_end__ = .;
+    } > FLASH
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    bss_size = __bss_end__ - __bss_start__;
+
+    .heap (COPY):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+    } > RAM
+
+    .psp_stack :
+    {
+        . = ALIGN(8);
+        KEEP(*(.psp_stack*))
+        . += __psp_stack_size__;
+    } > RAM
+    __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+    Stack_Mem = ADDR(.psp_stack);
+
+    .msp_stack :
+    {
+        . = ALIGN(8);
+        KEEP(*(.psp_stack*))
+        . += __msp_stack_size__;
+    } > RAM
+    __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+    .heap :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        . += __heap_size__;
+        __HeapLimit = .;
+        __heap_limit = .; /* Add for _sbrk */
+    } > RAM
+
+    PROVIDE(__stack = __initial_sp);
+}
diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
new file mode 100644
index 0000000..9123f30
--- /dev/null
+++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld
@@ -0,0 +1,237 @@
+;/*
+; * Copyright (c) 2017-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; *     http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "../partition/region_defs.h"
+
+MEMORY
+{
+  FLASH   (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
+  RAM     (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
+  VENEERS (rx)  : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE
+}
+
+__heap_size__  = 0x00001000;
+__psp_stack_size__ = 0x00001000;
+__msp_stack_size__ = 0x00000800;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.vectors))
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+         *crtbegin.o(.dtors)
+         *crtbegin?.o(.dtors)
+         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+         *(SORT(.dtors.*))
+         *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    /*
+     * Place the CMSE Veneers (containing the SG instruction) after the code, in a
+     * separate 32 bytes aligned region so that the SAU can programmed to just set
+     * this region as Non-Secure Callable.
+     */
+    .gnu.sgstubs :
+    {
+        . = ALIGN(4);
+        *(.gnu.sgstubs*)
+    } > VENEERS
+    Image$$ER_CODE_CMSE_VENEER$$Base = ADDR(.gnu.sgstubs);
+    Image$$ER_CODE_CMSE_VENEER$$Limit = ADDR(.gnu.sgstubs) + SIZEOF(.gnu.sgstubs);
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * define etext2/data2_start/data2_end and
+     * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_sse_200.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (DEFINED(__etext2) ? __etext2 : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+        LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+        __copy_table_end__ = .;
+    } > FLASH
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+        LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+        __zero_table_end__ = .;
+    } > FLASH
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    bss_size = __bss_end__ - __bss_start__;
+
+    .heap (COPY):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+    } > RAM
+
+    .psp_stack :
+    {
+        . = ALIGN(8);
+        KEEP(*(.psp_stack*))
+        . += __psp_stack_size__;
+    } > RAM
+    __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+    Stack_Mem = ADDR(.psp_stack);
+
+    .msp_stack :
+    {
+        . = ALIGN(8);
+        KEEP(*(.psp_stack*))
+        . += __msp_stack_size__;
+    } > RAM
+    __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+    .TFM_SECURE_STACK :
+    {
+        . = ALIGN(8);
+        KEEP(*(.TFM_SECURE_STACK*))
+        . += 0x4000;
+    } > RAM
+
+    Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
+    Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
+
+    .TFM_UNPRIV_SCRATCH :
+    {
+        . = ALIGN(32);
+        KEEP(*(.TFM_UNPRIV_SCRATCH*))
+        . += 0x400;
+    } > RAM
+
+
+    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
+    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
+
+    .heap :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        __HeapBase = .;
+        . += __heap_size__;
+        __HeapLimit = .;
+        __heap_limit = .; /* Add for _sbrk */
+    } > RAM
+
+    PROVIDE(__stack = __initial_sp);
+}
diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S
new file mode 100644
index 0000000..08c0696
--- /dev/null
+++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S
@@ -0,0 +1,386 @@
+;/*

+; * Copyright (c) 2016-2018 ARM Limited

+; *

+; * Licensed under the Apache License, Version 2.0 (the "License");

+; * you may not use this file except in compliance with the License.

+; * You may obtain a copy of the License at

+; *

+; *     http://www.apache.org/licenses/LICENSE-2.0

+; *

+; * Unless required by applicable law or agreed to in writing, software

+; * distributed under the License is distributed on an "AS IS" BASIS,

+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+; * See the License for the specific language governing permissions and

+; * limitations under the License.

+; */

+;

+; /* This file is derivative of CMSIS V5.00 startup_ARMv8MML.s */

+

+

+.syntax    unified

+.arch    armv8-m.main

+

+.section .vectors

+.align 2

+.globl    __Vectors

+

+__Vectors:

+    .long     __initial_msp             /* Top of Stack          */

+    .long     Reset_Handler             /* Reset Handler         */

+    .long     NMI_Handler               /* NMI Handler           */

+    .long     HardFault_Handler         /* Hard Fault Handler    */

+    .long     MemManage_Handler         /* MPU Fault Handler     */

+    .long     BusFault_Handler          /* Bus Fault Handler     */

+    .long     UsageFault_Handler        /* Usage Fault Handler   */

+    .long     SecureFault_Handler       /* Secure Fault Handler  */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     SVC_Handler               /* SVCall Handler        */

+    .long     DebugMon_Handler          /* Debug Monitor Handler */

+    .long     0                         /* Reserved              */

+    .long     PendSV_Handler            /* PendSV Handler        */

+    .long     SysTick_Handler           /* SysTick Handler       */

+

+    /* Core IoT Interrupts */

+    .long      NONSEC_WATCHDOG_RESET_Handler  /* - 0 Non-Secure Watchdog Reset Handler */

+    .long      NONSEC_WATCHDOG_Handler        /* - 1 Non-Secure Watchdog Handler       */

+    .long      S32K_TIMER_Handler             /* - 2 S32K Timer Handler                */

+    .long      TIMER0_Handler                 /* - 3 TIMER 0 Handler                   */

+    .long      TIMER1_Handler                 /* - 4 TIMER 1 Handler                   */

+    .long      DUALTIMER_Handler              /* - 5 Dual Timer Handler                */

+    .long      0                              /* Reserved - 6                          */

+    .long      0                              /* Reserved - 7                          */

+    .long      0                              /* Reserved - 8                          */

+    .long      MPC_Handler                    /* - 9 MPC Combined (Secure) Handler     */

+    .long      PPC_Handler                    /* - 10 PPC Combined (Secure) Handler    */

+    .long      0                              /* Reserved - 11                         */

+    .long      0                              /* Reserved - 12                         */

+    .long      0                              /* Reserved - 13                         */

+    .long      0                              /* Reserved - 14                         */

+    .long      0                              /* Reserved - 15                         */

+    .long      0                              /* Reserved - 16                         */

+    .long      0                              /* Reserved - 17                         */

+    .long      0                              /* Reserved - 18                         */

+    .long      0                              /* Reserved - 19                         */

+    .long      0                              /* Reserved - 20                         */

+    .long      0                              /* Reserved - 21                         */

+    .long      0                              /* Reserved - 22                         */

+    .long      0                              /* Reserved - 23                         */

+    .long      0                              /* Reserved - 24                         */

+    .long      0                              /* Reserved - 25                         */

+    .long      0                              /* Reserved - 26                         */

+    .long      0                              /* Reserved - 27                         */

+    .long      0                              /* Reserved - 28                         */

+    .long      0                              /* Reserved - 29                         */

+    .long      0                              /* Reserved - 30                         */

+    .long      0                              /* Reserved - 31                         */

+    /* External Interrupts */

+    .long     UARTRX0_Handler           /* 32 UART 0 RX Handler               */

+    .long     UARTTX0_Handler           /* 33 UART 0 TX Handler               */

+    .long     UARTRX1_Handler           /* 34 UART 1 RX Handler               */

+    .long     UARTTX1_Handler           /* 35 UART 1 TX Handler               */

+    .long     UARTRX2_Handler           /* 36 UART 2 RX Handler               */

+    .long     UARTTX2_Handler           /* 37 UART 2 TX Handler               */

+    .long     UARTRX3_Handler           /* 38 UART 3 RX Handler               */

+    .long     UARTTX3_Handler           /* 39 UART 3 TX Handler               */

+    .long     UARTRX4_Handler           /* 40 UART 4 RX Handler               */

+    .long     UARTTX4_Handler           /* 41 UART 4 TX Handler               */

+    .long     UART0_Handler             /* 42 UART 0 combined Handler         */

+    .long     UART1_Handler             /* 43 UART 1 combined Handler         */

+    .long     UART2_Handler             /* 44 UART 0 combined Handler         */

+    .long     UART3_Handler             /* 45 UART 1 combined Handler         */

+    .long     UART4_Handler             /* 46 UART 0 combined Handler         */

+    .long     UARTOVF_Handler           /* 47 UART 0,1,2,3,4 Overflow Handler */

+    .long     ETHERNET_Handler          /* 48 Ethernet Handler                */

+    .long     I2S_Handler               /* 49 I2S Handler                     */

+    .long     TSC_Handler               /* 50 Touch Screen Handler            */

+    .long     SPI0_Handler              /* 51 SPI 0 Handler                   */

+    .long     SPI1_Handler              /* 52 SPI 1 Handler                   */

+    .long     SPI2_Handler              /* 53 SPI 2 Handler                   */

+    .long     SPI3_Handler              /* 54 SPI 3 Handler                   */

+    .long     SPI4_Handler              /* 55 SPI 4 Handler                   */

+    .long     DMA0_ERROR_Handler        /* 56 DMA 0 Error Handler             */

+    .long     DMA0_TC_Handler           /* 57 DMA 0 Terminal Count Handler    */

+    .long     DMA0_Handler              /* 58 DMA 0 Combined Handler          */

+    .long     DMA1_ERROR_Handler        /* 59 DMA 1 Error Handler             */

+    .long     DMA1_TC_Handler           /* 60 DMA 1 Terminal Count Handler    */

+    .long     DMA1_Handler              /* 61 DMA 1 Combined Handler          */

+    .long     DMA2_ERROR_Handler        /* 62 DMA 2 Error Handler             */

+    .long     DMA2_TC_Handler           /* 63 DMA 2 Terminal Count Handler    */

+    .long     DMA2_Handler              /* 64 DMA 2 Combined Handler          */

+    .long     DMA3_ERROR_Handler        /* 65 DMA 3 Error Handler             */

+    .long     DMA3_TC_Handler           /* 66 DMA 3 Terminal Count Handler    */

+    .long     DMA3_Handler              /* 67 DMA 3 Combined Handler          */

+    .long     GPIO0_Handler             /* 68 GPIO 0 Comboned Handler         */

+    .long     GPIO1_Handler             /* 69 GPIO 1 Comboned Handler         */

+    .long     GPIO2_Handler             /* 70 GPIO 2 Comboned Handler         */

+    .long     GPIO3_Handler             /* 71 GPIO 3 Comboned Handler         */

+    .long     GPIO0_0_Handler           /* 72,                                */

+    .long     GPIO0_1_Handler           /* 73,                                */

+    .long     GPIO0_2_Handler           /* 74,                                */

+    .long     GPIO0_3_Handler           /* 75,                                */

+    .long     GPIO0_4_Handler           /* 76,                                */

+    .long     GPIO0_5_Handler           /* 77,                                */

+    .long     GPIO0_6_Handler           /* 78,                                */

+    .long     GPIO0_7_Handler           /* 79,                                */

+    .long     GPIO0_8_Handler           /* 80,                                */

+    .long     GPIO0_9_Handler           /* 81,                                */

+    .long     GPIO0_10_Handler          /* 82,                                */

+    .long     GPIO0_11_Handler          /* 83,                                */

+    .long     GPIO0_12_Handler          /* 84,                                */

+    .long     GPIO0_13_Handler          /* 85,                                */

+    .long     GPIO0_14_Handler          /* 86,                                */

+    .long     GPIO0_15_Handler          /* 87,                                */

+    .long     GPIO1_0_Handler           /* 88,                                */

+    .long     GPIO1_1_Handler           /* 89,                                */

+    .long     GPIO1_2_Handler           /* 90,                                */

+    .long     GPIO1_3_Handler           /* 91,                                */

+    .long     GPIO1_4_Handler           /* 92,                                */

+    .long     GPIO1_5_Handler           /* 93,                                */

+    .long     GPIO1_6_Handler           /* 94,                                */

+    .long     GPIO1_7_Handler           /* 95,                                */

+

+    .size    __Vectors, . - __Vectors

+

+    .text

+    .thumb

+    .thumb_func

+    .align    2

+    .globl    Reset_Handler

+    .type    Reset_Handler, %function

+Reset_Handler:

+/*  Firstly it copies data from read only memory to RAM. There are two schemes

+ *  to copy. One can copy more than one sections. Another can only copy

+ *  one section.  The former scheme needs more instructions and read-only

+ *  data to implement than the latter.

+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */

+

+ /* Only run on core 0 */

+    mov     r0, #0x50000000

+    add     r0, #0x0001F000

+    ldr     r0, [r0]

+    cmp     r0,#0

+not_the_core_to_run_on:

+    bne     not_the_core_to_run_on

+

+#ifdef __STARTUP_COPY_MULTIPLE

+/*  Multiple sections scheme.

+ *

+ *  Between symbol address __copy_table_start__ and __copy_table_end__,

+ *  there are array of triplets, each of which specify:

+ *    offset 0: LMA of start of a section to copy from

+ *    offset 4: VMA of start of a section to copy to

+ *    offset 8: size of the section to copy. Must be multiply of 4

+ *

+ *  All addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r4, =__copy_table_start__

+    ldr    r5, =__copy_table_end__

+

+.L_loop0:

+    cmp    r4, r5

+    bge    .L_loop0_done

+    ldr    r1, [r4]

+    ldr    r2, [r4, #4]

+    ldr    r3, [r4, #8]

+

+.L_loop0_0:

+    subs    r3, #4

+    ittt    ge

+    ldrge    r0, [r1, r3]

+    strge    r0, [r2, r3]

+    bge    .L_loop0_0

+

+    adds    r4, #12

+    b    .L_loop0

+

+.L_loop0_done:

+#else

+/*  Single section scheme.

+ *

+ *  The ranges of copy from/to are specified by following symbols

+ *    __etext: LMA of start of the section to copy from. Usually end of text

+ *    __data_start__: VMA of start of the section to copy to

+ *    __data_end__: VMA of end of the section to copy to

+ *

+ *  All addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r1, =__etext

+    ldr    r2, =__data_start__

+    ldr    r3, =__data_end__

+

+.L_loop1:

+    cmp    r2, r3

+    ittt    lt

+    ldrlt    r0, [r1], #4

+    strlt    r0, [r2], #4

+    blt    .L_loop1

+#endif /*__STARTUP_COPY_MULTIPLE */

+

+/*  This part of work usually is done in C library startup code. Otherwise,

+ *  define this macro to enable it in this startup.

+ *

+ *  There are two schemes too. One can clear multiple BSS sections. Another

+ *  can only clear one section. The former is more size expensive than the

+ *  latter.

+ *

+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.

+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.

+ */

+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE

+/*  Multiple sections scheme.

+ *

+ *  Between symbol address __copy_table_start__ and __copy_table_end__,

+ *  there are array of tuples specifying:

+ *    offset 0: Start of a BSS section

+ *    offset 4: Size of this BSS section. Must be multiply of 4

+ */

+    ldr    r3, =__zero_table_start__

+    ldr    r4, =__zero_table_end__

+

+.L_loop2:

+    cmp    r3, r4

+    bge    .L_loop2_done

+    ldr    r1, [r3]

+    ldr    r2, [r3, #4]

+    movs    r0, 0

+

+.L_loop2_0:

+    subs    r2, #4

+    itt    ge

+    strge    r0, [r1, r2]

+    bge    .L_loop2_0

+

+    adds    r3, #8

+    b    .L_loop2

+.L_loop2_done:

+#elif defined (__STARTUP_CLEAR_BSS)

+/*  Single BSS section scheme.

+ *

+ *  The BSS section is specified by following symbols

+ *    __bss_start__: start of the BSS section.

+ *    __bss_end__: end of the BSS section.

+ *

+ *  Both addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r1, =__bss_start__

+    ldr    r2, =__bss_end__

+

+    movs    r0, 0

+.L_loop3:

+    cmp    r1, r2

+    itt    lt

+    strlt    r0, [r1], #4

+    blt    .L_loop3

+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */

+

+#ifndef __NO_SYSTEM_INIT

+    bl    SystemInit

+#endif

+

+    ldr     r0, =__initial_sp

+    msr     psp, r0

+

+#ifndef __START

+#define __START _start

+#endif

+    bl    __START

+

+    .pool

+    .size    Reset_Handler, . - Reset_Handler

+

+    .align    1

+

+/* Dummy Exception Handlers (infinite loops which can be modified) */

+

+    .macro    def_irq_default_handler    handler_name

+    .weak     \handler_name

+    .thumb_func

+    \handler_name:

+    b        \handler_name

+    .endm

+

+    def_irq_default_handler NMI_Handler

+    def_irq_default_handler HardFault_Handler

+    def_irq_default_handler MemManage_Handler

+    def_irq_default_handler BusFault_Handler

+    def_irq_default_handler UsageFault_Handler

+    def_irq_default_handler SecureFault_Handler

+    def_irq_default_handler SVC_Handler

+    def_irq_default_handler DebugMon_Handler

+    def_irq_default_handler PendSV_Handler

+    def_irq_default_handler SysTick_Handler

+    def_irq_default_handler MPC_Handler

+    def_irq_default_handler PPC_Handler

+    def_irq_default_handler NONSEC_WATCHDOG_RESET_Handler

+    def_irq_default_handler NONSEC_WATCHDOG_Handler

+    def_irq_default_handler S32K_TIMER_Handler

+    def_irq_default_handler TIMER0_Handler

+    def_irq_default_handler TIMER1_Handler

+    def_irq_default_handler DUALTIMER_Handler

+    def_irq_default_handler UARTRX0_Handler

+    def_irq_default_handler UARTTX0_Handler

+    def_irq_default_handler UARTRX1_Handler

+    def_irq_default_handler UARTTX1_Handler

+    def_irq_default_handler UARTRX2_Handler

+    def_irq_default_handler UARTTX2_Handler

+    def_irq_default_handler UARTRX3_Handler

+    def_irq_default_handler UARTTX3_Handler

+    def_irq_default_handler UARTRX4_Handler

+    def_irq_default_handler UARTTX4_Handler

+    def_irq_default_handler UART0_Handler

+    def_irq_default_handler UART1_Handler

+    def_irq_default_handler UART2_Handler

+    def_irq_default_handler UART3_Handler

+    def_irq_default_handler UART4_Handler

+    def_irq_default_handler UARTOVF_Handler

+    def_irq_default_handler ETHERNET_Handler

+    def_irq_default_handler I2S_Handler

+    def_irq_default_handler TSC_Handler

+    def_irq_default_handler SPI0_Handler

+    def_irq_default_handler SPI1_Handler

+    def_irq_default_handler SPI2_Handler

+    def_irq_default_handler SPI3_Handler

+    def_irq_default_handler SPI4_Handler

+    def_irq_default_handler DMA0_ERROR_Handler

+    def_irq_default_handler DMA0_TC_Handler

+    def_irq_default_handler DMA0_Handler

+    def_irq_default_handler DMA1_ERROR_Handler

+    def_irq_default_handler DMA1_TC_Handler

+    def_irq_default_handler DMA1_Handler

+    def_irq_default_handler DMA2_ERROR_Handler

+    def_irq_default_handler DMA2_TC_Handler

+    def_irq_default_handler DMA2_Handler

+    def_irq_default_handler DMA3_ERROR_Handler

+    def_irq_default_handler DMA3_TC_Handler

+    def_irq_default_handler DMA3_Handler

+    def_irq_default_handler GPIO0_Handler

+    def_irq_default_handler GPIO1_Handler

+    def_irq_default_handler GPIO2_Handler

+    def_irq_default_handler GPIO3_Handler

+    def_irq_default_handler GPIO0_0_Handler

+    def_irq_default_handler GPIO0_1_Handler

+    def_irq_default_handler GPIO0_2_Handler

+    def_irq_default_handler GPIO0_3_Handler

+    def_irq_default_handler GPIO0_4_Handler

+    def_irq_default_handler GPIO0_5_Handler

+    def_irq_default_handler GPIO0_6_Handler

+    def_irq_default_handler GPIO0_7_Handler

+    def_irq_default_handler GPIO0_8_Handler

+    def_irq_default_handler GPIO0_9_Handler

+    def_irq_default_handler GPIO0_10_Handler

+    def_irq_default_handler GPIO0_11_Handler

+    def_irq_default_handler GPIO0_12_Handler

+    def_irq_default_handler GPIO0_13_Handler

+    def_irq_default_handler GPIO0_14_Handler

+    def_irq_default_handler GPIO0_15_Handler

+    def_irq_default_handler GPIO1_0_Handler

+    def_irq_default_handler GPIO1_1_Handler

+    def_irq_default_handler GPIO1_2_Handler

+    def_irq_default_handler GPIO1_3_Handler

+    def_irq_default_handler GPIO1_4_Handler

+    def_irq_default_handler GPIO1_5_Handler

+    def_irq_default_handler GPIO1_6_Handler

+    def_irq_default_handler GPIO1_7_Handler

+    .end

diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S
new file mode 100644
index 0000000..3e316cc
--- /dev/null
+++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S
@@ -0,0 +1,375 @@
+;/*

+; * Copyright (c) 2016-2018 ARM Limited

+; *

+; * Licensed under the Apache License, Version 2.0 (the "License");

+; * you may not use this file except in compliance with the License.

+; * You may obtain a copy of the License at

+; *

+; *     http://www.apache.org/licenses/LICENSE-2.0

+; *

+; * Unless required by applicable law or agreed to in writing, software

+; * distributed under the License is distributed on an "AS IS" BASIS,

+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+; * See the License for the specific language governing permissions and

+; * limitations under the License.

+; */

+;

+; /* This file is derivative of CMSIS V5.00 startup_ARMv8MML.s */

+

+

+.syntax    unified

+.arch    armv8-m.main

+

+.section .vectors

+.align 2

+.globl    __Vectors

+

+__Vectors:

+    .long     __initial_msp             /* Top of Stack          */

+    .long     Reset_Handler             /* Reset Handler         */

+    .long     NMI_Handler               /* NMI Handler           */

+    .long     HardFault_Handler         /* Hard Fault Handler    */

+    .long     MemManage_Handler         /* MPU Fault Handler     */

+    .long     BusFault_Handler          /* Bus Fault Handler     */

+    .long     UsageFault_Handler        /* Usage Fault Handler   */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     SVC_Handler               /* SVCall Handler        */

+    .long     DebugMon_Handler          /* Debug Monitor Handler */

+    .long     0                         /* Reserved              */

+    .long     PendSV_Handler            /* PendSV Handler        */

+    .long     SysTick_Handler           /* SysTick Handler       */

+

+    /* Core IoT Interrupts */

+    .long      NONSEC_WATCHDOG_RESET_Handler  /* - 0 Non-Secure Watchdog Reset Handler */

+    .long      NONSEC_WATCHDOG_Handler        /* - 1 Non-Secure Watchdog Handler       */

+    .long      S32K_TIMER_Handler             /* - 2 S32K Timer Handler                */

+    .long      TIMER0_Handler                 /* - 3 TIMER 0 Handler                   */

+    .long      TIMER1_Handler                 /* - 4 TIMER 1 Handler                   */

+    .long      DUALTIMER_Handler              /* - 5 Dual Timer Handler                */

+    .long      0                              /* Reserved - 6                          */

+    .long      0                              /* Reserved - 7                          */

+    .long      0                              /* Reserved - 8                          */

+    .long      0                              /* Reserved - 9                          */

+    .long      0                              /* Reserved - 10                         */

+    .long      0                              /* Reserved - 11                         */

+    .long      0                              /* Reserved - 12                         */

+    .long      0                              /* Reserved - 13                         */

+    .long      0                              /* Reserved - 14                         */

+    .long      0                              /* Reserved - 15                         */

+    .long      0                              /* Reserved - 16                         */

+    .long      0                              /* Reserved - 17                         */

+    .long      0                              /* Reserved - 18                         */

+    .long      0                              /* Reserved - 19                         */

+    .long      0                              /* Reserved - 20                         */

+    .long      0                              /* Reserved - 21                         */

+    .long      0                              /* Reserved - 22                         */

+    .long      0                              /* Reserved - 23                         */

+    .long      0                              /* Reserved - 24                         */

+    .long      0                              /* Reserved - 25                         */

+    .long      0                              /* Reserved - 26                         */

+    .long      0                              /* Reserved - 27                         */

+    .long      0                              /* Reserved - 28                         */

+    .long      0                              /* Reserved - 29                         */

+    .long      0                              /* Reserved - 30                         */

+    .long      0                              /* Reserved - 31                         */

+    /* External Interrupts */

+    .long     UARTRX0_Handler           /* 32 UART 0 RX Handler               */

+    .long     UARTTX0_Handler           /* 33 UART 0 TX Handler               */

+    .long     UARTRX1_Handler           /* 34 UART 1 RX Handler               */

+    .long     UARTTX1_Handler           /* 35 UART 1 TX Handler               */

+    .long     UARTRX2_Handler           /* 36 UART 2 RX Handler               */

+    .long     UARTTX2_Handler           /* 37 UART 2 TX Handler               */

+    .long     UARTRX3_Handler           /* 38 UART 3 RX Handler               */

+    .long     UARTTX3_Handler           /* 39 UART 3 TX Handler               */

+    .long     UARTRX4_Handler           /* 40 UART 4 RX Handler               */

+    .long     UARTTX4_Handler           /* 41 UART 4 TX Handler               */

+    .long     UART0_Handler             /* 42 UART 0 combined Handler         */

+    .long     UART1_Handler             /* 43 UART 1 combined Handler         */

+    .long     UART2_Handler             /* 44 UART 0 combined Handler         */

+    .long     UART3_Handler             /* 45 UART 1 combined Handler         */

+    .long     UART4_Handler             /* 46 UART 0 combined Handler         */

+    .long     UARTOVF_Handler           /* 47 UART 0,1,2,3,4 Overflow Handler */

+    .long     ETHERNET_Handler          /* 48 Ethernet Handler                */

+    .long     I2S_Handler               /* 49 I2S Handler                     */

+    .long     TSC_Handler               /* 50 Touch Screen Handler            */

+    .long     SPI0_Handler              /* 51 SPI 0 Handler                   */

+    .long     SPI1_Handler              /* 52 SPI 1 Handler                   */

+    .long     SPI2_Handler              /* 53 SPI 2 Handler                   */

+    .long     SPI3_Handler              /* 54 SPI 3 Handler                   */

+    .long     SPI4_Handler              /* 55 SPI 4 Handler                   */

+    .long     DMA0_ERROR_Handler        /* 56 DMA 0 Error Handler             */

+    .long     DMA0_TC_Handler           /* 57 DMA 0 Terminal Count Handler    */

+    .long     DMA0_Handler              /* 58 DMA 0 Combined Handler          */

+    .long     DMA1_ERROR_Handler        /* 59 DMA 1 Error Handler             */

+    .long     DMA1_TC_Handler           /* 60 DMA 1 Terminal Count Handler    */

+    .long     DMA1_Handler              /* 61 DMA 1 Combined Handler          */

+    .long     DMA2_ERROR_Handler        /* 62 DMA 2 Error Handler             */

+    .long     DMA2_TC_Handler           /* 63 DMA 2 Terminal Count Handler    */

+    .long     DMA2_Handler              /* 64 DMA 2 Combined Handler          */

+    .long     DMA3_ERROR_Handler        /* 65 DMA 3 Error Handler             */

+    .long     DMA3_TC_Handler           /* 66 DMA 3 Terminal Count Handler    */

+    .long     DMA3_Handler              /* 67 DMA 3 Combined Handler          */

+    .long     GPIO0_Handler             /* 68 GPIO 0 Comboned Handler         */

+    .long     GPIO1_Handler             /* 69 GPIO 1 Comboned Handler         */

+    .long     GPIO2_Handler             /* 70 GPIO 2 Comboned Handler         */

+    .long     GPIO3_Handler             /* 71 GPIO 3 Comboned Handler         */

+    .long     GPIO0_0_Handler           /* 72,                                */

+    .long     GPIO0_1_Handler           /* 73,                                */

+    .long     GPIO0_2_Handler           /* 74,                                */

+    .long     GPIO0_3_Handler           /* 75,                                */

+    .long     GPIO0_4_Handler           /* 76,                                */

+    .long     GPIO0_5_Handler           /* 77,                                */

+    .long     GPIO0_6_Handler           /* 78,                                */

+    .long     GPIO0_7_Handler           /* 79,                                */

+    .long     GPIO0_8_Handler           /* 80,                                */

+    .long     GPIO0_9_Handler           /* 81,                                */

+    .long     GPIO0_10_Handler          /* 82,                                */

+    .long     GPIO0_11_Handler          /* 83,                                */

+    .long     GPIO0_12_Handler          /* 84,                                */

+    .long     GPIO0_13_Handler          /* 85,                                */

+    .long     GPIO0_14_Handler          /* 86,                                */

+    .long     GPIO0_15_Handler          /* 87,                                */

+    .long     GPIO1_0_Handler           /* 88,                                */

+    .long     GPIO1_1_Handler           /* 89,                                */

+    .long     GPIO1_2_Handler           /* 90,                                */

+    .long     GPIO1_3_Handler           /* 91,                                */

+    .long     GPIO1_4_Handler           /* 92,                                */

+    .long     GPIO1_5_Handler           /* 93,                                */

+    .long     GPIO1_6_Handler           /* 94,                                */

+    .long     GPIO1_7_Handler           /* 95,                                */

+

+    .size    __Vectors, . - __Vectors

+

+    .text

+    .thumb

+    .thumb_func

+    .align    2

+    .globl    Reset_Handler

+    .type    Reset_Handler, %function

+Reset_Handler:

+/*  Firstly it copies data from read only memory to RAM. There are two schemes

+ *  to copy. One can copy more than one sections. Another can only copy

+ *  one section.  The former scheme needs more instructions and read-only

+ *  data to implement than the latter.

+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */

+

+#ifdef __STARTUP_COPY_MULTIPLE

+/*  Multiple sections scheme.

+ *

+ *  Between symbol address __copy_table_start__ and __copy_table_end__,

+ *  there are array of triplets, each of which specify:

+ *    offset 0: LMA of start of a section to copy from

+ *    offset 4: VMA of start of a section to copy to

+ *    offset 8: size of the section to copy. Must be multiply of 4

+ *

+ *  All addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r4, =__copy_table_start__

+    ldr    r5, =__copy_table_end__

+

+.L_loop0:

+    cmp    r4, r5

+    bge    .L_loop0_done

+    ldr    r1, [r4]

+    ldr    r2, [r4, #4]

+    ldr    r3, [r4, #8]

+

+.L_loop0_0:

+    subs    r3, #4

+    ittt    ge

+    ldrge    r0, [r1, r3]

+    strge    r0, [r2, r3]

+    bge    .L_loop0_0

+

+    adds    r4, #12

+    b    .L_loop0

+

+.L_loop0_done:

+#else

+/*  Single section scheme.

+ *

+ *  The ranges of copy from/to are specified by following symbols

+ *    __etext: LMA of start of the section to copy from. Usually end of text

+ *    __data_start__: VMA of start of the section to copy to

+ *    __data_end__: VMA of end of the section to copy to

+ *

+ *  All addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r1, =__etext

+    ldr    r2, =__data_start__

+    ldr    r3, =__data_end__

+

+.L_loop1:

+    cmp    r2, r3

+    ittt    lt

+    ldrlt    r0, [r1], #4

+    strlt    r0, [r2], #4

+    blt    .L_loop1

+#endif /*__STARTUP_COPY_MULTIPLE */

+

+/*  This part of work usually is done in C library startup code. Otherwise,

+ *  define this macro to enable it in this startup.

+ *

+ *  There are two schemes too. One can clear multiple BSS sections. Another

+ *  can only clear one section. The former is more size expensive than the

+ *  latter.

+ *

+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.

+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.

+ */

+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE

+/*  Multiple sections scheme.

+ *

+ *  Between symbol address __copy_table_start__ and __copy_table_end__,

+ *  there are array of tuples specifying:

+ *    offset 0: Start of a BSS section

+ *    offset 4: Size of this BSS section. Must be multiply of 4

+ */

+    ldr    r3, =__zero_table_start__

+    ldr    r4, =__zero_table_end__

+

+.L_loop2:

+    cmp    r3, r4

+    bge    .L_loop2_done

+    ldr    r1, [r3]

+    ldr    r2, [r3, #4]

+    movs    r0, 0

+

+.L_loop2_0:

+    subs    r2, #4

+    itt    ge

+    strge    r0, [r1, r2]

+    bge    .L_loop2_0

+

+    adds    r3, #8

+    b    .L_loop2

+.L_loop2_done:

+#elif defined (__STARTUP_CLEAR_BSS)

+/*  Single BSS section scheme.

+ *

+ *  The BSS section is specified by following symbols

+ *    __bss_start__: start of the BSS section.

+ *    __bss_end__: end of the BSS section.

+ *

+ *  Both addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r1, =__bss_start__

+    ldr    r2, =__bss_end__

+

+    movs    r0, 0

+.L_loop3:

+    cmp    r1, r2

+    itt    lt

+    strlt    r0, [r1], #4

+    blt    .L_loop3

+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */

+

+    mrs     r0, control    /* Get control value */

+    orr     r0, r0, #1     /* Select switch to unprivilage mode */

+    orr     r0, r0, #2     /* Select switch to PSP */

+    msr     control, r0

+    ldr     r0, =__initial_sp

+    msr     psp, r0

+

+#ifndef __START

+#define __START _start

+#endif

+    bl    __START

+

+    .pool

+    .size    Reset_Handler, . - Reset_Handler

+

+    .align    1

+

+/* Dummy Exception Handlers (infinite loops which can be modified) */

+

+    .macro    def_irq_default_handler    handler_name

+    .weak     \handler_name

+    .thumb_func

+    \handler_name:

+    b        \handler_name

+    .endm

+

+    def_irq_default_handler NMI_Handler

+    def_irq_default_handler HardFault_Handler

+    def_irq_default_handler MemManage_Handler

+    def_irq_default_handler BusFault_Handler

+    def_irq_default_handler UsageFault_Handler

+    def_irq_default_handler SVC_Handler

+    def_irq_default_handler DebugMon_Handler

+    def_irq_default_handler PendSV_Handler

+    def_irq_default_handler SysTick_Handler

+    def_irq_default_handler NONSEC_WATCHDOG_RESET_Handler

+    def_irq_default_handler NONSEC_WATCHDOG_Handler

+    def_irq_default_handler S32K_TIMER_Handler

+    def_irq_default_handler TIMER0_Handler

+    def_irq_default_handler TIMER1_Handler

+    def_irq_default_handler DUALTIMER_Handler

+    def_irq_default_handler UARTRX0_Handler

+    def_irq_default_handler UARTTX0_Handler

+    def_irq_default_handler UARTRX1_Handler

+    def_irq_default_handler UARTTX1_Handler

+    def_irq_default_handler UARTRX2_Handler

+    def_irq_default_handler UARTTX2_Handler

+    def_irq_default_handler UARTRX3_Handler

+    def_irq_default_handler UARTTX3_Handler

+    def_irq_default_handler UARTRX4_Handler

+    def_irq_default_handler UARTTX4_Handler

+    def_irq_default_handler UART0_Handler

+    def_irq_default_handler UART1_Handler

+    def_irq_default_handler UART2_Handler

+    def_irq_default_handler UART3_Handler

+    def_irq_default_handler UART4_Handler

+    def_irq_default_handler UARTOVF_Handler

+    def_irq_default_handler ETHERNET_Handler

+    def_irq_default_handler I2S_Handler

+    def_irq_default_handler TSC_Handler

+    def_irq_default_handler SPI0_Handler

+    def_irq_default_handler SPI1_Handler

+    def_irq_default_handler SPI2_Handler

+    def_irq_default_handler SPI3_Handler

+    def_irq_default_handler SPI4_Handler

+    def_irq_default_handler DMA0_ERROR_Handler

+    def_irq_default_handler DMA0_TC_Handler

+    def_irq_default_handler DMA0_Handler

+    def_irq_default_handler DMA1_ERROR_Handler

+    def_irq_default_handler DMA1_TC_Handler

+    def_irq_default_handler DMA1_Handler

+    def_irq_default_handler DMA2_ERROR_Handler

+    def_irq_default_handler DMA2_TC_Handler

+    def_irq_default_handler DMA2_Handler

+    def_irq_default_handler DMA3_ERROR_Handler

+    def_irq_default_handler DMA3_TC_Handler

+    def_irq_default_handler DMA3_Handler

+    def_irq_default_handler GPIO0_Handler

+    def_irq_default_handler GPIO1_Handler

+    def_irq_default_handler GPIO2_Handler

+    def_irq_default_handler GPIO3_Handler

+    def_irq_default_handler GPIO0_0_Handler

+    def_irq_default_handler GPIO0_1_Handler

+    def_irq_default_handler GPIO0_2_Handler

+    def_irq_default_handler GPIO0_3_Handler

+    def_irq_default_handler GPIO0_4_Handler

+    def_irq_default_handler GPIO0_5_Handler

+    def_irq_default_handler GPIO0_6_Handler

+    def_irq_default_handler GPIO0_7_Handler

+    def_irq_default_handler GPIO0_8_Handler

+    def_irq_default_handler GPIO0_9_Handler

+    def_irq_default_handler GPIO0_10_Handler

+    def_irq_default_handler GPIO0_11_Handler

+    def_irq_default_handler GPIO0_12_Handler

+    def_irq_default_handler GPIO0_13_Handler

+    def_irq_default_handler GPIO0_14_Handler

+    def_irq_default_handler GPIO0_15_Handler

+    def_irq_default_handler GPIO1_0_Handler

+    def_irq_default_handler GPIO1_1_Handler

+    def_irq_default_handler GPIO1_2_Handler

+    def_irq_default_handler GPIO1_3_Handler

+    def_irq_default_handler GPIO1_4_Handler

+    def_irq_default_handler GPIO1_5_Handler

+    def_irq_default_handler GPIO1_6_Handler

+    def_irq_default_handler GPIO1_7_Handler

+    .end

diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
new file mode 100644
index 0000000..3f7f3ba
--- /dev/null
+++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S
@@ -0,0 +1,381 @@
+;/*

+; * Copyright (c) 2016-2018 ARM Limited

+; *

+; * Licensed under the Apache License, Version 2.0 (the "License");

+; * you may not use this file except in compliance with the License.

+; * You may obtain a copy of the License at

+; *

+; *     http://www.apache.org/licenses/LICENSE-2.0

+; *

+; * Unless required by applicable law or agreed to in writing, software

+; * distributed under the License is distributed on an "AS IS" BASIS,

+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+; * See the License for the specific language governing permissions and

+; * limitations under the License.

+; */

+;

+; /* This file is derivative of CMSIS V5.00 startup_ARMv8MML.s */

+

+

+.syntax    unified

+.arch    armv8-m.main

+

+.section .vectors

+.align 2

+.globl    __Vectors

+

+__Vectors:

+    .long     __initial_msp             /* Top of Stack          */

+    .long     Reset_Handler             /* Reset Handler         */

+    .long     NMI_Handler               /* NMI Handler           */

+    .long     HardFault_Handler         /* Hard Fault Handler    */

+    .long     MemManage_Handler         /* MPU Fault Handler     */

+    .long     BusFault_Handler          /* Bus Fault Handler     */

+    .long     UsageFault_Handler        /* Usage Fault Handler   */

+    .long     SecureFault_Handler       /* Secure Fault Handler  */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     0                         /* Reserved              */

+    .long     SVC_Handler               /* SVCall Handler        */

+    .long     DebugMon_Handler          /* Debug Monitor Handler */

+    .long     0                         /* Reserved              */

+    .long     PendSV_Handler            /* PendSV Handler        */

+    .long     SysTick_Handler           /* SysTick Handler       */

+

+    /* Core IoT Interrupts */

+    .long      NONSEC_WATCHDOG_RESET_Handler  /* - 0 Non-Secure Watchdog Reset Handler */

+    .long      NONSEC_WATCHDOG_Handler        /* - 1 Non-Secure Watchdog Handler       */

+    .long      S32K_TIMER_Handler             /* - 2 S32K Timer Handler                */

+    .long      TIMER0_Handler                 /* - 3 TIMER 0 Handler                   */

+    .long      TIMER1_Handler                 /* - 4 TIMER 1 Handler                   */

+    .long      DUALTIMER_Handler              /* - 5 Dual Timer Handler                */

+    .long      0                              /* Reserved - 6                          */

+    .long      0                              /* Reserved - 7                          */

+    .long      0                              /* Reserved - 8                          */

+    .long      MPC_Handler                    /* - 9 MPC Combined (Secure) Handler     */

+    .long      PPC_Handler                    /* - 10 PPC Combined (Secure) Handler    */

+    .long      0                              /* Reserved - 11                         */

+    .long      0                              /* Reserved - 12                         */

+    .long      0                              /* Reserved - 13                         */

+    .long      0                              /* Reserved - 14                         */

+    .long      0                              /* Reserved - 15                         */

+    .long      0                              /* Reserved - 16                         */

+    .long      0                              /* Reserved - 17                         */

+    .long      0                              /* Reserved - 18                         */

+    .long      0                              /* Reserved - 19                         */

+    .long      0                              /* Reserved - 20                         */

+    .long      0                              /* Reserved - 21                         */

+    .long      0                              /* Reserved - 22                         */

+    .long      0                              /* Reserved - 23                         */

+    .long      0                              /* Reserved - 24                         */

+    .long      0                              /* Reserved - 25                         */

+    .long      0                              /* Reserved - 26                         */

+    .long      0                              /* Reserved - 27                         */

+    .long      0                              /* Reserved - 28                         */

+    .long      0                              /* Reserved - 29                         */

+    .long      0                              /* Reserved - 30                         */

+    .long      0                              /* Reserved - 31                         */

+    /* External Interrupts */

+    .long     UARTRX0_Handler           /* 32 UART 0 RX Handler               */

+    .long     UARTTX0_Handler           /* 33 UART 0 TX Handler               */

+    .long     UARTRX1_Handler           /* 34 UART 1 RX Handler               */

+    .long     UARTTX1_Handler           /* 35 UART 1 TX Handler               */

+    .long     UARTRX2_Handler           /* 36 UART 2 RX Handler               */

+    .long     UARTTX2_Handler           /* 37 UART 2 TX Handler               */

+    .long     UARTRX3_Handler           /* 38 UART 3 RX Handler               */

+    .long     UARTTX3_Handler           /* 39 UART 3 TX Handler               */

+    .long     UARTRX4_Handler           /* 40 UART 4 RX Handler               */

+    .long     UARTTX4_Handler           /* 41 UART 4 TX Handler               */

+    .long     UART0_Handler             /* 42 UART 0 combined Handler         */

+    .long     UART1_Handler             /* 43 UART 1 combined Handler         */

+    .long     UART2_Handler             /* 44 UART 0 combined Handler         */

+    .long     UART3_Handler             /* 45 UART 1 combined Handler         */

+    .long     UART4_Handler             /* 46 UART 0 combined Handler         */

+    .long     UARTOVF_Handler           /* 47 UART 0,1,2,3,4 Overflow Handler */

+    .long     ETHERNET_Handler          /* 48 Ethernet Handler                */

+    .long     I2S_Handler               /* 49 I2S Handler                     */

+    .long     TSC_Handler               /* 50 Touch Screen Handler            */

+    .long     SPI0_Handler              /* 51 SPI 0 Handler                   */

+    .long     SPI1_Handler              /* 52 SPI 1 Handler                   */

+    .long     SPI2_Handler              /* 53 SPI 2 Handler                   */

+    .long     SPI3_Handler              /* 54 SPI 3 Handler                   */

+    .long     SPI4_Handler              /* 55 SPI 4 Handler                   */

+    .long     DMA0_ERROR_Handler        /* 56 DMA 0 Error Handler             */

+    .long     DMA0_TC_Handler           /* 57 DMA 0 Terminal Count Handler    */

+    .long     DMA0_Handler              /* 58 DMA 0 Combined Handler          */

+    .long     DMA1_ERROR_Handler        /* 59 DMA 1 Error Handler             */

+    .long     DMA1_TC_Handler           /* 60 DMA 1 Terminal Count Handler    */

+    .long     DMA1_Handler              /* 61 DMA 1 Combined Handler          */

+    .long     DMA2_ERROR_Handler        /* 62 DMA 2 Error Handler             */

+    .long     DMA2_TC_Handler           /* 63 DMA 2 Terminal Count Handler    */

+    .long     DMA2_Handler              /* 64 DMA 2 Combined Handler          */

+    .long     DMA3_ERROR_Handler        /* 65 DMA 3 Error Handler             */

+    .long     DMA3_TC_Handler           /* 66 DMA 3 Terminal Count Handler    */

+    .long     DMA3_Handler              /* 67 DMA 3 Combined Handler          */

+    .long     GPIO0_Handler             /* 68 GPIO 0 Comboned Handler         */

+    .long     GPIO1_Handler             /* 69 GPIO 1 Comboned Handler         */

+    .long     GPIO2_Handler             /* 70 GPIO 2 Comboned Handler         */

+    .long     GPIO3_Handler             /* 71 GPIO 3 Comboned Handler         */

+    .long     GPIO0_0_Handler           /* 72,                                */

+    .long     GPIO0_1_Handler           /* 73,                                */

+    .long     GPIO0_2_Handler           /* 74,                                */

+    .long     GPIO0_3_Handler           /* 75,                                */

+    .long     GPIO0_4_Handler           /* 76,                                */

+    .long     GPIO0_5_Handler           /* 77,                                */

+    .long     GPIO0_6_Handler           /* 78,                                */

+    .long     GPIO0_7_Handler           /* 79,                                */

+    .long     GPIO0_8_Handler           /* 80,                                */

+    .long     GPIO0_9_Handler           /* 81,                                */

+    .long     GPIO0_10_Handler          /* 82,                                */

+    .long     GPIO0_11_Handler          /* 83,                                */

+    .long     GPIO0_12_Handler          /* 84,                                */

+    .long     GPIO0_13_Handler          /* 85,                                */

+    .long     GPIO0_14_Handler          /* 86,                                */

+    .long     GPIO0_15_Handler          /* 87,                                */

+    .long     GPIO1_0_Handler           /* 88,                                */

+    .long     GPIO1_1_Handler           /* 89,                                */

+    .long     GPIO1_2_Handler           /* 90,                                */

+    .long     GPIO1_3_Handler           /* 91,                                */

+    .long     GPIO1_4_Handler           /* 92,                                */

+    .long     GPIO1_5_Handler           /* 93,                                */

+    .long     GPIO1_6_Handler           /* 94,                                */

+    .long     GPIO1_7_Handler           /* 95,                                */

+

+    .size    __Vectors, . - __Vectors

+

+    .text

+    .thumb

+    .thumb_func

+    .align    2

+    .globl    Reset_Handler

+    .type    Reset_Handler, %function

+Reset_Handler:

+/*  Firstly it copies data from read only memory to RAM. There are two schemes

+ *  to copy. One can copy more than one sections. Another can only copy

+ *  one section.  The former scheme needs more instructions and read-only

+ *  data to implement than the latter.

+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */

+

+#ifdef __STARTUP_COPY_MULTIPLE

+/*  Multiple sections scheme.

+ *

+ *  Between symbol address __copy_table_start__ and __copy_table_end__,

+ *  there are array of triplets, each of which specify:

+ *    offset 0: LMA of start of a section to copy from

+ *    offset 4: VMA of start of a section to copy to

+ *    offset 8: size of the section to copy. Must be multiply of 4

+ *

+ *  All addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r4, =__copy_table_start__

+    ldr    r5, =__copy_table_end__

+

+.L_loop0:

+    cmp    r4, r5

+    bge    .L_loop0_done

+    ldr    r1, [r4]

+    ldr    r2, [r4, #4]

+    ldr    r3, [r4, #8]

+

+.L_loop0_0:

+    subs    r3, #4

+    ittt    ge

+    ldrge    r0, [r1, r3]

+    strge    r0, [r2, r3]

+    bge    .L_loop0_0

+

+    adds    r4, #12

+    b    .L_loop0

+

+.L_loop0_done:

+#else

+/*  Single section scheme.

+ *

+ *  The ranges of copy from/to are specified by following symbols

+ *    __etext: LMA of start of the section to copy from. Usually end of text

+ *    __data_start__: VMA of start of the section to copy to

+ *    __data_end__: VMA of end of the section to copy to

+ *

+ *  All addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r1, =__etext

+    ldr    r2, =__data_start__

+    ldr    r3, =__data_end__

+

+.L_loop1:

+    cmp    r2, r3

+    ittt    lt

+    ldrlt    r0, [r1], #4

+    strlt    r0, [r2], #4

+    blt    .L_loop1

+#endif /*__STARTUP_COPY_MULTIPLE */

+

+/*  This part of work usually is done in C library startup code. Otherwise,

+ *  define this macro to enable it in this startup.

+ *

+ *  There are two schemes too. One can clear multiple BSS sections. Another

+ *  can only clear one section. The former is more size expensive than the

+ *  latter.

+ *

+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.

+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.

+ */

+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE

+/*  Multiple sections scheme.

+ *

+ *  Between symbol address __copy_table_start__ and __copy_table_end__,

+ *  there are array of tuples specifying:

+ *    offset 0: Start of a BSS section

+ *    offset 4: Size of this BSS section. Must be multiply of 4

+ */

+    ldr    r3, =__zero_table_start__

+    ldr    r4, =__zero_table_end__

+

+.L_loop2:

+    cmp    r3, r4

+    bge    .L_loop2_done

+    ldr    r1, [r3]

+    ldr    r2, [r3, #4]

+    movs    r0, 0

+

+.L_loop2_0:

+    subs    r2, #4

+    itt    ge

+    strge    r0, [r1, r2]

+    bge    .L_loop2_0

+

+    adds    r3, #8

+    b    .L_loop2

+.L_loop2_done:

+#elif defined (__STARTUP_CLEAR_BSS)

+/*  Single BSS section scheme.

+ *

+ *  The BSS section is specified by following symbols

+ *    __bss_start__: start of the BSS section.

+ *    __bss_end__: end of the BSS section.

+ *

+ *  Both addresses must be aligned to 4 bytes boundary.

+ */

+    ldr    r1, =__bss_start__

+    ldr    r2, =__bss_end__

+

+    movs    r0, 0

+.L_loop3:

+    cmp    r1, r2

+    itt    lt

+    strlt    r0, [r1], #4

+    blt    .L_loop3

+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */

+

+#ifndef __NO_SYSTEM_INIT

+    bl    SystemInit

+#endif

+

+    mrs     r0, control    /* Get control value */

+    orr     r0, r0, #2     /* Select switch to PSP */

+    msr     control, r0

+    ldr     r0, =__initial_sp

+    msr     psp, r0

+

+#ifndef __START

+#define __START _start

+#endif

+    bl    __START

+

+    .pool

+    .size    Reset_Handler, . - Reset_Handler

+

+    .align    1

+

+/* Dummy Exception Handlers (infinite loops which can be modified) */

+

+    .macro    def_irq_default_handler    handler_name

+    .weak     \handler_name

+    .thumb_func

+    \handler_name:

+    b        \handler_name

+    .endm

+

+    def_irq_default_handler NMI_Handler

+    def_irq_default_handler HardFault_Handler

+    def_irq_default_handler MemManage_Handler

+    def_irq_default_handler BusFault_Handler

+    def_irq_default_handler UsageFault_Handler

+    def_irq_default_handler SecureFault_Handler

+    def_irq_default_handler SVC_Handler

+    def_irq_default_handler DebugMon_Handler

+    def_irq_default_handler PendSV_Handler

+    def_irq_default_handler SysTick_Handler

+    def_irq_default_handler MPC_Handler

+    def_irq_default_handler PPC_Handler

+    def_irq_default_handler NONSEC_WATCHDOG_RESET_Handler

+    def_irq_default_handler NONSEC_WATCHDOG_Handler

+    def_irq_default_handler S32K_TIMER_Handler

+    def_irq_default_handler TIMER0_Handler

+    def_irq_default_handler TIMER1_Handler

+    def_irq_default_handler DUALTIMER_Handler

+    def_irq_default_handler UARTRX0_Handler

+    def_irq_default_handler UARTTX0_Handler

+    def_irq_default_handler UARTRX1_Handler

+    def_irq_default_handler UARTTX1_Handler

+    def_irq_default_handler UARTRX2_Handler

+    def_irq_default_handler UARTTX2_Handler

+    def_irq_default_handler UARTRX3_Handler

+    def_irq_default_handler UARTTX3_Handler

+    def_irq_default_handler UARTRX4_Handler

+    def_irq_default_handler UARTTX4_Handler

+    def_irq_default_handler UART0_Handler

+    def_irq_default_handler UART1_Handler

+    def_irq_default_handler UART2_Handler

+    def_irq_default_handler UART3_Handler

+    def_irq_default_handler UART4_Handler

+    def_irq_default_handler UARTOVF_Handler

+    def_irq_default_handler ETHERNET_Handler

+    def_irq_default_handler I2S_Handler

+    def_irq_default_handler TSC_Handler

+    def_irq_default_handler SPI0_Handler

+    def_irq_default_handler SPI1_Handler

+    def_irq_default_handler SPI2_Handler

+    def_irq_default_handler SPI3_Handler

+    def_irq_default_handler SPI4_Handler

+    def_irq_default_handler DMA0_ERROR_Handler

+    def_irq_default_handler DMA0_TC_Handler

+    def_irq_default_handler DMA0_Handler

+    def_irq_default_handler DMA1_ERROR_Handler

+    def_irq_default_handler DMA1_TC_Handler

+    def_irq_default_handler DMA1_Handler

+    def_irq_default_handler DMA2_ERROR_Handler

+    def_irq_default_handler DMA2_TC_Handler

+    def_irq_default_handler DMA2_Handler

+    def_irq_default_handler DMA3_ERROR_Handler

+    def_irq_default_handler DMA3_TC_Handler

+    def_irq_default_handler DMA3_Handler

+    def_irq_default_handler GPIO0_Handler

+    def_irq_default_handler GPIO1_Handler

+    def_irq_default_handler GPIO2_Handler

+    def_irq_default_handler GPIO3_Handler

+    def_irq_default_handler GPIO0_0_Handler

+    def_irq_default_handler GPIO0_1_Handler

+    def_irq_default_handler GPIO0_2_Handler

+    def_irq_default_handler GPIO0_3_Handler

+    def_irq_default_handler GPIO0_4_Handler

+    def_irq_default_handler GPIO0_5_Handler

+    def_irq_default_handler GPIO0_6_Handler

+    def_irq_default_handler GPIO0_7_Handler

+    def_irq_default_handler GPIO0_8_Handler

+    def_irq_default_handler GPIO0_9_Handler

+    def_irq_default_handler GPIO0_10_Handler

+    def_irq_default_handler GPIO0_11_Handler

+    def_irq_default_handler GPIO0_12_Handler

+    def_irq_default_handler GPIO0_13_Handler

+    def_irq_default_handler GPIO0_14_Handler

+    def_irq_default_handler GPIO0_15_Handler

+    def_irq_default_handler GPIO1_0_Handler

+    def_irq_default_handler GPIO1_1_Handler

+    def_irq_default_handler GPIO1_2_Handler

+    def_irq_default_handler GPIO1_3_Handler

+    def_irq_default_handler GPIO1_4_Handler

+    def_irq_default_handler GPIO1_5_Handler

+    def_irq_default_handler GPIO1_6_Handler

+    def_irq_default_handler GPIO1_7_Handler

+    .end

diff --git a/platform/ext/target/mps2/an521/partition/region_defs.h b/platform/ext/target/mps2/an521/partition/region_defs.h
index 6123e6f..410ba43 100644
--- a/platform/ext/target/mps2/an521/partition/region_defs.h
+++ b/platform/ext/target/mps2/an521/partition/region_defs.h
@@ -97,7 +97,7 @@
 #define S_CODE_LIMIT    (S_CODE_START + S_CODE_SIZE - 1)
 
 #define S_DATA_START    (S_RAM_ALIAS(0x0))
-#define S_DATA_SIZE     (TOTAL_RAM_SIZE/2)
+#define S_DATA_SIZE     (TOTAL_RAM_SIZE / 2)
 #define S_DATA_LIMIT    (S_DATA_START + S_DATA_SIZE - 1)
 
 /* CMSE Veneers region */
@@ -125,8 +125,8 @@
             (NS_PARTITION_START + FLASH_PARTITION_SIZE - 1)
 #endif /* BL2 */
 
-#define NS_DATA_START   (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
-#define NS_DATA_SIZE    (TOTAL_RAM_SIZE/2)
+#define NS_DATA_START   (NS_RAM_ALIAS(TOTAL_RAM_SIZE / 2))
+#define NS_DATA_SIZE    (TOTAL_RAM_SIZE / 2)
 #define NS_DATA_LIMIT   (NS_DATA_START + NS_DATA_SIZE -1)
 
 #ifdef BL2
diff --git a/platform/ext/target/mps2/an521/target_cfg.c b/platform/ext/target/mps2/an521/target_cfg.c
index adb584d..6aaaa18 100644
--- a/platform/ext/target/mps2/an521/target_cfg.c
+++ b/platform/ext/target/mps2/an521/target_cfg.c
@@ -59,7 +59,7 @@
 
     /* Clears LSB of the function address to indicate the function-call
        will perform the switch from secure to non-secure */
-    nsfptr_t ns_entry = (nsfptr_t) cmse_nsfptr_create(entry_ptr);
+    nsfptr_t ns_entry = (nsfptr_t) (entry_ptr&(~0x1));
 
     /* All changes made to memory will be effective after this point */
     __DSB();
diff --git a/secure_fw/core/tfm_handler.c b/secure_fw/core/tfm_handler.c
index 9c0db65..0986f27 100644
--- a/secure_fw/core/tfm_handler.c
+++ b/secure_fw/core/tfm_handler.c
@@ -68,9 +68,9 @@
         }
     } else {
         if (lr & EXC_RETURN_STACK_PROCESS) {
-            sp = __arm_rsr("PSP_NS");
+            sp =  __TZ_get_PSP_NS();
         } else {
-            sp = __arm_rsr("MSP_NS");
+            sp = __TZ_get_MSP_NS();
         }
     }