Platform: Add support for AN519 FPGA
- Add platform specific files to an519 platform directory:
drivers, register definitions, startup codes, scatter files
- Add Config*.cmake files for the new target
- Update documentation of supported platforms
- Update compiler flags necessary for Cortex-M23 build
- Add core_cm23.h to cmsis directory
Change-Id: I1519e1ed284dc4f3bc321a0f119d75168e200656
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
diff --git a/ConfigCoreTest.cmake b/ConfigCoreTest.cmake
index 6118ec6..7045d2b 100644
--- a/ConfigCoreTest.cmake
+++ b/ConfigCoreTest.cmake
@@ -13,6 +13,8 @@
message(FATAL_ERROR "ERROR: TARGET_PLATFORM is not set in command line")
elseif(${TARGET_PLATFORM} STREQUAL "AN521")
set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN521.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN519")
+ set (PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN519.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/ConfigDefault.cmake b/ConfigDefault.cmake
index 358b098..c9dbf2f 100644
--- a/ConfigDefault.cmake
+++ b/ConfigDefault.cmake
@@ -13,6 +13,8 @@
message(FATAL_ERROR "ERROR: TARGET_PLATFORM is not set in command line")
elseif(${TARGET_PLATFORM} STREQUAL "AN521")
set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN521.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN519")
+ set (PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN519.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/ConfigRegression.cmake b/ConfigRegression.cmake
index 3595aa7..2a50771 100644
--- a/ConfigRegression.cmake
+++ b/ConfigRegression.cmake
@@ -13,6 +13,8 @@
message(FATAL_ERROR "ERROR: TARGET_PLATFORM is not set in command line")
elseif(${TARGET_PLATFORM} STREQUAL "AN521")
set(PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN521.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN519")
+ set (PLATFORM_CMAKE_FILE "${CMAKE_CURRENT_LIST_DIR}/platform/ext/Mps2AN519.cmake")
else()
message(FATAL_ERROR "ERROR: Target \"${TARGET_PLATFORM}\" is not supported.")
endif()
diff --git a/cmake/Common/CompilerArmClang67.cmake b/cmake/Common/CompilerArmClang67.cmake
index 2bfd1db..c4a5703 100644
--- a/cmake/Common/CompilerArmClang67.cmake
+++ b/cmake/Common/CompilerArmClang67.cmake
@@ -18,6 +18,8 @@
elseif (${ARM_CPU_ARHITECTURE} STREQUAL "ARM8-M-BASE")
string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "--target=" VAL "--target=arm-arm-none-eabi")
string_append_unique_item(STRING CMAKE_C_FLAGS_CPU KEY "-march=" VAL "-march=armv8-m.base")
+ #following is to work around an armclang compiler bug that is fixed in 6.10
+ string_append_unique_item(STRING CMAKE_C_FLAGS KEY "-fno-optimize-sibling-calls" VAL "-fno-optimize-sibling-calls")
string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "--target=" VAL "--target=arm-arm-none-eabi")
string_append_unique_item(STRING CMAKE_CXX_FLAGS_CPU KEY "-march=" VAL "-march=armv8-m.base")
string_append_unique_item(STRING CMAKE_ASM_FLAGS_CPU KEY "--cpu=" VAL "--cpu=8-M.Base")
@@ -43,22 +45,24 @@
#Prefer arhitecture definition over cpu type.
if(NOT DEFINED ARM_CPU_ARHITECTURE)
if(NOT DEFINED ARM_CPU_TYPE)
- set(_NO_ARM_CPU_TYPE true)
+ string_append_unique_item(_NO_ARM_CPU_TYPE true)
elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M3")
- set (CMAKE_C_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m3")
- set (CMAKE_CXX_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m3")
- set (CMAKE_ASM_FLAGS_CPU "--cpu=Cortex-M3")
- set (CMAKE_LINK_FLAGS_CPU "--cpu=Cortex-M3")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m3")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m3")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu=Cortex-M3")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu=Cortex-M3")
elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M33")
- set (CMAKE_C_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m33")
- set (CMAKE_CXX_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m33")
- set (CMAKE_ASM_FLAGS_CPU "--cpu=Cortex-M33")
- set (CMAKE_LINK_FLAGS_CPU "--cpu=Cortex-M33")
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m33")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m33")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu=Cortex-M33")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu=Cortex-M33")
elseif(${ARM_CPU_TYPE} STREQUAL "Cortex-M23")
- set (CMAKE_C_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m23")
- set (CMAKE_CXX_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m23")
- set (CMAKE_ASM_FLAGS_CPU "--cpu=Cortex-M23")
- set (CMAKE_LINK_FLAGS_CPU "--cpu=Cortex-M23")
+ #-fno-optimize-sibling-calls is here to work around an armclang compiler
+ #bug that is fixed in 6.10
+ string_append_unique_item (CMAKE_C_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m23 -fno-optimize-sibling-calls")
+ string_append_unique_item (CMAKE_CXX_FLAGS_CPU "--target=arm-arm-none-eabi -mcpu=cortex-m23 -fno-optimize-sibling-calls")
+ string_append_unique_item (CMAKE_ASM_FLAGS_CPU "--cpu=Cortex-M23")
+ string_append_unique_item (CMAKE_LINK_FLAGS_CPU "--cpu=Cortex-M23")
else()
message(FATAL_ERROR "Unknown ARM cpu setting.")
endif()
diff --git a/platform/ext/Mps2AN519.cmake b/platform/ext/Mps2AN519.cmake
new file mode 100644
index 0000000..2a62c6b
--- /dev/null
+++ b/platform/ext/Mps2AN519.cmake
@@ -0,0 +1,115 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file gathers all MPS2/AN519 specific files in the application.
+
+#MPS2/AN519 has a Cortex M23 CPU.
+include("Common/CpuM23")
+
+set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+#Specify the location of platform specific build dependencies.
+set (BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/armclang/mps2_an519_bl2.sct")
+set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/armclang/mps2_an519_s.sct")
+set (NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/mps2/an519/armclang/mps2_an519_ns.sct")
+set (FLASH_LAYOUT "${PLATFORM_DIR}/target/mps2/an519/partition/flash_layout.h")
+if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib")
+endif()
+
+if (BL2)
+ set (BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
+endif()
+
+embedded_include_directories(PATH "${PLATFORM_DIR}/cmsis" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519/cmsis_core" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519/retarget" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519/native_drivers" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519/partition" ABSOLUTE)
+
+#Gather all source files we need.
+if (NOT DEFINED BUILD_CMSIS_CORE)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_CORE (true|false) is undefined!")
+elseif(BUILD_CMSIS_CORE)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.c")
+endif()
+
+if (NOT DEFINED BUILD_RETARGET)
+ message(FATAL_ERROR "Configuration variable BUILD_RETARGET (true|false) is undefined!")
+elseif(BUILD_RETARGET)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/retarget/platform_retarget_dev.c")
+endif()
+
+if (NOT DEFINED BUILD_UART_STDOUT)
+ message(FATAL_ERROR "Configuration variable BUILD_UART_STDOUT (true|false) is undefined!")
+elseif(BUILD_UART_STDOUT)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/uart_stdout.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+ set(BUILD_NATIVE_DRIVERS true)
+ set(BUILD_CMSIS_DRIVERS true)
+endif()
+
+if (NOT DEFINED BUILD_NATIVE_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_NATIVE_DRIVERS (true|false) is undefined!")
+elseif(BUILD_NATIVE_DRIVERS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/native_drivers/arm_uart_drv.c")
+
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/mps2/an519/native_drivers/mpc_sie200_drv.c"
+ "${PLATFORM_DIR}/target/mps2/an519/native_drivers/ppc_sse200_drv.c"
+ )
+endif()
+
+if (NOT DEFINED BUILD_TIME)
+ message(FATAL_ERROR "Configuration variable BUILD_TIME (true|false) is undefined!")
+elseif(BUILD_TIME)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519/native_drivers/timer_cmsdk" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_STARTUP)
+ message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
+elseif(BUILD_STARTUP)
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s")
+ else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TARGET_CFG)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_CFG (true|false) is undefined!")
+elseif(BUILD_TARGET_CFG)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/target_cfg.c")
+endif()
+
+if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/dummy_crypto_keys.c")
+endif()
+
+if (NOT DEFINED BUILD_CMSIS_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_DRIVERS (true|false) is undefined!")
+elseif(BUILD_CMSIS_DRIVERS)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/mps2/an519/cmsis_drivers/Driver_MPC.c"
+ "${PLATFORM_DIR}/target/mps2/an519/cmsis_drivers/Driver_PPC.c")
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/mps2/an519/cmsis_drivers/Driver_USART.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps2/an519/cmsis_drivers" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_FLASH)
+ message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
+elseif(BUILD_FLASH)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/flash_memory_mapped.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+endif()
diff --git a/platform/ext/cmsis/core_cm23.h b/platform/ext/cmsis/core_cm23.h
new file mode 100644
index 0000000..db8938e
--- /dev/null
+++ b/platform/ext/cmsis/core_cm23.h
@@ -0,0 +1,1888 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.3
+ * @date 09. August 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/platform/ext/target/mps2/an519/RTE_Device.h b/platform/ext/target/mps2/an519/RTE_Device.h
new file mode 100644
index 0000000..860a49f
--- /dev/null
+++ b/platform/ext/target/mps2/an519/RTE_Device.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI0]
+// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define RTE_SPI0 0
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI0]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1 0
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI1]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI2]
+// <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI
+#define RTE_SPI2 0
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI2]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI3]
+// <i> Configuration settings for Driver_SPI3 in component ::Drivers:SPI
+#define RTE_SPI3 0
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI3]
+
+// <e> SPI (Serial Peripheral Interface) [Driver_SPI4]
+// <i> Configuration settings for Driver_SPI4 in component ::Drivers:SPI
+#define RTE_SPI4 0
+// </e> SPI (Serial Peripheral Interface) [Driver_SPI4]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+#define RTE_I2C0 0
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C0]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C1]
+// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1 0
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C1]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+// <i> Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2 0
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+
+// <e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C3]
+// <i> Configuration settings for Driver_I2C3 in component ::Drivers:I2C
+#define RTE_I2C3 0
+// </e> I2C (Inter-integrated Circuit Interface 2) [Driver_I2C3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_USART0 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_USART1 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_USART2 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::Drivers:USART
+#define RTE_USART3 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+// <i> Configuration settings for Driver_USART4 in component ::Drivers:USART
+#define RTE_USART4 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
+#define RTE_ISRAM0_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
+#define RTE_ISRAM1_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+// <i> Configuration settings for Driver_ISRAM2_MPC in component ::Drivers:MPC
+#define RTE_ISRAM2_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+// <i> Configuration settings for Driver_ISRAM3_MPC in component ::Drivers:MPC
+#define RTE_ISRAM3_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+// <i> Configuration settings for Driver_SRAM1_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM1_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM2_MPC]
+// <i> Configuration settings for Driver_SRAM2_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM2_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_SRAM2_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_SRAM3_MPC]
+// <i> Configuration settings for Driver_SRAM3_MPC in component ::Drivers:MPC
+#define RTE_CODE_SRAM3_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_SRAM3_MPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+// <i> Configuration settings for Driver_AHB_PPCEXP0 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1]
+// <i> Configuration settings for Driver_AHB_PPCEXP1 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2]
+// <i> Configuration settings for Driver_AHB_PPCEXP2 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP2 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3]
+// <i> Configuration settings for Driver_AHB_PPCEXP3 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+// <i> Configuration settings for Driver_APB_PPC0 in component ::Drivers:MPC
+#define RTE_APB_PPC0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+// <i> Configuration settings for Driver_APB_PPC1 in component ::Drivers:MPC
+#define RTE_APB_PPC1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+// <i> Configuration settings for Driver_APB_PPCEXP0 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP0 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+// <i> Configuration settings for Driver_APB_PPCEXP1 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP1 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+// <i> Configuration settings for Driver_APB_PPCEXP2 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+// <i> Configuration settings for Driver_APB_PPCEXP3 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP3 0
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3]
+
+#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct
new file mode 100644
index 0000000..cc25ab9
--- /dev/null
+++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct
@@ -0,0 +1,30 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../partition/region_defs.h"
+
+LR_CODE BL2_CODE_START {
+ ER_CODE BL2_CODE_START BL2_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA BL2_DATA_START BL2_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+}
diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct
new file mode 100644
index 0000000..c4c90b1
--- /dev/null
+++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct
@@ -0,0 +1,31 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../partition/region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA NS_DATA_START NS_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+}
+
diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct
new file mode 100644
index 0000000..f22f16d
--- /dev/null
+++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct
@@ -0,0 +1,112 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "../partition/region_defs.h"
+
+LR_CODE S_CODE_START {
+
+ /**** This initial section contains common code for TEE */
+ ER_TFM_CODE S_CODE_START S_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+#if TFM_LVL == 1
+
+ ER_TFM_DATA S_DATA_START S_DATA_SIZE {
+ .ANY (+RW +ZI)
+ }
+
+ TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x4000 {
+ }
+
+ TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
+ }
+
+#else /* TFM_LVL == 1 */
+
+ /**** Unprivileged Secure code start here */
+ TFM_UNPRIV_CODE +0 ALIGN 32 {
+ tfm_unpriv_api.o (+RO)
+ platform_retarget_dev.o (+RO)
+ *(SFN)
+ }
+
+ TFM_SEC_FUNC_STORAGE +0 ALIGN 32 {
+ *tfm_storage* (+RO)
+ }
+
+#ifdef CORE_TEST_SERVICES
+ TFM_SEC_FUNC_CORE_TEST +0 ALIGN 32 {
+ *tfm_ss_core_test.* (+RO)
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_2 +0 ALIGN 32 {
+ *tfm_ss_core_test_2.* (+RO)
+ }
+#endif /* CORE_TEST_SERVICES */
+
+ ER_TFM_DATA S_DATA_START S_DATA_SIZE {
+ .ANY (+RW +ZI)
+ }
+
+ TFM_UNPRIV_RO_DATA +0 ALIGN 32 {
+ tfm_unpriv_api.o (+RW +ZI)
+ platform_retarget_dev.o (+RW +ZI)
+ }
+
+ TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
+ }
+
+ TFM_SEC_FUNC_STORAGE_DATA +0 ALIGN 32 {
+ *tfm_storage* (+RW +ZI)
+ }
+
+ TFM_SEC_FUNC_STORAGE_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+
+#ifdef CORE_TEST_SERVICES
+ TFM_SEC_FUNC_CORE_TEST_DATA +0 ALIGN 32 {
+ tfm_ss_core_test.o (+RW +ZI)
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_2_DATA +0 ALIGN 32 {
+ tfm_ss_core_test_2.o (+RW +ZI)
+ }
+
+ TFM_SEC_FUNC_CORE_TEST_2_STACK +0 ALIGN 128 EMPTY 0x2000 {
+ }
+#endif /* CORE_TEST_SERVICES */
+
+#endif /* TFM_LVL == 1 */
+
+}
+
+LR_VENEER CMSE_VENEER_REGION_START {
+ /*
+ * Place the CMSE Veneers (containing the SG instruction) in a separate
+ * 32 bytes aligned region so that the SAU can be programmed to
+ * just set this region as Non-Secure Callable.
+ */
+ ER_CODE_CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
diff --git a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s
new file mode 100644
index 0000000..e80b1a0
--- /dev/null
+++ b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s
@@ -0,0 +1,346 @@
+;/*
+; * Copyright (c) 2016-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00010000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+MPC_Handler PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+PPC_Handler PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s
new file mode 100644
index 0000000..cd25673
--- /dev/null
+++ b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s
@@ -0,0 +1,400 @@
+;/*
+; * Copyright (c) 2016-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_msp
+
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00001000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD 0 ; Reserved - 9
+ DCD 0 ; Reserved - 10
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ MOVS R1, #1
+ ORRS R0, R0, R1 ; Select switch to unprivileged mode
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__initial_sp
+ MOV SP, R0 ; Initialise PSP
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
+ EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
+ EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
+ EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
+ EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
+ EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
+ EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
+ EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
+ EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
+ EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
+ EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
+ EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
+ EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
+ EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
+ EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
+ EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
+ EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73
+ EXPORT GPIO0_2_Handler [WEAK] ; 74
+ EXPORT GPIO0_3_Handler [WEAK] ; 75
+ EXPORT GPIO0_4_Handler [WEAK] ; 76
+ EXPORT GPIO0_5_Handler [WEAK] ; 77
+ EXPORT GPIO0_6_Handler [WEAK] ; 78
+ EXPORT GPIO0_7_Handler [WEAK] ; 79
+ EXPORT GPIO0_8_Handler [WEAK] ; 80
+ EXPORT GPIO0_9_Handler [WEAK] ; 81
+ EXPORT GPIO0_10_Handler [WEAK] ; 82
+ EXPORT GPIO0_11_Handler [WEAK] ; 83
+ EXPORT GPIO0_12_Handler [WEAK] ; 84
+ EXPORT GPIO0_13_Handler [WEAK] ; 85
+ EXPORT GPIO0_14_Handler [WEAK] ; 86
+ EXPORT GPIO0_15_Handler [WEAK] ; 87
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
+ EXPORT GPIO1_1_Handler [WEAK] ; 89
+ EXPORT GPIO1_2_Handler [WEAK] ; 90
+ EXPORT GPIO1_3_Handler [WEAK] ; 91
+ EXPORT GPIO1_4_Handler [WEAK] ; 92
+ EXPORT GPIO1_5_Handler [WEAK] ; 93
+ EXPORT GPIO1_6_Handler [WEAK] ; 94
+ EXPORT GPIO1_7_Handler [WEAK] ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s
new file mode 100644
index 0000000..d4dc32f
--- /dev/null
+++ b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s
@@ -0,0 +1,413 @@
+;/*
+; * Copyright (c) 2016-2018 ARM Limited
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00001000
+MSP_STACK_SIZE EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT Stack_Mem
+Stack_Mem SPACE Stack_Size
+__initial_msp
+__initial_sp EQU __initial_msp - MSP_STACK_SIZE
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00001000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ PRESERVE8
+
+__Vectors DCD __initial_msp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler
+ DCD TIMER0_Handler ; - 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; - 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; - 5 Dual Timer Handler
+ DCD 0 ; Reserved - 6
+ DCD 0 ; Reserved - 7
+ DCD 0 ; Reserved - 8
+ DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler
+ DCD 0 ; Reserved - 11
+ DCD 0 ; Reserved - 12
+ DCD 0 ; Reserved - 13
+ DCD 0 ; Reserved - 14
+ DCD 0 ; Reserved - 15
+ DCD 0 ; Reserved - 16
+ DCD 0 ; Reserved - 17
+ DCD 0 ; Reserved - 18
+ DCD 0 ; Reserved - 19
+ DCD 0 ; Reserved - 20
+ DCD 0 ; Reserved - 21
+ DCD 0 ; Reserved - 22
+ DCD 0 ; Reserved - 23
+ DCD 0 ; Reserved - 24
+ DCD 0 ; Reserved - 25
+ DCD 0 ; Reserved - 26
+ DCD 0 ; Reserved - 27
+ DCD 0 ; Reserved - 28
+ DCD 0 ; Reserved - 29
+ DCD 0 ; Reserved - 30
+ DCD 0 ; Reserved - 31
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 0 combined Handler
+ DCD UART3_Handler ; 45 UART 1 combined Handler
+ DCD UART4_Handler ; 46 UART 0 combined Handler
+ DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD SPI0_Handler ; 51 SPI 0 Handler
+ DCD SPI1_Handler ; 52 SPI 1 Handler
+ DCD SPI2_Handler ; 53 SPI 2 Handler
+ DCD SPI3_Handler ; 54 SPI 3 Handler
+ DCD SPI4_Handler ; 55 SPI 4 Handler
+ DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+ DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+ DCD DMA0_Handler ; 58 DMA 0 Combined Handler
+ DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+ DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+ DCD DMA1_Handler ; 61 DMA 1 Combined Handler
+ DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+ DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+ DCD DMA2_Handler ; 64 DMA 2 Combined Handler
+ DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+ DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+ DCD DMA3_Handler ; 67 DMA 3 Combined Handler
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72,
+ DCD GPIO0_1_Handler ; 73,
+ DCD GPIO0_2_Handler ; 74,
+ DCD GPIO0_3_Handler ; 75,
+ DCD GPIO0_4_Handler ; 76,
+ DCD GPIO0_5_Handler ; 77,
+ DCD GPIO0_6_Handler ; 78,
+ DCD GPIO0_7_Handler ; 79,
+ DCD GPIO0_8_Handler ; 80,
+ DCD GPIO0_9_Handler ; 81,
+ DCD GPIO0_10_Handler ; 82,
+ DCD GPIO0_11_Handler ; 83,
+ DCD GPIO0_12_Handler ; 84,
+ DCD GPIO0_13_Handler ; 85,
+ DCD GPIO0_14_Handler ; 86,
+ DCD GPIO0_15_Handler ; 87,
+ DCD GPIO1_0_Handler ; 88,
+ DCD GPIO1_1_Handler ; 89,
+ DCD GPIO1_2_Handler ; 90,
+ DCD GPIO1_3_Handler ; 91,
+ DCD GPIO1_4_Handler ; 92,
+ DCD GPIO1_5_Handler ; 93,
+ DCD GPIO1_6_Handler ; 94,
+ DCD GPIO1_7_Handler ; 95,
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ MOVS R1, #2
+ ORRS R0, R0, R1 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__initial_sp
+ MOVS R1, #7
+ BICS R0, R1 ; Make sure that the SP address is aligned to 8
+ MOV SP, R0 ; Initialise PSP
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+MPC_Handler PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+PPC_Handler PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; - 0 Non-Secure Watchdog Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; - 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; - 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; - 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; - 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; - 5 Dual Timer Handler
+; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART 0,1,2,3,4 Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 51 SPI 0 Handler
+ EXPORT SPI1_Handler [WEAK] ; 52 SPI 1 Handler
+ EXPORT SPI2_Handler [WEAK] ; 53 SPI 2 Handler
+ EXPORT SPI3_Handler [WEAK] ; 54 SPI 3 Handler
+ EXPORT SPI4_Handler [WEAK] ; 55 SPI 4 Handler
+ EXPORT DMA0_ERROR_Handler [WEAK] ; 56 DMA 0 Error Handler
+ EXPORT DMA0_TC_Handler [WEAK] ; 57 DMA 0 Terminal Count Handler
+ EXPORT DMA0_Handler [WEAK] ; 58 DMA 0 Combined Handler
+ EXPORT DMA1_ERROR_Handler [WEAK] ; 59 DMA 1 Error Handler
+ EXPORT DMA1_TC_Handler [WEAK] ; 60 DMA 1 Terminal Count Handler
+ EXPORT DMA1_Handler [WEAK] ; 61 DMA 1 Combined Handler
+ EXPORT DMA2_ERROR_Handler [WEAK] ; 62 DMA 2 Error Handler
+ EXPORT DMA2_TC_Handler [WEAK] ; 63 DMA 2 Terminal Count Handler
+ EXPORT DMA2_Handler [WEAK] ; 64 DMA 2 Combined Handler
+ EXPORT DMA3_ERROR_Handler [WEAK] ; 65 DMA 3 Error Handler
+ EXPORT DMA3_TC_Handler [WEAK] ; 66 DMA 3 Terminal Count Handler
+ EXPORT DMA3_Handler [WEAK] ; 67 DMA 3 Combined Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO 1 has 16 individual Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73
+ EXPORT GPIO0_2_Handler [WEAK] ; 74
+ EXPORT GPIO0_3_Handler [WEAK] ; 75
+ EXPORT GPIO0_4_Handler [WEAK] ; 76
+ EXPORT GPIO0_5_Handler [WEAK] ; 77
+ EXPORT GPIO0_6_Handler [WEAK] ; 78
+ EXPORT GPIO0_7_Handler [WEAK] ; 79
+ EXPORT GPIO0_8_Handler [WEAK] ; 80
+ EXPORT GPIO0_9_Handler [WEAK] ; 81
+ EXPORT GPIO0_10_Handler [WEAK] ; 82
+ EXPORT GPIO0_11_Handler [WEAK] ; 83
+ EXPORT GPIO0_12_Handler [WEAK] ; 84
+ EXPORT GPIO0_13_Handler [WEAK] ; 85
+ EXPORT GPIO0_14_Handler [WEAK] ; 86
+ EXPORT GPIO0_15_Handler [WEAK] ; 87
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO 1 has 8 individual Handlers
+ EXPORT GPIO1_1_Handler [WEAK] ; 89
+ EXPORT GPIO1_2_Handler [WEAK] ; 90
+ EXPORT GPIO1_3_Handler [WEAK] ; 91
+ EXPORT GPIO1_4_Handler [WEAK] ; 92
+ EXPORT GPIO1_5_Handler [WEAK] ; 93
+ EXPORT GPIO1_6_Handler [WEAK] ; 94
+ EXPORT GPIO1_7_Handler [WEAK] ; 95
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; - 2 S32K Timer Handler
+TIMER0_Handler ; - 3 TIMER 0 Handler
+TIMER1_Handler ; - 4 TIMER 1 Handler
+DUALTIMER_Handler ; - 5 Dual Timer Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 51 SPI 0 Handler
+SPI1_Handler ; 52 SPI 1 Handler
+SPI2_Handler ; 53 SPI 2 Handler
+SPI3_Handler ; 54 SPI 3 Handler
+SPI4_Handler ; 55 SPI 4 Handler
+DMA0_ERROR_Handler ; 56 DMA 0 Error Handler
+DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler
+DMA0_Handler ; 58 DMA 0 Combined Handler
+DMA1_ERROR_Handler ; 59 DMA 1 Error Handler
+DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler
+DMA1_Handler ; 61 DMA 1 Combined Handler
+DMA2_ERROR_Handler ; 62 DMA 2 Error Handler
+DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler
+DMA2_Handler ; 64 DMA 2 Combined Handler
+DMA3_ERROR_Handler ; 65 DMA 3 Error Handler
+DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler
+DMA3_Handler ; 67 DMA 3 Combined Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO 0 has 16 individual Handlers
+GPIO0_1_Handler ; 73
+GPIO0_2_Handler ; 74
+GPIO0_3_Handler ; 75
+GPIO0_4_Handler ; 76
+GPIO0_5_Handler ; 77
+GPIO0_6_Handler ; 78
+GPIO0_7_Handler ; 79
+GPIO0_8_Handler ; 80
+GPIO0_9_Handler ; 81
+GPIO0_10_Handler ; 82
+GPIO0_11_Handler ; 83
+GPIO0_12_Handler ; 84
+GPIO0_13_Handler ; 85
+GPIO0_14_Handler ; 86
+GPIO0_15_Handler ; 87
+GPIO1_0_Handler ; 88 GPIO 1 has 8 individual Handlers
+GPIO1_1_Handler ; 89
+GPIO1_2_Handler ; 90
+GPIO1_3_Handler ; 91
+GPIO1_4_Handler ; 92
+GPIO1_5_Handler ; 93
+GPIO1_6_Handler ; 94
+GPIO1_7_Handler ; 95
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, = __initial_sp
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/platform/ext/target/mps2/an519/cmsis_core/cmsis.h b/platform/ext/target/mps2/an519/cmsis_core/cmsis.h
new file mode 100644
index 0000000..9080739
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/cmsis.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MPS2_AN519_CMSIS_H__
+#define __MPS2_AN519_CMSIS_H__
+
+/* M23 Subsystem Design for V2M-MPS2+ */
+#include "mps2_an519.h"
+
+#endif /*__MPS2_AN519_CMSIS_H__ */
diff --git a/platform/ext/target/mps2/an519/cmsis_core/cmsis_cpu.h b/platform/ext/target/mps2/an519/cmsis_core/cmsis_cpu.h
new file mode 100644
index 0000000..cd9cff6
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/cmsis_cpu.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_CPU_H__
+#define __CMSIS_CPU_H__
+
+/* -------- Configuration of the Cortex-M23 Processor and Core Peripherals ------ */
+#define __CM23_REV 0x0000U /* Core revision r0p1 */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+
+#include "core_cm23.h"
+
+#endif /* __CMSIS_CPU_H__ */
diff --git a/platform/ext/target/mps2/an519/cmsis_core/mps2_an519.h b/platform/ext/target/mps2/an519/cmsis_core/mps2_an519.h
new file mode 100644
index 0000000..52153ee
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/mps2_an519.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MPS2_AN519_H__
+#define __MPS2_AN519_H__
+
+#include "platform_irq.h" /* Platform IRQ numbers */
+
+#include "cmsis_cpu.h" /* Processor and core peripherals */
+#include "system_cmsdk_mps2_an519.h" /* System Header */
+
+#include "platform_regs.h" /* Platform registers */
+#include "platform_retarget.h" /* Peripherals base addresses */
+
+#endif /* __MPS2_AN519_H__ */
diff --git a/platform/ext/target/mps2/an519/cmsis_core/platform_irq.h b/platform/ext/target/mps2/an519/cmsis_core/platform_irq.h
new file mode 100644
index 0000000..856b4d6
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/platform_irq.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_AN519_IRQN_H__
+#define __ARM_LTD_AN519_IRQN_H__
+
+typedef enum _IRQn_Type {
+ NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* HardFault Interrupt */
+ SVCall_IRQn = -5, /* SV Call Interrupt */
+ PendSV_IRQn = -2, /* Pend SV Interrupt */
+ SysTick_IRQn = -1, /* System Tick Interrupt */
+ NONSEC_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset
+ * Interrupt */
+ NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
+ S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
+ TIMER0_IRQn = 3, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 4, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 5, /* Dual Timer Interrupt */
+ MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */
+ PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */
+ MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */
+ BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined
+ *(Secure) Interrupt */
+ UARTRX0_IRQn = 32, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 33, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 34, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 35, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 36, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 37, /* UART 2 TX Interrupt */
+ UARTRX3_IRQn = 38, /* UART 3 RX Interrupt */
+ UARTTX3_IRQn = 39, /* UART 3 TX Interrupt */
+ UARTRX4_IRQn = 40, /* UART 4 RX Interrupt */
+ UARTTX4_IRQn = 41, /* UART 4 TX Interrupt */
+ UART0_IRQn = 42, /* UART 0 combined Interrupt */
+ UART1_IRQn = 43, /* UART 1 combined Interrupt */
+ UART2_IRQn = 44, /* UART 2 combined Interrupt */
+ UART3_IRQn = 45, /* UART 3 combined Interrupt */
+ UART4_IRQn = 46, /* UART 4 combined Interrupt */
+ UARTOVF_IRQn = 47, /* UART Overflow (0, 1, 2, 3 & 4) */
+ ETHERNET_IRQn = 48, /* Ethernet Interrupt */
+ I2S_IRQn = 49, /* Audio I2S Interrupt */
+ TSC_IRQn = 50, /* Touch Screen Interrupt */
+ SPI0_IRQn = 51, /* SPI 0 Interrupt */
+ SPI1_IRQn = 52, /* SPI 1 Interrupt */
+ SPI2_IRQn = 53, /* SPI 2 Interrupt */
+ SPI3_IRQn = 54, /* SPI 3 Interrupt */
+ SPI4_IRQn = 55, /* SPI 4 Interrupt */
+ DMA0_ERROR_IRQn = 56, /* DMA 0 Error Interrupt */
+ DMA0_TC_IRQn = 57, /* DMA 0 Terminal Count Interrupt */
+ DMA0_IRQn = 58, /* DMA 0 Combined Interrupt */
+ DMA1_ERROR_IRQn = 59, /* DMA 1 Error Interrupt */
+ DMA1_TC_IRQn = 60, /* DMA 1 Terminal Count Interrupt */
+ DMA1_IRQn = 61, /* DMA 1 Combined Interrupt */
+ DMA2_ERROR_IRQn = 62, /* DMA 2 Error Interrupt */
+ DMA2_TC_IRQn = 63, /* DMA 2 Terminal Count Interrupt */
+ DMA2_IRQn = 64, /* DMA 2 Combined Interrupt */
+ DMA3_ERROR_IRQn = 65, /* DMA 3 Error Interrupt */
+ DMA3_TC_IRQn = 66, /* DMA 3 Terminal Count Interrupt */
+ DMA3_IRQn = 67, /* DMA 3 Combined Interrupt */
+ GPIO0_IRQn = 68, /* GPIO 0 Combined Interrupt */
+ GPIO1_IRQn = 69, /* GPIO 1 Combined Interrupt */
+ GPIO2_IRQn = 70, /* GPIO 2 Combined Interrupt */
+ GPIO3_IRQn = 71, /* GPIO 3 Combined Interrupt */
+ GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */
+ GPIO0_1_IRQn = 73,
+ GPIO0_2_IRQn = 74,
+ GPIO0_3_IRQn = 75,
+ GPIO0_4_IRQn = 76,
+ GPIO0_5_IRQn = 77,
+ GPIO0_6_IRQn = 78,
+ GPIO0_7_IRQn = 79,
+ GPIO0_8_IRQn = 80,
+ GPIO0_9_IRQn = 81,
+ GPIO0_10_IRQn = 82,
+ GPIO0_11_IRQn = 83,
+ GPIO0_12_IRQn = 84,
+ GPIO0_13_IRQn = 85,
+ GPIO0_14_IRQn = 86,
+ GPIO0_15_IRQn = 87,
+ GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */
+ GPIO1_1_IRQn = 89,
+ GPIO1_2_IRQn = 90,
+ GPIO1_3_IRQn = 91,
+ GPIO1_4_IRQn = 92,
+ GPIO1_5_IRQn = 93,
+ GPIO1_6_IRQn = 94,
+ GPIO1_7_IRQn = 95,
+ GPIO1_8_IRQn = 96,
+ GPIO1_9_IRQn = 97,
+ GPIO1_10_IRQn = 98,
+ GPIO1_11_IRQn = 99,
+ GPIO1_12_IRQn = 100,
+ GPIO1_13_IRQn = 101,
+ GPIO1_14_IRQn = 102,
+ GPIO1_15_IRQn = 103,
+ GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */
+ GPIO2_1_IRQn = 105,
+ GPIO2_2_IRQn = 106,
+ GPIO2_3_IRQn = 107,
+ GPIO2_4_IRQn = 108,
+ GPIO2_5_IRQn = 109,
+ GPIO2_6_IRQn = 110,
+ GPIO2_7_IRQn = 111,
+ GPIO2_8_IRQn = 112,
+ GPIO2_9_IRQn = 113,
+ GPIO2_10_IRQn = 114,
+ GPIO2_11_IRQn = 115,
+ GPIO2_12_IRQn = 116,
+ GPIO2_13_IRQn = 117,
+ GPIO2_14_IRQn = 118,
+ GPIO2_15_IRQn = 119,
+ GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */
+ GPIO3_1_IRQn = 121,
+ GPIO3_2_IRQn = 122,
+ GPIO3_3_IRQn = 123,
+}IRQn_Type;
+
+#endif /* __ARM_LTD_AN519_IRQN_H__ */
diff --git a/platform/ext/target/mps2/an519/cmsis_core/platform_regs.h b/platform/ext/target/mps2/an519/cmsis_core/platform_regs.h
new file mode 100644
index 0000000..0dac90c
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/platform_regs.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_AN519_REGS_H__
+#define __ARM_LTD_AN519_REGS_H__
+
+#include <stdint.h>
+
+/* System information (SYSINFO) */
+#define CMSDK_SYSINFO_BASE_NS 0x40020000
+#define CMSDK_SYSINFO_BASE_S 0x50020000
+
+/* System info memory mapped register access structure */
+struct sysinfo_t {
+ volatile uint32_t sys_version; /* (R/ ) System version */
+ volatile uint32_t sys_config; /* (R/ ) System configuration */
+ volatile uint32_t reserved0[1008];
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved1[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* System Control (SYSCTRL) */
+#define CMSDK_SYSCTRL_BASE_S 0x50021000
+
+/* System control memory mapped register access structure */
+struct sysctrl_t {
+ volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
+ * Status Register */
+ volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
+ * Set Register */
+ volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
+ * Clear Register */
+ volatile uint32_t reserved0[61];
+ volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
+ volatile uint32_t resetmask; /* (R/W) Reset MASK */
+ volatile uint32_t swreset; /* ( /W) Software Reset */
+ volatile uint32_t gretreg; /* (R/W) General Purpose Retention
+ * Register */
+ volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector
+ * Register For CPU 0 */
+ volatile uint32_t reserved1;
+ volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control
+ * after reset */
+ volatile uint32_t bus_wait; /* (R/W) Bus Access wait control
+ after reset */
+ volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and
+ * Acknowledgement */
+ volatile uint32_t reserved2[939]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t reserved3[3]; /* Reserved */
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* Secure Privilege Control */
+#define CMSDK_SPCTRL_BASE_S 0x50080000
+#define CMSDK_SPCTRL ((struct spctrl_def*)CMSDK_SPCTRL_BASE_S)
+
+/* SPCTRL memory mapped register access structure */
+struct spctrl_def {
+ volatile uint32_t reserved[4];
+ volatile uint32_t secrespcfg;
+ volatile uint32_t nsccfg;
+ volatile uint32_t reserved2;
+ volatile uint32_t secmpcintstatus;
+ volatile uint32_t secppcintstat;
+ volatile uint32_t secppcintclr;
+ volatile uint32_t secppcinten;
+ volatile uint32_t reserved3;
+ volatile uint32_t secmscintstat;
+ volatile uint32_t secmscintclr;
+ volatile uint32_t secmscinten;
+ volatile uint32_t reserved4;
+ volatile uint32_t brgintstat;
+ volatile uint32_t brgintclr;
+ volatile uint32_t brginten;
+ volatile uint32_t reserved5;
+ volatile uint32_t ahbnsppc0;
+ volatile uint32_t reserved6[3];
+ volatile uint32_t ahbnsppcexp0;
+ volatile uint32_t ahbnsppcexp1;
+ volatile uint32_t ahbnsppcexp2;
+ volatile uint32_t ahbnsppcexp3;
+ volatile uint32_t apbnsppc0;
+ volatile uint32_t apbnsppc1;
+ volatile uint32_t reserved7[2];
+ volatile uint32_t apbnsppcexp0;
+ volatile uint32_t apbnsppcexp1;
+ volatile uint32_t apbnsppcexp2;
+ volatile uint32_t apbnsppcexp3;
+ volatile uint32_t ahbspppc0;
+ volatile uint32_t reserved8[3];
+ volatile uint32_t ahbspppcexp0;
+ volatile uint32_t ahbspppcexp1;
+ volatile uint32_t ahbspppcexp2;
+ volatile uint32_t ahbspppcexp3;
+ volatile uint32_t apbspppc0;
+ volatile uint32_t apbspppc1;
+ volatile uint32_t reserved9[2];
+ volatile uint32_t apbspppcexp0;
+ volatile uint32_t apbspppcexp1;
+ volatile uint32_t apbspppcexp2;
+ volatile uint32_t apbspppcexp3;
+ volatile uint32_t nsmscexp;
+ volatile uint32_t reserved10[959];
+ volatile uint32_t pid4;
+ volatile uint32_t pid5;
+ volatile uint32_t pid6;
+ volatile uint32_t pid7;
+ volatile uint32_t pid0;
+ volatile uint32_t pid1;
+ volatile uint32_t pid2;
+ volatile uint32_t pid3;
+ volatile uint32_t cid0;
+ volatile uint32_t cid1;
+ volatile uint32_t cid2;
+ volatile uint32_t cid3;
+};
+
+/* PPC interrupt position mask */
+#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0)
+#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1)
+#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+#define CMSDK_AHB_PPC0_INT_POS_MASK (1UL << 16)
+#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+
+/* Non-Secure Access slave PPCs register addresses */
+#define CMSDK_SPCTRL_AHB_NS_PPC0 (CMSDK_SPCTRL_BASE_S + 0x050)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP0 (CMSDK_SPCTRL_BASE_S + 0x060)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP1 (CMSDK_SPCTRL_BASE_S + 0x064)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP2 (CMSDK_SPCTRL_BASE_S + 0x068)
+#define CMSDK_SPCTRL_AHB_NS_PPCEXP3 (CMSDK_SPCTRL_BASE_S + 0x06C)
+#define CMSDK_SPCTRL_APB_NS_PPC0 (CMSDK_SPCTRL_BASE_S + 0x070)
+#define CMSDK_SPCTRL_APB_NS_PPC1 (CMSDK_SPCTRL_BASE_S + 0x074)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP0 (CMSDK_SPCTRL_BASE_S + 0x080)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP1 (CMSDK_SPCTRL_BASE_S + 0x084)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP2 (CMSDK_SPCTRL_BASE_S + 0x088)
+#define CMSDK_SPCTRL_APB_NS_PPCEXP3 (CMSDK_SPCTRL_BASE_S + 0x08C)
+
+/* Secure Unprivileged (SP) Access slave PPCs register addresses */
+#define CMSDK_SPCTRL_AHB_PPC0_SP (CMSDK_SPCTRL_BASE_S + 0x090)
+#define CMSDK_SPCTRL_AHB_PPCEXP0_SP (CMSDK_SPCTRL_BASE_S + 0x0A0)
+#define CMSDK_SPCTRL_AHB_PPCEXP1_SP (CMSDK_SPCTRL_BASE_S + 0x0A4)
+#define CMSDK_SPCTRL_AHB_PPCEXP2_SP (CMSDK_SPCTRL_BASE_S + 0x0A8)
+#define CMSDK_SPCTRL_AHB_PPCEXP3_SP (CMSDK_SPCTRL_BASE_S + 0x0AC)
+#define CMSDK_SPCTRL_APB_PPC0_SP (CMSDK_SPCTRL_BASE_S + 0x0B0)
+#define CMSDK_SPCTRL_APB_PPC1_SP (CMSDK_SPCTRL_BASE_S + 0x0B4)
+#define CMSDK_SPCTRL_APB_PPCEXP0_SP (CMSDK_SPCTRL_BASE_S + 0x0C0)
+#define CMSDK_SPCTRL_APB_PPCEXP1_SP (CMSDK_SPCTRL_BASE_S + 0x0C4)
+#define CMSDK_SPCTRL_APB_PPCEXP2_SP (CMSDK_SPCTRL_BASE_S + 0x0C8)
+#define CMSDK_SPCTRL_APB_PPCEXP3_SP (CMSDK_SPCTRL_BASE_S + 0x0CC)
+
+/* Non-Secure Privilege Control */
+#define CMSDK_NSPCTRL_BASE_NS 0x40080000
+#define CMSDK_NSPCTRL ((struct nspctrl_def*)CMSDK_NSPCTRL_BASE_NS)
+
+/* NSPCTRL memory mapped register access structure */
+struct nspctrl_def {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved3[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved4[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+ volatile uint32_t reserved5[960];
+ volatile uint32_t pidr4;
+ volatile uint32_t reserved7; /* pidr5 */
+ volatile uint32_t reserved8; /* pidr6 */
+ volatile uint32_t reserved9; /* pidr7 */
+ volatile uint32_t pidr0;
+ volatile uint32_t pidr1;
+ volatile uint32_t pidr2;
+ volatile uint32_t pidr3;
+ volatile uint32_t cidr0;
+ volatile uint32_t cidr1;
+ volatile uint32_t cidr2;
+ volatile uint32_t cidr3;
+};
+
+/* Non-Secure Unprivileged Access (NSP) Access slave PPCs register addresses */
+#define CMSDK_NSPCTRL_AHB_PPC0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x090)
+#define CMSDK_NSPCTRL_AHB_PPCEXP0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A0)
+#define CMSDK_NSPCTRL_AHB_PPCEXP1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A4)
+#define CMSDK_NSPCTRL_AHB_PPCEXP2_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A8)
+#define CMSDK_NSPCTRL_AHB_PPCEXP3_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0AC)
+#define CMSDK_NSPCTRL_APB_PPC0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0B0)
+#define CMSDK_NSPCTRL_APB_PPC1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0B4)
+#define CMSDK_NSPCTRL_APB_PPCEXP0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C0)
+#define CMSDK_NSPCTRL_APB_PPCEXP1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C4)
+#define CMSDK_NSPCTRL_APB_PPCEXP2_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C8)
+#define CMSDK_NSPCTRL_APB_PPCEXP3_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0CC)
+
+/* ARM APB PPC0 peripherals definition */
+#define CMSDK_TIMER0_APB_PPC_POS 0U
+#define CMSDK_TIMER1_APB_PPC_POS 1U
+#define CMSDK_DTIMER_APB_PPC_POS 2U
+#define CMSDK_MHU0_APB_PPC_POS 3U
+#define CMSDK_MHU1_APB_PPC_POS 4U
+/* The bits 31:5 are reserved */
+/* End ARM APB PPC0 peripherals definition */
+
+/* ARM APB PPC1 peripherals definition */
+#define CMSDK_S32K_TIMER_PPC_POS 0U
+/* The bits 31:1 are reserved */
+/* End ARM APB PPC1 peripherals definition */
+
+/* ARM APB PPCEXP0 peripherals definition */
+#define CMSDK_SSRAM1_APB_PPC_POS 0U
+#define CMSDK_SSRAM2_APB_PPC_POS 1U
+#define CMSDK_SSRAM3_APB_PPC_POS 2U
+/* The bits 31:3 are reserved */
+/* End ARM APB PPCEXP0 peripherals definition */
+
+/* ARM APB PPCEXP1 peripherals definition */
+#define CMSDK_SPI0_APB_PPC_POS 0U
+#define CMSDK_SPI1_APB_PPC_POS 1U
+#define CMSDK_SPI2_APB_PPC_POS 2U
+#define CMSDK_SPI3_APB_PPC_POS 3U
+#define CMSDK_SPI4_APB_PPC_POS 4U
+#define CMSDK_UART0_APB_PPC_POS 5U
+#define CMSDK_UART1_APB_PPC_POS 6U
+#define CMSDK_UART2_APB_PPC_POS 7U
+#define CMSDK_UART3_APB_PPC_POS 8U
+#define CMSDK_UART4_APB_PPC_POS 9U
+#define CMSDK_I2C0_APB_PPC_POS 10U
+#define CMSDK_I2C1_APB_PPC_POS 11U
+#define CMSDK_I2C2_APB_PPC_POS 12U
+#define CMSDK_I2C3_APB_PPC_POS 13U
+/* The bits 31:14 are reserved */
+/* End ARM APB PPCEXP1 peripherals definition */
+
+/* ARM APB PPCEXP2 peripherals definition */
+#define CMSDK_FPGA_SCC_PPC_POS 0U
+#define CMSDK_FPGA_AUDIO_PPC_POS 1U
+#define CMSDK_FPGA_IO_PPC_POS 2U
+/* The bits 31:3 are reserved */
+/* End ARM APB PPCEXP2 peripherals definition */
+
+/* ARM APB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End ARM APB PPCEXP3 peripherals definition */
+
+/* ARM AHB PPC0 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPC0 peripherals definition */
+
+/* ARM AHB PPCEXP0 peripherals definition */
+#define CMSDK_VGA_PPC_POS 0U
+#define CMSDK_GPIO0_PPC_POS 1U
+#define CMSDK_GPIO1_PPC_POS 2U
+#define CMSDK_GPIO2_PPC_POS 3U
+#define CMSDK_GPIO3_PPC_POS 4U
+/* The bits 31:5 are reserved */
+/* End of ARM AHB PPCEXP0 peripherals definition */
+
+/* ARM AHB PPCEXP1 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP1 peripherals definition */
+
+/* ARM AHB PPCEXP2 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP2 peripherals definition */
+
+/* ARM AHB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+
+/* End of ARM AHB PPCEXP3 peripherals definition */
+
+#endif /* __ARM_LTD_AN519_REGS_H__ */
diff --git a/platform/ext/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.c b/platform/ext/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.c
new file mode 100644
index 0000000..0cb198f
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+
+/*
+ * MPS2 AN519 has different frequencies for system core clock (20MHz) and
+ * peripherals clock (25MHz).
+ */
+#define OSCCLK0 (40000000UL)
+#define OSCCLK2 (25000000UL)
+
+#define SYSTEM_CLOCK (OSCCLK0/2)
+#define PERIPHERAL_CLOCK (OSCCLK2)
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t PeripheralClock = PERIPHERAL_CLOCK;
+
+/* System Core Clock update function */
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/* System initialization function */
+void SystemInit (void)
+{
+#if __DOMAIN_NS != 1U
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+#endif /* __DOMAIN_NS != 1U */
+
+ SystemCoreClock = SYSTEM_CLOCK;
+ PeripheralClock = PERIPHERAL_CLOCK;
+}
diff --git a/platform/ext/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.h b/platform/ext/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.h
new file mode 100644
index 0000000..a98ea4b
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_core/system_cmsdk_mps2_an519.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_CMSDK_MPS2_AN519_H__
+#define __SYSTEM_CMSDK_MPS2_AN519_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
+
+/**
+ * \brief Initializes the system
+ */
+void SystemInit(void);
+
+/**
+ * \brief Restores system core clock
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_CMSDK_MPS2_AN519_H__ */
diff --git a/platform/ext/target/mps2/an519/cmsis_drivers/Driver_MPC.c b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_MPC.c
new file mode 100644
index 0000000..b0e62dd
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_MPC.c
@@ -0,0 +1,1017 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Driver_MPC.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+/* driver version */
+#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_MPC_API_VERSION,
+ ARM_MPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+/*
+ * \brief Translates error codes from native API to CMSIS API.
+ *
+ * \param[in] err Error code to translate (\ref mpc_sie200_error_t).
+ *
+ * \return Returns CMSIS error code.
+ */
+static int32_t error_trans(enum mpc_sie200_error_t err)
+{
+ switch(err) {
+ case MPC_SIE200_ERR_NONE:
+ return ARM_DRIVER_OK;
+ case MPC_SIE200_INVALID_ARG:
+ return ARM_DRIVER_ERROR_PARAMETER;
+ case MPC_SIE200_NOT_INIT:
+ return ARM_MPC_ERR_NOT_INIT;
+ case MPC_SIE200_ERR_NOT_IN_RANGE:
+ return ARM_MPC_ERR_NOT_IN_RANGE;
+ case MPC_SIE200_ERR_NOT_ALIGNED:
+ return ARM_MPC_ERR_NOT_ALIGNED;
+ case MPC_SIE200_ERR_INVALID_RANGE:
+ return ARM_MPC_ERR_INVALID_RANGE;
+ case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE:
+ return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.
+ */
+ }
+}
+
+#if (RTE_ISRAM0_MPC)
+/* Ranges controlled by this ISRAM0_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_S = {
+ .base = MPC_ISRAM0_RANGE_BASE_S,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_NS = {
+ .base = MPC_ISRAM0_RANGE_BASE_NS,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM0_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN]=
+ {&MPC_ISRAM0_RANGE_S, &MPC_ISRAM0_RANGE_NS};
+
+/* ISRAM0_MPC Driver wrapper functions */
+static int32_t ISRAM0_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM0_DEV_S,
+ MPC_ISRAM0_RANGE_LIST,
+ MPC_ISRAM0_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM0_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM0_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM0_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM0_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM0_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM0_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM0_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM0_DEV_S);
+}
+
+
+static void ISRAM0_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM0_DEV_S);
+}
+
+static uint32_t ISRAM0_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM0_DEV_S);
+}
+
+static int32_t ISRAM0_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM0_DEV_S);
+}
+
+/* ISRAM0_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
+ARM_DRIVER_MPC Driver_ISRAM0_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM0_MPC_Initialize,
+ .Uninitialize = ISRAM0_MPC_Uninitialize,
+ .GetBlockSize = ISRAM0_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM0_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM0_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM0_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM0_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM0_MPC_ClearInterrupt,
+ .InterruptState = ISRAM0_MPC_InterruptState,
+ .LockDown = ISRAM0_MPC_LockDown,
+};
+#endif /* RTE_ISRAM0_MPC */
+
+#if (RTE_ISRAM1_MPC)
+/* Ranges controlled by this ISRAM1_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_S = {
+ .base = MPC_ISRAM1_RANGE_BASE_S,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_NS = {
+ .base = MPC_ISRAM1_RANGE_BASE_NS,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN]=
+ {&MPC_ISRAM1_RANGE_S, &MPC_ISRAM1_RANGE_NS};
+
+/* ISRAM1_MPC Driver wrapper functions */
+static int32_t ISRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM1_DEV_S,
+ MPC_ISRAM1_RANGE_LIST,
+ MPC_ISRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM1_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM1_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM1_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM1_DEV_S);
+}
+
+
+static void ISRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM1_DEV_S);
+}
+
+static uint32_t ISRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM1_DEV_S);
+}
+
+static int32_t ISRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM1_DEV_S);
+}
+
+/* ISRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
+ARM_DRIVER_MPC Driver_ISRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM1_MPC_Initialize,
+ .Uninitialize = ISRAM1_MPC_Uninitialize,
+ .GetBlockSize = ISRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM1_MPC_ClearInterrupt,
+ .InterruptState = ISRAM1_MPC_InterruptState,
+ .LockDown = ISRAM1_MPC_LockDown,
+};
+#endif /* RTE_ISRAM1_MPC */
+
+#if (RTE_ISRAM2_MPC)
+/* Ranges controlled by this ISRAM2_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_S = {
+ .base = MPC_ISRAM2_RANGE_BASE_S,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_NS = {
+ .base = MPC_ISRAM2_RANGE_BASE_NS,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN]=
+ {&MPC_ISRAM2_RANGE_S, &MPC_ISRAM2_RANGE_NS};
+
+/* ISRAM2_MPC Driver wrapper functions */
+static int32_t ISRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM2_DEV_S,
+ MPC_ISRAM2_RANGE_LIST,
+ MPC_ISRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM2_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM2_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM2_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM2_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM2_DEV_S);
+}
+
+
+static void ISRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM2_DEV_S);
+}
+
+static uint32_t ISRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM2_DEV_S);
+}
+
+static int32_t ISRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM2_DEV_S);
+}
+
+/* ISRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
+ARM_DRIVER_MPC Driver_ISRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM2_MPC_Initialize,
+ .Uninitialize = ISRAM2_MPC_Uninitialize,
+ .GetBlockSize = ISRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM2_MPC_ClearInterrupt,
+ .InterruptState = ISRAM2_MPC_InterruptState,
+ .LockDown = ISRAM2_MPC_LockDown,
+};
+#endif /* RTE_ISRAM2_MPC */
+
+#if (RTE_ISRAM3_MPC)
+/* Ranges controlled by this ISRAM3_MPC */
+static struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_S = {
+ .base = MPC_ISRAM3_RANGE_BASE_S,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_NS = {
+ .base = MPC_ISRAM3_RANGE_BASE_NS,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN]=
+ {&MPC_ISRAM3_RANGE_S, &MPC_ISRAM3_RANGE_NS};
+
+/* ISRAM3_MPC Driver wrapper functions */
+static int32_t ISRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM3_DEV_S,
+ MPC_ISRAM3_RANGE_LIST,
+ MPC_ISRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM3_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM3_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM3_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM3_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void ISRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM3_DEV_S);
+}
+
+
+static void ISRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM3_DEV_S);
+}
+
+static uint32_t ISRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM3_DEV_S);
+}
+
+static int32_t ISRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM3_DEV_S);
+}
+
+/* ISRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
+ARM_DRIVER_MPC Driver_ISRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM3_MPC_Initialize,
+ .Uninitialize = ISRAM3_MPC_Uninitialize,
+ .GetBlockSize = ISRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM3_MPC_ClearInterrupt,
+ .InterruptState = ISRAM3_MPC_InterruptState,
+ .LockDown = ISRAM3_MPC_LockDown,
+};
+#endif /* RTE_ISRAM3_MPC */
+
+#if (RTE_CODE_SRAM1_MPC)
+/* Ranges controlled by this SRAM1_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM1_RANGE_S = {
+ .base = MPC_CODE_SRAM1_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM1_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM1_RANGE_NS = {
+ .base = MPC_CODE_SRAM1_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM1_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM1_RANGE_LIST[MPC_CODE_SRAM1_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM1_RANGE_S, &MPC_CODE_SRAM1_RANGE_NS};
+
+/* SRAM1_MPC Driver wrapper functions */
+static int32_t SRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM1_DEV_S,
+ MPC_CODE_SRAM1_RANGE_LIST,
+ MPC_CODE_SRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM1_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM1_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM1_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM1_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM1_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM1_DEV_S);
+}
+
+
+static void SRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM1_DEV_S);
+}
+
+static uint32_t SRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM1_DEV_S);
+}
+
+static int32_t SRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM1_DEV_S);
+}
+
+/* SRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+ARM_DRIVER_MPC Driver_SRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM1_MPC_Initialize,
+ .Uninitialize = SRAM1_MPC_Uninitialize,
+ .GetBlockSize = SRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM1_MPC_ClearInterrupt,
+ .InterruptState = SRAM1_MPC_InterruptState,
+ .LockDown = SRAM1_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM1_MPC */
+
+#if (RTE_CODE_SRAM2_MPC)
+/* Ranges controlled by this SRAM2_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM2_RANGE_S = {
+ .base = MPC_CODE_SRAM2_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM2_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM2_RANGE_NS = {
+ .base = MPC_CODE_SRAM2_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM2_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM2_RANGE_LIST[MPC_CODE_SRAM2_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM2_RANGE_S, &MPC_CODE_SRAM2_RANGE_NS};
+
+/* SRAM2_MPC Driver wrapper functions */
+static int32_t SRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM2_DEV_S,
+ MPC_CODE_SRAM2_RANGE_LIST,
+ MPC_CODE_SRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM2_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM2_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM2_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM2_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM2_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM2_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM2_DEV_S);
+}
+
+
+static void SRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM2_DEV_S);
+}
+
+static uint32_t SRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM2_DEV_S);
+}
+
+static int32_t SRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM2_DEV_S);
+}
+
+/* SRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM2_MPC;
+ARM_DRIVER_MPC Driver_SRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM2_MPC_Initialize,
+ .Uninitialize = SRAM2_MPC_Uninitialize,
+ .GetBlockSize = SRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM2_MPC_ClearInterrupt,
+ .InterruptState = SRAM2_MPC_InterruptState,
+ .LockDown = SRAM2_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM2_MPC */
+
+#if (RTE_CODE_SRAM3_MPC)
+/* Ranges controlled by this SRAM3_MPC */
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM3_RANGE_S = {
+ .base = MPC_CODE_SRAM3_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM3_RANGE_LIMIT_S,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static struct mpc_sie200_memory_range_t MPC_CODE_SRAM3_RANGE_NS = {
+ .base = MPC_CODE_SRAM3_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM3_RANGE_LIMIT_NS,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t* MPC_CODE_SRAM3_RANGE_LIST[MPC_CODE_SRAM3_RANGE_LIST_LEN]=
+ {&MPC_CODE_SRAM3_RANGE_S, &MPC_CODE_SRAM3_RANGE_NS};
+
+/* SRAM3_MPC Driver wrapper functions */
+static int32_t SRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM3_DEV_S,
+ MPC_CODE_SRAM3_RANGE_LIST,
+ MPC_CODE_SRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SRAM3_MPC_GetBlockSize(uint32_t* blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM3_DEV_S, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM3_DEV_S, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM3_DEV_S, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR* attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM3_DEV_S, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM3_DEV_S);
+
+ return error_trans(ret);
+}
+
+static void SRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM3_DEV_S);
+}
+
+
+static void SRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM3_DEV_S);
+}
+
+static uint32_t SRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM3_DEV_S);
+}
+
+static int32_t SRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM3_DEV_S);
+}
+
+/* SRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM3_MPC;
+ARM_DRIVER_MPC Driver_SRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SRAM3_MPC_Initialize,
+ .Uninitialize = SRAM3_MPC_Uninitialize,
+ .GetBlockSize = SRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = SRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = SRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = SRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = SRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = SRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = SRAM3_MPC_ClearInterrupt,
+ .InterruptState = SRAM3_MPC_InterruptState,
+ .LockDown = SRAM3_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM3_MPC */
diff --git a/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c
new file mode 100644
index 0000000..9787d05
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_PPC.c
@@ -0,0 +1,883 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_PPC.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+/* Driver version */
+#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_PPC_API_VERSION,
+ ARM_PPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+#if (RTE_AHB_PPCEXP0)
+/* AHB PPCEXP0 Driver wrapper functions */
+static int32_t AHB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP0_DEV_S, AHB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP0_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP0_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP0_DEV_S);
+}
+
+static void AHB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP0_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP0_DEV_S);
+}
+
+/* AHB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP0_Initialize,
+ .Uninitialize = AHB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP0_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP0_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP0 */
+
+#if (RTE_AHB_PPCEXP1)
+/* AHB PPCEXP1 Driver wrapper functions */
+static int32_t AHB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP1_DEV_S, AHB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP1_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP1_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP1_DEV_S);
+}
+
+static void AHB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP1_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP1_DEV_S);
+}
+
+/* AHB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP1;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP1_Initialize,
+ .Uninitialize = AHB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP1_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP1_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP1 */
+
+#if (RTE_AHB_PPCEXP2)
+/* AHB PPCEXP2 Driver wrapper functions */
+static int32_t AHB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP2_DEV_S, AHB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP2_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP2_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP2_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP2_DEV_S);
+}
+
+static void AHB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP2_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP2_DEV_S);
+}
+
+/* AHB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP2;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP2_Initialize,
+ .Uninitialize = AHB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP2_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP2_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP2 */
+
+#if (RTE_AHB_PPCEXP3)
+/* AHB PPCEXP3 Driver wrapper functions */
+static int32_t AHB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP3_DEV_S, AHB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP3_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP3_DEV_S, periph);
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP3_DEV_S, periph);
+}
+
+static int32_t AHB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP3_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP3_DEV_S);
+}
+
+static void AHB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP3_DEV_S);
+}
+
+static uint32_t AHB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP3_DEV_S);
+}
+
+/* AHB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP3;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP3_Initialize,
+ .Uninitialize = AHB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP3_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP3_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP3 */
+
+#if (RTE_APB_PPC0)
+/* APB PPC0 Driver wrapper functions */
+static int32_t APB_PPC0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC0_DEV_S, APB_PPC0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC0_DEV_S, periph);
+}
+
+static uint32_t APB_PPC0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC0_DEV_S, periph);
+}
+
+static int32_t APB_PPC0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC0_DEV_S);
+}
+
+static void APB_PPC0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC0_DEV_S);
+}
+
+static uint32_t APB_PPC0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC0_DEV_S);
+}
+
+/* APB PPC0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC0;
+ARM_DRIVER_PPC Driver_APB_PPC0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC0_Initialize,
+ .Uninitialize = APB_PPC0_Uninitialize,
+ .ConfigPeriph = APB_PPC0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC0_EnableInterrupt,
+ .DisableInterrupt = APB_PPC0_DisableInterrupt,
+ .ClearInterrupt = APB_PPC0_ClearInterrupt,
+ .InterruptState = APB_PPC0_InterruptState
+};
+#endif /* RTE_APB_PPC0 */
+
+#if (RTE_APB_PPC1)
+/* APB PPC1 Driver wrapper functions */
+static int32_t APB_PPC1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC1_DEV_S, APB_PPC1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC1_DEV_S, periph);
+}
+
+static uint32_t APB_PPC1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC1_DEV_S, periph);
+}
+static int32_t APB_PPC1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC1_DEV_S);
+}
+
+static void APB_PPC1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC1_DEV_S);
+}
+
+static uint32_t APB_PPC1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC1_DEV_S);
+}
+
+/* APB PPC1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC1;
+ARM_DRIVER_PPC Driver_APB_PPC1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC1_Initialize,
+ .Uninitialize = APB_PPC1_Uninitialize,
+ .ConfigPeriph = APB_PPC1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC1_EnableInterrupt,
+ .DisableInterrupt = APB_PPC1_DisableInterrupt,
+ .ClearInterrupt = APB_PPC1_ClearInterrupt,
+ .InterruptState = APB_PPC1_InterruptState
+};
+#endif /* RTE_APB_PPC1 */
+
+#if (RTE_APB_PPCEXP0)
+/* APB PPCEXP0 Driver wrapper functions */
+static int32_t APB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP0_DEV_S, APB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP0_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP0_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP0_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP0_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP0_DEV_S);
+}
+
+static void APB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP0_DEV_S);
+}
+
+static uint32_t APB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP0_DEV_S);
+}
+
+/* APB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP0;
+ARM_DRIVER_PPC Driver_APB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP0_Initialize,
+ .Uninitialize = APB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP0_ClearInterrupt,
+ .InterruptState = APB_PPCEXP0_InterruptState
+};
+#endif /* RTE_APB_PPCEXP0 */
+
+#if (RTE_APB_PPCEXP1)
+/* APB PPCEXP1 Driver wrapper functions */
+static int32_t APB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP1_DEV_S, APB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP1_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP1_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP1_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP1_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP1_DEV_S);
+}
+
+static void APB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP1_DEV_S);
+}
+
+static uint32_t APB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP1_DEV_S);
+}
+
+/* APB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP1;
+ARM_DRIVER_PPC Driver_APB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP1_Initialize,
+ .Uninitialize = APB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP1_ClearInterrupt,
+ .InterruptState = APB_PPCEXP1_InterruptState
+};
+#endif /* RTE_APB_PPCEXP1 */
+
+#if (RTE_APB_PPCEXP2)
+/* APB PPCEXP2 Driver wrapper functions */
+static int32_t APB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP2_DEV_S, APB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP2_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP2_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP2_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP2_DEV_S);
+}
+
+static void APB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP2_DEV_S);
+}
+
+static uint32_t APB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP2_DEV_S);
+}
+
+/* APB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP2;
+ARM_DRIVER_PPC Driver_APB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP2_Initialize,
+ .Uninitialize = APB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP2_ClearInterrupt,
+ .InterruptState = APB_PPCEXP2_InterruptState
+};
+#endif /* RTE_APB_PPCEXP2 */
+
+#if (RTE_APB_PPCEXP3)
+/* APB PPCEXP3 Driver wrapper functions */
+static int32_t APB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP3_DEV_S, APB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP3_DEV_S, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP3_DEV_S, periph);
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP3_DEV_S, periph);
+}
+
+static int32_t APB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP3_DEV_S);
+
+ if( ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP3_DEV_S);
+}
+
+static void APB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP3_DEV_S);
+}
+
+static uint32_t APB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP3_DEV_S);
+}
+
+/* APB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP3;
+ARM_DRIVER_PPC Driver_APB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP3_Initialize,
+ .Uninitialize = APB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP3_ClearInterrupt,
+ .InterruptState = APB_PPCEXP3_InterruptState
+};
+#endif /* RTE_APB_PPCEXP3 */
diff --git a/platform/ext/target/mps2/an519/cmsis_drivers/Driver_USART.c b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_USART.c
new file mode 100644
index 0000000..489708e
--- /dev/null
+++ b/platform/ext/target/mps2/an519/cmsis_drivers/Driver_USART.c
@@ -0,0 +1,719 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_USART.h"
+
+#include "cmsis.h"
+#include "platform_retarget_dev.h"
+#include "RTE_Device.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) (void)arg
+#endif
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_USART_API_VERSION,
+ ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+ 1, /* supports UART (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports UART Single-wire mode */
+ 0, /* supports UART IrDA mode */
+ 0, /* supports UART Smart Card mode */
+ 0, /* Smart Card Clock generator available */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+ 0 /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+typedef struct {
+ struct arm_uart_dev_t* dev; /* UART device structure */
+ uint32_t tx_nbr_bytes; /* Number of bytes transfered */
+ uint32_t rx_nbr_bytes; /* Number of bytes recevied */
+ ARM_USART_SignalEvent_t cb_event; /* Callback function for events */
+} UARTx_Resources;
+
+static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev)
+{
+ /* Initializes generic UART driver */
+ arm_uart_init(uart_dev->dev, PeripheralClock);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev,
+ ARM_POWER_STATE state)
+{
+ ARG_UNUSED(uart_dev);
+
+ switch (state) {
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *data,
+ uint32_t num)
+{
+ const uint8_t* p_data = (const uint8_t*)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ /* Invalid parameters */
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous TX counter */
+ uart_dev->tx_nbr_bytes = 0;
+
+ while(uart_dev->tx_nbr_bytes != num) {
+ /* Waits until UART is ready to transmit */
+ while(!arm_uart_tx_ready(uart_dev->dev)) {};
+
+ /* As UART is ready to transmit at this point, the write function can
+ * not return any transmit error */
+ (void)arm_uart_write(uart_dev->dev, *p_data);
+
+ uart_dev->tx_nbr_bytes++;
+ p_data++;
+ }
+
+ /* Waits until character is transmited */
+ while (!arm_uart_tx_ready(uart_dev->dev)){};
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev,
+ void *data, uint32_t num)
+{
+ uint8_t* p_data = (uint8_t*)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ // Invalid parameters
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous RX counter */
+ uart_dev->rx_nbr_bytes = 0;
+
+ while(uart_dev->rx_nbr_bytes != num) {
+ /* Waits until one character is received */
+ while (!arm_uart_rx_ready(uart_dev->dev)){};
+
+ /* As UART has received one byte, the read can not
+ * return any receive error at this point */
+ (void)arm_uart_read(uart_dev->dev, p_data);
+
+ uart_dev->rx_nbr_bytes++;
+ p_data++;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->tx_nbr_bytes;
+}
+
+static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev)
+{
+ return uart_dev->rx_nbr_bytes;
+}
+
+static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control,
+ uint32_t arg)
+{
+ switch (control & ARM_USART_CONTROL_Msk) {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ if(arm_uart_set_baudrate(uart_dev->dev, arg) != ARM_UART_ERR_NONE) {
+ return ARM_USART_ERROR_BAUDRATE;
+ }
+ break;
+ /* Unsupported command */
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Data bits */
+ if(control & ARM_USART_DATA_BITS_Msk) {
+ /* Data bit is not configurable */
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Parity */
+ if(control & ARM_USART_PARITY_Msk) {
+ /* Parity is not configurable */
+ return ARM_USART_ERROR_PARITY;
+ }
+
+ /* USART Stop bits */
+ if(control & ARM_USART_STOP_BITS_Msk) {
+ /* Stop bit is not configurable */
+ return ARM_USART_ERROR_STOP_BITS;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+#if (RTE_USART0)
+/* USART0 Driver wrapper functions */
+static UARTx_Resources USART0_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART0_DEV_NS,
+#else
+ .dev = &ARM_UART0_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART0_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART0_DEV);
+}
+
+static int32_t ARM_USART0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART0_DEV, state);
+}
+
+static int32_t ARM_USART0_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART0_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART0_DEV);
+}
+
+static uint32_t ARM_USART0_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART0_DEV);
+}
+static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART0_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART0_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART0;
+ARM_DRIVER_USART Driver_USART0 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART0_Initialize,
+ ARM_USART0_Uninitialize,
+ ARM_USART0_PowerControl,
+ ARM_USART0_Send,
+ ARM_USART0_Receive,
+ ARM_USART0_Transfer,
+ ARM_USART0_GetTxCount,
+ ARM_USART0_GetRxCount,
+ ARM_USART0_Control,
+ ARM_USART0_GetStatus,
+ ARM_USART0_SetModemControl,
+ ARM_USART0_GetModemStatus
+};
+#endif /* RTE_USART0 */
+
+#if (RTE_USART1)
+/* USART1 Driver wrapper functions */
+static UARTx_Resources USART1_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART1_DEV_NS,
+#else
+ .dev = &ARM_UART1_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART1_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART1_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART1_DEV);
+}
+
+static int32_t ARM_USART1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART1_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART1_DEV, state);
+}
+
+static int32_t ARM_USART1_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART1_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART1_DEV);
+}
+
+static uint32_t ARM_USART1_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART1_DEV);
+}
+static int32_t ARM_USART1_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART1_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART1_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART1_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART1_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART1;
+ARM_DRIVER_USART Driver_USART1 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART1_Initialize,
+ ARM_USART1_Uninitialize,
+ ARM_USART1_PowerControl,
+ ARM_USART1_Send,
+ ARM_USART1_Receive,
+ ARM_USART1_Transfer,
+ ARM_USART1_GetTxCount,
+ ARM_USART1_GetRxCount,
+ ARM_USART1_Control,
+ ARM_USART1_GetStatus,
+ ARM_USART1_SetModemControl,
+ ARM_USART1_GetModemStatus
+};
+#endif /* RTE_USART1 */
+
+#if (RTE_USART2)
+/* USART2 Driver wrapper functions */
+static UARTx_Resources USART2_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART2_DEV_NS,
+#else
+ .dev = &ARM_UART2_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART2_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART2_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART2_DEV);
+}
+
+static int32_t ARM_USART2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART2_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART2_DEV, state);
+}
+
+static int32_t ARM_USART2_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART2_DEV, data, num);
+}
+
+static int32_t ARM_USART2_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART2_DEV, data, num);
+}
+
+static int32_t ARM_USART2_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART2_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART2_DEV);
+}
+
+static uint32_t ARM_USART2_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART2_DEV);
+}
+static int32_t ARM_USART2_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART2_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART2_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART2_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART2_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART2;
+ARM_DRIVER_USART Driver_USART2 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART2_Initialize,
+ ARM_USART2_Uninitialize,
+ ARM_USART2_PowerControl,
+ ARM_USART2_Send,
+ ARM_USART2_Receive,
+ ARM_USART2_Transfer,
+ ARM_USART2_GetTxCount,
+ ARM_USART2_GetRxCount,
+ ARM_USART2_Control,
+ ARM_USART2_GetStatus,
+ ARM_USART2_SetModemControl,
+ ARM_USART2_GetModemStatus
+};
+#endif /* RTE_USART2 */
+
+#if (RTE_USART3)
+/* USART3 Driver wrapper functions */
+static UARTx_Resources USART3_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART3_DEV_NS,
+#else
+ .dev = &ARM_UART3_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART3_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART3_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART3_DEV);
+}
+
+static int32_t ARM_USART3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART3_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART3_DEV, state);
+}
+
+static int32_t ARM_USART3_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART3_DEV, data, num);
+}
+
+static int32_t ARM_USART3_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART3_DEV, data, num);
+}
+
+static int32_t ARM_USART3_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART3_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART3_DEV);
+}
+
+static uint32_t ARM_USART3_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART3_DEV);
+}
+static int32_t ARM_USART3_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART3_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART3_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART3_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART3_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART3;
+ARM_DRIVER_USART Driver_USART3 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART3_Initialize,
+ ARM_USART3_Uninitialize,
+ ARM_USART3_PowerControl,
+ ARM_USART3_Send,
+ ARM_USART3_Receive,
+ ARM_USART3_Transfer,
+ ARM_USART3_GetTxCount,
+ ARM_USART3_GetRxCount,
+ ARM_USART3_Control,
+ ARM_USART3_GetStatus,
+ ARM_USART3_SetModemControl,
+ ARM_USART3_GetModemStatus
+};
+#endif /* RTE_USART3 */
+
+#if (RTE_USART4)
+/* USART4 Driver wrapper functions */
+static UARTx_Resources USART4_DEV = {
+#if (__DOMAIN_NS == 1)
+ .dev = &ARM_UART4_DEV_NS,
+#else
+ .dev = &ARM_UART4_DEV_S,
+#endif
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART4_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART4_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART4_DEV);
+}
+
+static int32_t ARM_USART4_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART4_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART4_DEV, state);
+}
+
+static int32_t ARM_USART4_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART4_DEV, data, num);
+}
+
+static int32_t ARM_USART4_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART4_DEV, data, num);
+}
+
+static int32_t ARM_USART4_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART4_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART4_DEV);
+}
+
+static uint32_t ARM_USART4_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART4_DEV);
+}
+static int32_t ARM_USART4_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART4_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART4_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART4_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART4_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART4;
+ARM_DRIVER_USART Driver_USART4 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART4_Initialize,
+ ARM_USART4_Uninitialize,
+ ARM_USART4_PowerControl,
+ ARM_USART4_Send,
+ ARM_USART4_Receive,
+ ARM_USART4_Transfer,
+ ARM_USART4_GetTxCount,
+ ARM_USART4_GetRxCount,
+ ARM_USART4_Control,
+ ARM_USART4_GetStatus,
+ ARM_USART4_SetModemControl,
+ ARM_USART4_GetModemStatus
+};
+#endif /* RTE_USART4 */
diff --git a/platform/ext/target/mps2/an519/device_cfg.h b/platform/ext/target/mps2/an519/device_cfg.h
new file mode 100644
index 0000000..d4b68bd
--- /dev/null
+++ b/platform/ext/target/mps2/an519/device_cfg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief
+ * This is the default device configuration file with all peripherals
+ * defined and configured to be use via the secure and/or non-secure base
+ * address. This file is an example of how to define your own configuration
+ * file with the peripherals required for your application.
+ */
+
+/* ARM Memory Protection Controller (MPC) */
+#define MPC_CODE_SRAM1_S
+#define MPC_CODE_SRAM2_S
+
+/* ARM Peripheral Protection Controllers (PPC) */
+#define APB_PPCEXP2_S
+
+/* ARM UART */
+#define DEFAULT_UART_BAUDRATE 9600
+#define ARM_UART0_S
+#define ARM_UART0_NS
+#define ARM_UART1_S
+#define ARM_UART1_NS
+
+/* CMSDK Timers */
+#define CMSDK_TIMER0_S
+#define CMSDK_TIMER0_NS
+#define CMSDK_TIMER1_S
+#define CMSDK_TIMER1_NS
+
+#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/mps2/an519/dummy_crypto_keys.c b/platform/ext/target/mps2/an519/dummy_crypto_keys.c
new file mode 100644
index 0000000..315e216
--- /dev/null
+++ b/platform/ext/target/mps2/an519/dummy_crypto_keys.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/plat_crypto_keys.h"
+
+#define TFM_KEY_LEN_BYTES 16
+
+static uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] =
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
+enum tfm_plat_errno_t plat_get_crypto_huk(uint8_t* key, uint32_t size)
+{
+ /* FIXME: this function should be implemented by platform vendor. For the
+ * security of the storage system, it is critical to use a hardware unique
+ * key.
+ *
+ * AN519 does not have any available hardware unique key engine, so a
+ * software stub has been implemented in this case.
+ */
+ uint32_t i;
+ uint8_t* p_dst = key;
+ uint8_t* p_huk = sample_tfm_key;
+
+ if(size > TFM_KEY_LEN_BYTES) {
+ return TFM_PLAT_ERRNO_SYSTEM_ERR;
+ }
+
+ for (i = size; i > 0; i--) {
+ *((uint8_t*)p_dst) = *((uint8_t*)p_huk);
+ p_huk++;
+ p_dst++;
+ }
+
+ return TFM_PLAT_ERRNO_SUCCESS;
+}
+
diff --git a/platform/ext/target/mps2/an519/native_drivers/arm_uart_drv.c b/platform/ext/target/mps2/an519/native_drivers/arm_uart_drv.c
new file mode 100644
index 0000000..d61ae48
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/arm_uart_drv.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_uart_drv.h"
+
+#include <stddef.h>
+
+/* UART register map structure */
+struct _arm_uart_reg_map_t {
+ volatile uint32_t data; /* Offset: 0x000 (R/W) data register */
+ volatile uint32_t state; /* Offset: 0x004 (R/W) status register */
+ volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */
+ union {
+ volatile uint32_t intrstatus; /* Offset: 0x00c (R/ ) interrupt status
+ * register */
+ volatile uint32_t intrclear; /* Offset: 0x00c ( /W) interrupt clear
+ * register */
+ }intr_reg;
+ volatile uint32_t bauddiv; /* Offset: 0x010 (R/W) Baudrate divider
+ * register */
+};
+
+/* CTRL Register */
+#define ARM_UART_TX_EN (1ul << 0)
+#define ARM_UART_RX_EN (1ul << 1)
+#define ARM_UART_TX_INTR_EN (1ul << 2)
+#define ARM_UART_RX_INTR_EN (1ul << 3)
+
+/* STATE Register */
+#define ARM_UART_TX_BF (1ul << 0)
+#define ARM_UART_RX_BF (1ul << 1)
+
+/* INTSTATUS Register */
+#define ARM_UART_TX_INTR (1ul << 0)
+#define ARM_UART_RX_INTR (1ul << 1)
+
+/* UART state definitions */
+#define ARM_UART_INITIALIZED (1ul << 0)
+
+enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev,
+ uint32_t system_clk)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+ if(system_clk == 0) {
+ return ARM_UART_ERR_INVALID_ARG;
+ }
+
+ /* Sets baudrate and system clock */
+ dev->data->system_clk = system_clk;
+ dev->data->baudrate = dev->cfg->default_baudrate;
+
+ /* Sets baudrate */
+ p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate);
+
+ /* Enables receiver and transmitter */
+ p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN;
+
+ dev->data->state = ARM_UART_INITIALIZED;
+
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev,
+ uint32_t baudrate)
+{
+ uint32_t bauddiv;
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(baudrate == 0) {
+ return ARM_UART_ERR_INVALID_BAUD;
+ }
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ /* Sets baudrate */
+ bauddiv = (dev->data->system_clk / baudrate);
+ dev->data->baudrate = baudrate;
+
+ /* Minimum bauddiv value */
+ if(bauddiv < 16) {
+ return ARM_UART_ERR_INVALID_BAUD;
+ }
+
+ p_uart->bauddiv = bauddiv;
+
+ return ARM_UART_ERR_NONE;
+}
+
+uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev)
+{
+ return dev->data->baudrate;
+}
+
+enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev,
+ uint32_t system_clk)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(system_clk == 0) {
+ return ARM_UART_ERR_INVALID_ARG;
+ }
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ /* Sets system clock */
+ dev->data->system_clk = system_clk;
+
+ /* Updates baudrate divider */
+ p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate);
+
+ /* Enables receiver and transmitter */
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(p_uart->state & ARM_UART_RX_BF)) {
+ return ARM_UART_ERR_NOT_READY;
+ }
+
+ /* Reads data */
+ *byte = (uint8_t)p_uart->data;
+
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(p_uart->state & ARM_UART_TX_BF) {
+ return ARM_UART_ERR_NOT_READY;
+ }
+
+ /* Sends data */
+ p_uart->data = byte;
+
+ return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ p_uart->ctrl |= ARM_UART_TX_INTR_EN;
+
+ return ARM_UART_ERR_NONE;
+}
+
+void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & ARM_UART_INITIALIZED ) {
+ p_uart->ctrl &= ~ARM_UART_TX_INTR_EN;
+ }
+}
+
+uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return 0;
+ }
+
+ return !(p_uart->state & ARM_UART_TX_BF);
+}
+
+enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return ARM_UART_ERR_NOT_INIT;
+ }
+
+ p_uart->ctrl |= ARM_UART_RX_INTR_EN;
+
+ return ARM_UART_ERR_NONE;
+}
+
+void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & ARM_UART_INITIALIZED) {
+ p_uart->ctrl &= ~ARM_UART_RX_INTR_EN;
+ }
+}
+
+uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+ return 0;
+ }
+
+ return (p_uart->state & ARM_UART_RX_BF);
+}
+
+void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev,
+ enum arm_uart_irq_t irq)
+{
+ struct _arm_uart_reg_map_t* p_uart =
+ (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & ARM_UART_INITIALIZED) {
+ /* Clears pending interrupts */
+ switch(irq) {
+ case ARM_UART_IRQ_RX:
+ p_uart->intr_reg.intrclear = ARM_UART_RX_INTR;
+ break;
+ case ARM_UART_IRQ_TX:
+ p_uart->intr_reg.intrclear = ARM_UART_TX_INTR;
+ break;
+ case ARM_UART_IRQ_COMBINED:
+ p_uart->intr_reg.intrclear = (ARM_UART_RX_INTR | ARM_UART_TX_INTR);
+ break;
+ /* default: not defined to force all cases to be handled */
+ }
+ }
+}
diff --git a/platform/ext/target/mps2/an519/native_drivers/arm_uart_drv.h b/platform/ext/target/mps2/an519/native_drivers/arm_uart_drv.h
new file mode 100644
index 0000000..64d8200
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/arm_uart_drv.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_uart_drv.h
+ * \brief Generic driver for ARM UART.
+ */
+
+#ifndef __ARM_UART_DRV_H__
+#define __ARM_UART_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ARM UART device configuration structure */
+struct arm_uart_dev_cfg_t {
+ const uint32_t base; /*!< UART base address */
+ const uint32_t default_baudrate; /*!< Default baudrate */
+};
+
+/* ARM UART device data structure */
+struct arm_uart_dev_data_t {
+ uint32_t state; /*!< Indicates if the uart driver
+ is initialized and enabled */
+ uint32_t system_clk; /*!< System clock */
+ uint32_t baudrate; /*!< Baudrate */
+};
+
+/* ARM UART device structure */
+struct arm_uart_dev_t {
+ const struct arm_uart_dev_cfg_t* const cfg; /*!< UART configuration */
+ struct arm_uart_dev_data_t* const data; /*!< UART data */
+};
+
+/* ARM UART enumeration types */
+enum arm_uart_error_t {
+ ARM_UART_ERR_NONE = 0, /*!< No error */
+ ARM_UART_ERR_INVALID_ARG, /*!< Error invalid input argument */
+ ARM_UART_ERR_INVALID_BAUD, /*!< Invalid baudrate */
+ ARM_UART_ERR_NOT_INIT, /*!< Error UART not initialized */
+ ARM_UART_ERR_NOT_READY, /*!< Error UART not ready */
+};
+
+enum arm_uart_irq_t {
+ ARM_UART_IRQ_RX, /*!< RX interrupt source */
+ ARM_UART_IRQ_TX, /*!< TX interrupt source */
+ ARM_UART_IRQ_COMBINED /*!< RX-TX combined interrupt source */
+};
+
+/**
+ * \brief Initializes UART. It uses the default baudrate to configure
+ * the peripheral at this point.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] system_clk System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev,
+ uint32_t system_clk);
+
+/**
+ * \brief Sets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] baudrate New baudrate.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev,
+ uint32_t baudrate);
+
+/**
+ * \brief Gets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns the UART baudrate.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Sets system clock.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] system_clk System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev,
+ uint32_t system_clk);
+/**
+ * \brief Reads one byte from UART dev.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] byte Pointer to byte.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note For better performance, this function doesn't check if dev and byte
+ * pointer are NULL, and if the driver is initialized.
+ */
+enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte);
+
+/**
+ * \brief Writes a byte to UART dev.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] byte Byte to write.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte);
+
+/**
+ * \brief Enables TX interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Disables TX interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Verifies if Tx is ready to send more data.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return 1 if TX is ready, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Enables RX interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Disables RX interrupt
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Verifies if Rx has data.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ *
+ * \return 1 if RX has data, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Clears UART interrupt.
+ *
+ * \param[in] dev UART device struct \ref arm_uart_dev_t
+ * \param[in] irq IRQ source to clean \ref arm_uart_irq_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev,
+ enum arm_uart_irq_t irq);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ARM_UART_DRV_H__ */
diff --git a/platform/ext/target/mps2/an519/native_drivers/mpc_sie200_drv.c b/platform/ext/target/mps2/an519/native_drivers/mpc_sie200_drv.c
new file mode 100644
index 0000000..e842681
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/mpc_sie200_drv.c
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mpc_sie200_drv.h"
+
+#include <stddef.h>
+
+#include "cmsis.h"
+
+#define MPC_SIE200_BLK_CFG_OFFSET 5U
+
+#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a
+ * bus error */
+#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */
+#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */
+
+/* ARM MPC interrupt */
+#define MPC_SIE200_INT_EN 1UL
+#define MPC_SIE200_INT_STAT 1UL
+
+/* ARM MPC state definitions */
+#define MPC_SIE200_INITIALIZED (1 << 0)
+
+/* Error code returned by the internal driver functions */
+enum mpc_sie200_intern_error_t{
+ MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE,
+ MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE,
+ MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED,
+ MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE,
+ MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE =
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE,
+ /* Calculated block index
+ is higher than the maximum allowed by the MPC. It should never
+ happen unless the controlled ranges of the MPC are misconfigured
+ in the driver or if the IP has not enough LUTs to cover the
+ range, due to wrong reported block size for example.
+ */
+ MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1,
+
+};
+
+/* ARM MPC memory mapped register access structure */
+struct mpc_sie200_reg_map_t {
+ volatile uint32_t ctrl; /* (R/W) MPC Control */
+ volatile uint32_t reserved[3];/* Reserved */
+ volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */
+ volatile uint32_t blk_cfg; /* (R/ ) Block configuration */
+ volatile uint32_t blk_idx; /* (R/W) Index value for accessing block
+ * based look up table */
+ volatile uint32_t blk_lutn; /* (R/W) Block based gating
+ * Look Up Table (LUT) */
+ volatile uint32_t int_stat; /* (R/ ) Interrupt state */
+ volatile uint32_t int_clear; /* ( /W) Interrupt clear */
+ volatile uint32_t int_en; /* (R/W) Interrupt enable */
+ volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */
+ volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */
+ volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */
+ volatile uint32_t reserved2[997]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */
+ volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */
+ volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/*
+ * Checks if the address is controlled by the MPC and returns
+ * the range index in which it is contained.
+ *
+ * \param[in] dev MPC device to initalize \ref mpc_sie200_dev_t
+ * \param[in] addr Address to check if it is controlled by MPC.
+ * \param[out] addr_range Range index in which it is contained.
+ *
+ * \return True if the base is controller by the range list, false otherwise.
+ */
+static uint32_t is_ctrl_by_range_list(struct mpc_sie200_dev_t* dev, uint32_t addr,
+ const struct mpc_sie200_memory_range_t** addr_range)
+{
+ uint32_t i;
+ const struct mpc_sie200_memory_range_t* range;
+
+ for(i = 0; i < dev->data->nbr_of_ranges; i++) {
+ range = dev->data->range_list[i];
+ if(addr >= range->base && addr <= range->limit) {
+ *addr_range = range;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Gets the masks selecting the bits in the LUT of the MPC corresponding
+ * to the base address (included) up to the limit address (included)
+ *
+ * \param[in] mpc_dev The MPC device.
+ * \param[in] base Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[in] limit Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[out] range Memory range in which the base address and
+ * limit are.
+ * \param[out] first_word_idx Index of the first touched word in the LUT.
+ * \param[out] nr_words Number of words used in the LUT. If 1, only
+ * first_word_mask is valid and limit_word_mask
+ * must not be used.
+ * \param[out] first_word_mask First word mask in the LUT will be stored here.
+ * \param[out] limit_word_mask Limit word mask in the LUT will be stored here.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_intern_error_t
+ */
+static enum mpc_sie200_intern_error_t get_lut_masks(
+ struct mpc_sie200_dev_t* dev,
+ const uint32_t base, const uint32_t limit,
+ const struct mpc_sie200_memory_range_t** range,
+ uint32_t *first_word_idx,
+ uint32_t *nr_words,
+ uint32_t *first_word_mask,
+ uint32_t *limit_word_mask)
+{
+ const struct mpc_sie200_memory_range_t* base_range;
+ uint32_t block_size;
+ uint32_t base_block_idx;
+ uint32_t base_word_idx;
+ uint32_t blk_max;
+ const struct mpc_sie200_memory_range_t* limit_range;
+ uint32_t limit_block_idx;
+ uint32_t limit_word_idx;
+ uint32_t mask;
+ uint32_t norm_base;
+ uint32_t norm_limit;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ /*
+ * Check that the addresses are within the controlled regions
+ * of this MPC
+ */
+ if(!is_ctrl_by_range_list(dev, base, &base_range) ||
+ !is_ctrl_by_range_list(dev, limit, &limit_range)) {
+ return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE;
+ }
+
+ /* Base and limit should be part of the same range */
+ if(base_range != limit_range) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+ *range = base_range;
+
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ /* Base and limit+1 addresses must be aligned on the MPC block size */
+ if(base % block_size || (limit+1) % block_size) {
+ return MPC_SIE200_INTERN_ERR_NOT_ALIGNED;
+ }
+
+ /*
+ * Get a normalized address that is an offset from the beginning
+ * of the lowest range controlled by the MPC
+ */
+ norm_base = (base - base_range->base);
+ norm_limit = (limit - base_range->base);
+
+ /*
+ * Calculate block index and to which 32 bits word it belongs
+ */
+ limit_block_idx = norm_limit/block_size;
+ limit_word_idx = limit_block_idx/32;
+
+ base_block_idx = norm_base/block_size;
+ base_word_idx = base_block_idx/32;
+
+ if(base_block_idx > limit_block_idx) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+
+ /* Transmit the information to the caller */
+ *nr_words = limit_word_idx - base_word_idx + 1;
+ *first_word_idx = base_word_idx;
+
+ /* Limit to the highest block that can be configured */
+ blk_max = p_mpc->blk_max;
+
+ if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) {
+ return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH;
+ }
+
+ /*
+ * Create the mask for the first word to only select the limit N bits
+ */
+ *first_word_mask = ~((1 << (base_block_idx % 32)) - 1);
+
+ /*
+ * Create the mask for the limit word to select only the first M bits.
+ */
+ *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1;
+ /*
+ * If limit_word_mask is 0, it means that the limit touched block index is
+ * the limit in its word, so the limit word mask has all its bits selected
+ */
+ if(*limit_word_mask == 0) {
+ *limit_word_mask = 0xFFFFFFFF;
+ }
+
+ /*
+ * If the blocks to configure are all packed in one word, only
+ * touch this word.
+ * Code using the computed masks should test if this mask
+ * is non-zero, and if so, only use this one instead of the limit_word_mask
+ * and first_word_mask.
+ * As the only bits that are the same in both masks are the 1 that we want
+ * to select, just use XOR to extract them.
+ */
+ if(base_word_idx == limit_word_idx) {
+ mask = ~(*first_word_mask ^ *limit_word_mask);
+ *first_word_mask = mask;
+ *limit_word_mask = mask;
+ }
+
+ return MPC_SIE200_INTERN_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges)
+{
+ if((range_list == NULL) || (nbr_of_ranges == 0)) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ dev->data->range_list = range_list;
+ dev->data->nbr_of_ranges = nbr_of_ranges;
+ dev->data->state = MPC_SIE200_INITIALIZED;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(blk_size == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /* Calculate the block size in byte according to the manual */
+ *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr)
+{
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_mask;
+ uint32_t limit_word_idx;
+ uint32_t nr_words;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ /* Sanity check to make sure the given range is within this MPCs range */
+ if ((dev->data->range_list[attr]->base > base) ||
+ (dev->data->range_list[attr]->limit < limit) ) {
+ return MPC_SIE200_ERR_NOT_IN_RANGE;
+ }
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx + nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to a generic errpr */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /*
+ * The memory range should allow accesses in with the wanted security
+ * attribute if it requires special attribute for successfull accesses
+ */
+ if(range->attr != attr) {
+ return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ }
+
+ /*
+ * Starts changing actual configuration so issue DMB to ensure every
+ * transaction has completed by now
+ */
+ __DMB();
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* First word */
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ /* Partially configure the first word */
+ p_mpc->blk_lutn = word_value;
+
+ /* Fully configure the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ p_mpc->blk_lutn = 0xFFFFFFFF;
+ } else {
+ p_mpc->blk_lutn = 0x00000000;
+ }
+ }
+
+ /* Partially configure the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= limit_word_mask;
+ } else {
+ word_value &= ~limit_word_mask;
+ }
+ p_mpc->blk_idx = limit_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base, uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr)
+{
+ enum mpc_sie200_sec_attr_t attr_prev;
+ uint32_t block_size;
+ uint32_t block_size_mask;
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_idx;
+ uint32_t limit_word_mask;
+ uint32_t nr_words;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(attr == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /*
+ * Initialize the security attribute to mixed in case of early
+ * termination of this function. A caller that does not check the
+ * returned error will act as if it does not know anything about the
+ * region queried, which is the safest bet
+ */
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+
+ /*
+ * If the base and limit are not aligned, align them and make sure
+ * that the resulting region fully includes the original region
+ */
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ block_size_mask = block_size - 1;
+ base &= ~(block_size_mask);
+ limit &= ~(block_size_mask);
+ limit += block_size - 1; /* Round to the upper block address,
+ * and then remove one to get the preceding
+ * address.
+ */
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx+nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to generic error */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ word_value &= first_word_mask;
+ if(word_value == 0) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ /*
+ * If there are differences between the mask and the word value,
+ * it means that the security attributes of blocks are mixed
+ */
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* Get the partial configuration of the first word */
+ word_value = p_mpc->blk_lutn & first_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ /*
+ * Bail out as the security attribute will be the same regardless
+ * of the configuration of other blocks
+ */
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ /*
+ * Store the current found attribute, to check that all the blocks indeed
+ * have the same security attribute.
+ */
+ attr_prev = *attr;
+
+ /* Get the configuration of the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ word_value = p_mpc->blk_lutn;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value == 0xFFFFFFFF) {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* If the attribute is different than the one found before, bail out */
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+ attr_prev = *attr;
+ }
+
+ /* Get the partial configuration of the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn & limit_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(ctrl_val == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ *ctrl_val = p_mpc->ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl = mpc_ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(sec_rep == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) {
+ *sec_rep = MPC_SIE200_RESP_BUS_ERROR;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ *sec_rep = MPC_SIE200_RESP_RAZ_WI;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->int_en |= MPC_SIE200_INT_EN;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_en &= ~MPC_SIE200_INT_EN;
+}
+
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_clear = MPC_SIE200_INT_EN;
+}
+
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ return (p_mpc->int_stat & MPC_SIE200_INT_STAT);
+}
+
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT
+ | MPC_SIE200_CTRL_SEC_LOCK_DOWN);
+
+ return MPC_SIE200_ERR_NONE;
+}
diff --git a/platform/ext/target/mps2/an519/native_drivers/mpc_sie200_drv.h b/platform/ext/target/mps2/an519/native_drivers/mpc_sie200_drv.h
new file mode 100644
index 0000000..02bd1d9
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/mpc_sie200_drv.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file mpc_sie200_drv.h
+ * \brief Generic driver for ARM SIE 200 Memory Protection
+ * Controllers (MPC).
+ */
+
+#ifndef __MPC_SIE_200_DRV_H__
+#define __MPC_SIE_200_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Error code returned by the driver functions */
+enum mpc_sie200_error_t {
+ MPC_SIE200_ERR_NONE, /*!< No error */
+ MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */
+ MPC_SIE200_NOT_INIT, /*!< MPC not initialized */
+ MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range
+ * controlled by the MPC */
+ MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size
+ * of this MPC */
+ MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure
+ * is invalid. This could be because:
+ * - The base and limit swapped
+ * - The base and limit addresses
+ * are in different ranges */
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be
+ * accessed with the wanted
+ * security attributes */
+};
+
+/* Security attribute used in various place of the API */
+enum mpc_sie200_sec_attr_t {
+ MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */
+ MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */
+ /*!< Used when getting the configuration of a memory range and some blocks
+ * are secure whereas some other are non secure */
+ MPC_SIE200_SEC_ATTR_MIXED,
+};
+
+/* What can happen when trying to do an illegal memory access */
+enum mpc_sie200_sec_resp_t {
+ MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */
+ MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */
+};
+
+/* Description of a memory range controlled by the MPC */
+struct mpc_sie200_memory_range_t {
+ const uint32_t base; /*!< Base address (included in the range) */
+ const uint32_t limit; /*!< Limit address (excluded in the range) */
+ const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute
+ needed to be matched when
+ accessing this range.
+ For example, the non-secure
+ alias of a memory region can not
+ be accessed using secure access,
+ and configuring the MPC to
+ secure using that range will not
+ be permitted by the driver. */
+};
+
+/* ARM MPC SIE 200 device configuration structure */
+struct mpc_sie200_dev_cfg_t {
+ const uint32_t base; /*!< MPC base address */
+};
+
+/* ARM MPC SIE 200 device data structure */
+struct mpc_sie200_dev_data_t {
+ const struct mpc_sie200_memory_range_t** range_list; /*!< Array of pointers
+ to memory ranges
+ controlled by
+ the MPC */
+ uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */
+ uint8_t state; /*!< Indicates if the MPC driver
+ is initialized and enabled */
+ uint16_t reserved; /*!< 32 bits alignment */
+};
+
+/* ARM MPC SIE 200 device structure */
+struct mpc_sie200_dev_t {
+ const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */
+ struct mpc_sie200_dev_data_t* const data; /*!< MPC data */
+};
+
+/**
+ * \brief Initializes a MPC device.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] range_list List of memory ranges controller by the MPC
+ * (\ref mpc_sie200_memory_range_t). This list can not
+ * freed after the initializations.
+ * \param[in] nbr_of_ranges Number of memory ranges
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges);
+
+/**
+ * \brief Gets MPC block size. All regions must be aligned on this block
+ * size (base address and limit+1 address).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] blk_size MPC block size
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size);
+
+/**
+ * \brief Configures a memory region (base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to poll. This bound is
+ * included. It does not need to be aligned in any way.
+ *
+ * \param[in] limit Limit address of the region to poll. This bound is
+ * included. (limit+1) does not need to be aligned
+ * in any way.
+ * \param[in] attr Security attribute of the region. If the region has mixed
+ * secure/non-secure, a special value is returned
+ * (\ref mpc_sie200_sec_attr_t).
+ *
+ * In case base and limit+1 addresses are not aligned on
+ * the block size, the enclosing region with base and
+ * limit+1 aligned on block size will be queried.
+ * In case of early termination of the function (error), the
+ * security attribute will be set to MPC_SIE200_ATTR_MIXED.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr);
+
+/**
+ * \brief Gets a memory region configuration(base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to get the configuration.
+ * \param[in] limit Limit address of the region to get the configuration.
+ * \param[out] attr Security attribute of the region
+ * \ref mpc_sie200_sec_attr_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base,
+ uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr);
+
+/**
+ * \brief Gets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] ctrl_val Current MPC control value.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val);
+
+/**
+ * \brief Sets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] mpc_ctrl New MPC control value
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl);
+
+/**
+ * \brief Gets the configured secure response.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t).
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep);
+
+/**
+ * \brief Enables MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Disables MPC interrupt
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Clears MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Returns the MPC interrupt state.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Locks down the MPC configuration.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MPC_SIE_200_DRV_H__ */
diff --git a/platform/ext/target/mps2/an519/native_drivers/ppc_sse200_drv.c b/platform/ext/target/mps2/an519/native_drivers/ppc_sse200_drv.c
new file mode 100644
index 0000000..8db96e2
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/ppc_sse200_drv.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ppc_sse200_drv.h"
+
+/* SPCTRL PPCs control memory mapped registers access structure */
+struct arm_spctrl_ppc_sse200_t {
+ volatile uint32_t reserved[8];
+ volatile uint32_t secppcintstat; /* Secure PPC Interrupt Status */
+ volatile uint32_t secppcintclr; /* Secure PPC Interrupt Clear */
+ volatile uint32_t secppcinten; /* Secure PPC Interrupt Enable */
+ volatile uint32_t reserved1[9];
+ volatile uint32_t ahbnsppc0; /* Non-Secure Access AHB slave Peripheral
+ Protection Control #0 */
+ volatile uint32_t reserved2[3]; /* Reserved for Future Non-secure Access
+ AHB Slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbnsppcexp0; /* Expansion 0 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp1; /* Expansion 1 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp2; /* Expansion 2 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbnsppcexp3; /* Expansion 3 Non_Secure Access AHB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppc0; /* Non-Secure Access APB slave Peripheral
+ Protection Control 0 */
+ volatile uint32_t apbnsppc1; /* Non-Secure Access APB slave Peripheral
+ Protection Control 1 */
+ volatile uint32_t reserved3[2]; /* Non-Secure Access APB slave Peripheral
+ Protection Control [3:1] */
+ volatile uint32_t apbnsppcexp0; /* Expansion 0 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp1; /* Expansion 1 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp2; /* Expansion 2 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t apbnsppcexp3; /* Expansion 3 Non_Secure Access APB
+ slave Peripheral Protection Control */
+ volatile uint32_t ahbspppc0; /* Secure Unprivileged Access AHB slave
+ Peripheral Protection Control 0 */
+ volatile uint32_t reserved4[3]; /* Reserved for Future Secure Unprivileged
+ Access AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t ahbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ AHB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppc0; /* Secure Unprivileged Access APB slave
+ Peripheral 0 */
+ volatile uint32_t apbspppc1; /* Secure Unprivileged Access APB slave
+ Peripheral 1 */
+ volatile uint32_t reserved5[2]; /* Reserved for Future Secure Unprivileged
+ Access APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+ volatile uint32_t apbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ APB slave Peripheral Protection
+ Control */
+};
+
+/* NSPCTRL PPCs memory mapped register access structure */
+struct arm_nspctrl_ppc_sse200_t {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved1[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved2[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+};
+
+/* PPC interrupt position mask */
+#define APB_PPC0_INT_POS_MASK (1UL << 0)
+#define APB_PPC1_INT_POS_MASK (1UL << 1)
+/* Reseved bits 2:3 */
+#define APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+/* Reseved bits 8:15 */
+#define AHB_PPC0_INT_POS_MASK (1UL << 16)
+/* Reseved bits 17:19 */
+#define AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+/* Reseved bits 24:31 */
+
+/* ARM PPC state definitions */
+#define PPC_SSE200_INITIALIZED (1 << 0)
+
+/* Default peripheral states */
+#define SECURE_AS_DEFAULT_PERIPHERAL_STATE 1
+#define PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE 1
+
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+ struct arm_nspctrl_ppc_sse200_t* p_nspctrl =
+ (struct arm_nspctrl_ppc_sse200_t*)dev->cfg->nspctrl_base;
+
+ switch(ppc_name) {
+ case AHB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppc0;
+ dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp0;
+ dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp1;
+ dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp2;
+ dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp3;
+ dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK;
+ break;
+ case APB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc0;
+ dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK;
+ break;
+ case APB_PPC1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc1;
+ dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp0;
+ dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp1;
+ dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp2;
+ dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp3;
+ dev->data->int_bit_mask = APB_PPCEXP3_INT_POS_MASK;
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.*/
+ }
+
+ dev->data->state = PPC_SSE200_INITIALIZED;
+}
+
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ if(sec_attr == PPC_SSE200_SECURE_ONLY) {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) &= ~(1U << periph);
+
+ /* Uses secure unprivileged access address (SPCTRL) to set privilege
+ * attribute */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_sp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_sp_ppc) |= (1U << periph);
+ }
+ } else {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) |= (1U << periph);
+
+ /* Uses non-secure unprivileged access address (NSPCTRL) to set
+ * privilege attribute */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_nsp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_nsp_ppc) |= (1U << periph);
+ }
+ }
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return SECURE_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ return ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0);
+}
+
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ if ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0) {
+ /* Returns secure unprivileged access address (SPCTRL) */
+ return ((*(dev->data->p_sp_ppc) & (1U << periph)) == 0);
+ } else {
+ /* Returns non-secure unprivileged access address (NSPCTRL) */
+ return ((*(dev->data->p_nsp_ppc) & (1U << periph)) == 0);
+ }
+}
+
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ p_spctrl->secppcinten |= dev->data->int_bit_mask;
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcinten &= ~(dev->data->int_bit_mask);
+ }
+}
+
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcintclr = dev->data->int_bit_mask;
+ }
+}
+
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return 0;
+ }
+
+ return ((p_spctrl->secppcintstat & dev->data->int_bit_mask) != 0);
+}
diff --git a/platform/ext/target/mps2/an519/native_drivers/ppc_sse200_drv.h b/platform/ext/target/mps2/an519/native_drivers/ppc_sse200_drv.h
new file mode 100644
index 0000000..c09650b
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/ppc_sse200_drv.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file ppc_sse200_drv.h
+ * \brief Generic driver for ARM SEE 200 Peripheral Protection
+ * Controllers (PPC).
+ */
+
+#ifndef __PPC_SSE_200_DRV_H__
+#define __PPC_SSE_200_DRV_H__
+
+#include <stdint.h>
+
+/* Secure Privilege Control Block aka SPCTRL */
+/* Non-Secure Privilege Control Block aka NSPCTRL */
+
+/* ARM TrustZone PPC device configuration structure */
+struct ppc_sse200_dev_cfg_t {
+ uint32_t const spctrl_base; /*!< SPCTRL base address */
+ uint32_t const nspctrl_base; /*!< NSPCTRL base address */
+};
+
+/* ARM TrustZone PPC device data structure */
+struct ppc_sse200_dev_data_t {
+ volatile uint32_t* p_ns_ppc; /*!< Pointer to non-secure register */
+ volatile uint32_t* p_sp_ppc; /*!< Pointer to secure unprivileged
+ register */
+ volatile uint32_t* p_nsp_ppc; /*!< Pointer to non-secure unprivileged
+ register */
+ uint32_t int_bit_mask; /*!< Interrupt bit mask */
+ uint8_t state; /*!< Indicates if the PPC driver
+ is initialized */
+ uint8_t reserved[3]; /*!< 32 bits alignment */
+};
+
+/* ARM PPC device structure */
+struct ppc_sse200_dev_t {
+ const struct ppc_sse200_dev_cfg_t* const cfg; /*!< PPC configuration */
+ struct ppc_sse200_dev_data_t* const data; /*!< PPC data */
+};
+
+/* Security attribute used to configure the peripheral */
+enum ppc_sse200_sec_attr_t {
+ PPC_SSE200_SECURE_ONLY, /*! Secure access */
+ PPC_SSE200_NONSECURE_ONLY, /*! Non-secure access */
+};
+
+/* Privilege attribute used to configure the peripheral */
+enum ppc_sse200_priv_attr_t {
+ PPC_SSE200_PRIV_AND_NONPRIV, /*! Privilege and non-Privilege access */
+ PPC_SSE200_PRIV_ONLY, /*! Privilege only access */
+};
+
+/* ARM PPC error codes */
+enum ppc_sse200_error_t {
+ PPC_SSE200_ERR_NONE = 0, /*!< No error */
+ PPC_SSE200_NOT_INIT, /*!< PPC not initialized */
+};
+
+/* ARM PPC names */
+enum ppc_sse200_name_t {
+ AHB_PPC0 = 0, /*!< AHB PPC0 */
+ AHB_PPC_EXP0, /*!< Expansion 0 AHB PPC */
+ AHB_PPC_EXP1, /*!< Expansion 1 AHB PPC */
+ AHB_PPC_EXP2, /*!< Expansion 2 AHB PPC */
+ AHB_PPC_EXP3, /*!< Expansion 3 AHB PPC */
+ APB_PPC0, /*!< APB PPC0 */
+ APB_PPC1, /*!< APB PPC1 */
+ APB_PPC_EXP0, /*!< Expansion 0 APB PPC */
+ APB_PPC_EXP1, /*!< Expansion 1 APB PPC */
+ APB_PPC_EXP2, /*!< Expansion 2 APB PPC */
+ APB_PPC_EXP3 /*!< Expansion 3 APB PPC */
+};
+
+/**
+ * \brief Initialize the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] ppc_name PPC name \ref ppc_sse200_name_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name);
+
+/**
+ * \brief Configures the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ * \param[in] sec_attr Secure attribute value.
+ * \param[in] priv_attr Privilege attribute value.
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr);
+/**
+ * \brief Checks if the peripheral is configured as secure or non-secure.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for secure and 0 for non-secure.
+ * If the driver is not initalized the return value is 1 (secure) as
+ * it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+
+/**
+ * \brief Checks if the peripheral is configured as Privilege only or
+ * Privilege and non-Privilege access mode.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for Privilege only configuration and 0 for Privilege and
+ * non-Privilege access.
+ * If the driver is not initalized the return of this function is
+ * 1 (Privilege only) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+/**
+ * \brief Enables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Disables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Clears PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Returns the PPC interrupt state.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active and otherwise 0.
+ * If the driver is not initalized the return of this function is
+ * 0 (not active) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev);
+
+#endif /* __PPC_SSE_200_DRV_H__ */
diff --git a/platform/ext/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.c b/platform/ext/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.c
new file mode 100644
index 0000000..1037f2d
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk.c
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#include "timer_cmsdk.h"
+
+/** Setter bit manipulation macro */
+#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
+/** Clearing bit manipulation macro */
+#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
+/** Getter bit manipulation macro */
+#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
+
+/**
+ * \brief Timer register map structure
+ *
+ */
+struct cmsdk_timer_reg_map_t {
+ volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */
+ volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */
+ volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */
+ union {
+ volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt
+ * status register */
+ volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt
+ * clear register */
+ }intreg;
+};
+
+/**
+ * \brief CTRL register bit definitions
+ *
+ */
+enum ctrl_reg_bits_t{
+ CTRL_REG_ENUM_ENABLE_INDEX = 0,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2,
+ CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3
+};
+
+/**
+ * \brief INTSTATUS/INTCLEAR register bit definitions
+ *
+ */
+enum interrupt_reg_bits_t{
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0
+};
+
+void cmsdk_timer_init(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+
+ if (dev->data->is_initialized == 0) {
+ register_map->ctrl = 0;
+ register_map->reload = CMSDK_TIMER_DEFAULT_RELOAD;
+ dev->data->is_initialized = 1;
+ }
+}
+
+bool cmsdk_timer_is_initialized(const struct cmsdk_timer_dev_t* dev)
+{
+ return dev->data->is_initialized;
+}
+
+void cmsdk_timer_enable_external_input(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable_external_input(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_external_input_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void cmsdk_timer_set_clock_to_internal(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void cmsdk_timer_set_clock_to_external(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+bool cmsdk_timer_is_clock_external(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void cmsdk_timer_enable(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void cmsdk_timer_enable_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+void cmsdk_timer_disable_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_interrupt_enabled(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool cmsdk_timer_is_interrupt_active(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->intreg.intstatus,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+void cmsdk_timer_clear_interrupt(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->intreg.intclear,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+uint32_t cmsdk_timer_get_current_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->value;
+}
+
+void cmsdk_timer_set_reload_value(const struct cmsdk_timer_dev_t* dev,
+ uint32_t reload)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ register_map->reload = reload;
+}
+
+void cmsdk_timer_reset(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ register_map->value = register_map->reload;
+}
+
+uint32_t cmsdk_timer_get_reload_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->reload;
+}
+
+uint32_t cmsdk_timer_get_elapsed_value(const struct cmsdk_timer_dev_t* dev)
+{
+ struct cmsdk_timer_reg_map_t* register_map =
+ (struct cmsdk_timer_reg_map_t*)dev->cfg->base;
+ return register_map->reload - register_map->value;
+}
diff --git a/platform/ext/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.h b/platform/ext/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.h
new file mode 100644
index 0000000..52d9d5c
--- /dev/null
+++ b/platform/ext/target/mps2/an519/native_drivers/timer_cmsdk/timer_cmsdk.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk.h
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#ifndef __CMSDK_TIMER_DRV_H__
+#define __CMSDK_TIMER_DRV_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Maximum reload value */
+#define CMSDK_TIMER_MAX_RELOAD INT32_MAX /* max of 32-bit */
+#define CMSDK_TIMER_DEFAULT_RELOAD CMSDK_TIMER_MAX_RELOAD
+
+/** CMSDK timer device configuration structure */
+struct cmsdk_timer_dev_cfg_t {
+ const uintptr_t base; /*!< Timer base address */
+};
+
+/** CMSDK timer device data structure */
+struct cmsdk_timer_dev_data_t {
+ bool is_initialized; /*!< Indicates if the timer is initialized */
+};
+
+/* CMSDK timer device structure */
+struct cmsdk_timer_dev_t {
+ const struct cmsdk_timer_dev_cfg_t* const cfg; /*!< Timer configuration */
+ struct cmsdk_timer_dev_data_t* const data; /*!< Timer data */
+};
+
+/**
+ * \brief Initializes timer to a known default state, which is:
+ * - timer disabled
+ * - timer interrupt disabled
+ * - clock source set to internal
+ * - external input disabled
+ * - reload value maxed out
+ * Init should be called prior to any other process and
+ * it's the caller's responsibility to follow proper call order.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_init(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is initialized.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if initialized, false otherwise
+ */
+bool cmsdk_timer_is_initialized(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables external input, which could be used as clock source
+ * by calling \ref cmsdk_timer_set_clock_to_external.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable_external_input(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables external input.
+ * Make sure if the timer is explicitly wanted to be stopped or set
+ * the clock source to internal by \ref cmsdk_timer_set_clock_to_internal.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable_external_input(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if external input is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_external_input_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to internal.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_set_clock_to_internal(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to external.
+ * Make sure external input is enabled correspondingly
+ * by \ref cmsdk_timer_enable_external_input.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_set_clock_to_external(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if clock source is external input.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if external, false if internal
+ */
+bool cmsdk_timer_is_clock_external(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables timer operation.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables the given hardware timer.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Enables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_enable_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Disables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_disable_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Checks if a timer interrupt is enabled.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool cmsdk_timer_is_interrupt_enabled(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Gets timer interrupt status
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * * \return true if active, false otherwise
+ */
+bool cmsdk_timer_is_interrupt_active(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Clears timer interrupt
+ * The interrupt request is held until it is cleared.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_clear_interrupt(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Reads timer current value.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Timer value
+ */
+uint32_t cmsdk_timer_get_current_value(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Sets the reload value of the selected timer.
+ *
+ * New reload value takes effect when:
+ * - timer is restarted
+ * - on timer underflow
+ * - when cmsdk_timer_reset is called
+ *
+ * \note In r1p0 technical reference manual it's incorrectly stated
+ * writing the reload value automatically sets the current value also.
+ * r1p1 technical reference manual includes the fix.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ * \param[in] reload Timer reload value to set.
+ * This is the start value of the 32-bit down counter,
+ * which automatically reloaded if 0 is reached.
+ */
+void cmsdk_timer_set_reload_value(const struct cmsdk_timer_dev_t* dev,
+ uint32_t reload);
+
+/**
+ * \brief Resets the timer counter to the reload value instantly
+ * (i.e. without waiting for underflow).
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ */
+void cmsdk_timer_reset(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Gets the reload value of the selected timer.
+ * This is the start value of the 32-bit down counter,
+ * which is automatically reloaded if 0 is reached by the counter.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Reload value of the selected timer.
+ */
+uint32_t cmsdk_timer_get_reload_value(const struct cmsdk_timer_dev_t* dev);
+
+/**
+ * \brief Reads the number of ticks elapsed in the current cycle.
+ *
+ * \param[in] dev Timer configuration \ref cmsdk_timer_dev_t
+ *
+ * \return Get elapsed number of ticks since last reload was set.
+ * Elapsed = (Reload value - Current value)
+ */
+uint32_t cmsdk_timer_get_elapsed_value(const struct cmsdk_timer_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CMSDK_TIMER_DRV_H__ */
diff --git a/platform/ext/target/mps2/an519/partition/flash_layout.h b/platform/ext/target/mps2/an519/partition/flash_layout.h
new file mode 100644
index 0000000..a957832
--- /dev/null
+++ b/platform/ext/target/mps2/an519/partition/flash_layout.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/* Flash layout on MPS2 AN519 with BL2:
+ *
+ * 0x0000_0000 BL2 - MCUBoot
+ * 0x0008_0000 Flash_area_image_0:
+ * 0x0008_0000 Secure image primary
+ * 0x0010_0000 Non-secure image primary
+ * 0x0018_0000 Flash_area_image_1:
+ * 0x0018_0000 Secure image secondary
+ * 0x0020_0000 Non-secure image secondary
+ * 0x0028_0000 Scratch area
+ */
+#define FLASH_BASE_ADDRESS (0x0)
+
+#define FLASH_ALIGN (1)
+
+/* The size of a partition. This should be large enough to contain a S or NS
+ * sw binary. Each FLASH_AREA_IMAGE contains two partitions. See Flash layout
+ * above.
+ */
+#define FLASH_PARTITION_SIZE (0x80000)
+
+/* Sector size of the flash hardware */
+#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x4000)
+
+/* Offset and size definitions of the flash partitions that are handled by the
+ * bootloader. The image swapping is done between IMAGE_0 and IMAGE_1, SCRATCH
+ * is used to make notes of the progress of the image swapping.
+ */
+#define FLASH_AREA_BL2_OFFSET (0x0)
+#define FLASH_AREA_BL2_SIZE (FLASH_PARTITION_SIZE)
+
+#define FLASH_AREA_IMAGE_0_OFFSET (0x080000)
+#define FLASH_AREA_IMAGE_0_SIZE (2 * FLASH_PARTITION_SIZE)
+
+#define FLASH_AREA_IMAGE_1_OFFSET (0x180000)
+#define FLASH_AREA_IMAGE_1_SIZE (2 * FLASH_PARTITION_SIZE)
+
+#define FLASH_AREA_IMAGE_SCRATCH_OFFSET (0x280000)
+#define FLASH_AREA_IMAGE_SCRATCH_SIZE (2 * FLASH_PARTITION_SIZE)
+
+/* Offset and size definition in flash area, used by assemble.py */
+#define SECURE_IMAGE_OFFSET 0x0
+#define SECURE_IMAGE_MAX_SIZE 0x80000
+
+#define NON_SECURE_IMAGE_OFFSET 0x80000
+#define NON_SECURE_IMAGE_MAX_SIZE 0x80000
+
+#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/mps2/an519/partition/region_defs.h b/platform/ext/target/mps2/an519/partition/region_defs.h
new file mode 100644
index 0000000..bdf4b27
--- /dev/null
+++ b/platform/ext/target/mps2/an519/partition/region_defs.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "flash_layout.h"
+
+#define TOTAL_ROM_SIZE (0x00400000) /* 4MB */
+#define TOTAL_RAM_SIZE (0x00200000) /* 2MB */
+
+/*
+ * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment
+ * of partitions is defined in accordance with this constraint.
+ */
+
+/*Flash partitions on MPS2 AN519 with BL2:
+ *
+ * 0x0000_0000 BL2 - MCUBoot
+ * 0x0008_0000 Flash_area_image_0:
+ * 0x0008_0000 Secure image primary
+ * 0x0010_0000 Non-secure image primary
+ * 0x0018_0000 Flash_area_image_1:
+ * 0x0018_0000 Secure image secondary
+ * 0x0020_0000 Non-secure image secondary
+ * 0x0028_0000 Scratch area
+ *
+ * Flash partitions on bare metal, if BL2 not defined:
+ * 0x0000_0000 Secure image
+ * 0x0010_0000 Non-secure image
+ */
+
+#ifdef BL2
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET)
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0)
+#endif /* BL2 */
+
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (0x100000)
+
+/*
+ * Boot partition structure if MCUBoot is used:
+ * 0x0_0000 Bootloader header
+ * 0x0_0200 Image area
+ * 0x7_0000 Trailer
+ */
+/* IMAGE_CODE_SIZE is the space available for the software binary image.
+ * It is less than the FLASH_PARTITION_SIZE because we reserve space
+ * for the image header and trailer introduced by the bootloader. */
+#ifdef BL2
+#define BL2_HEADER_SIZE (0x400)
+#define BL2_TRAILER_SIZE (0x10000)
+#else
+/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */
+#define BL2_HEADER_SIZE (0x0)
+#define BL2_TRAILER_SIZE (0x10400)
+#endif /* BL2 */
+
+#define IMAGE_CODE_SIZE \
+ (FLASH_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+
+#define CMSE_VENEER_REGION_SIZE (0x00000080)
+
+/* Use SRAM1 memory to store Code data */
+#define S_ROM_ALIAS_BASE (0x10000000)
+#define NS_ROM_ALIAS_BASE (0x00000000)
+
+/* FIXME: Use SRAM2 memory to store RW data */
+#define S_RAM_ALIAS_BASE (0x38000000)
+#define NS_RAM_ALIAS_BASE (0x28000000)
+
+/* Alias definitions for secure and non-secure areas*/
+#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + x)
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + x)
+
+#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + x)
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + x)
+
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET \
+ (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
+#define S_CODE_SIZE (IMAGE_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+
+#define S_DATA_START (S_RAM_ALIAS(0x0))
+#define S_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
+
+/* CMSE Veneers region */
+#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+#define CMSE_VENEER_REGION_LIMIT (CMSE_VENEER_REGION_START + \
+ CMSE_VENEER_REGION_SIZE - 1)
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET \
+ (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
+#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
+#define NS_CODE_SIZE (IMAGE_CODE_SIZE)
+#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
+
+/* NS partition information is used for MPC configuration */
+#define NS_PARTITION_START \
+ (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
+
+#ifdef BL2
+/* Cover: non-secure primary + secure secondary + non-secure secondary area */
+#define NS_PARTITION_LIMIT \
+ (NS_PARTITION_START + 3 * FLASH_PARTITION_SIZE - 1)
+#else
+#define NS_PARTITION_LIMIT \
+ (NS_PARTITION_START + FLASH_PARTITION_SIZE - 1)
+#endif /* BL2 */
+
+#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE/2))
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE/2)
+#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE -1)
+
+#ifdef BL2
+/* Bootloader regions */
+#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET))
+#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
+#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
+
+#define BL2_DATA_START (S_RAM_ALIAS(0x0))
+#define BL2_DATA_SIZE (TOTAL_RAM_SIZE)
+#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
+#endif /* BL2 */
+
+#endif /* __REGION_DEFS_H__ */
+
diff --git a/platform/ext/target/mps2/an519/retarget/platform_retarget.h b/platform/ext/target/mps2/an519/retarget/platform_retarget.h
new file mode 100644
index 0000000..60b3001
--- /dev/null
+++ b/platform/ext/target/mps2/an519/retarget/platform_retarget.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget.h
+ * \brief This file defines all the peripheral base addresses for MPS2/AN519 platform.
+ */
+
+#ifndef __ARM_LTD_AN519_RETARGET_H__
+#define __ARM_LTD_AN519_RETARGET_H__
+
+#include "platform_regs.h" /* Platform registers */
+#include "platform_irq.h" /* IRQ numbers */
+#include "platform_retarget_pins.h" /* Platform pin names */
+
+/* ======= Defines peripherals memory map addresses ======= */
+/* Non-secure memory map addresses */
+#define CMSDK_TIMER0_BASE_NS 0x40000000
+#define CMSDK_TIMER1_BASE_NS 0x40001000
+#define APB_DUALTIMER_BASE_NS 0x40002000
+#define S32K_TIMER_BASE_NS 0x4002F000
+#define S32K_WATCHDOG_BASE_NS 0x4002E000
+#define APB_WATCHDOG_BASE_NS 0x40081000
+#define GPIO0_BASE_NS 0x40100000
+#define GPIO1_BASE_NS 0x40101000
+#define GPIO2_BASE_NS 0x40102000
+#define GPIO3_BASE_NS 0x40103000
+#define UART0_BASE_NS 0x40200000
+#define UART1_BASE_NS 0x40201000
+#define UART2_BASE_NS 0x40202000
+#define UART3_BASE_NS 0x40203000
+#define UART4_BASE_NS 0x40204000
+#define I2C0_SBCON_BASE_NS 0x40207000 /* Touchscreen I2C Base Address */
+#define I2C1_SBCON_BASE_NS 0x40208000 /* Audio I2C Base Address */
+#define I2C2_SBCON_BASE_NS 0x4020C000 /* Shield 0 SBCon Base Address */
+#define I2C3_SBCON_BASE_NS 0x4020D000 /* Shield 1 SBCon Base Address */
+#define SSP0_BASE_NS 0x40206000 /* CLCD SSP PL022 Base Address */
+#define SSP1_BASE_NS 0x40205000 /* User SSP PL022 Base Address */
+#define SSP2_BASE_NS 0x40209000 /* ADC SPI PL022 Base Address */
+#define SSP3_BASE_NS 0x4020A000 /* Shield 0 SPI PL022 Base Address */
+#define SSP4_BASE_NS 0x4020B000 /* Shield 1 SPI PL022 Base Address */
+#define MPS2_IO_SCC_BASE_NS 0x40300000
+#define MPS2_IO_FPGAIO_BASE_NS 0x40302000
+
+/* Secure memory map addresses */
+#define CMSDK_TIMER0_BASE_S 0x50000000
+#define CMSDK_TIMER1_BASE_S 0x50001000
+#define APB_DUALTIMER_BASE_S 0x50002000
+#define S32K_TIMER_BASE_S 0x5002F000
+#define S32K_WATCHDOG_BASE_S 0x5002E000
+#define APB_WATCHDOG_BASE_S 0x50081000
+#define GPIO0_BASE_S 0x50100000
+#define GPIO1_BASE_S 0x50101000
+#define GPIO2_BASE_S 0x50102000
+#define GPIO3_BASE_S 0x50103000
+#define UART0_BASE_S 0x50200000
+#define UART1_BASE_S 0x50201000
+#define UART2_BASE_S 0x50202000
+#define UART3_BASE_S 0x50203000
+#define UART4_BASE_S 0x50204000
+#define I2C0_SBCON_BASE_S 0x50207000
+#define I2C1_SBCON_BASE_S 0x50208000
+#define I2C2_SBCON_BASE_S 0x5020C000
+#define I2C3_SBCON_BASE_S 0x5020D000
+#define SSP0_BASE_S 0x50206000
+#define SSP1_BASE_S 0x50205000
+#define SSP2_BASE_S 0x50209000
+#define SSP3_BASE_S 0x5020A000
+#define SSP4_BASE_S 0x5020B000
+#define MPS2_IO_SCC_BASE_S 0x50300000
+#define MPS2_IO_FPGAIO_BASE_S 0x50302000
+#define MPC_ISRAM0_BASE_S 0x50083000
+#define MPC_CODE_SRAM1_BASE_S 0x58007000
+#define MPC_CODE_SRAM2_BASE_S 0x58008000
+#define MPC_CODE_SRAM3_BASE_S 0x58009000
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
+#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
+#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
+#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
+
+/* External SSRAM memory */
+#define MPC_CODE_SRAM1_RANGE_BASE_NS 0x00000000
+#define MPC_CODE_SRAM1_RANGE_LIMIT_NS 0x003FFFFF
+#define MPC_CODE_SRAM1_RANGE_BASE_S 0x10000000
+#define MPC_CODE_SRAM1_RANGE_LIMIT_S 0x103FFFFF
+
+#define MPC_CODE_SRAM2_RANGE_BASE_NS 0x28000000
+#define MPC_CODE_SRAM2_RANGE_LIMIT_NS 0x281FFFFF
+#define MPC_CODE_SRAM2_RANGE_BASE_S 0x38000000
+#define MPC_CODE_SRAM2_RANGE_LIMIT_S 0x381FFFFF
+
+#define MPC_CODE_SRAM3_RANGE_BASE_NS 0x28200000
+#define MPC_CODE_SRAM3_RANGE_LIMIT_NS 0x283FFFFF
+#define MPC_CODE_SRAM3_RANGE_BASE_S 0x38200000
+#define MPC_CODE_SRAM3_RANGE_LIMIT_S 0x383FFFFF
+
+#endif /* __ARM_LTD_AN519_RETARGET_H__ */
diff --git a/platform/ext/target/mps2/an519/retarget/platform_retarget_dev.c b/platform/ext/target/mps2/an519/retarget/platform_retarget_dev.c
new file mode 100644
index 0000000..1540586
--- /dev/null
+++ b/platform/ext/target/mps2/an519/retarget/platform_retarget_dev.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_dev.c
+ * \brief This file defines exports the structures based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#include "platform_retarget_dev.h"
+#include "platform_retarget.h"
+#include "system_cmsdk_mps2_an519.h"
+
+/* ARM UART driver structures */
+#ifdef ARM_UART0_S
+static const struct arm_uart_dev_cfg_t ARM_UART0_DEV_CFG_S = {
+ .base = UART0_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART0_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART0_DEV_S = {&(ARM_UART0_DEV_CFG_S),
+ &(ARM_UART0_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART0_NS
+static const struct arm_uart_dev_cfg_t ARM_UART0_DEV_CFG_NS = {
+ .base = UART0_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART0_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART0_DEV_NS = {&(ARM_UART0_DEV_CFG_NS),
+ &(ARM_UART0_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART1_S
+static const struct arm_uart_dev_cfg_t ARM_UART1_DEV_CFG_S = {
+ .base = UART1_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART1_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART1_DEV_S = {&(ARM_UART1_DEV_CFG_S),
+ &(ARM_UART1_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART1_NS
+static const struct arm_uart_dev_cfg_t ARM_UART1_DEV_CFG_NS = {
+ .base = UART1_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART1_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART1_DEV_NS = {&(ARM_UART1_DEV_CFG_NS),
+ &(ARM_UART1_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART2_S
+static const struct arm_uart_dev_cfg_t ARM_UART2_DEV_CFG_S = {
+ .base = UART2_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART2_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART2_DEV_S = {&(ARM_UART2_DEV_CFG_S),
+ &(ARM_UART2_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART2_NS
+static const struct arm_uart_dev_cfg_t ARM_UART2_DEV_CFG_NS = {
+ .base = UART2_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART2_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART2_DEV_NS = {&(ARM_UART2_DEV_CFG_NS),
+ &(ARM_UART2_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART3_S
+static const struct arm_uart_dev_cfg_t ARM_UART3_DEV_CFG_S = {
+ .base = UART3_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART3_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART3_DEV_S = {&(ARM_UART3_DEV_CFG_S),
+ &(ARM_UART3_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART3_NS
+static const struct arm_uart_dev_cfg_t ARM_UART3_DEV_CFG_NS = {
+ .base = UART3_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART3_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART3_DEV_NS = {&(ARM_UART3_DEV_CFG_NS),
+ &(ARM_UART3_DEV_DATA_NS)};
+#endif
+
+#ifdef ARM_UART4_S
+static const struct arm_uart_dev_cfg_t ARM_UART4_DEV_CFG_S = {
+ .base = UART4_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART4_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART4_DEV_S = {&(ARM_UART4_DEV_CFG_S),
+ &(ARM_UART4_DEV_DATA_S)};
+#endif
+#ifdef ARM_UART4_NS
+static const struct arm_uart_dev_cfg_t ARM_UART4_DEV_CFG_NS = {
+ .base = UART4_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART4_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0};
+struct arm_uart_dev_t ARM_UART4_DEV_NS = {&(ARM_UART4_DEV_CFG_NS),
+ &(ARM_UART4_DEV_DATA_NS)};
+#endif
+
+/* ARM PPC SIE 200 driver structures */
+#ifdef AHB_PPC0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPC0_DEV_S = {
+ &AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = {
+ &AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP1_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sie200_dev_t AHB_PPCEXP1_DEV_S = {
+ &AHB_PPCEXP1_DEV_CFG_S, &AHB_PPCEXP1_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP2_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S = {
+ &AHB_PPCEXP2_DEV_CFG_S, &AHB_PPCEXP2_DEV_DATA_S };
+#endif
+
+#ifdef AHB_PPCEXP3_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP3_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t AHB_PPCEXP3_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S = {
+ &AHB_PPCEXP3_DEV_CFG_S, &AHB_PPCEXP3_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPC0_S
+static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPC0_DEV_S = {
+ &APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPC1_S
+static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPC1_DEV_S = {
+ &APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S};
+#endif
+
+#ifdef APB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = {
+ &APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = {
+ &APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = {
+ &APB_PPCEXP2_DEV_CFG, &APB_PPCEXP2_DEV_DATA_S };
+#endif
+
+#ifdef APB_PPCEXP3_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP3_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS };
+static struct ppc_sse200_dev_data_t APB_PPCEXP3_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0 };
+struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S = {
+ &APB_PPCEXP3_DEV_CFG, &APB_PPCEXP3_DEV_DATA_S };
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
+ .base = CMSDK_TIMER0_BASE_S};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
+ &(CMSDK_TIMER0_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER0_NS
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
+ .base = CMSDK_TIMER0_BASE_NS};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
+ &(CMSDK_TIMER0_DEV_DATA_NS)};
+#endif
+
+#ifdef CMSDK_TIMER1_S
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
+ .base = CMSDK_TIMER1_BASE_S};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
+ &(CMSDK_TIMER1_DEV_DATA_S)};
+#endif
+#ifdef CMSDK_TIMER1_NS
+static const struct cmsdk_timer_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
+ .base = CMSDK_TIMER1_BASE_NS};
+static struct cmsdk_timer_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
+ .is_initialized = 0};
+struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
+ &(CMSDK_TIMER1_DEV_DATA_NS)};
+#endif
+
+/* ARM MPC SSE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = {
+ .base = MPC_ISRAM0_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = {
+ &(MPC_ISRAM0_DEV_CFG_S),
+ &(MPC_ISRAM0_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = {
+ .base = MPC_ISRAM1_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = {
+ &(MPC_ISRAM1_DEV_CFG_S),
+ &(MPC_ISRAM1_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM2_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = {
+ .base = MPC_ISRAM2_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = {
+ &(MPC_ISRAM2_DEV_CFG_S),
+ &(MPC_ISRAM2_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_ISRAM3_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = {
+ .base = MPC_ISRAM3_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = {
+ &(MPC_ISRAM3_DEV_CFG_S),
+ &(MPC_ISRAM3_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM1_DEV_CFG_S = {
+ .base = MPC_CODE_SRAM1_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_S = {
+ &(MPC_CODE_SRAM1_DEV_CFG_S),
+ &(MPC_CODE_SRAM1_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM2_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM2_DEV_CFG_S = {
+ .base = MPC_CODE_SRAM2_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM2_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM2_DEV_S = {
+ &(MPC_CODE_SRAM2_DEV_CFG_S),
+ &(MPC_CODE_SRAM2_DEV_DATA_S)};
+#endif
+
+#ifdef MPC_CODE_SRAM3_S
+static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM3_DEV_CFG_S = {
+ .base = MPC_CODE_SRAM3_BASE_S};
+static struct mpc_sie200_dev_data_t MPC_CODE_SRAM3_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0};
+struct mpc_sie200_dev_t MPC_CODE_SRAM3_DEV_S = {
+ &(MPC_CODE_SRAM3_DEV_CFG_S),
+ &(MPC_CODE_SRAM3_DEV_DATA_S)};
+#endif
diff --git a/platform/ext/target/mps2/an519/retarget/platform_retarget_dev.h b/platform/ext/target/mps2/an519/retarget/platform_retarget_dev.h
new file mode 100644
index 0000000..d8028d7
--- /dev/null
+++ b/platform/ext/target/mps2/an519/retarget/platform_retarget_dev.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_dev.h
+ * \brief The structure definitions in this file are exported based on the peripheral
+ * definitions from device_cfg.h.
+ * This retarget file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#ifndef __ARM_LTD_AN519_RETARGET_DEV_H__
+#define __ARM_LTD_AN519_RETARGET_DEV_H__
+
+#include "device_cfg.h"
+
+
+/* ======= Defines peripheral configuration structures ======= */
+/* ======= and includes generic driver headers if necessary ======= */
+/* ARM UART driver structures */
+#ifdef ARM_UART0_S
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART0_DEV_S;
+#endif
+#ifdef ARM_UART0_NS
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART0_DEV_NS;
+#endif
+
+#ifdef ARM_UART1_S
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART1_DEV_S;
+#endif
+#ifdef ARM_UART1_NS
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART1_DEV_NS;
+#endif
+
+#ifdef ARM_UART2_S
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART2_DEV_S;
+#endif
+#ifdef ARM_UART2_NS
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART2_DEV_NS;
+#endif
+
+#ifdef ARM_UART3_S
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART3_DEV_S;
+#endif
+#ifdef ARM_UART3_NS
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART3_DEV_NS;
+#endif
+
+#ifdef ARM_UART4_S
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART4_DEV_S;
+#endif
+#ifdef ARM_UART4_NS
+#include "arm_uart_drv.h"
+extern struct arm_uart_dev_t ARM_UART4_DEV_NS;
+#endif
+
+/* ARM PPC driver structures */
+#ifdef AHB_PPC0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP1_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sie200_dev_t AHB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP2_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP3_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S;
+#endif
+
+#ifdef APB_PPC0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPC0_DEV_S;
+#endif
+
+#ifdef APB_PPC1_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPC1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP1_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP2_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP3_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S;
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+#include "timer_cmsdk/timer_cmsdk.h"
+extern struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_S;
+#endif
+#ifdef CMSDK_TIMER0_NS
+#include "timer_cmsdk/timer_cmsdk.h"
+extern struct cmsdk_timer_dev_t CMSDK_TIMER0_DEV_NS;
+#endif
+
+#ifdef CMSDK_TIMER1_S
+#include "timer_cmsdk/timer_cmsdk.h"
+extern struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_S;
+#endif
+#ifdef CMSDK_TIMER1_NS
+#include "timer_cmsdk/timer_cmsdk.h"
+extern struct cmsdk_timer_dev_t CMSDK_TIMER1_DEV_NS;
+#endif
+
+/* ARM MPC SSE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM1_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM2_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM3_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S;
+#endif
+
+#ifdef MPC_CODE_SRAM1_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM1_DEV_S;
+#endif
+
+#ifdef MPC_CODE_SRAM2_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM2_DEV_S;
+#endif
+
+#ifdef MPC_CODE_SRAM3_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_CODE_SRAM3_DEV_S;
+#endif
+
+#endif /* __ARM_LTD_AN519_RETARGET_DEV_H__ */
diff --git a/platform/ext/target/mps2/an519/retarget/platform_retarget_pins.h b/platform/ext/target/mps2/an519/retarget/platform_retarget_pins.h
new file mode 100644
index 0000000..a20f584
--- /dev/null
+++ b/platform/ext/target/mps2/an519/retarget/platform_retarget_pins.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_retarget_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __ARM_LTD_AN519_RETARGET_PINS_H__
+#define __ARM_LTD_AN519_RETARGET_PINS_H__
+
+/* AHB GPIO pin names */
+enum arm_gpio_pin_name_t {
+ AHB_GPIO0_0 = 0U,
+ AHB_GPIO0_1 = 1U,
+ AHB_GPIO0_2 = 2U,
+ AHB_GPIO0_3 = 3U,
+ AHB_GPIO0_4 = 4U,
+ AHB_GPIO0_5 = 5U,
+ AHB_GPIO0_6 = 6U,
+ AHB_GPIO0_7 = 7U,
+ AHB_GPIO0_8 = 8U,
+ AHB_GPIO0_9 = 9U,
+ AHB_GPIO0_10 = 10U,
+ AHB_GPIO0_11 = 11U,
+ AHB_GPIO0_12 = 12U,
+ AHB_GPIO0_13 = 13U,
+ AHB_GPIO0_14 = 14U,
+ AHB_GPIO0_15 = 15U,
+ AHB_GPIO1_0 = 0U,
+ AHB_GPIO1_1 = 1U,
+ AHB_GPIO1_2 = 2U,
+ AHB_GPIO1_3 = 3U,
+ AHB_GPIO1_4 = 4U,
+ AHB_GPIO1_5 = 5U,
+ AHB_GPIO1_6 = 6U,
+ AHB_GPIO1_7 = 7U,
+ AHB_GPIO1_8 = 8U,
+ AHB_GPIO1_9 = 9U,
+ AHB_GPIO1_10 = 10U,
+ AHB_GPIO1_11 = 11U,
+ AHB_GPIO1_12 = 12U,
+ AHB_GPIO1_13 = 13U,
+ AHB_GPIO1_14 = 14U,
+ AHB_GPIO1_15 = 15U,
+ AHB_GPIO2_0 = 0U,
+ AHB_GPIO2_1 = 1U,
+ AHB_GPIO2_2 = 2U,
+ AHB_GPIO2_3 = 3U,
+ AHB_GPIO2_4 = 4U,
+ AHB_GPIO2_5 = 5U,
+ AHB_GPIO2_6 = 6U,
+ AHB_GPIO2_7 = 7U,
+ AHB_GPIO2_8 = 8U,
+ AHB_GPIO2_9 = 9U,
+ AHB_GPIO2_10 = 10U,
+ AHB_GPIO2_11 = 11U,
+ AHB_GPIO2_12 = 12U,
+ AHB_GPIO2_13 = 13U,
+ AHB_GPIO2_14 = 14U,
+ AHB_GPIO2_15 = 15U,
+ AHB_GPIO3_0 = 0U,
+ AHB_GPIO3_1 = 1U,
+ AHB_GPIO3_2 = 2U,
+ AHB_GPIO3_3 = 3U,
+};
+
+/* Pin definitions for the MPS2 Arduino adapter shields.
+ * Reference: Application Note AN502 */
+
+/*
+ * Shield buttons adaptor
+ * The user buttons on the shield are linked to the pins 5 and 6 of GPIO1.
+ */
+#define SHIELD_ADAPTOR_PB0 AHB_GPIO1_5
+#define SHIELD_ADAPTOR_PB1 AHB_GPIO1_6
+
+/* GPIO shield 0 definition */
+#define SH0_UART_RX AHB_GPIO0_0
+#define SH0_UART_TX AHB_GPIO0_4
+#define SH0_I2C_SCL AHB_GPIO0_5
+#define SH0_I2C_SDA AHB_GPIO0_15
+#define SH0_SPI_SCK AHB_GPIO0_11
+#define SH0_SPI_SS AHB_GPIO0_12
+#define SH0_SPI_MOSI AHB_GPIO0_13
+#define SH0_SPI_MISO AHB_GPIO0_14
+#define SH0_LED_RED AHB_GPIO0_6
+#define SH0_LED_GREEN AHB_GPIO0_10
+#define SH0_LED_BLUE AHB_GPIO0_9
+#define SH0_SPEAKER AHB_GPIO0_7
+#define SH0_LCD_CS SH0_SPI_SS
+#define SH0_LCD_A0 AHB_GPIO0_8
+#define SH0_LCD_RST SH0_SPI_MISO
+#define SH0_JT AHB_GPIO0_1
+
+/* GPIO shield 1 definition */
+#define SH1_UART_RX AHB_GPIO1_10
+#define SH1_UART_TX AHB_GPIO1_14
+#define SH1_I2C_SCL AHB_GPIO1_15
+#define SH1_I2C_SDA AHB_GPIO2_9
+#define SH1_SPI_SS AHB_GPIO2_6
+#define SH1_SPI_MOSI AHB_GPIO2_7
+#define SH1_SPI_MISO AHB_GPIO2_8
+#define SH1_SPI_SCK AHB_GPIO2_12
+#define SH1_LED_RED AHB_GPIO2_0
+#define SH1_LED_GREEN AHB_GPIO2_4
+#define SH1_LED_BLUE AHB_GPIO2_3
+#define SH1_SPEAKER AHB_GPIO2_1
+#define SH1_LCD_CS SH1_SPI_SS
+#define SH1_LCD_A0 AHB_GPIO2_2
+#define SH1_LCD_RST SH1_SPI_MISO
+#define SH1_JT AHB_GPIO1_11
+
+/* GPIO ADC SPI */
+#define ADC_SPI_SS AHB_GPIO1_0
+#define ADC_SPI_MOSI AHB_GPIO1_1
+#define ADC_SPI_MISO AHB_GPIO1_2
+#define ADC_SPI_SCK AHB_GPIO1_3
+
+/* GPIO BlueTooth/XBEE UART */
+#define BT_UART_RX AHB_GPIO1_7
+#define BT_UART_TX AHB_GPIO1_8
+#define BT_BOOT AHB_GPIO1_9
+
+#endif /* __ARM_LTD_AN519_RETARGET_PINS_H__ */
diff --git a/platform/ext/target/mps2/an519/target_cfg.c b/platform/ext/target/mps2/an519/target_cfg.c
new file mode 100644
index 0000000..e5570b3
--- /dev/null
+++ b/platform/ext/target/mps2/an519/target_cfg.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <arm_cmse.h>
+
+#include "cmsis.h"
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "platform_retarget_dev.h"
+#include "region_defs.h"
+#include "tfm_secure_api.h"
+
+/*
+ * This function pointer is meant to only hold non secure function pointers.
+ * It will be turned into a non-secure one (LSB cleared) before being called
+ * whatever happens anyway (unless cast to another function pointer type).
+ * Registers will be cleared before branching so that no information leaks
+ * from secure to non-secure world.
+ */
+typedef void __attribute__((cmse_nonsecure_call)) (*nsfptr_t) (void);
+
+/* Allows software, via SAU, to define the code region as a NSC */
+#define NSCCFG_CODENSC 1
+
+/* Import MPC driver */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC, Driver_SRAM2_MPC;
+
+/* Define Peripherals NS address range for the platform */
+#define PERIPHERALS_BASE_NS_START (0x40000000)
+#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF)
+
+void configure_ns_code()
+{
+ /* SCB_NS.VTOR points to the Non-secure vector table base address */
+ SCB_NS->VTOR = (NS_CODE_START);
+
+ /* Setups Main stack pointer of the non-secure code */
+ uint32_t ns_msp = *((uint32_t*)(NS_CODE_START));
+ __TZ_set_MSP_NS(ns_msp);
+}
+
+void jump_to_ns_code()
+{
+ /* The entry contains address of the Reset_handler (CMSIS-CORE) function */
+ uint32_t entry_ptr = *((uint32_t*)(NS_CODE_START + 4));
+
+ /* Clears LSB of the function address to indicate the function-call
+ will perform the switch from secure to non-secure */
+ nsfptr_t ns_entry = (nsfptr_t) cmse_nsfptr_create(entry_ptr);
+
+ /* All changes made to memory will be effective after this point */
+ __DSB();
+ __ISB();
+
+ /* Calls the non-secure Reset_Handler to jump to the non-secure binary */
+ ns_entry();
+}
+
+void enable_fault_handlers(void)
+{
+ /* Fault handles enable registers are not present in a baseline
+ * implementation
+ */
+}
+
+/*------------------- NVIC interrupt target state to NS configuration ----------*/
+void nvic_interrupt_target_state_cfg()
+{
+ /* Target every interrupt to NS; unimplemented interrupts will be WI */
+ for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) {
+ NVIC->ITNS[i] = 0xFFFFFFFF;
+ }
+
+ /* Make sure that MPC and PPC are targeted to S state */
+ NVIC_ClearTargetState(MPC_IRQn);
+ NVIC_ClearTargetState(PPC_IRQn);
+
+ /* UART1 is a secure peripheral, so its IRQs have to target S state */
+ NVIC_ClearTargetState(UARTRX1_IRQn);
+ NVIC_ClearTargetState(UARTTX1_IRQn);
+ NVIC_ClearTargetState(UART1_IRQn);
+}
+
+/*------------------- NVIC interrupt enabling for S peripherals ----------------*/
+void nvic_interrupt_enable()
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+
+ /* MPC interrupt enabling */
+ Driver_SRAM1_MPC.EnableInterrupt();
+ Driver_SRAM2_MPC.EnableInterrupt();
+ NVIC_EnableIRQ(MPC_IRQn);
+
+ /* PPC interrupt enabling */
+ /* Clear pending PPC interrupts */
+ /* In the PPC configuration function, we have used the Non-Secure
+ * Privilege Control Block to grant unprivilged NS access to some
+ * peripherals used by NS. That triggers a PPC0 exception as that
+ * register is meant for NS privileged access only. Clear it here
+ */
+ spctrl->secppcintclr |= CMSDK_APB_PPC0_INT_POS_MASK;
+
+ /* Enable PPC interrupts for APB PPC */
+ spctrl->secppcinten |= CMSDK_APB_PPC0_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPC1_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP0_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP1_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP2_INT_POS_MASK;
+ spctrl->secppcinten |= CMSDK_APB_PPCEXP3_INT_POS_MASK;
+ NVIC_EnableIRQ(PPC_IRQn);
+}
+
+/*------------------- SAU/IDAU configuration functions -------------------------*/
+
+void sau_and_idau_cfg(void)
+{
+ /* Enables SAU */
+ TZ_SAU_Enable();
+
+ /* Configures SAU regions to be non-secure */
+ SAU->RNR = TFM_NS_REGION_CODE;
+ SAU->RBAR = (NS_PARTITION_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_PARTITION_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ SAU->RNR = TFM_NS_REGION_DATA;
+ SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ /* Configures veneers region to be non-secure callable */
+ SAU->RNR = TFM_NS_REGION_VENEER;
+ SAU->RBAR = (CMSE_VENEER_REGION_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (CMSE_VENEER_REGION_LIMIT & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk
+ | SAU_RLAR_NSC_Msk;
+
+ /* Configure the peripherals space */
+ /* Only UART1 is configured as a secure peripheral */
+ SAU->RNR = TFM_NS_REGION_PERIPH_1;
+ SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = ((UART1_BASE_NS-1) & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk;
+
+ /* The UART1 range is considered as a (secure) gap */
+
+ SAU->RNR = TFM_NS_REGION_PERIPH_2;
+ SAU->RBAR = (UART2_BASE_NS & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk;
+
+ /* Allows SAU to define the code region as a NSC */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ spctrl->nsccfg |= NSCCFG_CODENSC;
+}
+
+/*------------------- Memory configuration functions -------------------------*/
+
+void mpc_init_cfg(void)
+{
+ Driver_SRAM1_MPC.Initialize();
+ Driver_SRAM1_MPC.ConfigRegion(NS_PARTITION_START,
+ NS_PARTITION_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+
+ Driver_SRAM2_MPC.Initialize();
+ Driver_SRAM2_MPC.ConfigRegion(NS_DATA_START, NS_DATA_LIMIT,
+ ARM_MPC_ATTR_NONSECURE);
+
+ /* Lock down the MPC configuration */
+ Driver_SRAM1_MPC.LockDown();
+ Driver_SRAM2_MPC.LockDown();
+
+ /* Add barriers to assure the MPC configuration is done before continue
+ * the execution. */
+ __DSB();
+ __ISB();
+}
+
+/*------------------- PPC configuration functions -------------------------*/
+
+void ppc_init_cfg(void)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ struct nspctrl_def* nspctrl = CMSDK_NSPCTRL;
+
+ /* Grant non-secure access to peripherals in the PPC0
+ * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1) */
+ spctrl->apbnsppc0 |= (1U << CMSDK_TIMER0_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_TIMER1_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_DTIMER_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_MHU0_APB_PPC_POS);
+ spctrl->apbnsppc0 |= (1U << CMSDK_MHU1_APB_PPC_POS);
+ /* Grant non-secure access to S32K Timer in PPC1*/
+ spctrl->apbnsppc1 |= (1U << CMSDK_S32K_TIMER_PPC_POS);
+ /* Grant non-secure access for APB peripherals on EXP1 */
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI0_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI1_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI2_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI3_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_SPI4_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART0_APB_PPC_POS);
+ /* Do not do it for UART1 as it's a Secure peripheral */
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART2_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART3_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_UART4_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C0_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C1_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C2_APB_PPC_POS);
+ spctrl->apbnsppcexp1 |= (1U << CMSDK_I2C3_APB_PPC_POS);
+ /* Grant non-secure access for APB peripherals on EXP2 */
+ spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_SCC_PPC_POS);
+ spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_AUDIO_PPC_POS);
+ spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_IO_PPC_POS);
+ /* Grant non-secure access for AHB peripherals on PPC0 */
+ spctrl->ahbnsppc0 |= (1U << CMSDK_VGA_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO0_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO1_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO2_PPC_POS);
+ spctrl->ahbnsppc0 |= (1U << CMSDK_GPIO3_PPC_POS);
+
+ /* Grant non-secure access to all peripherals on AHB EXP:
+ * The SSE-200 doesn't have any peripheral connected to
+ * the AHB expansions. But the SIE-200 has peripherals,
+ * in particular the Ethernet driver on EXP1. Make sure
+ * that all possible peripherals are enabled by default
+ */
+ spctrl->ahbnsppcexp0 = 0xFFFFFFFF;
+ spctrl->ahbnsppcexp1 = 0xFFFFFFFF;
+ spctrl->ahbnsppcexp2 = 0xFFFFFFFF;
+ spctrl->ahbnsppcexp3 = 0xFFFFFFFF;
+
+ /* in NS, grant un-privileged for UART0 */
+ nspctrl->apbnspppcexp1 |= (1U << CMSDK_UART0_APB_PPC_POS);
+
+ /* in NS, grant un-privileged access for LEDs */
+ nspctrl->apbnspppcexp2 |= (1U << CMSDK_FPGA_SCC_PPC_POS);
+ nspctrl->apbnspppcexp2 |= (1U << CMSDK_FPGA_IO_PPC_POS);
+
+ /* Configure the response to a security violation as a
+ * bus error instead of RAZ/WI */
+ spctrl->secrespcfg |= 1U;
+}
+
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t pos)
+{
+ /* Clear NS flag for peripheral to prevent NS access */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbnsppc0))[bank] |= (1U << pos);
+}
+
+void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t pos)
+{
+ /* Clear NS flag for peripheral to prevent NS access */
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbnsppc0))[bank] &= ~(1U << pos);
+}
+
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbspppc0))[bank] |= (1U << pos);
+}
+
+void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ ((uint32_t*)&(spctrl->ahbspppc0))[bank] &= ~(1U << pos);
+}
+
+void ppc_clear_irq(void)
+{
+ struct spctrl_def* spctrl = CMSDK_SPCTRL;
+ /* Clear APC PPC EXP2 IRQ */
+ spctrl->secppcintclr |= CMSDK_APB_PPCEXP2_INT_POS_MASK;
+}
diff --git a/platform/ext/target/mps2/an519/target_cfg.h b/platform/ext/target/mps2/an519/target_cfg.h
new file mode 100644
index 0000000..d590cfe
--- /dev/null
+++ b/platform/ext/target/mps2/an519/target_cfg.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SSE200_TARGET_CFG_H__
+#define __SSE200_TARGET_CFG_H__
+
+/**
+ * \brief Defines the word offsets of Slave Peripheral Protection Controller
+ * Registers
+ */
+enum ppc_bank_e
+{
+ PPC_SP_AHB_PPC0 = 0,
+ PPC_SP_RES0,
+ PPC_SP_RES1,
+ PPC_SP_RES2,
+ PPC_SP_AHB_PPC_EXP0,
+ PPC_SP_AHB_PPC_EXP1,
+ PPC_SP_AHB_PPC_EXP2,
+ PPC_SP_AHB_PPC_EXP3,
+ PPC_SP_APB_PPC0,
+ PPC_SP_APB_PPC1,
+ PPC_SP_RES3,
+ PPC_SP_RES4,
+ PPC_SP_APB_PPC_EXP0,
+ PPC_SP_APB_PPC_EXP1,
+ PPC_SP_APB_PPC_EXP2,
+ PPC_SP_APB_PPC_EXP3,
+};
+
+/**
+ * \brief Configures non-secure code.
+ */
+void configure_ns_code(void);
+
+/**
+ * \brief Jumps to non-secure code.
+ */
+void jump_to_ns_code(void);
+
+/**
+ * \brief BusFault, UsageFault, MemManageFault and SecureFault
+ * are not present on AN519 so the body of this function
+ * is empty
+ */
+void enable_fault_handlers(void);
+
+/**
+ * \brief Configures all external interrupts to target the
+ * NS state, apart for the ones associated to secure
+ * peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_target_state_cfg();
+
+/**
+ * \brief This function enable the interrupts associated
+ * to the secure peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_enable();
+
+/**
+ * \brief Configures the Memory Protection Controller.
+ */
+void mpc_init_cfg(void);
+
+/**
+ * \brief Configures the Peripheral Protection Controller.
+ */
+void ppc_init_cfg(void);
+
+/**
+ * \brief Restict access to peripheral to secure
+ */
+void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Allow non-secure access to peripheral
+ */
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Enable secure unprivileged access to peripheral
+ */
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clear secure unprivileged access to peripheral
+ */
+void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clears PPC interrupt.
+ */
+void ppc_clear_irq(void);
+
+/**
+ * \brief Configures SAU and IDAU.
+ */
+void sau_and_idau_cfg(void);
+
+
+#endif /* __SSE200_TARGET_CFG_H__ */
diff --git a/readme.md b/readme.md
index 2439980..ba72698 100644
--- a/readme.md
+++ b/readme.md
@@ -73,8 +73,10 @@
Current release has been tested on
* Cortex M33 based SSE-200 system -
- * [FPGA running on MPS2 board.](https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-systems/mps2)
+ * [FPGA image loaded on MPS2 board.](https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-systems/mps2)
* [Fast model FVP_MPS2_AEMv8M.](https://developer.arm.com/products/system-design/fixed-virtual-platforms)
+* Cortex M23 based IoT Kit system -
+ * [FPGA image loaded on MPS2 board.](https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-systems/mps2)
## Getting Started
diff --git a/secure_fw/core/tfm_handler.c b/secure_fw/core/tfm_handler.c
index 6c3130c..aebf2dd 100644
--- a/secure_fw/core/tfm_handler.c
+++ b/secure_fw/core/tfm_handler.c
@@ -55,6 +55,7 @@
uint32_t RETPSR;
} tfm_fault_context;
+#if defined(__ARM_ARCH_8M_MAIN__)
/**
* \brief Overwrites default Secure fault handler.
*/
@@ -86,28 +87,32 @@
memcpy(&tfm_fault_context, (const void *)sp, sizeof(tfm_fault_context));
}
- /*
- * FixMe: Due to an issue on the FVP, the MPC fault doesn't trigger a
- * MPC IRQ which is handled by the MPC_handler.
- * In the FVP, the MPC fault is handled by the SecureFault_handler.
- */
-
- if (Driver_SRAM1_MPC.InterruptState() != 0) {
- /* Clear MPC interrupt flag and pending MPC IRQ */
- Driver_SRAM1_MPC.ClearInterrupt();
- NVIC_ClearPendingIRQ(MPC_IRQn);
- /* Print fault message and block execution */
- LOG_MSG("Oops... MPC/Secure fault!!!");
- while (1) {
- ;
- }
- } else {
- LOG_MSG("Oops... Secure fault!!! You're not going anywhere!");
- while (1) {
- ;
- }
+ LOG_MSG("Oops... Secure fault!!! You're not going anywhere!");
+ while (1) {
+ ;
}
}
+#elif defined(__ARM_ARCH_8M_BASE__)
+/**
+ * \brief Overwrites default Hard fault handler.
+ *
+ * In case of a baseline implementation fault conditions that would generate a
+ * SecureFault in a mainline implementation instead generate a Secure HardFault.
+ */
+void HardFault_Handler(void)
+{
+ /* In a baseline implementation there is no way, to find out whether this is
+ * a hard fault triggered directly, or another fault that has been
+ * escalated.
+ */
+ while (1) {
+ ;
+ }
+}
+#else
+#error "Unsupported ARM Architecture."
+#endif
+
void MPC_Handler(void)
{