commit 0101fd3766913ff9786b95568cbc69cf58c1946b
author Mate Toth-Pal <mate.toth-pal@arm.com> Tue Mar 26 10:19:53 2019 +0100
committer Ken Liu <ken.liu@arm.com> Fri Mar 29 06:37:20 2019 +0000
tree 49334ca7d2eb2977f938d68480778f73ba8704ba
parent 1d95e5a0f08f68c38a351f0eab2ef8bfc291b058

Platform: Fix CoreIPC build for MUSCA_* boards

Remove Core Test from CoreIPC build config and fix section symbols
for MUSCA_B1

Change-Id: I148cf0a96c6921648c84e1d016b9350f578cd054
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>

ConfigCoreIPC.cmake

diff --git a/ConfigCoreIPC.cmake b/ConfigCoreIPC.cmake
index b87a834..545fd49 100644
--- a/ConfigCoreIPC.cmake
+++ b/ConfigCoreIPC.cmake
@@ -27,7 +27,7 @@
 #various project specific settings (e.g. what files to build, macro
 #definitions) based on these.
 set (REGRESSION False)
-set (CORE_TEST True)
+set (CORE_TEST False)
 set (CORE_IPC True)
 
 # TF-M isolation level: 1..3

platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld

diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld
index 3369b47..4bd2f06 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld
@@ -822,8 +822,8 @@
         . = ALIGN(4);
 
     } > RAM AT> FLASH
-    Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
-    Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
+    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
+    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
 
     .TFM_BSS : ALIGN(4)
     {
@@ -833,8 +833,8 @@
         . = ALIGN(4);
         __bss_end__ = .;
     } > RAM AT> FLASH
-    Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
-    Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
+    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
+    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
 
     Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);
     Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);

platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template

diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template
index 73655de..ea0fc6a 100644
--- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template
+++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template
@@ -421,8 +421,8 @@
         . = ALIGN(4);
 
     } > RAM AT> FLASH
-    Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
-    Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
+    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
+    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
 
     .TFM_BSS : ALIGN(4)
     {
@@ -432,8 +432,8 @@
         . = ALIGN(4);
         __bss_end__ = .;
     } > RAM AT> FLASH
-    Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
-    Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
+    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
+    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
 
     Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA);
     Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS);