- e86efe4 Merge changes I1dfb95aa,I9eb61c48 into integration by Yann Gautier · 4 months ago
- 204d5e6 feat(intel): implementation of SiPSVC-V3 protocol framework by Sieu Mun Tang · 5 months ago
- d1c58d8 feat(intel): provide atf build version via smc call by Girisha Dengi · 8 months ago
- 646a9a1 fix(intel): update warm reset routine and bootscratch register usage by Jit Loon Lim · 8 months ago
- 2c878eb Merge "feat(intel): add build option for boot source" into integration by Mark Dykes · 9 months ago
- beba204 fix(intel): refactor SDMMC driver for Altera products by Sieu Mun Tang · 10 months ago
- ef8b05f feat(intel): add build option for boot source by Sieu Mun Tang · 10 months ago
- 57c20e2 Merge "fix(intel): correct macro naming" into integration by Mark Dykes · 10 months ago
- 815245e fix(intel): correct macro naming by Sieu Mun Tang · 10 months ago
- 1838a39 fix(intel): update all the platforms hand-off data offset value by Sieu Mun Tang · 10 months ago
- f29765f fix(intel): update preloaded_bl33_base for legacy product by Sieu Mun Tang · 10 months ago
- b3d2850 fix(intel): update Agilex5 BL2 init flow and other misc changes by Sieu Mun Tang · 11 months ago
- 51ff56e Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration by Sandrine Bailleux · 1 year, 7 months ago
- 9c65344 Merge changes Id85b2541,I4d253e2f into integration by Sandrine Bailleux · 1 year, 7 months ago
- a72f86a fix(intel): update system counter back to 400MHz by Sieu Mun Tang · 1 year, 8 months ago
- d0e400b fix(intel): revert back to use L4 clock by Sieu Mun Tang · 1 year, 8 months ago
- 6cf16b3 feat(intel): support QSPI ECC Linux for N5X by Jit Loon Lim · 1 year, 10 months ago
- 9118bdf Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration by Sandrine Bailleux · 1 year, 8 months ago
- 92f8e89 Merge "fix(intel): bl31 overwrite OCRAM configuration" into integration by Sandrine Bailleux · 1 year, 8 months ago
- 32a87d4 feat(intel): enable SDMMC frontdoor load for ATF->Linux by Jit Loon Lim · 1 year, 10 months ago
- 150d2be fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · 2 years, 1 month ago
- cfbac59 fix(intel): bl31 overwrite OCRAM configuration by Jit Loon Lim · 1 year, 10 months ago
- 47ca43b feat(intel): restructure watchdog by Sieu Mun Tang · 2 years, 2 months ago
- 13ff6e9 chore: remove MULTI_CONSOLE_API references by Michal Simek · 1 year, 11 months ago
- 7931d33 feat(intel): platform enablement for Agilex5 SoC FPGA by Jit Loon Lim · 2 years, 3 months ago
- b653f3c feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · 2 years, 3 months ago
- 1b491ee fix(tree): correct some typos by Elyes Haouas · 2 years, 6 months ago
- 5f06bff fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 2 years, 8 months ago
- 02a9d70 feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 3 years, 1 month ago
- 42d4d3b refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years, 9 months ago
- 8e53b2f fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 3 years, 1 month ago
- ad47f14 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 3 years, 3 months ago
- f0f631f Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 3 years, 3 months ago
- f65bdf3 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 3 years, 4 months ago
- 11f4f03 feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 3 years, 3 months ago
- 447e699 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · 4 years ago
- 39f262c build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 4 years, 3 months ago
- f571183 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 3 years, 5 months ago
- c703d75 fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 3 years, 5 months ago
- 1f1c020 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 5 years ago
- 325eb35 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 3 years, 5 months ago