| Nicolas Le Bayon | dcb00b1 | 2023-09-29 09:58:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2025 - All Rights Reserved |
| 4 | * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _DT_BINDINGS_STM32MP21_RESET_H_ |
| 8 | #define _DT_BINDINGS_STM32MP21_RESET_H_ |
| 9 | |
| 10 | /* TF-A use a binding required by driver, not aligned with Linux*/ |
| 11 | |
| 12 | #define SYS_R 8192 |
| 13 | #define C1_R 8224 |
| 14 | #define C2_R 8288 |
| 15 | #define C2_HOLDBOOT_R 8608 |
| 16 | #define C1_HOLDBOOT_R 8609 |
| 17 | #define VSW_R 8672 |
| 18 | #define C1MS_R 8840 |
| 19 | #define IWDG2_KER_R 9106 |
| 20 | #define IWDG4_KER_R 9234 |
| 21 | #define DDRCP_R 9888 |
| 22 | #define DDRCAPB_R 9920 |
| 23 | #define DDRPHYCAPB_R 9952 |
| 24 | #define DDRCFG_R 10016 |
| 25 | #define DDR_R 10048 |
| 26 | #define OSPI1_R 10400 |
| 27 | #define OSPI1DLL_R 10416 |
| 28 | #define FMC_R 10464 |
| 29 | #define DBG_R 10508 |
| 30 | #define GPIOA_R 10592 |
| 31 | #define GPIOB_R 10624 |
| 32 | #define GPIOC_R 10656 |
| 33 | #define GPIOD_R 10688 |
| 34 | #define GPIOE_R 10720 |
| 35 | #define GPIOF_R 10752 |
| 36 | #define GPIOG_R 10784 |
| 37 | #define GPIOH_R 10816 |
| 38 | #define GPIOI_R 10848 |
| 39 | #define GPIOZ_R 10944 |
| 40 | #define HPDMA1_R 10976 |
| 41 | #define HPDMA2_R 11008 |
| 42 | #define HPDMA3_R 11040 |
| 43 | #define IPCC1_R 11136 |
| 44 | #define SSMOD_R 11392 |
| 45 | #define TIM1_R 14336 |
| 46 | #define TIM2_R 14368 |
| 47 | #define TIM3_R 14400 |
| 48 | #define TIM4_R 14432 |
| 49 | #define TIM5_R 14464 |
| 50 | #define TIM6_R 14496 |
| 51 | #define TIM7_R 14528 |
| 52 | #define TIM8_R 14560 |
| 53 | #define TIM10_R 14592 |
| 54 | #define TIM11_R 14624 |
| 55 | #define TIM12_R 14656 |
| 56 | #define TIM13_R 14688 |
| 57 | #define TIM14_R 14720 |
| 58 | #define TIM15_R 14752 |
| 59 | #define TIM16_R 14784 |
| 60 | #define TIM17_R 14816 |
| 61 | #define LPTIM1_R 14880 |
| 62 | #define LPTIM2_R 14912 |
| 63 | #define LPTIM3_R 14944 |
| 64 | #define LPTIM4_R 14976 |
| 65 | #define LPTIM5_R 15008 |
| 66 | #define SPI1_R 15040 |
| 67 | #define SPI2_R 15072 |
| 68 | #define SPI3_R 15104 |
| 69 | #define SPI4_R 15136 |
| 70 | #define SPI5_R 15168 |
| 71 | #define SPI6_R 15200 |
| 72 | #define SPDIFRX_R 15296 |
| 73 | #define USART1_R 15328 |
| 74 | #define USART2_R 15360 |
| 75 | #define USART3_R 15392 |
| 76 | #define UART4_R 15424 |
| 77 | #define UART5_R 15456 |
| 78 | #define USART6_R 15488 |
| 79 | #define UART7_R 15520 |
| 80 | #define LPUART1_R 15616 |
| 81 | #define I2C1_R 15648 |
| 82 | #define I2C2_R 15680 |
| 83 | #define I2C3_R 15712 |
| 84 | #define SAI1_R 15904 |
| 85 | #define SAI2_R 15936 |
| 86 | #define SAI3_R 15968 |
| 87 | #define SAI4_R 16000 |
| 88 | #define MDF1_R 16064 |
| 89 | #define ADF1_R 16096 |
| 90 | #define FDCAN_R 16128 |
| 91 | #define HDP_R 16160 |
| 92 | #define ADC1_R 16192 |
| 93 | #define ADC2_R 16224 |
| 94 | #define ETH1_R 16256 |
| 95 | #define ETH2_R 16288 |
| 96 | #define USBH_R 16352 |
| 97 | #define USB2PHY1_R 16384 |
| 98 | #define OTG_R 16448 |
| 99 | #define USB2PHY2_R 16480 |
| 100 | #define SDMMC1_R 16768 |
| 101 | #define SDMMC1DLL_R 16784 |
| 102 | #define SDMMC2_R 16800 |
| 103 | #define SDMMC2DLL_R 16816 |
| 104 | #define SDMMC3_R 16832 |
| 105 | #define SDMMC3DLL_R 16848 |
| 106 | #define LTDC_R 16896 |
| 107 | #define CSI_R 17088 |
| 108 | #define DCMIPP_R 17120 |
| 109 | #define DCMIPSSI_R 17152 |
| 110 | #define RNG1_R 17280 |
| 111 | #define RNG2_R 17312 |
| 112 | #define PKA_R 17344 |
| 113 | #define SAES_R 17376 |
| 114 | #define HASH1_R 17408 |
| 115 | #define HASH2_R 17440 |
| 116 | #define CRYP1_R 17472 |
| 117 | #define CRYP2_R 17504 |
| 118 | #define WWDG1_R 17696 |
| 119 | #define VREF_R 17760 |
| 120 | #define DTS_R 17792 |
| 121 | #define CRC_R 17824 |
| 122 | #define SERC_R 17856 |
| 123 | #define I3C1_R 17984 |
| 124 | #define I3C2_R 18016 |
| 125 | #define I3C3_R 18048 |
| 126 | |
| 127 | #define RST_SCMI_C1_R 0 |
| 128 | #define RST_SCMI_C2_R 1 |
| 129 | #define RST_SCMI_C1_HOLDBOOT_R 2 |
| 130 | #define RST_SCMI_C2_HOLDBOOT_R 3 |
| 131 | #define RST_SCMI_FMC 4 |
| 132 | #define RST_SCMI_OSPI1 5 |
| 133 | #define RST_SCMI_OSPI1DLL 6 |
| 134 | |
| 135 | #endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */ |