| Varun Wadekar | 3a8c55f | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 1 | /* |
| Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 3a8c55f | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 3 | * |
| dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | 3a8c55f | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __DENVER_H__ |
| 8 | #define __DENVER_H__ |
| 9 | |
| Varun Wadekar | e956e22 | 2015-09-03 17:15:06 +0530 | [diff] [blame] | 10 | /* MIDR values for Denver */ |
| Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 11 | #define DENVER_MIDR_PN0 U(0x4E0F0000) |
| 12 | #define DENVER_MIDR_PN1 U(0x4E0F0010) |
| 13 | #define DENVER_MIDR_PN2 U(0x4E0F0020) |
| 14 | #define DENVER_MIDR_PN3 U(0x4E0F0030) |
| 15 | #define DENVER_MIDR_PN4 U(0x4E0F0040) |
| Varun Wadekar | e956e22 | 2015-09-03 17:15:06 +0530 | [diff] [blame] | 16 | |
| 17 | /* Implementer code in the MIDR register */ |
| Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 18 | #define DENVER_IMPL U(0x4E) |
| Varun Wadekar | 3a8c55f | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 19 | |
| 20 | /* CPU state ids - implementation defined */ |
| Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 21 | #define DENVER_CPU_STATE_POWER_DOWN U(0x3) |
| Varun Wadekar | 3a8c55f | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 22 | |
| Varun Wadekar | 9f1c5dd | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 23 | #ifndef __ASSEMBLY__ |
| 24 | |
| 25 | /* Disable Dynamic Code Optimisation */ |
| 26 | void denver_disable_dco(void); |
| 27 | |
| 28 | #endif |
| 29 | |
| Varun Wadekar | 3a8c55f | 2015-07-14 17:11:20 +0530 | [diff] [blame] | 30 | #endif /* __DENVER_H__ */ |