Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | c367b75 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 2 | * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Masahiro Yamada | 665e71b | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 7 | #include <common/bl_common.ld.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
| 10 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 11 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 9f98aa1 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 12 | ENTRY(bl31_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 13 | |
| 14 | |
| 15 | MEMORY { |
Juan Castillo | d7fbf13 | 2014-09-16 10:40:35 +0100 | [diff] [blame] | 16 | RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 17 | #if SEPARATE_NOBITS_REGION |
| 18 | NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE |
| 19 | #else |
| 20 | #define NOBITS RAM |
| 21 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 22 | } |
| 23 | |
Caesar Wang | ec69356 | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 24 | #ifdef PLAT_EXTRA_LD_SCRIPT |
| 25 | #include <plat.ld.S> |
| 26 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 27 | |
| 28 | SECTIONS |
| 29 | { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 30 | . = BL31_BASE; |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 31 | ASSERT(. == ALIGN(PAGE_SIZE), |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 32 | "BL31_BASE address is not aligned on a page boundary.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 33 | |
Soby Mathew | 931f7c6 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 34 | __BL31_START__ = .; |
| 35 | |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 36 | #if SEPARATE_CODE_AND_RODATA |
| 37 | .text . : { |
| 38 | __TEXT_START__ = .; |
| 39 | *bl31_entrypoint.o(.text*) |
Samuel Holland | ebd6efa | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 40 | *(SORT_BY_ALIGNMENT(.text*)) |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 41 | *(.vectors) |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 42 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 43 | __TEXT_END__ = .; |
| 44 | } >RAM |
| 45 | |
| 46 | .rodata . : { |
| 47 | __RODATA_START__ = .; |
Samuel Holland | ebd6efa | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 48 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 49 | |
Masahiro Yamada | 9fb288a | 2020-03-26 10:51:39 +0900 | [diff] [blame^] | 50 | RT_SVC_DESCS |
| 51 | FCONF_POPULATOR |
| 52 | PMF_SVC_DESCS |
| 53 | CPU_OPS |
| 54 | GOT |
Soby Mathew | 931f7c6 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 55 | |
Jeenu Viswambharan | 8e743bc | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 56 | /* Place pubsub sections for events */ |
| 57 | . = ALIGN(8); |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 58 | #include <lib/el3_runtime/pubsub_events.h> |
Jeenu Viswambharan | 8e743bc | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 59 | |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 60 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 61 | __RODATA_END__ = .; |
| 62 | } >RAM |
| 63 | #else |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 64 | ro . : { |
| 65 | __RO_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 66 | *bl31_entrypoint.o(.text*) |
Samuel Holland | ebd6efa | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 67 | *(SORT_BY_ALIGNMENT(.text*)) |
| 68 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 69 | |
Masahiro Yamada | 9fb288a | 2020-03-26 10:51:39 +0900 | [diff] [blame^] | 70 | RT_SVC_DESCS |
| 71 | FCONF_POPULATOR |
| 72 | PMF_SVC_DESCS |
| 73 | CPU_OPS |
| 74 | GOT |
Soby Mathew | 5bfac4f | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 75 | |
Jeenu Viswambharan | 8e743bc | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 76 | /* Place pubsub sections for events */ |
| 77 | . = ALIGN(8); |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 78 | #include <lib/el3_runtime/pubsub_events.h> |
Jeenu Viswambharan | 8e743bc | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 79 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 80 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 81 | __RO_END_UNALIGNED__ = .; |
| 82 | /* |
| 83 | * Memory page(s) mapped to this section will be marked as read-only, |
| 84 | * executable. No RW data from the next section must creep in. |
| 85 | * Ensure the rest of the current memory page is unused. |
| 86 | */ |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 87 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 88 | __RO_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 89 | } >RAM |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 90 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 91 | |
Soby Mathew | 9b47684 | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 92 | ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, |
| 93 | "cpu_ops not defined for this platform.") |
| 94 | |
Paul Beesley | 538b002 | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 95 | #if SPM_MM |
Ard Biesheuvel | 32e8353 | 2019-01-06 10:07:24 +0100 | [diff] [blame] | 96 | #ifndef SPM_SHIM_EXCEPTIONS_VMA |
| 97 | #define SPM_SHIM_EXCEPTIONS_VMA RAM |
| 98 | #endif |
| 99 | |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 100 | /* |
| 101 | * Exception vectors of the SPM shim layer. They must be aligned to a 2K |
| 102 | * address, but we need to place them in a separate page so that we can set |
| 103 | * individual permissions to them, so the actual alignment needed is 4K. |
| 104 | * |
| 105 | * There's no need to include this into the RO section of BL31 because it |
| 106 | * doesn't need to be accessed by BL31. |
| 107 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 108 | spm_shim_exceptions : ALIGN(PAGE_SIZE) { |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 109 | __SPM_SHIM_EXCEPTIONS_START__ = .; |
| 110 | *(.spm_shim_exceptions) |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 111 | . = ALIGN(PAGE_SIZE); |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 112 | __SPM_SHIM_EXCEPTIONS_END__ = .; |
Ard Biesheuvel | 32e8353 | 2019-01-06 10:07:24 +0100 | [diff] [blame] | 113 | } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM |
| 114 | |
| 115 | PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions)); |
| 116 | . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions); |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 117 | #endif |
| 118 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 119 | /* |
| 120 | * Define a linker symbol to mark start of the RW memory area for this |
| 121 | * image. |
| 122 | */ |
| 123 | __RW_START__ = . ; |
| 124 | |
Douglas Raillard | 51faada | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 125 | /* |
| 126 | * .data must be placed at a lower address than the stacks if the stack |
| 127 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 128 | * section can be placed independently of the main .data section. |
| 129 | */ |
| 130 | .data . : { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 131 | __DATA_START__ = .; |
Samuel Holland | ebd6efa | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 132 | *(SORT_BY_ALIGNMENT(.data*)) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 133 | __DATA_END__ = .; |
| 134 | } >RAM |
| 135 | |
Soby Mathew | 931f7c6 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 136 | /* |
| 137 | * .rela.dyn needs to come after .data for the read-elf utility to parse |
Soby Mathew | 5bfac4f | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 138 | * this section correctly. Ensure 8-byte alignment so that the fields of |
| 139 | * RELA data structure are aligned. |
Soby Mathew | 931f7c6 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 140 | */ |
Soby Mathew | 5bfac4f | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 141 | . = ALIGN(8); |
Soby Mathew | 931f7c6 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 142 | __RELA_START__ = .; |
| 143 | .rela.dyn . : { |
| 144 | } >RAM |
| 145 | __RELA_END__ = .; |
| 146 | |
Sandrine Bailleux | a1b6db6 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 147 | #ifdef BL31_PROGBITS_LIMIT |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 148 | ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") |
Sandrine Bailleux | a1b6db6 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 149 | #endif |
| 150 | |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 151 | #if SEPARATE_NOBITS_REGION |
| 152 | /* |
| 153 | * Define a linker symbol to mark end of the RW memory area for this |
| 154 | * image. |
| 155 | */ |
Madhukar Pappireddy | c367b75 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 156 | . = ALIGN(PAGE_SIZE); |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 157 | __RW_END__ = .; |
| 158 | __BL31_END__ = .; |
| 159 | |
| 160 | ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") |
| 161 | |
| 162 | . = BL31_NOBITS_BASE; |
| 163 | ASSERT(. == ALIGN(PAGE_SIZE), |
| 164 | "BL31 NOBITS base address is not aligned on a page boundary.") |
| 165 | |
| 166 | __NOBITS_START__ = .; |
| 167 | #endif |
| 168 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 169 | stacks (NOLOAD) : { |
| 170 | __STACKS_START__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | *(tzfw_normal_stacks) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 172 | __STACKS_END__ = .; |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 173 | } >NOBITS |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 174 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 175 | /* |
| 176 | * The .bss section gets initialised to 0 at runtime. |
Douglas Raillard | 308d359 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 177 | * Its base address should be 16-byte aligned for better performance of the |
| 178 | * zero-initialization code. |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 179 | */ |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 180 | .bss (NOLOAD) : ALIGN(16) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 181 | __BSS_START__ = .; |
Samuel Holland | ebd6efa | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 182 | *(SORT_BY_ALIGNMENT(.bss*)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 183 | *(COMMON) |
Masahiro Yamada | 9fb288a | 2020-03-26 10:51:39 +0900 | [diff] [blame^] | 184 | BAKERY_LOCK_NORMAL |
| 185 | PMF_TIMESTAMP |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 186 | __BSS_END__ = .; |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 187 | } >NOBITS |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 188 | |
Masahiro Yamada | 665e71b | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 189 | XLAT_TABLE_SECTION >NOBITS |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 190 | |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 191 | #if USE_COHERENT_MEM |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 192 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 193 | * The base address of the coherent memory section must be page-aligned (4K) |
| 194 | * to guarantee that the coherent data are stored on their own pages and |
| 195 | * are not mixed with normal data. This is required to set up the correct |
| 196 | * memory attributes for the coherent data page tables. |
| 197 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 198 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 199 | __COHERENT_RAM_START__ = .; |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 200 | /* |
| 201 | * Bakery locks are stored in coherent memory |
| 202 | * |
| 203 | * Each lock's data is contiguous and fully allocated by the compiler |
| 204 | */ |
| 205 | *(bakery_lock) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 206 | *(tzfw_coherent_mem) |
| 207 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 208 | /* |
| 209 | * Memory page(s) mapped to this section will be marked |
| 210 | * as device memory. No other unexpected data must creep in. |
| 211 | * Ensure the rest of the current memory page is unused. |
| 212 | */ |
Roberto Vargas | 5629b2b | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 213 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 214 | __COHERENT_RAM_END__ = .; |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 215 | } >NOBITS |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 216 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 218 | #if SEPARATE_NOBITS_REGION |
| 219 | /* |
| 220 | * Define a linker symbol to mark end of the NOBITS memory area for this |
| 221 | * image. |
| 222 | */ |
| 223 | __NOBITS_END__ = .; |
| 224 | |
| 225 | ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.") |
| 226 | #else |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 227 | /* |
| 228 | * Define a linker symbol to mark end of the RW memory area for this |
| 229 | * image. |
| 230 | */ |
| 231 | __RW_END__ = .; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 232 | __BL31_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 233 | |
Masahiro Yamada | 511046e | 2020-01-17 13:44:50 +0900 | [diff] [blame] | 234 | /DISCARD/ : { |
| 235 | *(.dynsym .dynstr .hash .gnu.hash) |
| 236 | } |
| 237 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 238 | ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") |
Samuel Holland | f8578e6 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 239 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 240 | } |