diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index de85adb..0d6a5dd 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -836,10 +836,22 @@
   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
   CPU. It is fixed in r1p2.
 
+- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3
+  CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
+  of the CPU. It is still open.
+
+- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3
+  CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
+  of the CPU. It is still open.
+
 - ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3
   CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2
   of the CPU and it is still open.
 
+- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3
+  CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of
+  the CPU. It is fixed in r1p2.
+
 For Cortex-X4, the following errata build flags are defined :
 
 - ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4
diff --git a/docs/security_advisories/index.rst b/docs/security_advisories/index.rst
index ad55546..a6fed96 100644
--- a/docs/security_advisories/index.rst
+++ b/docs/security_advisories/index.rst
@@ -16,3 +16,5 @@
    security-advisory-tfv-9.rst
    security-advisory-tfv-10.rst
    security-advisory-tfv-11.rst
+   security-advisory-tfv-12.rst
+   security-advisory-tfv-13.rst
diff --git a/docs/security_advisories/security-advisory-tfv-12.rst b/docs/security_advisories/security-advisory-tfv-12.rst
new file mode 100644
index 0000000..48d2cb8
--- /dev/null
+++ b/docs/security_advisories/security-advisory-tfv-12.rst
@@ -0,0 +1,86 @@
+Advisory TFV-12 (CVE-2024-5660)
+================================
+
++----------------+--------------------------------------------------------------+
+| Title          | When Hardware Page Aggregation (HPA) is enabled memory       |
+|                | accesses may be translated incorrectly.                      |
++================+==============================================================+
+| CVE ID         | `CVE-2024-5660`_                                             |
++----------------+--------------------------------------------------------------+
+| Date           | Reported on 26 Jan 2024                                      |
++----------------+--------------------------------------------------------------+
+| Versions       | TF-A version from v2.2 to v2.12                              |
+| Affected       | LTS releases lts-v2.8.0 to lts-v2.8.26                       |
+|                | LTS releases lts-v2.10.0 to lts-v2.10.10                     |
++----------------+--------------------------------------------------------------+
+| Configurations | Arm CPUs with Hardware Page Aggregation (HPA) running in     |
+| Affected       | environments where a modified, untrusted guest OS may        |
+|                | operate, especially with specific hypervisors.               |
++----------------+--------------------------------------------------------------+
+| Impact         | Potential for a compromised guest OS to attack the host via  |
+|                | HPA mechanism, resulting in possible information disclosure. |
++----------------+--------------------------------------------------------------+
+| Fix Version    | `Gerrit-Patches`_                                            |
++----------------+--------------------------------------------------------------+
+| Credit         | Arm                                                          |
++----------------+--------------------------------------------------------------+
+
+Description
+-----------
+
+A vulnerability has been identified in certain Arm CPUs implementing the
+Hardware Page Aggregation (HPA) feature. In environments utilizing virtualization,
+a specially crafted or compromised guest operating system could exploit this
+vulnerability to affect the host system. This could potentially lead to information
+disclosure depending on the deployment scenario and hypervisor configuration.
+
+The below table lists the CPUs that mitigate against this vulnerability in TF-A.
+
++---------------+
+| **Core**      |
++---------------+
+| Cortex-A77    |
++---------------+
+| Cortex-A78    |
++---------------+
+| Cortex-A78C   |
++---------------+
+| Cortex-A78AE  |
++---------------+
+| Cortex-A710   |
++---------------+
+| Cortex-X1     |
++---------------+
+| Cortex-X2     |
++---------------+
+| Cortex-X3     |
++---------------+
+| Cortex-X4     |
++---------------+
+| Cortex-X925   |
++---------------+
+| Neoverse-V1   |
++---------------+
+| Neoverse-V2   |
++---------------+
+| Neoverse-V3   |
++---------------+
+| Neoverse-N2   |
++---------------+
+
+Mitigation and Recommendations
+------------------------------
+
+Arm recommends following the mitigation steps and configuration changes described in the
+official advisory. The issue is avoided by setting CPUECTLR_EL1[46] to 1 which will
+disable hardware page aggregation.
+
+Users should refer to the latest firmware updates as provided by vendors
+and ensure that HPA-related security mitigations are enabled where applicable.
+
+For further technical information, affected CPUs, and detailed guidance, refer to the
+full `Official Arm Advisory`_.
+
+.. _CVE-2024-5660: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-5660
+.. _Gerrit-Patches: https://review.trustedfirmware.org/q/topic:%22sm/fix_erratum%22
+.. _Official Arm Advisory: https://developer.arm.com/documentation/110324/latest
diff --git a/docs/security_advisories/security-advisory-tfv-13.rst b/docs/security_advisories/security-advisory-tfv-13.rst
new file mode 100644
index 0000000..929e9b8
--- /dev/null
+++ b/docs/security_advisories/security-advisory-tfv-13.rst
@@ -0,0 +1,82 @@
+Advisory TFV-13 (CVE-2024-7881)
+================================
+
++----------------+-----------------------------------------------------------------+
+| Title          | An unprivileged context can trigger a data memory-dependent     |
+|                | prefetch engine to fetch the contents of a privileged location  |
+|                | and consume those contents as an address that is                |
+|                | also dereferenced.                                              |
+|                |                                                                 |
++================+=================================================================+
+| CVE ID         | `CVE-2024-7881`_                                                |
++----------------+-----------------------------------------------------------------+
+| Date           | Reported on 16 August 2024                                      |
++----------------+-----------------------------------------------------------------+
+| Versions       | TF-A version from v2.2 to v2.12                                 |
+| Affected       | LTS releases lts-v2.8.0 to lts-v2.8.28                          |
+|                | LTS releases lts-v2.10.0 to lts-v2.10.12                        |
++----------------+-----------------------------------------------------------------+
+| Configurations | All                                                             |
+| Affected       |                                                                 |
++----------------+-----------------------------------------------------------------+
+| Impact         | Potential leakage of secure world data to normal world.         |
++----------------+-----------------------------------------------------------------+
+| Fix Version    | `Gerrit topic #ar/smccc_arch_wa_4`_                             |
+|                | Also see mitigation guidance in the `Official Arm Advisory`_    |
++----------------+-----------------------------------------------------------------+
+| Credit         | Arm                                                             |
++----------------+-----------------------------------------------------------------+
+
+Description
+-----------
+
+An issue has been identified in some Arm-based CPUs that may allow
+an unprivileged context to trigger a data memory-dependent prefetch engine
+to fetch the contents of a privileged location (for which it
+does not have read permission) and consume those contents as an address
+that is also dereferenced.
+
+The below table lists all the CPUs impacted by this vulnerability and have
+mitigation in TF-A.
+
++----------------------+
+| Core                 |
++----------------------+
+| Cortex-X3            |
++----------------------+
+| Cortex-X4            |
++----------------------+
+| Cortex-X925          |
++----------------------+
+| Neoverse-V2          |
++----------------------+
+| Neoverse-V3          |
++----------------------+
+| Neoverse-V3AE        |
++----------------------+
+
+Mitigation and Recommendations
+------------------------------
+
+Arm recommends following the mitigation steps and configuration changes
+described in the official advisory. The mitigation for CVE-2024-7881 is
+implemented at EL3 and addresses vulnerabilities caused by memory-dependant
+speculative prefetching. This issue is avoided by setting CPUACTLR6_EL1[41]
+to 1, this disables the affected prefetcher.
+
+Arm has updated the SMC Calling Convention spec so that privileged normal world
+software can identify when the issue has been mitigated in
+firmware (SMCCC_ARCH_WORKAROUND_4). Refer to the `SMC Calling Convention
+Specification`_ for more details.
+
+The above workaround is enabled by default (on vulnerable CPUs only).
+Platforms can choose to disable them at compile time if
+they do not require them.
+
+For further technical information, affected CPUs, and detailed guidance,
+refer to the full `Official Arm Advisory`_.
+
+.. _CVE-2024-7881: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-7881
+.. _Gerrit topic #ar/smccc_arch_wa_4: https://review.trustedfirmware.org/q/topic:%22ar/smccc_arch_wa_4%22
+.. _SMC Calling Convention specification: https://developer.arm.com/documentation/den0028/latest
+.. _Official Arm Advisory: https://developer.arm.com/documentation/110326/latest
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 553f6f9..4a61187 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -59,7 +59,7 @@
 	msr	osdlr_el1, x0
 	isb
 
-	apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169, NO_GET_CPU_REV
+	apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169
 
 	dsb	sy
 	ret
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 065a1e4..836f392 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -276,7 +276,7 @@
 	 * ----------------------------------------------------
 	 */
 func cortex_a710_core_pwr_dwn
-	apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV
+	apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
 	apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
 
 	/* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 24c62a7..95202c0 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -511,7 +511,7 @@
 	 */
 	sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
 
-	apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102, NO_GET_CPU_REV
+	apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 82a20ec..09b25e2 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -169,7 +169,7 @@
 	sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
 		CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
 
-	apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV
+	apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index b166823..7623446 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -191,7 +191,7 @@
 func cortex_a78_core_pwr_dwn
 	sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
 
-	apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV
+	apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 19d988e..0349cc5 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -129,7 +129,7 @@
 	 */
 	sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
 
-	apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV
+	apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 8af6867..637d699 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -180,7 +180,7 @@
 	 */
 	sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
 
-	apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV
+	apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
 	isb
 	ret
 endfunc cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index f486a83..a44c12b 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -96,10 +96,28 @@
 
 check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
 
+workaround_reset_start cortex_x3, ERRATUM(3213672), ERRATA_X3_3213672
+	sysreg_bit_set	CORTEX_X3_CPUACTLR_EL1, BIT(36)
+workaround_reset_end cortex_x3, ERRATUM(3213672)
+
+check_erratum_ls cortex_x3, ERRATUM(3213672), CPU_REV(1, 2)
+
+workaround_reset_start cortex_x3, ERRATUM(3692984), ERRATA_X3_3692984
+	sysreg_bit_set	CORTEX_X3_CPUACTLR6_EL1, BIT(41)
+workaround_reset_end cortex_x3, ERRATUM(3692984)
+
+check_erratum_ls cortex_x3, ERRATUM(3692984), CPU_REV(1, 2)
+
 add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769
 
 check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
 
+workaround_reset_start cortex_x3, ERRATUM(3827463), ERRATA_X3_3827463
+	sysreg_bit_set	CORTEX_X3_CPUACTLR_EL1, BIT(1)
+workaround_reset_end cortex_x3, ERRATUM(3827463)
+
+check_erratum_ls cortex_x3, ERRATUM(3827463), CPU_REV(1, 1)
+
 workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	override_vector_table wa_cve_vbar_cortex_x3
@@ -136,7 +154,7 @@
 	 * ----------------------------------------------------
 	 */
 func cortex_x3_core_pwr_dwn
-	apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
+	apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
 	/* ---------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index dddf063..98be17e 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -153,7 +153,7 @@
 	 */
 	sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
 
-	apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
+	apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 4ff7d8f..ba07bd7 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -35,6 +35,7 @@
 
 add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
 
+.global check_erratum_cortex_x925_3701747
 check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
 
 workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index e821ecb..baeb83c 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -240,7 +240,7 @@
 	 */
 	sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
 
-	apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV
+	apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 7d9d7f1..2f053ac 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -274,7 +274,7 @@
 cpu_reset_func_end neoverse_n2
 
 func neoverse_n2_core_pwr_dwn
-	apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV
+	apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
 	apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
 
 	/* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index f975be0..96b52aa 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -253,7 +253,7 @@
 	 * ---------------------------------------------
 	 */
 	sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV
+	apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
 
 	isb
 	ret
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 9526b80..8224f93 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -113,7 +113,7 @@
 	 * ---------------------------------------------------
 	 */
 	sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-	apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
+	apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
 
 	isb
 	ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 42a2651..4bf76f9 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -846,6 +846,19 @@
 # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
 CPU_FLAG_LIST += ERRATA_X3_2779509
 
+# Flag to apply erratum 3213672 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu.
+# It is still open.
+CPU_FLAG_LIST += ERRATA_X3_3213672
+
+# Flag to apply erratum 3692984 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0, r1p1, r1p2 of the Cortex-X3 cpu and is still open.
+CPU_FLAG_LIST += ERRATA_X3_3692984
+
+# Flag to apply erratum 3827463 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu. It is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_3827463
+
 # Flag to apply erratum 2701112 workaround for platforms that do not use an
 # Arm interconnect IP. This erratum applies to revisions r0p0 of the Cortex-X4
 # cpu and is fixed in r0p1.