tree f06629e846961b853c91f308f199037907e24007
parent 114495b5482d88fd85c848a65a54d055c2c3733b
parent 5f06bffa831638fd95d2160209000ef36d2a22ce
author Sandrine Bailleux <sandrine.bailleux@arm.com> 1681741119 +0200
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1681741119 +0200

Merge changes I43a9d83c,Ibfaa47fb into integration

* changes:
  fix(intel): fix Agilex and N5X clock manager to main PLL C0
  feat(intel): implement timer init divider via CPU frequency for N5X