diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
index a2a4082..8efb7cf 100644
--- a/drivers/st/ddr/stm32mp2_ddr_helpers.c
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -363,8 +363,6 @@
 	mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
 		      RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
 
-	/* TODO: check if ddr_sr_exit_loop() is needed here */
-
 	return 0;
 }
 
@@ -390,13 +388,6 @@
 	return ddr_sr_exit_loop();
 }
 
-uint32_t ddr_get_io_calibration_val(void)
-{
-	/* TODO create related service */
-
-	return 0U;
-}
-
 int ddr_sr_entry(bool standby)
 {
 	int ret = -EINVAL;
diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c
index 95f05e7..2b0e317 100644
--- a/drivers/st/ddr/stm32mp2_ram.c
+++ b/drivers/st/ddr/stm32mp2_ram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -142,9 +142,6 @@
 			ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret);
 			panic();
 		}
-
-		/* TODO Restore area overwritten by training */
-		//stm32_restore_ddr_training_area();
 	} else {
 		size_t retsize;
 
diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
index 9329fff..d9bf7ae 100644
--- a/include/drivers/st/stm32mp2_ddr_helpers.h
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,7 +22,6 @@
 void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
 void ddr_wait_lp3_mode(bool state);
 int ddr_sr_exit_loop(void);
-uint32_t ddr_get_io_calibration_val(void);
 int ddr_sr_entry(bool standby);
 int ddr_sr_exit(void);
 enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);