tree 2492dc36586a504788c97a251033ecf1ef67892a
parent 567af710d8e1fa7b874f6643e4671555a60db123
author Bipin Ravi <bipin.ravi@arm.com> 1706218726 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1707296634 +0000

fix(cpus): workaround for Cortex X3 erratum 2641945

Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.

The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
(cherry picked from commit c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b)