Merge "fix(versal-net): use api_id directly without FUNCID_MASK" into integration
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index 7ae98b1..fff86a8 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -144,8 +144,12 @@
- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
| Default: stm32mp157c-ev1.dtb
+- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
+ | default location (end of the first 128MB) is used when absent
- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
| Default: 0 (disabled)
+- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
+ | Default: 0 (disabled)
- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
| Default: 115200
- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst
index a7b5984..a4db17d 100644
--- a/docs/security_advisories/security-advisory-tfv-9.rst
+++ b/docs/security_advisories/security-advisory-tfv-9.rst
@@ -85,7 +85,7 @@
+----------------------+
| Neoverse-V1 |
+----------------------+
-| Neoverse-Demeter |
+| Neoverse-V2 |
+----------------------+
| Neoverse-Poseidon |
+----------------------+
diff --git a/drivers/arm/rss/rss_comms.mk b/drivers/arm/rss/rss_comms.mk
new file mode 100644
index 0000000..8f19a0b
--- /dev/null
+++ b/drivers/arm/rss/rss_comms.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+RSS_COMMS_SOURCES := $(addprefix drivers/arm/rss/, \
+ rss_comms.c \
+ rss_comms_protocol.c \
+ rss_comms_protocol_embed.c \
+ rss_comms_protocol_pointer_access.c \
+ )
+
+RSS_COMMS_SOURCES += $(addprefix drivers/arm/mhu/, \
+ mhu_v2_x.c \
+ mhu_wrapper_v2_x.c \
+ )
+
+PLAT_INCLUDES += -Idrivers/arm/rss \
+ -Idrivers/arm/mhu
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index 80c2f41..01d1420 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -17,7 +17,6 @@
#include <platform_def.h>
-#define DT_UART_COMPAT "st,stm32h7-uart"
/*
* Get the frequency of an oscillator from its name in device tree.
* @param name: oscillator name
diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S
index e467f09..e3e0e67 100644
--- a/drivers/st/uart/aarch32/stm32_console.S
+++ b/drivers/st/uart/aarch32/stm32_console.S
@@ -46,10 +46,16 @@
cmp r0, #0
beq core_init_fail
#if !defined(IMAGE_BL2)
+#if STM32MP_RECONFIGURE_CONSOLE
+ /* UART clock rate is set to 0 in BL32, skip init in that case */
+ cmp r1, #0
+ beq 1f
+#else /* STM32MP_RECONFIGURE_CONSOLE */
/* Skip UART initialization if it is already enabled */
ldr r3, [r0, #USART_CR1]
ands r3, r3, #USART_CR1_UE
bne 1f
+#endif /* STM32MP_RECONFIGURE_CONSOLE */
#endif /* IMAGE_BL2 */
/* Check baud rate and uart clock for sanity */
cmp r1, #0
diff --git a/drivers/st/uart/stm32_uart.c b/drivers/st/uart/stm32_uart.c
index e2e5405..63970c7 100644
--- a/drivers/st/uart/stm32_uart.c
+++ b/drivers/st/uart/stm32_uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,9 @@
#include <string.h>
#include <common/bl_common.h>
+#include <drivers/clk.h>
#include <drivers/delay_timer.h>
+#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_uart.h>
#include <drivers/st/stm32_uart_regs.h>
#include <drivers/st/stm32mp_clkfunc.h>
@@ -106,7 +108,33 @@
{
uint32_t tmpreg;
unsigned long clockfreq;
+ unsigned long int_div;
uint32_t brrtemp;
+ uint32_t over_sampling;
+
+ /*---------------------- USART BRR configuration --------------------*/
+ clockfreq = uart_get_clock_freq(huart);
+ if (clockfreq == 0UL) {
+ return -ENODEV;
+ }
+
+ int_div = clockfreq / init->baud_rate;
+ if (int_div < 16U) {
+ uint32_t usartdiv = uart_div_sampling8(clockfreq,
+ init->baud_rate,
+ init->prescaler);
+
+ brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) |
+ ((usartdiv & USART_BRR_DIV_FRACTION) >> 1);
+ over_sampling = USART_CR1_OVER8;
+ } else {
+ brrtemp = uart_div_sampling16(clockfreq,
+ init->baud_rate,
+ init->prescaler) &
+ (USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA);
+ over_sampling = 0x0U;
+ }
+ mmio_write_32(huart->base + USART_BRR, brrtemp);
/*
* ---------------------- USART CR1 Configuration --------------------
@@ -115,12 +143,12 @@
* - set the M bits according to init->word_length value,
* - set PCE and PS bits according to init->parity value,
* - set TE and RE bits according to init->mode value,
- * - set OVER8 bit according to init->over_sampling value.
+ * - set OVER8 bit according baudrate and clock.
*/
tmpreg = init->word_length |
init->parity |
init->mode |
- init->over_sampling |
+ over_sampling |
init->fifo_mode;
mmio_clrsetbits_32(huart->base + USART_CR1, STM32_UART_CR1_FIELDS, tmpreg);
@@ -161,27 +189,6 @@
mmio_clrsetbits_32(huart->base + USART_PRESC, USART_PRESC_PRESCALER,
init->prescaler);
- /*---------------------- USART BRR configuration --------------------*/
- clockfreq = uart_get_clock_freq(huart);
- if (clockfreq == 0UL) {
- return -ENODEV;
- }
-
- if (init->over_sampling == STM32_UART_OVERSAMPLING_8) {
- uint32_t usartdiv = uart_div_sampling8(clockfreq,
- init->baud_rate,
- init->prescaler);
-
- brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) |
- ((usartdiv & USART_BRR_DIV_FRACTION) >> 1);
- } else {
- brrtemp = uart_div_sampling16(clockfreq,
- init->baud_rate,
- init->prescaler) &
- (USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA);
- }
- mmio_write_32(huart->base + USART_BRR, brrtemp);
-
return 0;
}
@@ -295,12 +302,14 @@
* @param init: UART initialization parameter.
* @retval UART status.
*/
-
int stm32_uart_init(struct stm32_uart_handle_s *huart,
uintptr_t base_addr,
const struct stm32_uart_init_s *init)
{
int ret;
+ int uart_node;
+ int clk;
+ void *fdt = NULL;
if (huart == NULL || init == NULL || base_addr == 0U) {
return -EINVAL;
@@ -308,6 +317,32 @@
huart->base = base_addr;
+ /* Search UART instance in DT */
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ if (fdt == NULL) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ uart_node = dt_match_instance_by_compatible(DT_UART_COMPAT, base_addr);
+ if (uart_node == -FDT_ERR_NOTFOUND) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* Pinctrl initialization */
+ if (dt_set_pinctrl_config(uart_node) != 0) {
+ return -FDT_ERR_BADVALUE;
+ }
+
+ /* Clock initialization */
+ clk = fdt_get_clock_id(uart_node);
+ if (clk < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+ clk_enable(clk);
+
/* Disable the peripheral */
stm32_uart_stop(huart->base);
diff --git a/include/drivers/st/stm32_uart.h b/include/drivers/st/stm32_uart.h
index 212968f..866e158 100644
--- a/include/drivers/st/stm32_uart.h
+++ b/include/drivers/st/stm32_uart.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,10 +34,6 @@
#define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE
#define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
-/* UART over sampling */
-#define STM32_UART_OVERSAMPLING_16 0x00000000U
-#define STM32_UART_OVERSAMPLING_8 USART_CR1_OVER8
-
/* UART prescaler */
#define STM32_UART_PRESCALER_DIV1 0x00000000U
#define STM32_UART_PRESCALER_DIV2 0x00000001U
@@ -112,13 +108,6 @@
* value of @ref STM32_UARTHWCONTROL_*.
*/
- uint32_t over_sampling; /*
- * Specifies whether the over sampling
- * 8 is enabled or disabled.
- * This parameter can be a value of
- * @ref STM32_UART_OVERSAMPLING_*.
- */
-
uint32_t one_bit_sampling; /*
* Specifies whether a single sample
* or three samples' majority vote is
diff --git a/include/lib/cpus/aarch64/neoverse_demeter.h b/include/lib/cpus/aarch64/neoverse_demeter.h
deleted file mode 100644
index f1afae7..0000000
--- a/include/lib/cpus/aarch64/neoverse_demeter.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NEOVERSE_DEMETER_H
-#define NEOVERSE_DEMETER_H
-
-#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0)
-
-/* Neoverse Demeter loop count for CVE-2022-23960 mitigation */
-#define NEOVERSE_DEMETER_BHB_LOOP_COUNT U(132)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* NEOVERSE_DEMETER_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h
new file mode 100644
index 0000000..efb960e
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_v2.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_V2_H
+#define NEOVERSE_V2_H
+
+#define NEOVERSE_V2_MIDR U(0x410FD4F0)
+
+/* Neoverse V2 loop count for CVE-2022-23960 mitigation */
+#define NEOVERSE_V2_BHB_LOOP_COUNT U(132)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_V2_H */
diff --git a/lib/cpus/aarch64/neoverse_demeter.S b/lib/cpus/aarch64/neoverse_demeter.S
deleted file mode 100644
index 41cb4ee..0000000
--- a/lib/cpus/aarch64/neoverse_demeter.S
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <neoverse_demeter.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-#include "wa_cve_2022_23960_bhb_vector.S"
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table NEOVERSE_DEMETER_BHB_LOOP_COUNT, neoverse_demeter
-#endif /* WORKAROUND_CVE_2022_23960 */
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func neoverse_demeter_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc neoverse_demeter_core_pwr_dwn
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_demeter_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse Demeter vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_demeter
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
- isb
- ret
-endfunc neoverse_demeter_reset_func
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse Demeter. Must follow AAPCS.
- */
-func neoverse_demeter_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, neoverse_demeter, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_demeter_errata_report
-#endif
-
- /* ---------------------------------------------
- * This function provides Neoverse Demeter-
- * specific register information for crash
- * reporting. It needs to return with x6
- * pointing to a list of register names in ascii
- * and x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.neoverse_demeter_regs, "aS"
-neoverse_demeter_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func neoverse_demeter_cpu_reg_dump
- adr x6, neoverse_demeter_regs
- mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1
- ret
-endfunc neoverse_demeter_cpu_reg_dump
-
-declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \
- neoverse_demeter_reset_func, \
- neoverse_demeter_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
new file mode 100644
index 0000000..4ea887f
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_v2.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+#include "wa_cve_2022_23960_bhb_vector.S"
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
+#endif /* WORKAROUND_CVE_2022_23960 */
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func neoverse_v2_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_v2_core_pwr_dwn
+
+func check_errata_cve_2022_23960
+#if WORKAROUND_CVE_2022_23960
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
+#endif
+ ret
+endfunc check_errata_cve_2022_23960
+
+func neoverse_v2_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+ /*
+ * The Neoverse V2 vectors are overridden to apply
+ * errata mitigation on exception entry from lower ELs.
+ */
+ adr x0, wa_cve_vbar_neoverse_v2
+ msr vbar_el3, x0
+#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ isb
+ ret
+endfunc neoverse_v2_reset_func
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Neoverse V2. Must follow AAPCS.
+ */
+func neoverse_v2_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
+
+ ldp x8, x30, [sp], #16
+ ret
+endfunc neoverse_v2_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Neoverse V2-
+ * specific register information for crash
+ * reporting. It needs to return with x6
+ * pointing to a list of register names in ascii
+ * and x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_v2_regs, "aS"
+neoverse_v2_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_v2_cpu_reg_dump
+ adr x6, neoverse_v2_regs
+ mrs x8, NEOVERSE_V2_CPUECTLR_EL1
+ ret
+endfunc neoverse_v2_cpu_reg_dump
+
+declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
+ neoverse_v2_reset_func, \
+ neoverse_v2_core_pwr_dwn
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index efcfed8..8d736cc 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -156,25 +156,26 @@
/*******************************************************************************
* This function verifies that the all the other cores in the system have been
* turned OFF and the current CPU is the last running CPU in the system.
- * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
- * otherwise.
+ * Returns true, if the current CPU is the last ON CPU or false otherwise.
******************************************************************************/
-unsigned int psci_is_last_on_cpu(void)
+bool psci_is_last_on_cpu(void)
{
unsigned int cpu_idx, my_idx = plat_my_core_pos();
- for (cpu_idx = 0; cpu_idx < psci_plat_core_count;
- cpu_idx++) {
+ for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
continue;
}
- if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
- return 0;
+ if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) {
+ VERBOSE("core=%u other than current core=%u %s\n",
+ cpu_idx, my_idx, "running in the system");
+ return false;
+ }
}
- return 1;
+ return true;
}
/*******************************************************************************
@@ -1009,11 +1010,11 @@
/* Need to wait for other cores to shutdown */
if (wait_ms != 0U) {
- while ((wait_ms-- != 0U) && (psci_is_last_on_cpu() != 0U)) {
+ while ((wait_ms-- != 0U) && (!psci_is_last_on_cpu())) {
mdelay(1U);
}
- if (psci_is_last_on_cpu() != 0U) {
+ if (!psci_is_last_on_cpu()) {
WARN("Failed to stop all cores!\n");
psci_print_power_domain_map();
return PSCI_E_DENIED;
@@ -1030,48 +1031,22 @@
*
* This API has following differences with psci_is_last_on_cpu
* 1. PSCI states are locked
- * 2. It caters for "forest" topology instead of just "tree"
- * TODO : Revisit both API's and unify them
******************************************************************************/
bool psci_is_last_on_cpu_safe(void)
{
unsigned int this_core = plat_my_core_pos();
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
- unsigned int i = 0;
- /*
- * Traverse the forest of PSCI nodes, nodes with no parents
- * (invalid-nodes) are the root nodes.
- */
- while ((i < PSCI_NUM_NON_CPU_PWR_DOMAINS) &&
- (psci_non_cpu_pd_nodes[i].parent_node ==
- PSCI_PARENT_NODE_INVALID)) {
- psci_get_parent_pwr_domain_nodes(
- psci_non_cpu_pd_nodes[i].cpu_start_idx,
- PLAT_MAX_PWR_LVL, parent_nodes);
+ psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes);
- psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+ psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
- for (unsigned int core = 0U;
- core < psci_non_cpu_pd_nodes[i].ncpus; core++) {
- if (core == this_core) {
- continue;
- }
-
- if (psci_get_aff_info_state_by_idx(core) !=
- AFF_STATE_OFF) {
- psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL,
- parent_nodes);
- VERBOSE("core=%u other than boot core=%u %s\n",
- core, this_core, "running in the system");
-
- return false;
- }
- }
-
+ if (!psci_is_last_on_cpu()) {
psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
- i++;
+ return false;
}
+ psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
return true;
}
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 52a8b8a..a631f3f 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -158,7 +158,7 @@
entry_point_info_t ep;
/* Check if the current CPU is the last ON CPU in the system */
- if (psci_is_last_on_cpu() == 0U)
+ if (!psci_is_last_on_cpu())
return PSCI_E_DENIED;
/* Validate the entry point and get the entry_point_info */
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index caade9c..1901c17 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -294,7 +294,7 @@
unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info);
void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl);
void psci_print_power_domain_map(void);
-unsigned int psci_is_last_on_cpu(void);
+bool psci_is_last_on_cpu(void);
int psci_spd_migrate_info(u_register_t *mpidr);
/*
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 2539712..9c3089a 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -132,7 +132,7 @@
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/neoverse_demeter.S \
+ lib/cpus/aarch64/neoverse_v2.S \
lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a710.S \
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index cfe4e28..9728a08 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -34,7 +34,7 @@
PLAT_INCLUDES += -I${RDN2_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \
- lib/cpus/aarch64/neoverse_demeter.S
+ lib/cpus/aarch64/neoverse_v2.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index 41467f7..223ac3e 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,9 +23,9 @@
/* SID Version values for RD-N2 variants */
#define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6
-/* SID Version values for RD-Edmunds */
-#define RD_EDMUNDS_SID_VER_PART_NUM 0x07F2
-#define RD_EDMUNDS_CONFIG_ID 0x1
+/* SID Version values for RD-V2 */
+#define RD_V2_SID_VER_PART_NUM 0x07F2
+#define RD_V2_CONFIG_ID 0x1
/* Structure containing SGI platform variant information */
typedef struct sgi_platform_info {
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index 7ef7e6f..27cf183 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -79,7 +79,7 @@
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
- sgi_plat_info.platform_id == RD_EDMUNDS_SID_VER_PART_NUM ||
+ sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
panic();
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index eacc4dd..facee0f 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -979,7 +979,7 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- if (data_size >= src_size) {
+ if (data_size > src_size) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 778d4af..79817e6 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -236,7 +236,7 @@
/* copy response data to input buffer if applicable */
ret_resp_len = MBOX_RESP_LEN(mailbox_resp_ctr.payload->header);
- if ((ret_resp_len > 0) && (response == NULL) && resp_len) {
+ if ((ret_resp_len > 0) && (response != NULL) && (resp_len != NULL)) {
if (*resp_len > ret_resp_len) {
*resp_len = ret_resp_len;
}
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index bbfa169..f85db8d 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -574,7 +574,7 @@
goto err;
}
- node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000");
+ node = ret = fdt_add_subnode(fdt, node, "spi@ee200000");
if (ret < 0) {
goto err;
}
diff --git a/plat/st/common/stm32cubeprogrammer_uart.c b/plat/st/common/stm32cubeprogrammer_uart.c
index 46ac9cf..d004dcf 100644
--- a/plat/st/common/stm32cubeprogrammer_uart.c
+++ b/plat/st/common/stm32cubeprogrammer_uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -486,13 +486,12 @@
/* Init UART: 115200, 8bit 1stop parity even and enable FIFO mode */
const struct stm32_uart_init_s init = {
- .baud_rate = U(115200),
+ .baud_rate = STM32MP_UART_BAUDRATE,
.word_length = STM32_UART_WORDLENGTH_9B,
.stop_bits = STM32_UART_STOPBITS_1,
.parity = STM32_UART_PARITY_EVEN,
.hw_flow_control = STM32_UART_HWCONTROL_NONE,
.mode = STM32_UART_MODE_TX_RX,
- .over_sampling = STM32_UART_OVERSAMPLING_16,
.fifo_mode = STM32_UART_FIFOMODE_EN,
};
diff --git a/plat/st/common/stm32cubeprogrammer_usb.c b/plat/st/common/stm32cubeprogrammer_usb.c
index 19a6bba..75e8038 100644
--- a/plat/st/common/stm32cubeprogrammer_usb.c
+++ b/plat/st/common/stm32cubeprogrammer_usb.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
+#include <string.h>
#include <tools_share/firmware_image_package.h>
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index d922d3c..eee983f 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -274,8 +274,11 @@
#if STM32MP_EARLY_CONSOLE
void stm32mp_setup_early_console(void)
{
+#if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE
plat_crash_console_init();
+#endif
set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
+ NOTICE("Early console setup\n");
}
#endif /* STM32MP_EARLY_CONSOLE */
diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h
index 8ecb4c3..fe4ef3d 100644
--- a/plat/st/stm32mp1/include/platform_def.h
+++ b/plat/st/stm32mp1/include/platform_def.h
@@ -103,8 +103,7 @@
#define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE
/* Needed by STM32CubeProgrammer support */
-#define DWL_BUFFER_BASE (STM32MP_DDR_BASE + U(0x08000000))
-#define DWL_BUFFER_SIZE U(0x08000000)
+#define DWL_BUFFER_SIZE U(0x01000000)
/*
* SSBL offset in case it's stored in eMMC boot partition.
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 7203de8..def2898 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -10,6 +10,7 @@
USE_COHERENT_MEM := 0
STM32MP_EARLY_CONSOLE ?= 0
+STM32MP_RECONFIGURE_CONSOLE ?= 0
STM32MP_UART_BAUDRATE ?= 115200
# Allow TF-A to concatenate BL2 & BL32 binaries in a single file,
@@ -121,6 +122,9 @@
STM32MP_USB_PROGRAMMER ?= 0
STM32MP_UART_PROGRAMMER ?= 0
+# Download load address for serial boot devices
+DWL_BUFFER_BASE ?= 0xC7000000
+
# Device tree
ifeq ($(STM32MP13),1)
BL2_DTSI := stm32mp13-bl2.dtsi
@@ -205,6 +209,7 @@
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
+ STM32MP_RECONFIGURE_CONSOLE \
STM32MP_SDMMC \
STM32MP_SPI_NAND \
STM32MP_SPI_NOR \
@@ -225,6 +230,7 @@
$(eval $(call add_defines,\
$(sort \
+ DWL_BUFFER_BASE \
PLAT_PARTITION_MAX_ENTRIES \
PLAT_XLAT_TABLES_DYNAMIC \
STM32_TF_A_COPIES \
@@ -235,6 +241,7 @@
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
+ STM32MP_RECONFIGURE_CONSOLE \
STM32MP_SDMMC \
STM32MP_SPI_NAND \
STM32MP_SPI_NOR \
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index 8106795..325666f 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -40,6 +40,8 @@
******************************************************************************/
void sp_min_plat_fiq_handler(uint32_t id)
{
+ (void)plat_crash_console_init();
+
switch (id & INT_ID_MASK) {
case STM32MP1_IRQ_TZC400:
tzc400_init(STM32MP1_TZC_BASE);
@@ -51,7 +53,7 @@
panic();
break;
default:
- ERROR("SECURE IT handler not define for it : %u", id);
+ ERROR("SECURE IT handler not define for it : %u\n", id);
break;
}
}
@@ -119,6 +121,8 @@
uintptr_t dt_addr = arg1;
#endif
+ stm32mp_setup_early_console();
+
/* Imprecise aborts can be masked in NonSecure */
write_scr(read_scr() | SCR_AW_BIT);
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 116bd5d..a74d58c 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -666,5 +666,6 @@
#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
#endif
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
+#define DT_UART_COMPAT "st,stm32h7-uart"
#endif /* STM32MP1_DEF_H */