Merge "feat(ti): enable power state validation for K3 SoCs" into integration
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index c679344..ec37d9f 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -226,6 +226,28 @@
wfi();
}
+static int k3_validate_power_state(unsigned int power_state, psci_power_state_t *req_state)
+{
+ unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+ unsigned int pstate = psci_get_pstate_type(power_state);
+
+ if (pwr_lvl > PLAT_MAX_PWR_LVL)
+ return PSCI_E_INVALID_PARAMS;
+
+ if (pstate == PSTATE_TYPE_STANDBY) {
+ /*
+ * It's possible to enter standby only on power level 0
+ * Ignore any other power level.
+ */
+ if (pwr_lvl != MPIDR_AFFLVL0)
+ return PSCI_E_INVALID_PARAMS;
+
+ CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
static void k3_pwr_domain_suspend_to_mode(const psci_power_state_t *target_state, uint8_t mode)
{
unsigned int core, proc_id;
@@ -286,6 +308,7 @@
.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
.system_off = k3_system_off,
.system_reset = k3_system_reset,
+ .validate_power_state = k3_validate_power_state,
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,