commit a40d9559b2f104923dc01c74dcdd4ac06b85adef
author Harrison Mutai <harrison.mutai@arm.com> Fri Dec 09 12:14:25 2022 +0000
committer Varun Wadekar <vwadekar@nvidia.com> Fri Feb 03 17:28:02 2023 +0000
tree c38526e678dd628579161c98a443f0bde193a43e
parent b33ea1e3e91430d03d4328f1c7c094af7622ff2d

fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
workaround is to execute a TSB CSYNC and DSB before executing WFI for
power down.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873361/latest
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
(cherry picked from commit aea4ccf8d9f3eabbc931f0e82df65ffca28c25e5)

docs/design/cpu-specific-build-macros.rst

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index f2408aa..9db29e6 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -673,7 +673,7 @@
    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
    r0p3 and r1p0, it is fixed in r1p1.
 
-- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
+-  ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
    r0p3, r1p0 and r1p1. It is fixed in r1p2.
 
@@ -685,6 +685,10 @@
    Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
    r0p3, r1p0, r1p1. It is fixed in r1p2.
 
+-  ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to
+   Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
+   r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
+
 DSU Errata Workarounds
 ----------------------