Merge "feat(cpus): update cpu_check_csv2 check" into lts-v2.10
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7ad8285..4ecdf6f 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -1043,6 +1043,12 @@
please note that this workaround results in increased DSU power consumption
on idle.
+- ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the
+ affected DSU-120 configurations. This erratum applies to some r2p0
+ implementations and is fixed in r2p1. The affected r2p0 implementations
+ are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit
+ and making sure it's clear.
+
CPU Specific optimizations
--------------------------
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index a251bec..41a978c 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -26,13 +26,17 @@
#define CLUSTERIDR_VAR_SHIFT U(4)
#define CLUSTERIDR_VAR_BITS U(4)
+#define CLUSTERREVIDR_EL1 S3_0_C15_C3_2
+
/********************************************************************
* DSU Cluster Auxiliary Control registers definitions
********************************************************************/
#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
-#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
-#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
+#define CLUSTERACTLR_EL1_ASSERT_CBUSY (ULL(1) << 8)
+#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
+#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
+#define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY (ULL(3) << 20)
/********************************************************************
* Masks applied for DSU errata workarounds
diff --git a/include/lib/cpus/aarch64/dsu_macros.S b/include/lib/cpus/aarch64/dsu_macros.S
index 6c8cb69..fd23f66 100644
--- a/include/lib/cpus/aarch64/dsu_macros.S
+++ b/include/lib/cpus/aarch64/dsu_macros.S
@@ -94,4 +94,44 @@
orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING
msr CLUSTERACTLR_EL1, x0
.endm
+
+/*
+ * Check if erratum is fixed via CLUSTERREVIDR_EL1 bit (\bitpos).
+ * If not fixed (bit is clear), set x0 = ERRATA_APPLIES (from x3).
+ * If fixed (bit is set), keep x0 = ERRATA_NOT_APPLIES.
+ */
+.macro check_revidr_bit bitpos:req
+ mrs x4, CLUSTERREVIDR_EL1
+ mov x1, #1
+ lsl x1, x1, #\bitpos
+ tst x1, x4
+ csel x0, x0, x3, NE
+.endm
+
+.macro check_errata_dsu_2900952_applies
+ mov x0, #ERRATA_NOT_APPLIES
+ mov x3, #ERRATA_APPLIES
+
+ /* Check if DSU revision is equal to r2p0 */
+ mrs x1, CLUSTERIDR_EL1
+
+ /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+ ubfx x2, x1, #CLUSTERIDR_REV_SHIFT,\
+ #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+ cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT)
+ b.ne 1f
+ check_revidr_bit 1
+1:
+.endm
+
+.macro errata_dsu_2900952_wa_apply
+
+ ldr x1, =((CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY | \
+ CLUSTERACTLR_EL1_ASSERT_CBUSY))
+
+ mrs x0, CLUSTERACTLR_EL1
+ orr x0, x0, x1
+ msr CLUSTERACTLR_EL1, x0
+.endm
+
#endif /* DSU_MACROS_S */
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index 6714a53..625b64d 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a520.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
.global check_erratum_cortex_a520_2938996
@@ -37,6 +38,15 @@
check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
+workaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a520, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a520, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a520, ERRATUM(2900952)
+
add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996
check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index 2991f93..29e9c9a 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a720.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
@@ -42,6 +43,15 @@
check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
+workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a720, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a720, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a720, ERRATUM(2900952)
+
workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
/* Erratum 2926083 workaround is required only if SPE is enabled */
#if ENABLE_SPE_FOR_NS != 0
diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index a8c0db2..1df0041 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_a725.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
@@ -25,6 +26,15 @@
.global check_erratum_cortex_a725_3699564
+workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a725, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a725, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_a725, ERRATUM(2900952)
+
add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564
check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index df117bf..dddf063 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_x4.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
@@ -64,6 +65,15 @@
check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x4, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x4, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_x4, ERRATUM(2900952)
+
workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
workaround_reset_end cortex_x4, ERRATUM(2923985)
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 6c852dd..4ff7d8f 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -9,6 +9,7 @@
#include <common/bl_common.h>
#include <cortex_x925.h>
#include <cpu_macros.S>
+#include <dsu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
@@ -23,6 +24,15 @@
cpu_reset_prologue cortex_x925
+workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952
+ errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x925, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x925, ERRATUM(2900952)
+ check_errata_dsu_2900952_applies
+ ret
+check_erratum_custom_end cortex_x925, ERRATUM(2900952)
+
add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index b749d99..ebe8958 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1057,6 +1057,13 @@
# results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_2313941
+# Flag to apply DSU erratum 2900952 during reset. This erratum applies
+# to some implementations of DSU-120 revision r2p0. Erratum might be fixed
+# in some implementations of r2p0. This can be determined by reading
+# the IMP_CLUSTERREVIDR_EL1 register where a set bit indicates that
+# the erratum is fixed in this part. It is fixed in r2p1.
+CPU_FLAG_LIST += ERRATA_DSU_2900952
+
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")