feat(gicv5): probe components
Asserts that the platform configuration is correct. No dynamic
discovery so only done in debug builds.
Change-Id: I56763cb422dcaa4a816a619ab4acfc6946427c64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
index 763fea0..786d0bb 100644
--- a/include/drivers/arm/gicv5.h
+++ b/include/drivers/arm/gicv5.h
@@ -44,6 +44,20 @@
#define PPI_DB_RL 1
#define PPI_DB_S 0
+/* Register fields common to all IRI components.
+ * They have the same name and offset in every config frame */
+#define IRI_AIDR_COMPONENT_SHIFT 8
+#define IRI_AIDR_COMPONENT_WIDTH 4
+#define IRI_AIDR_COMPONENT_IRS 0
+#define IRI_AIDR_COMPONENT_ITS 1
+#define IRI_AIDR_COMPONENT_IWB 2
+#define IRI_AIDR_ARCH_MAJOR_SHIFT 4
+#define IRI_AIDR_ARCH_MAJOR_WIDTH 4
+#define IRI_AIDR_ARCH_MAJOR_V5 0
+#define IRI_AIDR_ARCH_MINOR_SHIFT 0
+#define IRI_AIDR_ARCH_MINOR_WIDTH 4
+#define IRI_AIDR_ARCH_MINOR_P0 0
+
/* IRS register fields */
#define IRS_IDR6_SPI_IRS_RANGE_SHIFT 0
#define IRS_IDR6_SPI_IRS_RANGE_WIDTH 24
@@ -110,6 +124,8 @@
DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset) \
DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)
+DEFINE_GICV5_MMIO_READ_FUNC(iri_aidr, 0x44)
+
DEFINE_GICV5_MMIO_READ_FUNC(iwb_idr0, 0x00)
DEFINE_GICV5_MMIO_RW_FUNCS( iwb_cr0, 0x80)
DEFINE_GICV5_MMIO_READ_FUNC(iwb_wenable_statusr, 0xc0)