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review.trustedfirmware.org / next / TF-A / trusted-firmware-a / 4c3bd4a40457ea6742abf37a99eea05ff3d971f5^2..4c3bd4a40457ea6742abf37a99eea05ff3d971f5 / .
commit4c3bd4a40457ea6742abf37a99eea05ff3d971f5[log] [tgz]
authorGovindraj Raja <govindraj.raja@arm.com>Mon Jun 23 16:15:01 2025 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>Mon Jun 23 16:15:01 2025 +0000
tree3e473bbcc8ca57254660ca75dc899b70295fe900
parentf8901e3851759ed5a740b65f39b9fa53d09cf54f [diff]
parent66dec05e67caf441ee38a2604cba41fa73b98729 [diff]
Merge "docs(interrupt): corrected func name in interrupt-framework-design" into integration
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..6a89eeb
--- /dev/null
+++ b/.clang-format

@@ -0,0 +1,199 @@
+---
+AccessModifierOffset: -4
+AlignAfterOpenBracket: Align
+AlignArrayOfStructures: None
+AlignConsecutiveMacros: None
+AlignConsecutiveAssignments: None
+AlignConsecutiveBitFields: None
+AlignConsecutiveDeclarations: None
+AlignEscapedNewlines: Left
+AlignOperands:   Align
+AlignTrailingComments: false
+AllowAllArgumentsOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortEnumsOnASingleLine: true
+AllowShortBlocksOnASingleLine: Never
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortLambdasOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: MultiLine
+AttributeMacros:
+  - __capability
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+  AfterCaseLabel:  false
+  AfterClass:      false
+  AfterControlStatement: Never
+  AfterEnum:       false
+  AfterFunction:   true
+  AfterNamespace:  true
+  AfterObjCDeclaration: false
+  AfterStruct:     false
+  AfterUnion:      false
+  AfterExternBlock: false
+  BeforeCatch:     false
+  BeforeElse:      false
+  BeforeLambdaBody: false
+  BeforeWhile:     false
+  IndentBraces:    false
+  SplitEmptyFunction: true
+  SplitEmptyRecord: true
+  SplitEmptyNamespace: true
+BreakBeforeBinaryOperators: None
+BreakBeforeConceptDeclarations: true
+BreakBeforeBraces: Custom
+BreakBeforeInheritanceComma: false
+BreakInheritanceList: BeforeColon
+BreakBeforeTernaryOperators: false
+BreakConstructorInitializersBeforeComma: false
+BreakConstructorInitializers: BeforeComma
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: false
+ColumnLimit:     80
+CommentPragmas:  '^ IWYU pragma:'
+QualifierAlignment: Leave
+CompactNamespaces: false
+ConstructorInitializerIndentWidth: 8
+ContinuationIndentWidth: 8
+Cpp11BracedListStyle: false
+DeriveLineEnding: true
+DerivePointerAlignment: false
+DisableFormat:   false
+EmptyLineAfterAccessModifier: Never
+EmptyLineBeforeAccessModifier: LogicalBlock
+ExperimentalAutoDetectBinPacking: false
+PackConstructorInitializers: BinPack
+BasedOnStyle:    ''
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+AllowAllConstructorInitializersOnNextLine: true
+FixNamespaceComments: false
+ForEachMacros:
+  - fdt_for_each_compatible_node
+  - fdt_for_each_property_offset
+  - fdt_for_each_subnode
+  - for_each_err_record_info
+  - for_each_subscriber
+IfMacros:
+  - KJ_IF_MAYBE
+IncludeBlocks:   Regroup
+IncludeCategories:
+  - Regex:           '^<(assert|complex|ctype|errno|fenv|float|inttypes|iso646|limits|locale|math|setjmp|signal|stdalign|stdarg|stdatomic|stdbool|stdckdint|stddef|stdint|stdio|stdlib|stdnoreturn|string|tgmath|threads|time|uchar|wchar|wctype)\.h>$'
+    Priority:        0
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^<lib/(compiler-rt|libfdt|mbedtls|zlib)/.+>$'
+    Priority:        1
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^<(platform(_def)?\.h)|(plat[_/].+)>$'
+    Priority:        2
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^<.+>$'
+    Priority:        3
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^".+"$'
+    Priority:        4
+    SortPriority:    0
+    CaseSensitive:   false
+IncludeIsMainRegex: '(Test)?$'
+IncludeIsMainSourceRegex: ''
+IndentAccessModifiers: false
+IndentCaseLabels: false
+IndentCaseBlocks: false
+IndentGotoLabels: false
+IndentPPDirectives: None
+IndentExternBlock: AfterExternBlock
+IndentRequires:  false
+IndentWidth:     8
+IndentWrappedFunctionNames: false
+InsertTrailingCommas: None
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+LambdaBodyIndentation: Signature
+MacroBlockBegin: ''
+MacroBlockEnd:   ''
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 8
+ObjCBreakBeforeNestedBlockParam: true
+ObjCSpaceAfterProperty: true
+ObjCSpaceBeforeProtocolList: true
+PenaltyBreakAssignment: 10
+PenaltyBreakBeforeFirstCallParameter: 30
+PenaltyBreakComment: 10
+PenaltyBreakFirstLessLess: 0
+PenaltyBreakOpenParenthesis: 0
+PenaltyBreakString: 10
+PenaltyBreakTemplateDeclaration: 10
+PenaltyExcessCharacter: 100
+PenaltyReturnTypeOnItsOwnLine: 60
+PenaltyIndentedWhitespace: 0
+PointerAlignment: Right
+PPIndentWidth:   -1
+ReferenceAlignment: Pointer
+ReflowComments:  false
+RemoveBracesLLVM: false
+SeparateDefinitionBlocks: Leave
+ShortNamespaceLines: 1
+SortIncludes:    CaseInsensitive
+SortJavaStaticImport: Before
+SortUsingDeclarations: false
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCaseColon: false
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatementsExceptControlMacros
+SpaceBeforeParensOptions:
+  AfterControlStatements: true
+  AfterForeachMacros: false
+  AfterFunctionDefinitionName: false
+  AfterFunctionDeclarationName: false
+  AfterIfMacros:   false
+  AfterOverloadedOperator: false
+  BeforeNonEmptyParentheses: false
+SpaceAroundPointerQualifiers: Default
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceInEmptyBlock: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles:  Never
+SpacesInConditionalStatement: false
+SpacesInContainerLiterals: false
+SpacesInCStyleCastParentheses: false
+SpacesInLineCommentPrefix:
+  Minimum:         1
+  Maximum:         -1
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+SpaceBeforeSquareBrackets: false
+BitFieldColonSpacing: Both
+Standard:        c++03
+StatementAttributeLikeMacros:
+  - Q_EMIT
+StatementMacros:
+  - Q_UNUSED
+  - QT_REQUIRE_VERSION
+TabWidth:        8
+UseCRLF:         false
+UseTab:          Always
+WhitespaceSensitiveMacros:
+  - STRINGIZE
+  - PP_STRINGIZE
+  - BOOST_PP_STRINGIZE
+  - NS_SWIFT_NAME
+  - CF_SWIFT_NAME
+...

diff --git a/.commitlintrc.js b/.commitlintrc.js
index 53e3a63..51493ea 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,6 +67,6 @@
         "type-enum": [2, "always", types], /* Error */
 
         "scope-case": [2, "always", "lower-case"], /* Error */
-        "scope-enum": [1, "always", scopes] /* Warning */
+        "scope-enum": [2, "always", scopes] /* Error */
     },
 };

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..858e0c1
--- /dev/null
+++ b/.gitmodules

@@ -0,0 +1,4 @@
+[submodule "libtl"]
+	path = contrib/libtl
+	url = https://review.trustedfirmware.org/shared/transfer-list-library
+	shallow = true

diff --git a/Makefile b/Makefile
index eca70bd..88c7b69 100644
--- a/Makefile
+++ b/Makefile

@@ -8,7 +8,7 @@
 # Trusted Firmware Version
 #
 VERSION_MAJOR			:= 2
-VERSION_MINOR			:= 12
+VERSION_MINOR			:= 13
 # VERSION_PATCH is only used for LTS releases
 VERSION_PATCH			:= 0
 VERSION				:= ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
@@ -148,7 +148,7 @@
 		TF_CFLAGS_aarch64	:=	-target aarch64-arm-none-eabi
 	else
 		TF_CFLAGS_aarch32	=	$(target32-directive)
-		TF_CFLAGS_aarch64	:=	-target aarch64-elf
+		TF_CFLAGS_aarch64	:=	-target aarch64-unknown-none-elf
 	endif
 
 else ifeq ($($(ARCH)-cc-id),gnu-gcc)
@@ -492,6 +492,12 @@
 include ${PLAT_MAKEFILE_FULL}
 
 ################################################################################
+# Setup arch_features based on ARM_ARCH_MAJOR, ARM_ARCH_MINOR provided from
+# platform.
+################################################################################
+
+include ${MAKE_HELPERS_DIRECTORY}arch_features.mk
+################################################################################
 # Process BRANCH_PROTECTION value and set
 # Pointer Authentication and Branch Target Identification flags
 ################################################################################
@@ -517,56 +523,30 @@
 	# Turn on branch target identification mechanism
 	BP_OPTION := bti
 	ENABLE_BTI := 1
+else ifeq (${BRANCH_PROTECTION},5)
+	# Turn on branch target identification mechanism
+	BP_OPTION := standard
+	ENABLE_BTI := 2
+	ENABLE_PAUTH := 2
 else
         $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION})
 endif #(BRANCH_PROTECTION)
 
-ifeq ($(ENABLE_PAUTH),1)
-	CTX_INCLUDE_PAUTH_REGS := 1
+ifneq ($(ENABLE_PAUTH),0)
+	CTX_INCLUDE_PAUTH_REGS	:= ${ENABLE_PAUTH}
 endif
 ifneq (${BP_OPTION},none)
 	TF_CFLAGS_aarch64	+=	-mbranch-protection=${BP_OPTION}
 endif #(BP_OPTION)
 
 # Pointer Authentication sources
-ifeq (${ENABLE_PAUTH}, 1)
+ifneq (${ENABLE_PAUTH},0)
 # arm/common/aarch64/arm_pauth.c contains a sample platform hook to complete the
 # Pauth support. As it's not secure, it must be reimplemented for real platforms
-	BL_COMMON_SOURCES	+=	lib/extensions/pauth/pauth_helpers.S
+	BL_COMMON_SOURCES	+=	lib/extensions/pauth/pauth.c
 endif
 
 ################################################################################
-# Setup arch_features based on ARM_ARCH_MAJOR, ARM_ARCH_MINOR provided from
-# platform.
-################################################################################
-include ${MAKE_HELPERS_DIRECTORY}arch_features.mk
-
-####################################################
-# Enable required options for Memory Stack Tagging.
-####################################################
-
-# Currently, these options are enabled only for clang and armclang compiler.
-ifeq (${SUPPORT_STACK_MEMTAG},yes)
-    ifdef mem_tag_arch_support
-        # Check for armclang and clang compilers
-        ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
-        # Add "memtag" architecture feature modifier if not specified
-            ifeq ( ,$(findstring memtag,$(arch-features)))
-                arch-features	:=	$(arch-features)+memtag
-            endif	# memtag
-            ifeq ($($(ARCH)-cc-id),arm-clang)
-                TF_CFLAGS	+=	-mmemtag-stack
-            else ifeq ($($(ARCH)-cc-id),llvm-clang)
-                TF_CFLAGS	+=	-fsanitize=memtag
-            endif	# armclang
-        endif
-    else
-        $(error "Error: stack memory tagging is not supported for  \
-        architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
-	endif #(mem_tag_arch_support)
-endif #(SUPPORT_STACK_MEMTAG)
-
-################################################################################
 # RME dependent flags configuration, Enable optional features for RME.
 ################################################################################
 # FEAT_RME
@@ -581,6 +561,10 @@
 	CTX_INCLUDE_AARCH32_REGS := 0
 	CTX_INCLUDE_PAUTH_REGS := 1
 
+	ifneq ($(ENABLE_FEAT_MPAM), 0)
+		CTX_INCLUDE_MPAM_REGS := 1
+	endif
+
 	# RME enables CSV2_2 extension by default.
 	ENABLE_FEAT_CSV2_2 = 1
 endif #(FEAT_RME)
@@ -643,7 +627,7 @@
 ################################################################################
 include ${MAKE_HELPERS_DIRECTORY}march.mk
 
-TF_CFLAGS   +=	$(march-directive)
+TF_CFLAGS	+=	$(march-directive)
 ASFLAGS		+=	$(march-directive)
 
 # This internal flag is common option which is set to 1 for scenarios
@@ -755,6 +739,10 @@
 include lib/libc/libc.mk
 endif
 
+ifneq (${USE_GIC_DRIVER},0)
+include drivers/arm/gic/gic.mk
+endif
+
 ################################################################################
 # Check incompatible options and dependencies
 ################################################################################
@@ -913,18 +901,46 @@
 # If pointer authentication is used in the firmware, make sure that all the
 # registers associated to it are also saved and restored.
 # Not doing it would leak the value of the keys used by EL3 to EL1 and S-EL1.
-ifeq ($(ENABLE_PAUTH),1)
+ifneq ($(ENABLE_PAUTH),0)
 	ifeq ($(CTX_INCLUDE_PAUTH_REGS),0)
-                $(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS=1)
+                $(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS to be enabled)
 	endif
 endif #(ENABLE_PAUTH)
 
-ifeq ($(CTX_INCLUDE_PAUTH_REGS),1)
+ifneq ($(CTX_INCLUDE_PAUTH_REGS),0)
 	ifneq (${ARCH},aarch64)
                 $(error CTX_INCLUDE_PAUTH_REGS requires AArch64)
 	endif
 endif #(CTX_INCLUDE_PAUTH_REGS)
 
+# Check ENABLE_FEAT_PAUTH_LR
+ifneq (${ENABLE_FEAT_PAUTH_LR},0)
+
+# Make sure PAUTH is enabled
+ifeq (${ENABLE_PAUTH},0)
+	$(error Error: PAUTH_LR cannot be used without PAUTH (see BRANCH_PROTECTION))
+endif
+
+# Make sure SCTLR2 is enabled
+ifeq (${ENABLE_FEAT_SCTLR2},0)
+	$(error Error: PAUTH_LR cannot be used without ENABLE_FEAT_SCTLR2)
+endif
+
+# FEAT_PAUTH_LR is only supported in aarch64 state
+ifneq (${ARCH},aarch64)
+	$(error ENABLE_FEAT_PAUTH_LR requires AArch64)
+endif
+
+# Currently, FEAT_PAUTH_LR is only supported by arm/clang compilers
+# TODO implement for GCC when support is added
+ifeq ($($(ARCH)-cc-id),arm-clang)
+	arch-features	:= $(arch-features)+pauth-lr
+else
+	$(error Error: ENABLE_FEAT_PAUTH_LR not supported for GCC compiler)
+endif
+
+endif # ${ENABLE_FEAT_PAUTH_LR}
+
 ifeq ($(FEATURE_DETECTION),1)
         $(info FEATURE_DETECTION is an experimental feature)
 endif #(FEATURE_DETECTION)
@@ -971,7 +987,7 @@
 	endif
 
 	# FEAT_RNG_TRAP is not supported in AArch32
-	ifeq (${ENABLE_FEAT_RNG_TRAP},1)
+	ifneq (${ENABLE_FEAT_RNG_TRAP},0)
                 $(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32")
 	endif
 
@@ -986,6 +1002,9 @@
 	ifneq (${ENABLE_FEAT_MOPS},0)
 		$(error "ENABLE_FEAT_MOPS cannot be used with ARCH=aarch32")
 	endif
+	ifneq (${ENABLE_FEAT_GCIE},0)
+                $(error "ENABLE_FEAT_GCIE cannot be used with ARCH=aarch32")
+	endif
 endif #(ARCH=aarch32)
 
 ifneq (${ENABLE_FEAT_FPMR},0)
@@ -1095,6 +1114,10 @@
         $(info DICE_PROTECTION_ENVIRONMENT is an experimental feature)
 endif
 
+ifeq (${LFA_SUPPORT},1)
+        $(warning LFA_SUPPORT is an experimental feature)
+endif #(LFA_SUPPORT)
+
 ################################################################################
 # Process platform overrideable behaviour
 ################################################################################
@@ -1222,6 +1245,7 @@
 	ENABLE_RUNTIME_INSTRUMENTATION \
 	ENABLE_SME_FOR_SWD \
 	ENABLE_SVE_FOR_SWD \
+	ENABLE_FEAT_GCIE \
 	ENABLE_FEAT_RAS	\
 	FFH_SUPPORT	\
 	ERROR_DEPRECATED \
@@ -1235,6 +1259,7 @@
 	DISCRETE_TPM \
 	DICE_PROTECTION_ENVIRONMENT \
 	RMMD_ENABLE_EL3_TOKEN_SIGN \
+	RMMD_ENABLE_IDE_KEY_PROG \
 	DRTM_SUPPORT \
 	NS_TIMER_SWITCH \
 	OVERRIDE_LIBC \
@@ -1294,6 +1319,7 @@
 	EARLY_CONSOLE \
 	PRESERVE_DSU_PMU_REGS \
 	HOB_LIST \
+	LFA_SUPPORT \
 )))
 
 # Numeric_Flags
@@ -1310,6 +1336,7 @@
 	ENABLE_TRBE_FOR_NS \
 	ENABLE_BTI \
 	ENABLE_PAUTH \
+	ENABLE_FEAT_PAUTH_LR \
 	ENABLE_FEAT_AMU \
 	ENABLE_FEAT_AMUv1p1 \
 	ENABLE_FEAT_CSV2_2 \
@@ -1396,11 +1423,13 @@
 	ENABLE_FEAT_DEBUGV8P9 \
 	ENABLE_FEAT_MPAM \
 	ENABLE_PAUTH \
+	ENABLE_FEAT_PAUTH_LR \
 	ENABLE_PIE \
 	ENABLE_PMF \
 	ENABLE_PSCI_STAT \
 	ENABLE_RME \
 	RMMD_ENABLE_EL3_TOKEN_SIGN \
+	RMMD_ENABLE_IDE_KEY_PROG \
 	ENABLE_RUNTIME_INSTRUMENTATION \
 	ENABLE_SME_FOR_NS \
 	ENABLE_SME2_FOR_NS \
@@ -1505,6 +1534,7 @@
 	ENABLE_FEAT_D128 \
 	ENABLE_FEAT_GCS \
 	ENABLE_FEAT_MOPS \
+	ENABLE_FEAT_GCIE \
 	ENABLE_FEAT_MTE2 \
 	FEATURE_DETECTION \
 	TWED_DELAY \
@@ -1520,6 +1550,7 @@
 	EARLY_CONSOLE \
 	PRESERVE_DSU_PMU_REGS \
 	HOB_LIST \
+	LFA_SUPPORT \
 )))
 
 ifeq (${PLATFORM_REPORT_CTX_MEM_USE}, 1)
@@ -1807,7 +1838,7 @@
 
 memmap: all
 	$(if $(host-poetry),$(q)poetry -q install --no-root)
-	$(q)$(if $(host-poetry),poetry run )memory -sr ${BUILD_PLAT}
+	$(q)$(if $(host-poetry),poetry run )memory symbols --root ${BUILD_PLAT}
 
 tl: ${BUILD_PLAT}/tl.bin
 ${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
@@ -1816,7 +1847,8 @@
 
 doc:
 	$(s)echo "  BUILD DOCUMENTATION"
-	$(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
+	$(if $(host-poetry),$(q)poetry -q install --with docs --no-root)
+	$(q)$(if $(host-poetry),poetry run )${MAKE} --no-print-directory -C ${DOCS_PATH} html
 
 enctool: ${ENCTOOL}
 

diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index eaaf59a..3e3e002 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -224,15 +224,6 @@
 	 */
 	bl	prepare_el3_entry
 
-#if ENABLE_PAUTH
-	/* -----------------------------------------------------
-	 * Load and program stored APIAKey firmware key.
-	 * Re-enable pointer authentication in EL3, as it was
-	 * disabled before jumping to the next boot image.
-	 * -----------------------------------------------------
-	 */
-	bl	pauth_load_bl1_apiakey_enable
-#endif
 	/* -----------------------------------------------------
 	 * Populate the parameters for the SMC handler. We
 	 * already have x0-x4 in place. x5 will point to a

diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c
index 6d4dc7e..167a22e 100644
--- a/bl1/bl1_fwu.c
+++ b/bl1/bl1_fwu.c

@@ -170,6 +170,9 @@
 	uintptr_t checked_image_base, checked_image_end;
 
 	checked_desc = bl1_plat_get_image_desc(image_id);
+
+	assert(checked_desc != NULL);
+
 	checked_info = &checked_desc->image_info;
 
 	/* Image being checked mustn't be empty. */

diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 2b3a827..fba9102 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -52,14 +52,6 @@
 
 	/* Perform late platform-specific setup */
 	bl1_plat_arch_setup();
-
-#if CTX_INCLUDE_PAUTH_REGS
-	/*
-	 * Assert that the ARMv8.3-PAuth registers are present or an access
-	 * fault will be triggered when they are being saved or restored.
-	 */
-	assert(is_armv8_3_pauth_present());
-#endif /* CTX_INCLUDE_PAUTH_REGS */
 }
 
 /*******************************************************************************
@@ -127,12 +119,6 @@
 	/* Perform platform setup in BL1. */
 	bl1_platform_setup();
 
-#if ENABLE_PAUTH
-	/* Store APIAKey_EL1 key */
-	bl1_apiakey[0] = read_apiakeylo_el1();
-	bl1_apiakey[1] = read_apiakeyhi_el1();
-#endif /* ENABLE_PAUTH */
-
 	/* Get the image id of next image to load and run. */
 	image_id = bl1_plat_get_next_image_id();
 
@@ -148,6 +134,8 @@
 	/* Teardown the measured boot driver */
 	bl1_plat_mboot_finish();
 
+	crypto_mod_finish();
+
 	bl1_prepare_next_image(image_id);
 
 #if ENABLE_RUNTIME_INSTRUMENTATION

diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S
index 678d9c2..91fc682 100644
--- a/bl2/aarch32/bl2_entrypoint.S
+++ b/bl2/aarch32/bl2_entrypoint.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,10 +29,10 @@
 	 * use.
 	 * ---------------------------------------------
 	 */
-	mov	r9, r0
-	mov	r10, r1
-	mov	r11, r2
-	mov	r12, r3
+	mov	r8, r0
+	mov	r9, r1
+	mov	r10, r2
+	mov	r11, r3
 
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
@@ -114,10 +114,10 @@
 	 * Perform BL2 setup
 	 * ---------------------------------------------
 	 */
-	mov	r0, r9
-	mov	r1, r10
-	mov	r2, r11
-	mov	r3, r12
+	mov	r0, r8
+	mov	r1, r9
+	mov	r2, r10
+	mov	r3, r11
 
 	bl	bl2_setup
 

diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index a021e42..756c16d 100644
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S

@@ -48,6 +48,10 @@
 	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
 	mrs	x0, sctlr_el1
 	orr	x0, x0, x1
+#if ENABLE_BTI
+	/* Enable PAC branch type compatibility */
+	bic     x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
+#endif
 	bic	x0, x0, #SCTLR_DSSBS_BIT
 	msr	sctlr_el1, x0
 	isb

diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index f12c1a5..8ca7143 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -50,14 +50,6 @@
 
 	/* Perform late platform-specific setup */
 	bl2_el3_plat_arch_setup();
-
-#if CTX_INCLUDE_PAUTH_REGS
-	/*
-	 * Assert that the ARMv8.3-PAuth registers are present or an access
-	 * fault will be triggered when they are being saved or restored.
-	 */
-	assert(is_armv8_3_pauth_present());
-#endif /* CTX_INCLUDE_PAUTH_REGS */
 }
 #else /* RESET_TO_BL2 */
 
@@ -75,14 +67,6 @@
 
 	/* Perform late platform-specific setup */
 	bl2_plat_arch_setup();
-
-#if CTX_INCLUDE_PAUTH_REGS
-	/*
-	 * Assert that the ARMv8.3-PAuth registers are present or an access
-	 * fault will be triggered when they are being saved or restored.
-	 */
-	assert(is_armv8_3_pauth_present());
-#endif /* CTX_INCLUDE_PAUTH_REGS */
 }
 #endif /* RESET_TO_BL2 */
 
@@ -126,6 +110,8 @@
 	/* Teardown the Measured Boot backend */
 	bl2_plat_mboot_finish();
 
+	crypto_mod_finish();
+
 #if !BL2_RUNS_AT_EL3
 #ifndef __aarch64__
 	/*
@@ -136,12 +122,12 @@
 	disable_mmu_icache_secure();
 #endif /* !__aarch64__ */
 
-#if ENABLE_PAUTH
 	/*
 	 * Disable pointer authentication before running next boot image
 	 */
-	pauth_disable_el1();
-#endif /* ENABLE_PAUTH */
+	if (is_feat_pauth_supported()) {
+		pauth_disable_el1();
+	}
 
 #if ENABLE_RUNTIME_INSTRUMENTATION
 	PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
@@ -164,12 +150,12 @@
 #endif
 	console_flush();
 
-#if ENABLE_PAUTH
 	/*
 	 * Disable pointer authentication before running next boot image
 	 */
-	pauth_disable_el3();
-#endif /* ENABLE_PAUTH */
+	if (is_feat_pauth_supported()) {
+		pauth_disable_el3();
+	}
 
 	bl2_run_next_image(next_bl_ep_info);
 #endif /* BL2_RUNS_AT_EL3 */

diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S
index 15978b6..8fc34b3 100644
--- a/bl2u/aarch64/bl2u_entrypoint.S
+++ b/bl2u/aarch64/bl2u_entrypoint.S

@@ -45,6 +45,10 @@
 	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
 	mrs	x0, sctlr_el1
 	orr	x0, x0, x1
+#if ENABLE_BTI
+	/* Enable PAC branch type compatibility */
+	bic     x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
+#endif
 	bic	x0, x0, #SCTLR_DSSBS_BIT
 	msr	sctlr_el1, x0
 	isb

diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index b5bf575..7b61692 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S

@@ -397,8 +397,26 @@
 	ldr	x4, [x0, #REGSZ * 7]
 
 #if ENABLE_PAUTH
+#if ENABLE_PAUTH == 2
+	/* Skip if not present in hardware */
+	is_feat_pauth_present_asm x0, x1
+	beq	1f
+#endif
+	/*
+	 * The assembler must see support for xpaci. So turn the compiler
+	 * extension on. GCC prior to 10 doesn't understand the PAuth extension
+	 * but it does understand armv8.3-a in general. Avoid using 8.3 if
+	 * the compiler understands "pauth" so we don't downgrade a higher
+	 * -march that was specified on the commandline.
+	 */
+#if __GNUC__ < 10
+	.arch armv8.3-a
+#else
+	.arch_extension pauth
+#endif
 	/* Demangle address */
 	xpaci	x4
+1:
 #endif
 	bl	asm_print_hex
 	bl	asm_print_newline

diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index fce17e1..3f1b3ea 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -46,11 +46,6 @@
 	 */
 	bl	prepare_el3_entry
 
-#if ENABLE_PAUTH
-	/* Load and program APIAKey firmware key */
-	bl	pauth_load_bl31_apiakey
-#endif
-
 	/* Setup exception class and syndrome arguments for platform handler */
 	mov	x0, #ERROR_EA_SYNC
 	mrs	x1, esr_el3
@@ -78,11 +73,6 @@
 	 */
 	bl	prepare_el3_entry
 
-#if ENABLE_PAUTH
-	/* Load and program APIAKey firmware key */
-	bl	pauth_load_bl31_apiakey
-#endif
-
 	/* Setup exception class and syndrome arguments for platform handler */
 	mov	x0, #ERROR_EA_ASYNC
 	mrs	x1, esr_el3

diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 7423805..6537aa7 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -340,11 +340,6 @@
 	 */
 	bl	prepare_el3_entry
 
-#if ENABLE_PAUTH
-	/* Load and program APIAKey firmware key */
-	bl	pauth_load_bl31_apiakey
-#endif
-
 	/*
 	 * Populate the parameters for the SMC handler.
 	 * We already have x0-x4 in place. x5 will point to a cookie (not used
@@ -536,11 +531,6 @@
 	 */
 	bl	prepare_el3_entry
 
-#if ENABLE_PAUTH
-	/* Load and program APIAKey firmware key */
-	bl	pauth_load_bl31_apiakey
-#endif
-
 	/* Save the EL3 system registers needed to return from this exception */
 	mrs	x0, spsr_el3
 	mrs	x1, elr_el3

diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index e390915..d267b11 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk

@@ -164,6 +164,10 @@
 				${RMMD_SOURCES}
 endif
 
+ifeq (${USE_DSU_DRIVER},1)
+BL31_SOURCES		+=	drivers/arm/dsu/dsu.c
+endif
+
 ifeq ($(FEATURE_DETECTION),1)
 BL31_SOURCES		+=	common/feat_detect.c
 endif
@@ -177,6 +181,11 @@
 				${MBEDTLS_SOURCES}
 endif
 
+ifeq (${LFA_SUPPORT},1)
+include services/std_svc/lfa/lfa.mk
+BL31_SOURCES		+=	${LFA_SOURCES}
+endif
+
 ifeq ($(CROS_WIDEVINE_SMC),1)
 BL31_SOURCES		+=	services/oem/chromeos/widevine_smc_handlers.c
 endif
@@ -200,11 +209,13 @@
 	CRASH_REPORTING \
 	EL3_EXCEPTION_HANDLING \
 	SDEI_SUPPORT \
+	USE_DSU_DRIVER \
 )))
 
 $(eval $(call add_defines,\
     $(sort \
-        CRASH_REPORTING \
-        EL3_EXCEPTION_HANDLING \
-        SDEI_SUPPORT \
+	CRASH_REPORTING \
+	EL3_EXCEPTION_HANDLING \
+	SDEI_SUPPORT \
+	USE_DSU_DRIVER \
 )))

diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index db0ea6c..ba26366 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,6 +17,8 @@
 #include <common/debug.h>
 #include <common/feat_detect.h>
 #include <common/runtime_svc.h>
+#include <drivers/arm/dsu.h>
+#include <drivers/arm/gic.h>
 #include <drivers/console.h>
 #include <lib/bootmarker_capture.h>
 #include <lib/el3_runtime/context_debug.h>
@@ -55,7 +57,7 @@
  * Variable to indicate whether next image to execute after BL31 is BL33
  * (non-secure & default) or BL32 (secure).
  ******************************************************************************/
-static uint32_t next_image_type = NON_SECURE;
+static uint32_t next_image_type = (uint32_t)NON_SECURE;
 
 #ifdef SUPPORT_UNKNOWN_MPID
 /*
@@ -104,14 +106,6 @@
 	/* Perform late platform-specific setup */
 	bl31_plat_arch_setup();
 
-#if CTX_INCLUDE_PAUTH_REGS
-	/*
-	 * Assert that the ARMv8.3-PAuth registers are present or an access
-	 * fault will be triggered when they are being saved or restored.
-	 */
-	assert(is_armv8_3_pauth_present());
-#endif /* CTX_INCLUDE_PAUTH_REGS */
-
 	/* Prints context_memory allocated for all the security states */
 	report_ctx_memory_usage();
 }
@@ -153,6 +147,22 @@
 	/* Perform platform setup in BL31 */
 	bl31_platform_setup();
 
+#if USE_DSU_DRIVER
+	dsu_driver_init(&plat_dsu_data);
+#endif
+
+#if USE_GIC_DRIVER
+	/*
+	 * Initialize the GIC driver as well as per-cpu and global interfaces.
+	 * Platform has had an opportunity to initialise specifics.
+	 */
+	unsigned int core_pos = plat_my_core_pos();
+
+	gic_init(core_pos);
+	gic_pcpu_init(core_pos);
+	gic_cpuif_enable(core_pos);
+#endif /* USE_GIC_DRIVER */
+
 	/* Initialise helper libraries */
 	bl31_lib_init();
 
@@ -255,7 +265,7 @@
  ******************************************************************************/
 void __init bl31_prepare_next_image_entry(void)
 {
-	entry_point_info_t *next_image_info;
+	const entry_point_info_t *next_image_info;
 	uint32_t image_type;
 
 #if CTX_INCLUDE_AARCH32_REGS

diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index 984fdaa..114a57d 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c

@@ -90,19 +90,17 @@
  * Explicitly create all bits of SPSR to get PSTATE at exception return.
  *
  * The code is based on "Aarch64.exceptions.takeexception" described in
- * DDI0602 revision 2023-06.
- * "https://developer.arm.com/documentation/ddi0602/2023-06/Shared-Pseudocode/
+ * DDI0602 revision 2025-03.
+ * "https://developer.arm.com/documentation/ddi0597/2025-03/Shared-Pseudocode/
  * aarch64-exceptions-takeexception"
  *
- * NOTE: This piece of code must be reviewed every release to ensure that
- * we keep up with new ARCH features which introduces a new SPSR bit.
+ * NOTE: This piece of code must be reviewed every release against the latest
+ * takeexception sequence to ensure that we keep up with new arch features that
+ * affect the PSTATE.
  *
- * TF-A 2.12 release review
- * The latest version available is 2024-09, which has two extra features which
- * impacts generation of SPSR, since these features are not implemented in TF-A
- * at the time of release, just log the feature names here to be taken up when
- * feature support is introduced.
- *  - FEAT_PAuth_LR (2023 extension)
+ * TF-A 2.13 release review
+ *
+ * Review of version 2025-03 indicates we are missing support for one feature.
  *  - FEAT_UINJ (2024 extension)
  */
 u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el)
@@ -204,6 +202,12 @@
 		new_spsr |= (gcscr & GCSCR_EXLOCK_EN_BIT) ? SPSR_EXLOCK_BIT_AARCH64 : 0;
 	}
 
+	/* If FEAT_PAUTH_LR present then zero the PACM bit. */
+	new_spsr |= old_spsr & SPSR_PACM_BIT_AARCH64;
+	if (is_feat_pauth_lr_present()) {
+		new_spsr &= ~SPSR_PACM_BIT_AARCH64;
+	}
+
 	return new_spsr;
 }
 

diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index b1f4343..44d1e66 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -83,3 +83,7 @@
 SP_MIN_WITH_SECURE_FIQ 	?= 0
 $(eval $(call add_define,SP_MIN_WITH_SECURE_FIQ))
 $(eval $(call assert_boolean,SP_MIN_WITH_SECURE_FIQ))
+
+ifeq (${TRANSFER_LIST},1)
+BL32_SOURCES	+=	$(TRANSFER_LIST_SOURCES)
+endif

diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index a85b355..9add239 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -113,6 +113,7 @@
 	next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
 	next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
 	next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
+	next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
 	next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
 	next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
 	next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);

diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index e5ea88c..4ea2f5b 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -51,6 +51,15 @@
 	.endm
 
 func tsp_entrypoint _align=3
+	/*---------------------------------------------
+	 * Save arguments x0 - x3 from BL1 for future
+	 * use.
+	 * ---------------------------------------------
+	 */
+	mov	x20, x0
+	mov	x21, x1
+	mov	x22, x2
+	mov	x23, x3
 
 #if ENABLE_PIE
 		/*
@@ -94,6 +103,10 @@
 	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
 	mrs	x0, sctlr_el1
 	orr	x0, x0, x1
+#if ENABLE_BTI
+	/* Enable PAC branch type compatibility */
+	bic     x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
+#endif
 	bic	x0, x0, #SCTLR_DSSBS_BIT
 	msr	sctlr_el1, x0
 	isb
@@ -169,6 +182,16 @@
 	bl	update_stack_protector_canary
 #endif
 
+	/*---------------------------------------------
+	 * Save arguments x0 - x3 from prio stage for
+	 * future use.
+	 * ---------------------------------------------
+	 */
+	mov	x0, x20
+	mov	x1, x21
+	mov	x2, x22
+	mov	x3, x23
+
 	/* ---------------------------------------------
 	 * Perform TSP setup
 	 * ---------------------------------------------

diff --git a/bl32/tsp/tsp_common.c b/bl32/tsp/tsp_common.c
index 3a6c9d9..144349a 100644
--- a/bl32/tsp/tsp_common.c
+++ b/bl32/tsp/tsp_common.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -64,24 +64,17 @@
 /*******************************************************************************
  * Setup function for TSP.
  ******************************************************************************/
-void tsp_setup(void)
+void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+	       u_register_t arg3)
 {
 	/* Enable early console if EARLY_CONSOLE flag is enabled */
 	plat_setup_early_console();
 
 	/* Perform early platform-specific setup. */
-	tsp_early_platform_setup();
+	tsp_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Perform late platform-specific setup. */
 	tsp_plat_arch_setup();
-
-#if ENABLE_PAUTH
-	/*
-	 * Assert that the ARMv8.3-PAuth registers are present or an access
-	 * fault will be triggered when they are being saved or restored.
-	 */
-	assert(is_armv8_3_pauth_present());
-#endif /* ENABLE_PAUTH */
 }
 
 /*******************************************************************************
@@ -104,7 +97,7 @@
 	tsp_stats[linear_id].eret_count++;
 
 	INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets requests\n", read_mpidr(),
 	     tsp_stats[linear_id].smc_count,
 	     tsp_stats[linear_id].eret_count);
 
@@ -132,7 +125,7 @@
 	tsp_stats[linear_id].eret_count++;
 
 	INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets requests\n", read_mpidr(),
 	     tsp_stats[linear_id].smc_count,
 	     tsp_stats[linear_id].eret_count);
 

diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index a847b6c..9d86e3e 100644
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,8 +37,8 @@
 
 	VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n",
 		read_mpidr(), elr_el3);
-	VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
-		" %d sync s-el1 interrupt returns\n",
+	VERBOSE("TSP: cpu 0x%lx: %u sync s-el1 interrupt requests,"
+		" %u sync s-el1 interrupt returns\n",
 		read_mpidr(),
 		tsp_stats[linear_id].sync_sel1_intr_count,
 		tsp_stats[linear_id].sync_sel1_intr_ret_count);
@@ -54,7 +54,7 @@
 	uint32_t linear_id = plat_my_core_pos();
 
 	tsp_stats[linear_id].preempt_intr_count++;
-	VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
+	VERBOSE("TSP: cpu 0x%lx: %u preempt interrupt requests\n",
 		read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
 	return TSP_PREEMPTED;
 }
@@ -107,9 +107,9 @@
 
 	/* Update the statistics and print some messages */
 	tsp_stats[linear_id].sel1_intr_count++;
-	VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
+	VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %u\n",
 	       read_mpidr(), id);
-	VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
+	VERBOSE("TSP: cpu 0x%lx: %u S-EL1 requests\n",
 	     read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
 	return 0;
 }

diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 8c6b2ed..1b7116a 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -47,7 +47,7 @@
 	tsp_stats[linear_id].eret_count++;
 	tsp_stats[linear_id].cpu_on_count++;
 
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu on requests\n",
 	     read_mpidr(),
 	     tsp_stats[linear_id].smc_count,
 	     tsp_stats[linear_id].eret_count,
@@ -75,7 +75,7 @@
 	tsp_stats[linear_id].cpu_on_count++;
 
 	INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu on requests\n",
 		read_mpidr(),
 		tsp_stats[linear_id].smc_count,
 		tsp_stats[linear_id].eret_count,
@@ -112,7 +112,7 @@
 	tsp_stats[linear_id].cpu_off_count++;
 
 	INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu off requests\n",
 		read_mpidr(),
 		tsp_stats[linear_id].smc_count,
 		tsp_stats[linear_id].eret_count,
@@ -150,7 +150,7 @@
 	tsp_stats[linear_id].eret_count++;
 	tsp_stats[linear_id].cpu_suspend_count++;
 
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu suspend requests\n",
 		read_mpidr(),
 		tsp_stats[linear_id].smc_count,
 		tsp_stats[linear_id].eret_count,
@@ -184,9 +184,9 @@
 	tsp_stats[linear_id].eret_count++;
 	tsp_stats[linear_id].cpu_resume_count++;
 
-	INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
+	INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRIu64 "\n",
 	     read_mpidr(), max_off_pwrlvl);
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu resume requests\n",
 		read_mpidr(),
 		tsp_stats[linear_id].smc_count,
 		tsp_stats[linear_id].eret_count,
@@ -224,7 +224,7 @@
 	INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
 		((func >> 31) & 1) == 1 ? "fast" : "yielding",
 		func);
-	INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
+	INFO("TSP: cpu 0x%lx: %u smcs, %u erets\n", read_mpidr(),
 		tsp_stats[linear_id].smc_count,
 		tsp_stats[linear_id].eret_count);
 

diff --git a/changelog.yaml b/changelog.yaml
index 3f06369..e0a4f42 100644
--- a/changelog.yaml
+++ b/changelog.yaml

@@ -98,13 +98,16 @@
           - d128
           - debugv8p9
           - fgt2
+          - fpmr
           - gcs
           - hcx
+          - mops
           - mpam
           - mte
           - mte2
           - pauth
           - pmu
+          - pmuv3
           - rng-trap
           - sctlr2
           - feat_sctlr2
@@ -135,6 +138,13 @@
         deprecated:
           - plat/allwinner
 
+      - title: AMLogic
+        scope: amlogic
+
+        subsections:
+          - title: GXL
+            scope: gxl
+
       - title: Arm
         scope: arm
 
@@ -170,12 +180,6 @@
               - plat/fvp
               - fvp/tsp_manifest
 
-          - title: FVP-R
-            scope: fvp-r
-
-            deprecated:
-              - fvp_r
-
           - title: FVP Versatile Express
             scope: fvp_ve
 
@@ -192,21 +196,6 @@
             scope: neoverse-rd
 
             subsections:
-              - title: SGI-575
-                scope: sgi575
-
-              - title: RD-E1-Edge
-                scope: rde1edge
-
-              - title: RD-N1-Edge
-                scope: rdn1edge
-
-              - title: RD-V1
-                scope: rdv1
-
-              - title: RD-V1-MC
-                scope: rdv1mc
-
               - title: RD-N2
                 scope: rdn2
 
@@ -219,6 +208,7 @@
 
             deprecated:
               - neoverse
+              - neoverse_rd
 
           - title: TC
             scope: tc
@@ -226,13 +216,6 @@
             deprecated:
               - plat/tc
 
-            subsections:
-              - title: TC0
-                scope: tc0
-
-                deprecated:
-                  - plat/tc0
-
           - title: Corstone-1000
             scope: corstone-1000
 
@@ -329,6 +312,9 @@
           - title: MT8188
             scope: mt8188
 
+          - title: MT8189
+            scope: mt8189
+
           - title: MT8192
             scope: mt8192
 
@@ -343,6 +329,9 @@
               - plat/mediatek/mt8195
               - plat/mdeiatek/mt8195
 
+          - title: MT8196
+            scope: mt8196
+
       - title: NVIDIA
         scope: nvidia
 
@@ -576,6 +565,12 @@
         scope: rockchip
 
         subsections:
+          - title: PX30
+            scope: px30
+
+          - title: RK3288
+            scope: rk3288
+
           - title: RK3399
             scope: rk3399
 
@@ -586,6 +581,9 @@
           - title: RK3328
             scope: rk3328
 
+          - title: RK3576
+            scope: rk3576
+
           - title: RK3588
             scope: rk3588
 
@@ -623,6 +621,12 @@
             scope: stm32mp2
 
             subsections:
+              - title: STM32MP21
+                scope: stm32mp21
+
+              - title: STM32MP23
+                scope: stm32mp23
+
               - title: STM32MP25
                 scope: stm32mp25
 
@@ -744,6 +748,7 @@
             scope: el3-spmc
 
             deprecated:
+              - el3_spmc
               - spmc
 
           - title: SPMD
@@ -752,6 +757,9 @@
           - title: SPM MM
             scope: spm-mm
 
+            deprecated:
+              - spm_mm
+
       - title: DRTM
         scope: drtm
 
@@ -767,6 +775,9 @@
       - title: ChromeOS
         scope: cros
 
+      - title: Live Firmware Activation
+        scope: lfa
+
       - title: Secure Payload Dispatcher
         scope: spd
 
@@ -820,6 +831,9 @@
       - title: FCONF
         scope: fconf
 
+      - title: HOB
+        scope: hob
+
       - title: MPMM
         scope: mpmm
 
@@ -829,7 +843,7 @@
       - title: ROMlib
         scope: romlib
 
-      - title: GPT
+      - title: Granule Protection Tables
         scope: gpt
 
         deprecated:
@@ -841,6 +855,9 @@
       - title: Translation Tables
         scope: xlat
 
+        deprecated:
+          - xlat_tables_v2
+
       - title: C Standard Library
         scope: libc
 
@@ -982,6 +999,9 @@
             scope: gic
 
             subsections:
+              - title: GICv5
+                scope: gicv5
+
               - title: GICv3
                 scope: gicv3
 
@@ -1167,6 +1187,9 @@
           - title: Clock
             scope: nxp-clk
 
+          - title: uSDHC
+            scope: nxp-mmc
+
       - title: Renesas
         scope: renesas-drivers
 
@@ -1276,6 +1299,9 @@
       - title: AArch64
         scope: aarch64
 
+      - title: AArch32
+        scope: aarch32
+
       - title: Debug
         scope: debug
 
@@ -1312,31 +1338,43 @@
           - fdt
 
         subsections:
-          - title: Morello
-            scope: morello-fdts
-
-            deprecated:
-              - fdts/morello
-
-          - title: STM32MP1
-            scope: stm32mp1-fdts
-
-            deprecated:
-              - fdts stm32mp1
+          - title: Arm
 
             subsections:
-              - title: STM32MP13
-                scope: stm32mp13-fdts
+              - title: Morello
+                scope: morello-fdts
 
-              - title: STM32MP15
-                scope: stm32mp15-fdts
+                deprecated:
+                  - fdts/morello
 
-          - title: STM32MP2
-            scope: stm32mp2-fdts
+          - title: ST
 
             subsections:
-              - title: STM32MP25
-                scope: stm32mp25-fdts
+              - title: STM32MP1
+                scope: stm32mp1-fdts
+
+                deprecated:
+                - fdts stm32mp1
+
+                subsections:
+                  - title: STM32MP13
+                    scope: stm32mp13-fdts
+
+                  - title: STM32MP15
+                    scope: stm32mp15-fdts
+
+              - title: STM32MP2
+                scope: stm32mp2-fdts
+
+                subsections:
+                  - title: STM32MP21
+                    scope: stm32mp21-fdts
+
+                  - title: STM32MP23
+                    scope: stm32mp23-fdts
+
+                  - title: STM32MP25
+                    scope: stm32mp25-fdts
 
       - title: PIE
         scope: pie
@@ -1421,6 +1459,9 @@
     scope: tools
 
     subsections:
+      - title: Clang-Format
+        scope: clang-format
+
       - title: Dependabot
         scope: dependabot
 

diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c
index f994ae5..479c4fd 100644
--- a/common/backtrace/backtrace.c
+++ b/common/backtrace/backtrace.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include <arch_features.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/console.h>
@@ -41,15 +42,14 @@
 {
 	uintptr_t ret = address;
 
-#if ENABLE_PAUTH
 	/*
 	 * When pointer authentication is enabled, the LR value saved on the
 	 * stack contains a PAC. It must be stripped to retrieve the return
 	 * address.
 	 */
-
-	xpaci(ret);
-#endif
+	if (is_feat_pauth_supported()) {
+		ret = xpaci(address);
+	}
 
 	return ret;
 }

diff --git a/common/feat_detect.c b/common/feat_detect.c
index 821ccb8..fa817d9 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -66,7 +66,7 @@
 static void read_feat_pauth(void)
 {
 #if (ENABLE_PAUTH == FEAT_STATE_ALWAYS) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_ALWAYS)
-	feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH");
+	feat_detect_panic(is_feat_pauth_present(), "PAUTH");
 #endif
 }
 
@@ -279,6 +279,11 @@
 	return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
 			     ID_AA64MMFR3_EL1_D128_MASK);
 }
+static unsigned int read_feat_gcie_id_field(void)
+{
+	return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
+			     ID_AA64PFR2_EL1_GCIE_MASK);
+}
 
 static unsigned int read_feat_fpmr_id_field(void)
 {
@@ -330,7 +335,7 @@
 	 * revisions so that we catch them as they come along
 	 */
 	check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
-		      "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P8);
+		      "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9);
 
 	/* v8.1 features */
 	check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
@@ -425,10 +430,13 @@
 	/* v9.3 features */
 	check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
 		      "D128", 1, 1);
+	check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
+		      "GCIE", 1, 1);
 
 	/* v9.4 features */
 	check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
 	check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
+	check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), "PAUTH_LR", 1, 1);
 
 	if (tainted) {
 		panic();

diff --git a/common/tf_log.c b/common/tf_log.c
index 2d976f6..f678975 100644
--- a/common/tf_log.c
+++ b/common/tf_log.c

@@ -12,7 +12,7 @@
 #include <plat/common/platform.h>
 
 /* Set the default maximum log level to the `LOG_LEVEL` build flag */
-static unsigned int max_log_level = LOG_LEVEL;
+static uint32_t max_log_level = LOG_LEVEL;
 
 /*
  * The common log function which is invoked by TF-A code.
@@ -23,12 +23,12 @@
  */
 void tf_log(const char *fmt, ...)
 {
-	unsigned int log_level;
+	uint32_t log_level;
 	va_list args;
 	const char *prefix_str;
 
 	/* We expect the LOG_MARKER_* macro as the first character */
-	log_level = fmt[0];
+	log_level = (uint32_t)fmt[0];
 
 	/* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
 	assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
@@ -40,7 +40,7 @@
 	prefix_str = plat_log_get_prefix(log_level);
 
 	while (*prefix_str != '\0') {
-		(void)putchar(*prefix_str);
+		(void)putchar((int)*prefix_str);
 		prefix_str++;
 	}
 
@@ -51,7 +51,7 @@
 
 void tf_log_newline(const char log_fmt[2])
 {
-	unsigned int log_level = log_fmt[0];
+	uint32_t log_level = (uint32_t)log_fmt[0];
 
 	/* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
 	assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
@@ -61,7 +61,7 @@
 		return;
 	}
 
-	putchar('\n');
+	(void)putchar((int32_t)'\n');
 }
 
 /*
@@ -69,12 +69,12 @@
  * maximum log level is determined by `LOG_LEVEL` build flag at compile time
  * and this helper can set a lower (or equal) log level than the one at compile.
  */
-void tf_log_set_max_level(unsigned int log_level)
+void tf_log_set_max_level(uint32_t log_level)
 {
 	assert(log_level <= LOG_LEVEL_VERBOSE);
 	assert((log_level % 10U) == 0U);
 
 	/* Cap log_level to the compile time maximum. */
-	if (log_level <= (unsigned int)LOG_LEVEL)
+	if (log_level <= (uint32_t)LOG_LEVEL)
 		max_log_level = log_level;
 }

diff --git a/contrib/libtl b/contrib/libtl
new file mode 160000
index 0000000..9630cb0
--- /dev/null
+++ b/contrib/libtl

@@ -0,0 +1 @@
+Subproject commit 9630cb01984503a9fe6974d31b0d581fb693540c

diff --git a/docs/about/features.rst b/docs/about/features.rst
index 9b7bdf9..78f5ff3 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst

@@ -127,8 +127,8 @@
 Additionally the following libraries are marked experimental when included
 in a platform:
 
--  MPU translation library ``lib/xlat_mpu``
 -  RSE comms driver ``drivers/arm/rse``
+-  GICv5 driver ``drivers/arm/gicv5`` via ``USE_GIC_DRIVER=5``
 
 Still to come
 -------------
@@ -151,4 +151,4 @@
 
 --------------
 
-*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*

diff --git a/docs/about/lts.rst b/docs/about/lts.rst
index f5e5f8e..593f9dc 100644
--- a/docs/about/lts.rst
+++ b/docs/about/lts.rst

@@ -27,6 +27,8 @@
   +-------------+--------------------+-------------------------------------------------------+
   | 2025-01-07  | Govindraj Raja     | Updates based on learnings and suggestions.           |
   +-------------+--------------------+-------------------------------------------------------+
+  | 2025-03-27  | Chris Palmer       | Playbook for making a new release.                    |
+  +-------------+--------------------+-------------------------------------------------------+
 
 This document proposes a plan for long-term support (LTS) of the |TF-A| project.
 
@@ -263,6 +265,48 @@
 #. Monitor the mailing list for any LTS related issues
 #. Propose or solicit patches to the main branch and tag them as candidates for LTS
 
+Playbook for new releases
+-------------------------
+To make a new minor release (e.g. 2.x.y → 2.x.y+1), follow these steps.
+
+#. Every Friday, LTS maintainers receive a triage report email (subject: “TF-A
+   LTS Triage report”) that contains attached CSV files, 1 per
+   currently-supported LTS major release branch (e.g. lts-2.8, lts-2.10,
+   lts-2.12, etc.). It contains a list of patches to be cherry-picked into a new
+   minor release of each supported LTS branch.
+#. Run ``git fetch origin``.
+#. Run ``git checkout -b lts-v2.x.y+1 --track origin/lts-v2.x``.
+#. Run ``git log`` and verify that the most recent commit is the changelog for
+   the v2.x.y release, and that it has the origin/lts-v2.x tag.
+#. For the version 2.x for which you want to create a new release, open its CSV
+   file. For each patch listed, **from the bottom to the top**, run ``git
+   cherry-pick -x sha1-hash``.
+#. Some of the patches of this list may not be taken, mainly due to false
+   positive. If in doubt, that can be discussed either in the “tf-a-lts” channel
+   on Discord or during the LTS weekly meeting.
+#. Some dependency patches, not listed in the CSV file, may have to be taken, to ease the
+   application of the LTS patches. This can also be discussed with the other LTS maintainers.
+#. Push the stack of changes: ``git push origin
+   HEAD:refs/for/lts-v2.x%topic=for-lts-v2.x.y+1``. You might need the
+   ``--no-verify`` option: ``git push origin --no-verify
+   HEAD:refs/for/lts-v2.x%topic=for-lts-v2.x.y+1``.
+#. The AllowCI+2 job runs automatically on each LTS branch once a new
+   cherry-picked patch/patch-stack is pushed to the corresponding branch. If
+   this CI run passes, it automatically applies the Verified+1 (V+1) label to
+   the patch/all patches in the stack. The other LTS maintainers will provide
+   MR+1 and COR+1 votes. If the CI is OK and votes V+1, and if the
+   Maintainer-Review+1 (MR+1), Code-Owner-Review+1 (COR+1), and V+1 votes are
+   present, Gerrit will automatically merge the patch. LTS maintainers will then
+   trigger a Jenkins job that will take care of the release (tag, mail, and
+   readthedocs update).
+#. Some features may also require updates in other repositories (tf-a-ci-scripts,
+   tf-a-job-configs or tf-a-tests...). For tf-a-job-configs, there are no LTS branches, but
+   dedicated scripts for each LTS version which have to be updated manually. This is the case
+   for e.g. MbedTLS updates. For tf-a-ci-scripts and tf-a-tests, there are LTS branches and patches
+   will be cherry-picked from master branch to the LTS branch the same way it is done for TF-A.
+   There is no automation for those repositories. So the patches will have to be merged manually,
+   and for tf-a-ci-scripts and tf-a-tests, tags will also have to be set manually.
+
 Execution Plan
 **************
 This section lists the steps needed to put the LTS system in place. However,

diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 3e33824..569f932 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst

@@ -73,8 +73,6 @@
 :|G|: `vwadekar`_
 :|M|: Yann Gautier <yann.gautier@st.com>
 :|G|: `Yann-lms`_
-:|M|: Chris Palmer <palmer@google.com>
-:|G|: `noncombatant`_
 :|M|: Govindraj Raja <govindraj.raja@arm.com>
 :|G|: `govindraj-arm`_
 
@@ -113,8 +111,6 @@
 :|G|: `ManishVB-Arm`_
 :|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
 :|G|: `laurenw-arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
 :|F|: drivers/auth/
 
 Secure Partition Manager Core (EL3 FF-A SPMC)
@@ -226,10 +222,10 @@
 ^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Michal Simek <michal.simek@amd.com>
 :|G|: `michalsimek`_
-:|M|: Amit Nagal <amit.nagal@amd.com>
-:|G|: `amit-nagal`_
 :|M|: Akshay Belsare <akshay.belsare@amd.com>
 :|G|: `Akshay-Belsare`_
+:|M|: Maheedhar Sai Bollapalli <maheedharsai.bollapalli@amd.com>
+:|G|: `maheedhar-bollapalli`_
 :|F|: drivers/arm/dcc/
 :|F|: include/drivers/arm/dcc.h
 
@@ -241,6 +237,8 @@
 :|G|: `madhukar-Arm`_
 :|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
 :|G|: `laurenw-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/psci/
 :|F|: include/lib/psci/
 
@@ -284,6 +282,8 @@
 :|G|: `bipinravi-arm`_
 :|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
 :|G|: `laurenw-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/cpus/
 :|F|: include/lib/cpus/
 
@@ -293,6 +293,8 @@
 :|G|: `manish-pandey-arm`_
 :|M|: Olivier Deprez <olivier.deprez@arm.com>
 :|G|: `odeprez`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/extensions/ras/
 
 Activity Monitors Unit (AMU) extensions
@@ -301,24 +303,32 @@
 :|G|: `AlexeiFedorov`_
 :|M|: Chris Kay <chris.kay@arm.com>
 :|G|: `CJKay`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/extensions/amu/
 
 Memory Partitioning And Monitoring (MPAM) extensions
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Manish Pandey <manish.pandey2@arm.com>
 :|G|: `manish-pandey-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/extensions/mpam/
 
 Pointer Authentication (PAuth) and Branch Target Identification (BTI) extensions
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
 :|G|: `AlexeiFedorov`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/extensions/pauth/
 
 Statistical Profiling Extension (SPE)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Manish Pandey <manish.pandey2@arm.com>
 :|G|: `manish-pandey-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: lib/extensions/spe/
 
 Standard C library
@@ -361,6 +371,8 @@
 :|G|: `madhukar-Arm`_
 :|M|: Olivier Deprez <olivier.deprez@arm.com>
 :|G|: `odeprez`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: drivers/arm/gic/
 
 Message Handling Unit (MHU) driver
@@ -399,8 +411,8 @@
 :|G|: `sandrine-bailleux-arm`_
 :|M|: Manish Badarkhe <manish.badarkhe@arm.com>
 :|G|: `ManishVB-Arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
+:|M|: Harrison Mutai <harrison.mutai@arm.com>
+:|G|: `harrisonmutai-arm`_
 :|F|: drivers/measured_boot
 :|F|: include/drivers/measured_boot
 :|F|: docs/components/measured_boot
@@ -429,8 +441,8 @@
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
 :|G|: `sandrine-bailleux-arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
 :|F|: include/lib/psa
 :|F|: lib/psa
 
@@ -475,6 +487,8 @@
 :|G|: `manish-pandey-arm`_
 :|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
 :|G|: `madhukar-Arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
 :|F|: bl1/aarch32/bl1_context_mgmt.c
 :|F|: bl1/aarch64/bl1_context_mgmt.c
 :|F|: bl31/bl31_context_mgmt.c
@@ -493,6 +507,14 @@
 :|F|: include/services/arm_arch_svc.h
 :|F|: include/services/std_svc.h
 
+Live Firmware Activation Service
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|F|: services/std_svc/lfa
+:|F|: include/plat/common/plat_lfa.h
+:|F|: include/services/lfa_svc.h
+
 Platform Ports
 ~~~~~~~~~~~~~~
 
@@ -549,6 +571,8 @@
 :|G|: `manish-pandey-arm`_
 :|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
 :|G|: `madhukar-Arm`_
+:|M|: Harrison Mutai <harrison.mutai@arm.com>
+:|G|: `harrisonmutai-arm`_
 :|F|: plat/arm/board/fvp
 
 Arm Juno Platform port
@@ -587,18 +611,15 @@
 :|M|: Rohit Mathew <Rohit.Mathew@arm.com>
 :|G|: `rohit-arm`_
 :|F|: plat/arm/board/neoverse_rd/common
-:|F|: plat/arm/board/neoverse_rd/platform/rdn1edge/
 :|F|: plat/arm/board/neoverse_rd/platform/rdn2/
-:|F|: plat/arm/board/neoverse_rd/platform/rdv1/
-:|F|: plat/arm/board/neoverse_rd/platform/rdv1mc/
-:|F|: plat/arm/board/neoverse_rd/platform/sgi575/
+:|F|: plat/arm/board/neoverse_rd/platform/rdv3/
 
 Arm Total Compute platform port
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Vishnu Banavath <vishnu.banavath@arm.com>
-:|G|: `vishnu-banavath`_
-:|M|: Rupinderjit Singh <rupinderjit.singh@arm.com>
-:|G|: `rupsin01`_
+:|M|: Artem Kopotev <artem.kopotev@arm.com>
+:|G|: `artkopotev`_
+:|M|: Oleksandr Tarhunakov <Oleksandr.Tarhunakov@arm.com>
+:|G|: `o-tarhunakov`_
 :|F|: plat/arm/board/tc
 
 Arm Automotive RD platform port
@@ -915,15 +936,17 @@
 :|F|: docs/plat/socionext-uniphier.rst
 :|F|: plat/socionext/uniphier/
 
-Xilinx platform port
-^^^^^^^^^^^^^^^^^^^^
+AMD-Xilinx platform port
+^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Michal Simek <michal.simek@amd.com>
 :|G|: `michalsimek`_
-:|M|: Amit Nagal <amit.nagal@amd.com>
-:|G|: `amit-nagal`_
 :|M|: Akshay Belsare <akshay.belsare@amd.com>
 :|G|: `Akshay-Belsare`_
+:|M|: Maheedhar Sai Bollapalli <maheedharsai.bollapalli@amd.com>
+:|G|: `maheedhar-bollapalli`_
+:|F|: docs/plat/amd\*
 :|F|: docs/plat/xilinx\*
+:|F|: plat/amd/
 :|F|: plat/xilinx/
 
 
@@ -990,8 +1013,6 @@
 :|G|: `ManishVB-Arm`_
 :|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
 :|G|: `laurenw-arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
 :|F|: tools/cert_create/
 
 Encrypt_fw tool
@@ -1038,7 +1059,6 @@
 .. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
 .. _Akshay-Belsare: https://github.com/Akshay-Belsare
 .. _AlexeiFedorov: https://github.com/AlexeiFedorov
-.. _amit-nagal: https://github.com/amit-nagal
 .. _andersdellien-arm: https://github.com/andersdellien-arm
 .. _Andre-ARM: https://github.com/Andre-ARM
 .. _Anson-Huang: https://github.com/Anson-Huang
@@ -1078,7 +1098,6 @@
 .. _jcorbier: https://github.com/jcorbier
 .. _jenswi-linaro: https://github.com/jenswi-linaro
 .. _JiafeiPan: https://github.com/JiafeiPan
-.. _jimmy-brisson: https://github.com/theotherjimmy
 .. _joannafarley-arm: https://github.com/joannafarley-arm
 .. _jslater8: https://github.com/jslater8
 .. _jwerner-chromium: https://github.com/jwerner-chromium
@@ -1087,7 +1106,9 @@
 .. _laurenw-arm: https://github.com/laurenw-arm
 .. _leon-chen-mtk: https://github.com/leon-chen-mtk
 .. _linyidi: https://github.com/linyidi
+.. _loosper-arm: https://github.com/loosper-arm
 .. _madhukar-Arm: https://github.com/madhukar-Arm
+.. _maheedhar-bollapalli: https://github.com/maheedhar-bollapalli
 .. _manish-pandey-arm: https://github.com/manish-pandey-arm
 .. _ManishVB-Arm: https://github.com/ManishVB-Arm
 .. _marcbonnici: https://github.com/marcbonnici
@@ -1103,7 +1124,6 @@
 .. _MrVan: https://github.com/MrVan
 .. _Neal-liu: https://github.com/neal-liu
 .. _niej: https://github.com/niej
-.. _noncombatant: https://github.com/noncombatant
 .. _nmenon: https://github.com/nmenon
 .. _npoushin: https://github.com/npoushin
 .. _odeprez: https://github.com/odeprez
@@ -1116,7 +1136,7 @@
 .. _remi-triplefault: https://github.com/repk
 .. _rockchip-linux: https://github.com/rockchip-linux
 .. _rohit-arm: https://github.com/rohit-arm
-.. _rupsin01: https://github.com/rupsin01
+.. _o-tarhunakov: https://github.com/o-tarhunakov
 .. _rutigl: https://github.com/rutigl
 .. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
 .. _shawnguo2: https://github.com/shawnguo2
@@ -1131,11 +1151,11 @@
 .. _TravMurav: https://github.com/TravMurav
 .. _uarif1: https://github.com/uarif1
 .. _vijayenthiran-arm: https://github.com/vijayenthiran-arm
-.. _vishnu-banavath: https://github.com/vishnu-banavath
+.. _artkopotev: https://github.com/artkopotev
 .. _vwadekar: https://github.com/vwadekar
 .. _Yann-lms: https://github.com/Yann-lms
 .. _sjaypee208: https://github.com/sjaypee208
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.*

diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index dc2b2fd..0edd314 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst

@@ -74,6 +74,8 @@
 +-----------------+---------------------------+------------------------------+
 | v2.13           | 4th week of May '25       | 2nd week of May '25          |
 +-----------------+---------------------------+------------------------------+
+| v2.14           | 4th week of Nov '25       | 2nd week of Nov '25          |
++-----------------+---------------------------+------------------------------+
 
 Removal of Deprecated Interfaces
 --------------------------------

diff --git a/docs/change-log.md b/docs/change-log.md
index 721e0f3..c865c34 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md

@@ -3,6 +3,1203 @@
 This document contains a summary of the new features, changes, fixes and known
 issues in each release of Trusted Firmware-A.
 
+## [2.13.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.12.0..refs/tags/v2.13.0) (2025-05-14)
+
+The threat model for context management support is not available in the release.
+
+### âš  BREAKING CHANGES
+
+- **Platforms**
+
+  - **Arm**
+
+    - rename PLAT_MHU_VERSION flag
+
+      **See:** rename PLAT_MHU_VERSION flag ([a773955](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7739550946acc0f9fd9f3360738eb046057ce28))
+
+- **Bootloader Images**
+
+  - **BL32**
+
+    - **TSP**
+
+      - The prototype for `tsp_early_platform_setup` has been
+        redefined. Platforms must update their implementations to match the new
+        function signature.
+
+        **See:** cascade boot arguments to platforms ([32d9e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d9e8ec6c1f2889ffeb549007a7569754add5f1))
+
+- **Drivers**
+
+  - **Arm**
+
+    - **RSE**
+
+      - remove rse_comms_init
+
+        **See:** remove rse_comms_init ([91c7a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/91c7a952bedb34f1b4c691988f9da9af02209441))
+
+### New Features
+
+- **Architecture**
+
+  - **CPU feature like FEAT_XXXX / ID register handling in general**
+
+    - add support for FEAT_PAUTH_LR ([025b1b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/025b1b816b607c7ac43a77172040c44b7750a622))
+    - add support for PMUv3p9 ([ba9e6a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba9e6a342de0a8922d75559bc3c539a5174e2004))
+    - enable FEAT_BTI to FEAT_STATE_CHECKED ([10ecd58](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10ecd58093a34e95e2dfad65b1180610f29397cc))
+    - enable FEAT_PAuth to FEAT_STATE_CHECKED ([8d9f5f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d9f5f2586d32ca19c11f65f3c6954615f3efdf6))
+    - disable FPMR trap ([a57e18e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a57e18e4337b74ce3d133a18f07fa891f0fd5fa9))
+    - enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1 ([6b8df7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b8df7b9e5cc70ef0433a99bf73db6db6002482c))
+    - setup per world MDCR_EL3 ([c95aa2e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c95aa2eb0dc7471df5f2c7a3d1cf939046bc170e))
+    - add support for FEAT_SPE_FDS ([4fd9814](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fd9814f4865efdffca17b7bbfc8d4bd244866f3))
+
+- **Platforms**
+
+  - **AMLogic**
+
+    - **GXL**
+
+      - add support for booting from U-Boot SPL/with standard params ([8dca65d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dca65d96f787b6802b75bc72f830149293cbb6d))
+
+  - **Arm**
+
+    - add a macro for SPMC manifest base address ([eab1ed5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eab1ed54bfb6038a0c1ada79de409a5506e4dae0))
+    - add initrd props to dtb at build time ([1c08ff3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c08ff3277d47979c7897842ba683c23aa8197f7))
+    - add support for Transfer List creation ([4c5ccbf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c5ccbf43c1e34e3f2f71878f732efbe2449e9f6))
+    - convert arm platforms to expect a wakeup ([da305ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da305ec75dedca5e8e939790ab02fe7c0ba999d5))
+    - enable Linux boot from fip as BL33 ([eb8cb95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb8cb9534b58537e4ead8d1f8112ece45993c86d))
+    - migrate heap info to fw handoff ([ada4e59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ada4e59d166ab9fe7b039ed0f0b272398f71bdb9))
+    - port event log to firmware handoff ([b30d904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b30d9043be420f6a288687cf9f282d4e578f69aa))
+    - support AArch32 booting with handoff ([abdb953](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abdb953b00fff4aace32d9be10005b89751858d0))
+    - support boot info handoff and event log ([a852fa1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a852fa1d594f63bdc502a0c73eb77c5ce88aa02e))
+    - use provided algs for (swd/p)rotpk ([da57b6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da57b6e3cfdb36ad96d136d17ec3d300f699fee3))
+    - use the provided hash alg to hash rotpk ([d51981e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d51981e15dd8383d727bd15e718f657f2cd2aaf5))
+
+    - **FVP**
+
+      - add StandaloneMm manifest in fvp ([8416e79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8416e7917f9c82336e900659d35038942418582f))
+      - add stub function to retrieve DLME image auth features ([1733deb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1733deb46c02444febfd25e411d09b1888ba8a7b))
+      - add stub platform function to get ACPI table region size ([5d37755](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d377555e862dd07e11022ba0a70f0150e34454b))
+      - allocate L0 GPT at the top of SRAM ([7a4a070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a4a07078b3d15648c1cbbd9f309b0c11da56165))
+      - build hob library ([8740771](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/874077132cf9a0504cccde6651c5714fa97beb07))
+      - change size of PCIe memory region 2 ([2e55a3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e55a3d74d588780e04f1632c1b9d7ad33fb5f4f))
+      - define single Root region ([665a8fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/665a8fdf3aa372862d62c34d23ffd678798a265c))
+      - give bootargs on all configs ([a507f4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a507f4f5f07253986b585e03583d40a818ebc3fb))
+      - increase BL1 RW for PSA Crypto ([51bdb70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51bdb70fdb3719ad1eabb4e0d1037f4d89a552d6))
+      - increase bl2 mmap len for handoff ([24f7830](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24f78301288195f511528fc58b00e48f61933fa8))
+      - increase cactus-tertiary size ([dcd8d7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dcd8d7f13d5318ea3b38e6558c13e7401d57530c))
+      - increase GPT PPS to 1TB ([aeec55c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aeec55c8760f384bee46e1999287b0a757227c69))
+      - port event log to firmware handoff ([5bf0b80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bf0b80784e29e9e77edb26b605d2c1791ecded2))
+      - set defaults for build commandline ([bf9a25f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf9a25f075c4c94a3d47bc54c1a8a7b964444ff1))
+      - support AArch32 booting with handoff ([2ab298b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ab298b58bf3096f033ec922acc163c106118f62))
+
+    - **Neoverse-RD**
+
+      - deprecate and remove RD-N1-Edge platform variants ([71ad967](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ad967333a684f66eccd0de559ad2159ca9c1bd))
+      - deprecate and remove RD-V1 platform variants ([afb3075](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afb3075592bc8cc2f130f2ed6c5871a391bf0e56))
+      - deprecate and remove SGI-575 platform ([a023201](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0232015d089c0fca1e78b1d5fb9c8be61acca67))
+      - use larger stack size when S-EL2 spmc is enabled ([82f4659](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82f46593de26d758457391d8b5036abcc533c7e3))
+
+      - **RD-V3**
+
+        - add carveout for BL32 image ([6823f5f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6823f5f520e7dfcd0812bdf8d93deb8c770de5e8))
+        - add dts files to enable hafnium as BL32 ([4d9b828](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d9b8281f35256f7367a6b76b1259d9edbefe713))
+        - define SPMC manifest base address ([12973bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12973bcc89eff3a4bb4953061d48e8805b3c6079))
+        - enable the support to fetch dynamic config ([37cc7fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/37cc7fa539d9cfbbe1fefadb2346bc7415422fec))
+        - introduce platform handler for Group0 interrupt ([4593b93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4593b932396dca2ed945ab2c95c6cc6712c3eeeb))
+
+    - **TC**
+
+      - add 'kaslr-seed' node in device tree for TC3 ([2d967e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d967e92e00fe05f0c1ecaddf414d50078050f9d))
+      - add devicetree node for AP/RSE MHU ([06fa4c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06fa4c4df28165dbf1d08158d86ef9997f099ad6))
+      - add dsu pmu node for TC4 ([50ad0cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50ad0cfda371f520c3b0452af8955aac30634431))
+      - add MCN PMU nodes in dts for TC4 ([624deb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/624deb0825cf6b7e27165edf182bd075e58ee2ff))
+      - add SLC MSC nodes to TC4 DT ([99f6790](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99f6790cb9681d0a2960f8d30d82c20db19f6ab7))
+      - allow Android load and Boot From RAM ([932e64a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/932e64a1d79ef5ea7ed1525c45c9f11725ce5079))
+      - configure UART for TC4 FPGA ([84ca47a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84ca47a8ac03821cfd4dbe902c0ae71621e2f12f))
+      - define MCN related macros for TC4 ([8f61c20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f61c20457c8e683b9c6b2a3f3c4ebcf4b1a5371))
+      - enable Arm SPE for TC4 ([cea55c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cea55c836f205a988634c04416082e35ac350ff9))
+      - enable DSU PMU el1 access for TC4 ([00397b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00397b30b8da9489dd8ed5f51aa976bb34165a27))
+      - enable MCN non-secure access to pmu counters on TC4 ([d1062c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1062c472a2976a03c74479eb18327e46f604f6c))
+      - enable stack protector ([d1de6b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1de6b2b57d9e52c3b08c63ae4ce2d1e6703ce70))
+      - enable trng ([2ae197a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ae197acd6a91a96619090e503521d44bee494b2))
+      - fpga: Enable support for loading FIP image to DRAM ([969b759](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/969b7591dcd94b0380116d301c2ba463dd9bfd7c))
+      - get entropy with PSA Crypto API ([8f0235f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f0235fb8f2d46ee6ca6309f8c365ad57e3a1565))
+      - increase SCP BL2 size to support optimization 0 ([3755e82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3755e82c0f2c557d38dc4111f4ccd31a9394ee25))
+      - initialize MHU channels with RSE ([0328f34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0328f3422275a3d292c9025a1a1faaf9d54aa8d9))
+      - initialize the RSE communication in earlier phase ([a3f9617](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3f9617964ee30070855f9ba5e42ccb28dcc6a05))
+      - port BL1-BL2 interface to firmware handoff framework ([93c50ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93c50ae67fbdefd0fa2457a1b44fc538265b8fe0))
+      - port BL2-BL31 interface to firmware handoff framework ([2a36dee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a36dee8f158290cc30425df0753b6d887f12256))
+      - port BL31-BL33 interface to firmware handoff framework ([25a6bcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25a6bcd57104507c2f23760c2cc2ace43b5c00dd))
+      - print ni-tower discovery tree ([d87a856](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d87a8562306a46049560ba4387789918ecbca4b6))
+      - update CPU PMU nodes for tc4 ([1ce2c74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ce2c745a8b471dcc9e9f64e2163add566f5ce69))
+
+    - **Automotive RD**
+
+      - **RD-1 AE**
+
+        - add Generic Timer in device tree ([6e1bf7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e1bf7e97f7389f59c2ea0d28cfeef5399db7881))
+        - add support for OP-TEE SPMC ([8b27eb7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b27eb7d91d97d707af94fff11ea02963ee2c3c0))
+
+  - **Intel**
+
+    - add FDT support for Altera products ([29d1e29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29d1e29d7cb137311529603056ce36ff268f861c))
+    - add support for query SDM config error and status ([fcf906c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf906c90088227b51a526533e71f4c8cd879778))
+    - implementation of SiPSVC-V3 protocol framework ([204d5e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/204d5e67b90b9dfaf7d7e064c048b4587a73f965))
+    - provide atf build version via smc call ([d1c58d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1c58d86496164d701d3286786db73182925d0e9))
+    - support FCS commands with SiPSVC V3 framework ([597fff5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/597fff5f8739b29fb779075be216d16acc28ab58))
+
+  - **Marvell**
+
+    - add trng driver ([6d5fad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d5fad8d9ea4011fa49556592c7a4560e7206940))
+
+  - **MediaTek**
+
+    - add gic driver ([d905b3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d905b3df300c1a822e666c5d8bd903ce16f5d507))
+    - add UFS stub implementation ([57c7351](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57c7351545befba76ae4725ef602eca0491cc5ac))
+    - add vcp driver support ([a1763ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1763ae97eab53476eef556a068de4bdf36b737a))
+    - update mtk_sip_def.h ([ead2602](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ead26026ff9f877b65011de55e3b3874e14aa137))
+
+    - **MT8189**
+
+      - add GIC driver on MT8189 ([1d193f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d193f91ea89ad525acc9ec5d78084da445d3813))
+      - add GPIO support ([cecbb93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cecbb93c1e623f163621a97a2368c72ac9068bfb))
+      - add reset and poweroff function for PSCI call ([4e40a1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e40a1fdcf50dcfacd4331163f5a547d325714b3))
+      - disable L3C shared SRAM if the bootloader is coreboot ([7794e7c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7794e7c0b19f1fe470e62f59421d5770de1fcc95))
+      - enable cirq for Mediatek MT8189 ([83a5a0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83a5a0d1cc2d7cbb90ed9a11bb2b929a5f3b26e0))
+      - initialize platform for MT8189 ([6c60901](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c60901a4569ac2d7c5807158186d6701d3a2cf3))
+
+    - **MT8196**
+
+      - add APU kernel control operations ([5e5c57d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e5c57d52b1cfaec5182b2d01f804fae9ed54af4))
+      - add APU power on/off functions ([3ee4b2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ee4b2def6d1ee92dafb1730ff7852d8af532009))
+      - add APU power-on init flow ([0781f78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0781f7804a6922b3bb40f2b50880a9563e8ccd84))
+      - add APU RCX DevAPC setting ([f31932b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f31932b43087af86c56f919307a3ba4f7e994138))
+      - add APU SMMU hardware semaphore operations ([2d134d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d134d28f585f4bbcbf2e698443ab79b64128af2))
+      - add APUMMU setting ([e534d4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e534d4f633c30742ef7ced69abe077399b8eb5e6))
+      - add APUSYS AO DevAPC setting ([31a0b87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31a0b877566b0ebac6d11f2f8711cc11c0665e44))
+      - add CPC module for power management ([75530ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/75530ee280048a416844265f947d7a11b920d1f1))
+      - add DCM driver ([e578702](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e578702f71f99f728ca2406a89c1345132f44b78))
+      - add GPIO support ([4cb9f2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4cb9f2a5bf3a89d99f31505f830431e67a552709))
+      - add LPM v2 support ([da8cc41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da8cc41bc802555e15e280a7c7bf97bece8f69b3))
+      - add mcdi driver ([5cb0bc0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cb0bc07e3700ae9354e48adad8a990b02d7c80d))
+      - add mcusys moudles for power management ([95e974f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95e974fa15da2e5f5ff2e151d0d97390e483be98))
+      - add Mediatek EMI stub implementation for mt8196 ([39f5e27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39f5e2782061835650a80832a4a058921bd79568))
+      - add Mediatek MMinfra stub implementation ([4794746](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4794746eec6191563a97fec55c06027e42abe9bb))
+      - add mtcmos driver ([1f913a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f913a6e3a3eb6349db9a2263e15594c4dcd5766))
+      - add PMIC driver ([d4e6f98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d4e6f98d7f8b33ebd7706e8a440c568262500e21))
+      - add pwr_ctrl module for CPU power management ([4ba679d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4ba679da8b90ee15dd1234bc773854debb9b2466))
+      - add reset and poweroff function for PSCI call ([22d74da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22d74da7cd0132b3b40c2289a3cbd152e548632c))
+      - add SMMU driver for PM ([86dd08d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86dd08d838a6a49e7915df0f20c90c3a3e003056))
+      - add smpu protection for APU secure memory ([7ed4d67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ed4d67c6351e61dd5500a0887e4d5e85b8ab764))
+      - add SPM basic features support ([fb57af7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb57af70ae8c93ebe806eb6281036a15113dc4f5))
+      - add SPM common driver support ([a24b53e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a24b53e0e581cde7b5c43607ab76ded8336dc353))
+      - add SPM common version support ([5532feb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5532feb70c699c54a21b02fada8fed59a3992786))
+      - add SPM features support ([01ce1d5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/01ce1d5d2fedb4e7db2127286080f6495a5403cf))
+      - add SPMI driver ([adf73ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/adf73ae20a7aa6f8230cb7a19551edb239db8afe))
+      - add topology module for power management ([da54c72](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da54c7243618cbb21c5269cc153f4ac2508ee76f))
+      - add vcore dvfs drivers ([f0dce79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0dce79600f239d9c2f382ba4573aba5e5126001))
+      - disable debug flag in APU driver ([31137e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31137e1b1559b6e838e9a4e4b9f74a5473ba8837))
+      - enable appropriate errata ([0d11e62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d11e62e67deb9a898b2ac5e7fbda58408df371b))
+      - enable APU on mt8196 ([f5a6aa0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f5a6aa02a9332c42712c709c6017927b99ca04c2))
+      - enable APU spmi operation ([823a57e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/823a57e11cd98ee6043e9637ff3a4cf58feb60ff))
+      - enable apusys mailbox mpu protection ([83f836c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83f836c96238c0d0765d94cc1f8ed1c179d1878c))
+      - enable apusys security control ([9059a37](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9059a375eeb20c08cdcd5e604b9fd68b47a31e7e))
+      - enable cirq for MediaTek MT8196 ([49d8c11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d8c11285b28bddf9cdc7830ce039d4fc734f35))
+      - enable DP and eDP for mt8196 ([3e43d1d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e43d1d317fa0f4ba6fdfc95583b8e313333769d))
+      - enable IRQ configuration ([16f94b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/16f94b91f10a5f8d52b6eb16a685881c97f7df89))
+      - enable PMIC low power setting ([e8e8768](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8e87683f2b4d8213a84475e5f981961dcc8a16b))
+      - enable vcore dvfsrc feature ([a3c218a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3c218afd6596a46791b7f5d84a8d45d3c6977a0))
+      - fix MT8196 gpio driver ([6f891e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f891e68964888bb9d97f83600d85e606882a8d2))
+      - initialize platform for MediaTek MT8196 ([a65fadf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65fadfbbd5919939bfe367fe3f2d3c22ca4cbf0))
+      - link prebuilt library ([e033943](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0339436614a2b86cae04dabc74efdb31e2b0fb4))
+      - refactor LPM header include paths to use lpm_v2 ([6fac00a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fac00a49099beda9caeb66d8bc35b00f0f52f10))
+      - show ERROR log if need ([1ba50c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ba50c33fcdf10d2132d6d96a5238c378b57de2f))
+      - turn on APU smpu protection ([5de1ace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de1ace54a7088828dfaccd275ec2f1938ce7ee4))
+
+  - **NXP**
+
+    - **S32G274A**
+
+      - add console mapping ([a1e07b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1e07b399b5724e0d8f68a2e6ba6ce3102c2c424))
+      - dynamically map GIC regions ([5680f81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5680f81cecbbbb8a584dcf62bcb766a1cb25345f))
+      - dynamically map SIUL2 and fip img ([507ce7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/507ce7ed6f5c2c34a94f18c6d66db27b163e0f2a))
+      - enable MMU for BL2 stage ([eb4d418](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb4d4185fa67edb6d137a5f7a0eb5e209b4e6299))
+      - enable MMU for BL31 stage ([e2ae6ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2ae6ceccc6fc96debbfbacfb4b288cbf78da0f2))
+      - enable SDHC clock ([47b3a82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47b3a8251f1b7948360714254f8ec22b0e23875e))
+      - increase the number of MMU regions ([0089258](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/008925861f3d6b30722895bc9701b85ec3d81215))
+      - map each image before its loading ([34fb2b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34fb2b35b9996d2afe40ad52f3a004bb90bf95f2))
+      - split early clock initialization ([61b5ef2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/61b5ef21af8bcb38d3492e15d1d3d1fbecf3cf49))
+
+  - **QEMU**
+
+    - add hob support for qemu platforms ([648d2d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/648d2d8e2dab8cf939350a1788c5204751dcc9be))
+    - add plat_rmmd_mecid_key_update() ([9c9a31e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c9a31eb9ae36cab9db58ddc5d49f82ca3cf976d))
+    - hand off TPM event log via TL ([cc58f08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc58f08fe6a53ab375322dbdec6edbe5707110b8))
+    - update for renamed struct memory_bank ([991f536](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/991f5360b68d6cdfbda2950100dbf78ac1c482cc))
+
+    - **SBSA**
+
+      - add support for RME on SBSA machine ([acb0937](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/acb09373baa1f951b68168e044ddf94d299ef44f))
+      - adjust DT memory start address when supporting RME ([99bc6cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99bc6cf518c1d6c0995d53d00670c0ac972ea64d))
+      - configure GPT based on system RAM ([d079d65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d079d65d420d0f9edd4aa64b27305fc6537095da))
+      - configure RMM manifest based on system RAM ([fb4edc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb4edc35bc19e411ae566d1089198760042324eb))
+      - dissociate QEMU NS start address and NS_DRAM0_BASE ([26da60e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26da60e2a0e47768997b1b2079848beb9b5479c6))
+      - increase maximum FIP size ([122dbc2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/122dbc2c17494e96e7fd45ce6e03b68f8722585b))
+      - relocate DT after the RMM when RME is enabled ([17af959](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/17af9597e2b5d7cda2aaadad74b352e9805522d2))
+
+  - **QTI**
+
+    - platform support for qcs615 ([f60617d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f60617d3b1f9446d7f1528b3ac16fe6c4db9779d))
+
+  - **Raspberry Pi**
+
+    - **Raspberry Pi 3**
+
+      - add dTPM backed measured boot ([4f9894d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f9894db3572b6e375c7369bc2619cc690169604))
+      - implement eventlog handoff to BL33 ([6dfcf4e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dfcf4e1df3b4690fdf2629815d2a91294f34493))
+      - implement mboot for rpi3 ([c4c9e2b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4c9e2bc436198ee8f4544e8091c0067c4b4d9be))
+
+  - **Rockchip**
+
+    - increase FDT Buffer for Rockchip Devices ([ab99dce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab99dce4b7c8473d5bcb8c833bd410ab87b1e801))
+    - update uart baudrate for rk3399 ([6d7f1d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d7f1d4945ad3b85e33fb85eb7374d0fef2e9b64))
+
+    - **RK3576**
+
+      - support rk3576 ([036935a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/036935a8144b9c4b9f95f249ff4384945b846d40))
+
+  - **Socionext**
+
+    - **Synquacer**
+
+      - add support Hob creation ([357f28d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/357f28db6bcca7856a8cdbedfe6ce4668b06b48c))
+
+  - **ST**
+
+    - use dedicated version of DT for SP_MIN ([71ba164](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ba1647e09ca7ccecfeca417b22d1f7d023e338))
+
+    - **STM32MP1**
+
+      - rework SVC services ([39b08bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39b08bc366ff1bb08a2ab1dfd9c1eab3157fe16d))
+
+    - **STM32MP2**
+
+      - add a runtime service for STGEN configuration ([7f41506](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f41506fa7c10ba8cc393a9e67ae81bed379d07b))
+      - add common SMC runtime services ([f55b136](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f55b136abcdd2d6ba3bd5613eee8fff943de0fd1))
+      - add FWU support ([c28c0ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c28c0ca213147fff56555b038de8261fc5b92211))
+      - disable PIE by default on STM32MP2 platform ([ac9abe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac9abe7e597b1c5712a449b4a2366c859621e435))
+      - use USART1 for debug console on ultra-fly boards ([d59dd96](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d59dd96ddb2d58df989de07dc3d3fd86a1130652))
+
+  - **Texas Instruments**
+
+    - add support for TI mailbox driver ([9347ff4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9347ff4561e445d48839eac215cb452571cb8e54))
+    - introduce basic support for the AM62L ([21b14fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21b14fd2aef32cdb8e6304b0e1383157e651a86c))
+    - introduce PSCI Driver for AM62L ([1abdc20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1abdc20b35f7b39862f91dbf1dfb462872380f71))
+
+  - **Xilinx**
+
+    - **Versal NET**
+
+      - add SDEI support ([10510c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10510c98c7501a76af16f7345225cc4225ee2cda))
+
+    - **ZynqMP**
+
+      - add pin group for lower qspi interface ([fe81d9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe81d9c959968599db8b8a5b1f150224f3315a38))
+
+  - **AMD**
+
+    - **Versal Gen 2**
+
+      - add bufferless IPI Support ([af22b19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af22b19d6b9cc3985ca61c68eb1a364dff7c4874))
+      - add dependency macro for PM ([aec66c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aec66c38c72a71cd1d37926c29ce08a25823bf89))
+      - add support for platform management ([414cf08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/414cf08b76bcf7e8fdb841c3663716d151b133a8))
+      - extended SMCCC payload for EEMI ([0cc5e21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0cc5e2105564bbcf9fae8d39869d51fb6c58ba23))
+      - is OCM configured as coherent ([c3ab09d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3ab09d1c543bda64d543557556e8e03d2b26c32))
+      - retrieve DT address from transfer list ([ea45387](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea453871ef70c116d40c950926c3c1a2c4036896))
+      - update platform version to versal2 ([4003ac0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4003ac02eb4e5b0551614710f3e99a2e23cfe799))
+
+- **Bootloader Images**
+
+  - adding psa crypto - crypto_mod_finish() ([055c97a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/055c97afb2427092766687253d6ff851ee77455e))
+
+  - **BL32**
+
+    - enable r3 usage for boot args ([3fabca7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3fabca724a724266f41a210d377d79072b36e140))
+
+    - **TSP**
+
+      - cascade boot arguments to platforms ([32d9e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d9e8ec6c1f2889ffeb549007a7569754add5f1))
+
+- **Services**
+
+  - **FF-A**
+
+    - add FFA_MEM_PERM_GET/SET_SMC64 ([ddf72e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddf72e6a36bd6ef0958af5cfd638926861fe5c21))
+    - support FFA_MSG_SEND_DIRECT_REQ2/RESP2 ([09a580b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09a580b7961827501f94dd3dafbc27c7c5b69237))
+       ```
+       The FFA_MSG_SEND_DIRECT_REQ2/RESP2 early implementation in the EL3 SPMC is limited
+       to the use of 8 input/output registers per the SMCCC which isn't compliant to the
+       FF-A v1.2 specification mandating the use of 18 registers. This non compliance will
+       be fixed in the next release with the necessary versioning checks.
+       ```
+
+  - **RME**
+
+    - add SMMU and PCIe information to Boot manifest ([90552c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/90552c612e31ba88c6a7ad47c4081bc89d09c9c5))
+
+    - **TRP**
+
+      - test el3-rmm ide km interface ([8b3a89f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b3a89faddca3a955324adc4b48c864781e4c802))
+
+    - **RMMD**
+
+      - add FEAT_MEC support ([7e84f3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e84f3cf908c8eab1565b8e2d9a543e50de2e78e))
+      - add RMM_MECID_KEY_UPDATE call ([f801fdc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f801fdc22ef4fce3cc24fd1cbccde5772c15b633))
+      - el3-rmm ide key management interface ([2132c70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2132c707d73753338ce05f262843a91738177f5e))
+      - verify FEAT_MEC present before calling plat hoook ([609ada9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/609ada9691ca3793ad7203536fb4c95088bd3026))
+
+    - **RMM**
+
+      - add PCIe IO info to Boot manifest ([bef44f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bef44f60edaa763031bce6144c0267aefbb1f2bf))
+
+  - **SPM**
+
+    - use xfer list with Hob list in SPM_MM ([9ae5f67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ae5f67306b380c626a74782eff9e98b7f7996ee))
+
+    - **EL3 SPMC**
+
+      - ffa error handling in direct msg ([e1168bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1168bc37563d1f18d6d2a6dc4ed468eadf673f2))
+      - support Hob list to boot S-EL0 SP ([4053a64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4053a647f6eca71e5a34bc52303a049e3324ca90))
+      - use spmd_smc_switch_state after secure interrupt ([a0a7f15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0a7f158d2932117d57ec0d74113890a565e0cbc))
+
+    - **SPM MM**
+
+      - move mm_communication header define to general header ([b51436c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b51436c2ca4f1ceb2145dc752584df6ab1b77670))
+
+  - **DRTM**
+
+    - add platform API to retrieve ACPI tables region size ([7792bdb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7792bdbdf91a5854e580adea0f993886c3eec5df))
+    - ensure event types aligns with DRTM specification v1.1 ([8d24a30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d24a30d6073239a40eb835cb6014172080f2f06))
+    - introduce plat API for DLME authentication features ([0f7ebef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f7ebef73eb72f4627cf657fcb92f60c01001b41))
+    - log No-Action Event in Event Log for DRTM measurements ([2ec4488](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ec44880d0a47a60b851fea09b7bec0cd694e858))
+    - retrieve DLME image authentication features ([94127ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94127ae299aedf7642e598785c90961ab6e18266))
+    - update DLME data header with actual Event Log size ([9753238](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9753238fee94e97aff307a2c98d8e76bcbcfa211))
+    - validate launch features in DRTM parameters ([8666bcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8666bcfa75c2d7b80ccd0a92b252d5308e08216c))
+
+- **Libraries**
+
+  - **CPU Support**
+
+    - add ENABLE_ERRATA_ALL flag ([593ae35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/593ae35435f855ff3e48facc6a049261c0c37ea7))
+    - add support for Alto CPU ([940ecd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/940ecd072c695f51fc09eed1c13e50bbfa1690da))
+    - add sysreg_bit_toggle ([bb80185](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb801857eaf21365402a4748296c05cb3c6e861f))
+
+  - **EL3 Runtime**
+
+    - **RAS**
+
+      - add asynchronous error type corrected ([daeae49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/daeae495117e8e1496a44392217230ced17b39be))
+      - add eabort get helper function ([ec6f49c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec6f49c26be266e9d2b26818f35765ba9edd4e10))
+
+  - **HOB**
+
+    - copy StandaloneMm Hob creation library in edk2 ([2105831](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2105831848c4aef432f49e229c530cbda3489b10))
+    - introduce Hob creation library ([8953568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8953568a2db48032f2a2d4065e68fd1b20980caf))
+    - modify Hob creation code imported from edk2 ([6b68b4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b68b4a42f9858102f2c804026ed1ce136e15813))
+
+  - **PSCI**
+
+    - allow cores to wake up from powerdown ([2b5e00d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b5e00d4eacbac4b315c1c2925882d0b77bc9205))
+    - remove cpu context init by index ([ef738d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef738d19d3565e44ed44a6b06c6d9ab036322ac5))
+
+  - **ROMlib**
+
+    - add PSA Crypto ROMLIB support ([cf1b7fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf1b7fe657a3215423ab397363cc4fa1a0e6399f))
+
+  - **GPT**
+
+    - statically allocate bitlocks array ([b0f1c84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0f1c84035fb25e331b21f08f3f3e8e643c3394d))
+
+  - **SMCCC**
+
+    - add FEAT_TWED to ARCH_FEATURE_AVAILABILITY ([d33ff5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d33ff5e0eec0f90cf74a442fd83faec4a03ecde5))
+    - implement SMCCC_ARCH_FEATURE_AVAILABILITY ([8db1705](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8db170524de1eb83c21ee6344d628961f9b84456))
+
+  - **C Standard Library**
+
+    - import qsort implementation ([277713e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/277713e0ae3b9a20d661cbd9e214112f67bed35b))
+
+  - **PSA**
+
+    - add interface with RSE for retrieving entropy ([1147a47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1147a470c257403466cdbd55a13823ca1652063e))
+
+  - **Firmware Handoff**
+
+    - add 32-bit variant of ep info ([7ffc1d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ffc1d6cf3c3981d74a3ac830f8a57f953b4ff03))
+    - add 32-bit variant of SRAM layout ([8001247](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8001247ce267a583ae6a24a37a77f17427bd5204))
+    - add func to check and init a tl ([f1d9459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1d94593354a948dfc81ca569d4832afb20aaf41))
+    - add lib to sp-min sources ([79e7aae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79e7aae82dd173d1ccc63e5d553222f1d58f12f5))
+    - add Mbed-TLS heap info entry tag ([0e932b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e932b8563b6e25ae5f233a789cd420e46ae9297))
+    - add transfer entry printer ([937c513](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/937c513d5e8996d106e2661ea88786bde513ae74))
+    - common API for TPM event log handoff ([4d8b4ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d8b4ca0f5ab98e2d5d764a1530ae5fe55ba79bc))
+    - transfer entry ID for TPM event log ([9821775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9821775657a415aac4b1d1f9c66da6390a016934))
+
+- **Drivers**
+
+  - **Authentication**
+
+    - add crypto_mod_finish() function ([0331bd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0331bd22c6082776a3d82b3cd3a1e5771643562b))
+    - add update of current_pk_oid in auth ([9c18c35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c18c35cbb21632d817ed2650ce80e5d544cac3b))
+    - add util file for current pk_oid ([1716805](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/17168053b38878f700d5c4ac11421cb96a50bc1b))
+    - extend REGISTER_CRYPTO_LIB calls ([95d49c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95d49c624f7a7784db1af6bb4de2007d2f044d61))
+    - increase mbedtls heap for PSA RSA ([2ffc28c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ffc28c833337d72b32580178ace9b466c7ebc24))
+    - introducing auth.mk ([142ee34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/142ee34ea375479282d842e1905a61436e792cd8))
+    - mbedtls psa key id mgmt ([8a7505b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a7505b008c71e61fa4e4d2b973932ec5720d526))
+
+    - **mbedTLS**
+
+      - introduce crypto lib heap info struct ([24da55e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24da55eef7f032a8b4957fd9eb53dc3b87d01997))
+      - mbedtls config update for v3.6.2 ([c307efc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c307efce85cab2336ce0786b8ac46130508b8bfa))
+      - optimize SHA256 for reduced memory footprint ([b57468b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b57468b3d029cb123b7881cefc68290cdeb31d9d))
+      - update mbedtls to version 3.6.3 ([08f8c0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/08f8c0a503b5c61d32f07edc8dae1a8179a174cd))
+
+  - **I/O**
+
+    - add generic gpio spi bit-bang driver ([3c54570](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3c54570afca013e050db3d01a4c948ae938d908a))
+
+  - **Measured Boot**
+
+    - add fw handoff event log utils ([ca39163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca391636ada5a382e35bdc41b930b46852a822a1))
+    - make event log lib standalone ([cb03020](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb03020e20859e61e94a2cf6a3eda86f87e796e2))
+
+  - **TPM**
+
+    - add Infineon SLB9670 GPIO SPI config ([6fa56e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fa56e93679631b0d23c88e962b9e40c97971942))
+    - add tpm drivers and framework ([36e3d87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36e3d877cd6caf51155a74936f15b461cc9b814c))
+
+  - **Arm**
+
+    - **GIC**
+
+      - add support for local chip addressing ([c89438b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c89438bcea49bf9d265e6e17f1ef13e6cfc9f62b))
+
+  - **NXP**
+
+    - **Clock**
+
+      - add a basic get_rate implementation ([bd69113](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd691136639963b61c028e55d5889997430e7fa7))
+      - add base address for PERIPH_DFS ([29f8a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29f8a952cbbc7ee91188464cdf01b243735d41f8))
+      - add clock modules for uSDHC ([cf6d73d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf6d73d4c3b0fc4b299e6249f063b5adb5e3bedc))
+      - add clock objects for CGM dividers ([63d536f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63d536fe183bdf1c6ad99a5fd81cda7e2f32750f))
+      - add get_rate for clock muxes ([d1567da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1567da68d954be8f454ed641cbf7a08ca86f0bd))
+      - add get_rate for partition objects ([a74cf75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a74cf75f084e62888f57f7718f614bcd6e5eb50f))
+      - add get_rate for s32cc_clk ([46de0b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46de0b9c992fd4da90075b39ccff0a849a976301))
+      - add get_rate for s32cc_dfs ([2fb2550](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fb25509b800726342955194a0c6ac24299fb08e))
+      - add get_rate for s32cc_dfs_div ([8f23e76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f23e76fa5886ef9adbd867a546f291200fc2142))
+      - add get_rate for s32cc_fixed_div ([7c298eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c298ebcbf1003b98f815b86b2014112e89644d3))
+      - add get_rate for s32cc_pll ([fbebafa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbebafa518d5cbc69d0c64023f002ff6706019f2))
+      - add get_rate for s32cc_pll_out_div ([a762c50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a762c50579cb3bcae9c266e652c7c959e66fa943))
+      - dynamic map of the clock modules ([514c738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/514c738045b5c2de0f8e99b68830322af88dad4d))
+      - enable MC_CGM dividers ([2710bda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2710bdadc4cefd45bb7056c7e4c1e20dd1dfddc4))
+      - get MC_CGM divider's parent ([1586904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15869048b26f2ca2ebb78913ba1824532745744a))
+      - get MC_CGM divider's rate ([ad412c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad412c0d823ec1acad76f75419f40bdb09b2ad51))
+      - get parent for the fixed dividers ([35988a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35988a9db0aad69d068715ffe4d2f456aed5b508))
+      - get pll rate using get_module_rate ([43b4b29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43b4b29fb996ee05d2ca98c7f824d6a003342215))
+      - restore pll output dividers rate ([c23dde6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c23dde6c193d26fae9b2a8e18140b90faeba3661))
+      - set MC_CGM divider's rate ([f99078a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99078a6a09c09c93ac8f0aa679e1e85ab9658f3))
+      - set the rate for partition objects ([8501b1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8501b1fc60e3f6d01a38a3055dc0f274ecb039c6))
+
+  - **ST**
+
+    - **ST PMIC**
+
+      - add defines for NVM shadow registers ([c1222e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1222e7b8e635061690fe430e9213e86aae87920))
+
+- **Miscellaneous**
+  - add a generic EXTRACT macro ([f963578](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f963578b24906121b75375517f46c8d4d2a538fd))
+  - add EXTRACT_FIELD macro for field extraction ([af1dd6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af1dd6e1a58957dc04747b9c87f482166022265c))
+  - implement strnlen secure and strcpy secure function ([eb08889](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb088894dc9fb08eb3da82b86ebdabe82ae45940))
+
+  - **AArch64**
+
+    - add DBGPRCR_EL1 register accessors ([bdcef87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdcef87cf5e16896688ee69aef216f7929a065c5))
+
+  - **FDTs**
+
+    - **ST**
+
+      - **STM32MP1**
+
+        - **STM32MP15**
+
+          - add Linux Automation GmbH Fairy Tux 2 ([093c738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/093c738ab642005ca273aa6f21d306c81163012c))
+          - add Linux Automation GmbH TAC ([e67497f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e67497f9cc435e37c53b6a6361af3824247597df))
+          - add SP_MIN versions of DT files ([20544d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20544d66ccd53f8524d9d616fdab98dab88df37a))
+
+      - **STM32MP2**
+
+        - add LPDDR4 files ([64f82e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64f82e5a06cf4aeef9da40a8d503dc3f77cdb840))
+        - add STM32MP257F-DK board support ([6a9e5ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a9e5ffda76a7625786cfe6d4246dfdcb4a9f8f1))
+        - add dual-ranked LPDDR4 config for STM32MP2 ([99adf4d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99adf4d43e09915e190b645227f41fa3ea10dd51))
+
+        - **STM32MP25**
+
+          - enable WDQS for LPDDR4 ([29917d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29917d3a12c98ebe9776c3191cb699e1687771be))
+          - update 2GB DDR configs ([388cb47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/388cb47cf0275cfc435df305a75781f2cf5a5ca7))
+          - add support for STM32MP257D-based ultra-fly-sbc board ([a4e31cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4e31cf0d96438bca564e219490f55fa2e6abeb4))
+
+- **Documentation**
+
+  - update mboot threat model with dTPM ([b00f6ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b00f6ece560696a89bf2a91289ea9ef51a768c5d))
+
+- **Build System**
+
+  - rk3399: m0: add support for new binutils versions ([6fbec46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fbec46a59de301edd9ad63af3a8a007977173cf))
+
+- **Tools**
+
+  - **Secure Partition Tool**
+
+    - add StMM memory region descriptor ([3553087](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35530877967fd943186cd0afc895f71f0976bf23))
+    - add the HOB list creation script ([cc594af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc594af66e05b5f863b00dfab939f53e558d9c23))
+    - include HOB file in the TL pkg ([32ecc0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32ecc0ef781d44f462aaeb441458d72b7dd5023d))
+    - invoke the HOB list creation code ([2d317e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d317e80c201573e9a05472ac1c96b0e6fe6e3bf))
+    - populate secure partition number in makefile ([9327361](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93273613b48048a4a884770e292e765fa85e3ad7))
+    - specify endianness for HOB bin ([49c6566](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49c656633178d21679afd467e41f43a761d4238c))
+    - transfer list to replace SP Pkg ([0fe374e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0fe374ef046f70b6e990024922034d14d418b109))
+
+  - **Transfer List Compiler**
+
+    - add --align argument ([c4c8e26](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4c8e26a69411902516d394d8ca593db435c612b))
+    - formalise random generation of TEs ([157c619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/157c61978679ca7115e06df92d481b57fa2ae1ef))
+
+### Resolved Issues
+
+- **Architecture**
+
+  - **CPU feature like FEAT_XXXX / ID register handling in general**
+
+    - add support for 128-bit sysregs to EL3 crash handler ([58fadd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/58fadd62beba8e9fefddae884bfd34f71a183997))
+    - add feat_hcx check before enabling FEAT_MOPS ([484befb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/484befbfcbe5289fa237a96c36a2da75ff3ff2ba))
+    - avoid using mrrs/msrr for tspd ([f3e2b49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f3e2b499707c5cde85033c8ed16efe4f16de5231))
+    - improve xpaci wrapper ([787977c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/787977c3afe9d951a088a1f12959b00d8343a18d))
+    - include FEAT_MOPS declaration in aarch32 header ([8656bda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8656bdab57b22b5a65bb0480429553c084c1b0a6))
+    - replace "bti" mnemonic with hint instructions ([bdac600](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdac600bc8c61e2facdd0b872cacfb7a24045fe4))
+    - add a psb before updating context and remove context saving ([f808873](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f808873372381a401dcd86d7d45a5ee6fd164d50))
+    - add a tsb before context switching ([73d98e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/73d98e37593f4a4044dd28f52127cdc890911c0c))
+
+- **Platforms**
+
+  - **Arm**
+
+    - create build directory before key generation ([db69d11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/db69d118294f08aae86378c98aa082ac73e15b73))
+    - don't race on the build directory ([9855568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9855568cc5ab8af9a8bee54fcc35112240e16b28))
+    - reinit secure and non-secure tls ([2948d1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2948d1f81904f02034a0d12faf9b8c7f34b05795))
+    - resolve build issue with ARM_ROTPK_LOCATION=regs option ([4569a49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4569a496fd5b41b371c676b9313b796fe8bd27c2))
+    - resolve dangling comments around macros ([523c787](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/523c78704fabfd5f35f0e6abe6df2192d33a3c95))
+    - resolve misra rule R11.6 violation ([307a533](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/307a533301881869c0f54a5145a81a6a705156b9))
+    - update tsp_early_platform_setup prototype ([9018b7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9018b7b8401ab106228842140b53502ee64f1432))
+    - use EL3_PAS in MAP_BL2_TOTAL definition ([875423d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/875423de49646402cd6a7c1850f52982a3b56299))
+
+    - **Common**
+
+      - add missing curly braces ([7e288d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e288d11a5f155de4d6ad2ab9827fd71c0c9f74e))
+      - modify function to have single return ([50029b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50029b9ac3c60371f8606fb874df9038fb6839d0))
+      - remove platform_core_pos_helper() ([96e46f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/96e46f58d54a1a711bd7474a4ea949785119798e))
+      - remove fvp_r ([2cadf21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2cadf21bc8cc58e9ed8c7ae2af6089ffdb3d0a02))
+      - remove unused vfp code ([18b129f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18b129f4c1539444f9b91655d325a013264f7312))
+      - add missing curly braces ([0eeda63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0eeda638a8a6e8d9ff0448ba7405a8a5b86d17e0))
+      - ignore the unused function return value ([fc7a720](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc7a7208e0ccc0722bb29fcbb0cb7a3d74ff0953))
+
+    - **CSS**
+
+      - turn the redistributor off on PSCI CPU_OFF ([50009f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50009f61177421118f42d6a000611ba0e613d54b))
+
+    - **FVP**
+
+      - allow PSCI 0.2 in the device tree ([94b500d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94b500dcbb94b11c5b89657eda10e6f0b5fc87a1))
+      - exclude extend memory map TZC regions ([06cec93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06cec933def225ef64d81983829c349f47b89319))
+      - increase EventLog size for OP-TEE with multiple SPs ([d1a824e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1a824ea0e8887151d1237f3836e7e0df4d9e5bd))
+
+    - **Juno**
+
+      - resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1) ([dd566a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd566a9e565842eb97b6e14da63ba01d13d061ec))
+
+    - **Morello**
+
+      - remove stray white-space in 'morello/platform.mk' ([05533d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05533d99922f76af82b765159bb56e6592c09cf0))
+
+    - **Neoverse-RD**
+
+      - initialize CNTFRQ_EL0 for RESET_TO_BL31 ([94a4383](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94a4383a2b7de555ac68fc4f571d08105cdb3296))
+      - initialize timer before use in smmuv3_poll ([64ff172](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64ff172abe1edf333d41fb99aac1b4c50d85f248))
+      - set correct SVE vector lengths ([842ba2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/842ba2f22196beab45a581517ad43a6cdbf61d9a))
+
+      - **RD-N2**
+
+        - add LCA multichip data for RD-N2-Cfg2 ([289578e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/289578e610b6e4dfb62068a07bc56216e431fb17))
+        - correct RD-N2 StMM uuid format ([6fb8d8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fb8d8cf8427ebf2c63986ea3451ca835eac3aa2))
+
+      - **RD-V3**
+
+        - add console name to checksum calculation on RD-V3 ([222c87e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/222c87e75c747e4fb100a08910c5f870c473449d))
+        - add LCA multichip data for RD-V3-Cfg2 ([d0b93a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0b93a0dd04c755264355633cc77c8c1ea78ada4))
+        - correctly define plat_mboot_measure_key() ([fa0eb3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa0eb3cf5bab4cf86671a0ec3c7b0ceab33b7666))
+        - correctly handle FP regs context saving ([ac05182](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac05182df0b7c46c70faf92058063f8498a8624a))
+        - fix comment for DRAM1 carveout size ([4e2369c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e2369c707ba6ebd26810052532afa7d30cc4cc8))
+        - handle invalid build combination ([fe488c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe488c3796e01187fb6cffdd27a1bee1a33e0931))
+
+    - **TC**
+
+      - define status to fix SPM tests ([8d4d190](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d4d190915af07750cfc0c05b79c4ebd4bc1df4f))
+      - eliminate unneeded MbedTLS dependency ([22220e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22220e69f996b68c50dcc34cd05152a0fcb0e904))
+      - enable certificate on the last secure partition ([2e36131](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e361319ac1907009b42da657f7c55a50a9ccca0))
+      - enable Last-level cache (LLC) for tc4 ([7b41aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b41acaf72dc208601c315189756fdb9f24f4abf))
+      - fix compilation error ([26a520b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26a520b2befb310b9ee23da108854c9d9c294c11))
+      - fix SMMU streamId for tc4 gpu ([bf223c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf223c79377ed5d94f58acd2f354e8524ed6b1c6))
+      - map mem_protect flash region ([4bfe49e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4bfe49ec4eff17ded7f7b13fe4ceaa7307a78f92))
+      - modify DPU configuration in dts for TC4 FPGA ([bb9b893](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb9b89366f580d6166d0abcd4ae8b3c45943ca1c))
+      - modify ethernet configuration for TC4 FPGA ([8dec630](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dec63032e8d173215fc5a4b6540ecbc189cbf87))
+      - modify gpio controller base addr for TC4 FPGA ([5de9d79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de9d79bc4b2febe3b55db47039ab2004d8cd4af))
+      - modify mmc configuration for TC4 FPGA ([ba1faaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba1faaf117158dc1f1272192f3d8131421e96458))
+      - replace vencoder with simple panel for kernel > 6.6 ([1d2d96d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d2d96dd5cefdd8ae1872022d4b3b0d564188a29))
+      - set console baurate to 38400 for fvp as well ([5428938](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54289385f128e5ddad8d2f1be0d63a9edf685922))
+      - set system-coherency to 0(ACE-LITE) for tc4-gpu ([cada6ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cada6ca36c0a59a0050abf481ffa82a1838b1fe0))
+
+    - **Automotive RD**
+
+      - **RD-1 AE**
+
+        - fix rd1-ae device tree ([f72eeb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f72eeb2d227702817d38b44bec8ee988f30f1fb3))
+        - rename legacy MPAM build option ([7a5e580](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a5e580957a426ba4d4db2a07449a43d04628814))
+
+  - **Intel**
+
+    - add FPGA isolation trigger when reconfiguration ([6ce576c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ce576c63d6333261f48ecee301a11e77cc5f0d0))
+    - handle cold reset via physical reset switch ([bf3877e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf3877e072af2b718454e9ee1ee16d769980378e))
+    - redesign F2SOC bridge enable and disable flow for Agilex5 ([42e9062](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42e906205ecbb3e157a802a86ae98ef392a4b6eb))
+    - this patch is used to solve DDR and VAB ([458b40d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/458b40df58d60974f2f57017c8f17663e8e0973e))
+    - update debug messages to appropriate class ([a550aeb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a550aeb39460d34e5b75421639f54b215b46e616))
+    - update ssbl naming conventions ([bf2c213](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf2c213670feb2ecc6acc316be0c0342c5a5159f))
+    - update warm reset routine and bootscratch register usage ([646a9a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/646a9a16150066eaa3146d4e2819d589333b6454))
+    - add in support for agilex5 b0 jtag id ([8a0a006](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a0a006af3362a114ed899f2cfe6c2ef0ec84061))
+
+  - **Marvell**
+
+    - **Armada**
+
+      - don't race on the UART_IMAGE ([3395bd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3395bd12bcd7595b66902c0fc70ffee0a4681eea))
+
+  - **MediaTek**
+
+    - covert MTK_BL to uppercase for the build ([c710579](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7105798eda68240093d4c2bb34fcbc09f0ea587))
+
+    - **MT8189**
+
+      - fix mt8189 platform build failure ([49d8678](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d8678efbae57a2445af4c535f2ebd73dfb6b48))
+
+    - **MT8196**
+
+      - add whole-archive option to prebuilt library ([8f7d9bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f7d9bfa0a15d3063f9475da9c5e579ea935ac68))
+      - fix wrong register offset of dptx on MT8196 ([b38f8f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b38f8f7a3e2f4cdd323f195d2a17a6091aa75722))
+      - remove CPU_IDLE_SRAM_BASE entry from plat_mmap ([83f37d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83f37d998123f269e7ce901b190e016d52f9ebe3))
+      - remove EC_SUSPEND_PIN initial setting ([1185526](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11855267b55fb70522ed2ac015a6a0002641412e))
+      - remove SPM support for ES chip ([ee2e99c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee2e99c3e3fc8443bf48b05fe3776e3f2aaa6b23))
+
+  - **NXP**
+
+    - imx_trdc.h header guard ([2e9198d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e9198d0e0cbe9546348dd0a71ff6c3d2061d4eb))
+
+    - **i.MX**
+
+      - **i.MX 8M**
+
+        - fix imx8mq build break ([1b65be5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b65be5943fc4f6a0382d03a4ed7393b383e56a4))
+
+        - **i.MX 8M Plus**
+
+          - apply ERRATA_A53_1530924 erratum ([e6d39da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6d39da0473b84488dd012091c8deede0adc7d87))
+
+        - **i.MX 8Q**
+
+          - fix imx8mq build break due to hab ([3a36f70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a36f70ba02e88ed20083c1278a739c6c870aae0))
+
+      - **i.MX 9**
+
+        - **i.MX93**
+
+          - trdc: restrict BLK_CTRL_S_AONMIX to secure world ([c6bf928](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c6bf92894c6c7096e380fe60c0e57b3db87ea0c7))
+
+    - **S32G274A**
+
+      - reduce the uSDHC clock to 200MHz ([9c640e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c640e09a86bdcc4cf77233c71b2ac0d36b7f9d1))
+
+  - **QEMU**
+
+    - fix register convention in BL31 for qemu ([7ad6775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ad6775bde8fb719ab94ab7d47736fd2dd66cddc))
+    - fix RMM manifest checksum calculation ([d08dca4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d08dca4263e5286b7f9b36612dae5767aac74a63))
+    - ignore TPM error ([ddb5e2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddb5e2fd12a759270dd3566d086bbb91076ae0ae))
+    - statically allocate bitlocks array ([a32a77f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a32a77f9c7567141556a823c0b9d4d5488c95722))
+
+    - **SBSA**
+
+      - fix compilation error when accessing DT functions ([33ac6f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33ac6f99abcbb2d3b8303af5194390cafb4e6853))
+
+  - **QTI**
+
+    - **MSM8916**
+
+      - update tsp_early_platform_setup prototype ([2f02426](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2f024262e986f241fed5dbadbb7f0ab68165bb74))
+
+  - **Raspberry Pi**
+
+    - **Raspberry Pi 3**
+
+      - expose BL1_RW to BL2 map for mboot ([9acaade](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9acaaded3ca9b6966efb72e3a989f8ee753b3a44))
+      - use correct name for include guards ([5c0cbb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c0cbb2faaa0ddfbe7c36d037918fbda13a661f6))
+
+  - **Renesas**
+
+    - **R-Car**
+
+      - use platform_def ([99fe5c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99fe5c2fd531298457214a61dafcfae15053e900))
+
+  - **Rockchip**
+
+    - pmu: Do not mark already defined functions as weak ([7f25d3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f25d3cc782337ce2fd445d39cbe295090beb5c9))
+
+    - **PX30**
+
+      - remove unused function ([ce66647](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce666476812099bc5e27dcc1d336e712e0cd78fb))
+
+    - **RK3288**
+
+      - remove unused function ([6e38cc9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e38cc97df86ac1c45aacc9ce301f6df1fc72056))
+
+    - **RK3399**
+
+      - dram: Fix build with gcc 11 ([f86c230](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f86c230ab02ce94d54866c072e8c118095a8783e))
+      - fix unquoted .incbin for clang ([ddd70f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddd70f199bd0b09a229aa624497b86dbff5b8db5))
+      - m0: Makefile: fix outside array bounds warning ([5049f91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5049f910aec254b9656dafe6c4cf7dd3d8b91d5c))
+      - mark INCBIN-generated sections as SHF_ALLOC ([279cad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/279cad8ed38c186aebce3502f9f1ebc52e22b281))
+
+    - **RK3588**
+
+      - pmu: fix assembly symbol redefinition ([f879388](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f879388831795c948c7d5954d5ea6b1c224e6e08))
+
+  - **Socionext**
+
+    - update tsp_early_platform_setup prototype ([c45dbe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c45dbe7e5d28da67f831159830cdc835095b142b))
+
+  - **ST**
+
+    - **STM32MP2**
+
+      - correct early/crash console init ([23647bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/23647bd52c805594050c5cd0e387389760778492))
+
+  - **Texas Instruments**
+
+    - fix UNUSED_VALUE in AM62L PSCI Driver ([32302b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32302b44abc3a725b4197cec8f1411d8320542d9))
+
+  - **Xilinx**
+
+    - avoid unexpected variable update ([b3d25dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b3d25dca86ad438423e2554b0c72ea8e429c30fb))
+    - dcc console tests failing ([e14ae4b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e14ae4b30175d6c9877fd33497d43a8895f5b3d9))
+    - modify function to have single return ([906d589](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/906d58927760c70112fd8e70a7e67f2a4989e9ed))
+    - remove unused write_icc_asgi1r_el1() ([1c12cd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c12cd10fc4662141777f5b0fc0fbac2d00f50c3))
+    - resolve misra rule 10.3 violations ([72eb16b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72eb16b7f8d679e9da960185904e6e608d5c5a5c))
+    - resolve misra rule 10.4 violations ([bdba3c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdba3c84baa5c595e504ef2902832d04102a223a))
+    - resolve misra rule 11.3 violations ([c35fe29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c35fe2946b6e2b1e4e3fcf845289bcea791eb60a))
+    - resolve misra rule 14.4 violation ([a5d5cb3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5d5cb3cfc83928bee0a00dd987f2731e1b8ec56))
+    - resolve misra rule 15.7 violations ([fd44cc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd44cc7e9b660a8baae2e8a0d3a2b3efde2e2c7e))
+    - resolve misra rule 2.2 violations ([e5adcfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5adcfcdd143660bb9c3d56a44a42621066fca59))
+    - resolve misra rule 2.3 violations ([09abae0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09abae060d5c65ec8cb7a42a5ac75fa30eb1aabc))
+    - resolve misra rule 2.7 violations ([d87b0ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d87b0ce30189cf692a6a6e21393bde0ac5029780))
+    - resolve misra rule 8.3 violations ([3df32f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3df32f852400be6d4c1f3199c89d9f36169ede71))
+    - resolve misra rule 8.4 violations ([4b4080d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b4080d78637fd0f071e0d6860114eb9ea16dea5))
+    - resolve misra rule 8.6 violations ([eec03e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eec03e947b3855c0a19bb64d39b4627e253a22b5))
+    - runtime console to handle dt failure ([0791be8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0791be881388c32c13b5ed9e79dc640aeefaaab4))
+    - typecast expression to match data type ([50ab135](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50ab13577fd533ab99c874772e6630929506229c))
+    - typecast expressions to match data type ([83bcef3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83bcef3f509d77582e4534f75ca2b4fd3ea4ffee))
+    - typecast operands to match data type ([3a1a2da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a1a2dae10ef3058e3973715fc4406544ff4aad7))
+    - typecast operands to match data type ([7d15b94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d15b94ba3d7160c79c5c3229015f7e9373490ff))
+    - update tsp_early_platform_setup prototype ([470dd8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/470dd8b49dab7211ca425f16fd94e8c18bbd37bf))
+
+    - **Versal**
+
+      - add unsigned suffix to match data type ([4b23240](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b2324042a292d6e1bd877daaf91c05dc888a926))
+      - handle invalid entry point in cpu hotplug scenario ([435bc14](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/435bc14a94008ab811ebac2735875a99ea6e464c))
+      - modify function to have single return ([890781d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/890781d10ce362150359c00b06c8b7e9e1ee34d2))
+      - typecast expressions to match data type ([b802b27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b802b2784c8bcaae56d450ab55ee305880293c85))
+      - typecast operands to match data type ([8e4d5c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e4d5c6db0e462ea33db2eaee4229583ace6cd6f))
+      - typecast operands to match data type ([9b89de5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b89de5fc4aa22e0cdc8e9f216135041549bbdff))
+
+    - **Versal NET**
+
+      - add missing curly braces ([9334fdf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9334fdf9718fed0f98a990f2f7f43cc40426b6dc))
+      - add unsigned suffix to match data type ([baeeadd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/baeeaddff4840028d627f21af64e6397da88a058))
+      - enable PSCI reset2 interface ([5f22f57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f22f573adbbcb30b7e1793fdcc1ba7c88eceff0))
+      - handle invalid entry point in cpu hotplug scenario ([e5e417d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5e417ddecfaedd875adf47de4ad1396dd514ab9))
+      - modify function to have single return ([5003a33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5003a332b8e40ff93333b70a4365c1e13e8b1d10))
+      - remove_redundant_lock_defs ([19799fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19799fd8fb318682a8169d5e4fc32e41ae50c0b1))
+      - typecast expressions to match data type ([3cbe0ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3cbe0ae5b8b2f79fe87c73d160ef7e33603ae604))
+      - typecast operands to match data type ([d51c8e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d51c8e4c654a27e7487b7d15a64cec6f5eeab4e5))
+      - typecast operands to match data type ([3dc93e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3dc93e5139b262ff099c450d82433180b802a484))
+
+    - **ZynqMP**
+
+      - add missing curly braces ([e4a0c44](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4a0c44f690d0658310914bcb5ae2355808a17b7))
+      - align essential type categories ([1877bf2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1877bf2ce18092259cace97cec41ea32a97a8ed7))
+      - fix length of clock name ([f535068](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f535068c84c00da3d4af40d6b571d9df39e07264))
+      - fix syscnt frequency for QEMU ([55ae162](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55ae162fd521cbe2ba500570692785159777a0ff))
+      - handle invalid entry point in cpu hotplug scenario ([df44616](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df44616a12096c16dd497646fc06684bdc818760))
+      - modify function to have single return ([3f6d479](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f6d47945a4bd94eae2d6ad17f50b59cda551c10))
+      - typecast expression to match data type ([e2cc129](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2cc129bcc58234dcb4607fe9264c1bdf4b282ea))
+      - typecast expressions to match data type ([895e802](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/895e8029aa1f88da164966504be8fc8120c9f7a5))
+      - typecast operands to match data type ([6ae9562](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ae9562473812cce8d97f3a3f2a8ae7aafa75201))
+      - typecast operands to match data type ([2863b0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2863b0c46633d28a920ef14c68ee4a6e4842ab0b))
+
+  - **AMD**
+
+    - update transfer list args for OP-TEE ([573ec22](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/573ec2287eb616d1629b2c32fb28e894d852a78b))
+
+    - **Versal Gen 2**
+
+      - add missing curly braces ([9f51da5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9f51da5e2e6fcd81b22fb1c7f5cd5712bdc6cb3b))
+      - align QEMU APU GT frequency with silicon ([f7a380e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f7a380e23ce8c7e4835367ee71af0bdeb505baa7))
+      - enable system reset ([058edb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/058edb8fcd7d32346bda0e43389cd0903074034a))
+      - modify function to have single return ([fb2fdcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb2fdcd9536874aaff0c14f9c466214e717b0e91))
+      - pass tl address to bl32 ([1fb3446](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1fb3446ed230c1011c982eb0bf62214f8abd38b2))
+      - rename console build arg to generic ([2333ab4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2333ab4cd214150ac099ba0894bb6d1c3963d945))
+      - typecast expressions to match data type ([fbc415d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbc415d2046ca6e940323a88252fd40a68bebec4))
+      - typecast operands to match data type ([07be78d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07be78d500aaabf2401bb4b31eb3b40b677fa110))
+      - update DDR address map ([66569a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66569a76880ceb6c02fbcfe993584c67336df353))
+      - update transfer list as optional ([5cb9125](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cb9125e9654e374dff4f322c3bbaef59511fcda))
+
+- **Bootloader Images**
+
+  - **BL1**
+
+    - prevent null pointer dereference ([2d3b44e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d3b44e3073e8d6ec49dde45ec353d6f41290917))
+
+  - **BL31**
+
+    - add const qualifier ([e358089](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e358089d8382e4239a4b606b0e97cf5475da4976))
+    - add missing curly braces ([88edd9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88edd9c6a09cc867ea377c7ad968e6a17595acf5))
+
+  - **BL32**
+
+    - **TSP**
+
+      - use %u to display unsigned values ([3b06438](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b06438dd1e038a7453d3b812ca6ef2da54f6ba8))
+
+- **Services**
+
+  - avoid altering function parameters ([1a0f565](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a0f565b6240392ccb6982a15098ec288df7ea94))
+
+  - **RME**
+
+    - do not trap access to MPAM system registers in Realm mode ([d048af0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d048af0da1022a844e153093395087c724f12e40))
+    - map DEVICE0_BASE as EL3_PAS ([b577248](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b57724806143e36ae17be7e33e5792863c5c026c))
+    - remove ENABLE_PIE restriction ([e126ed1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e126ed1ae7d498110b349be5f0bbd40e3bdc32ba))
+
+    - **RMM**
+
+      - add support for BRBCR_EL2 register for feat_brbe ([41ae047](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/41ae04735284f7c97a3993dc6d2d45de3954c2b7))
+
+  - **SPM**
+
+    - **EL3 SPMC**
+
+      - fix FF-A v1.2 version check ([6feaad6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6feaad6c6e36f3bd92dd7181f08b2abc87f54240))
+      - move ERROR line inside conditional ([bbf28dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bbf28dc37d50ea8a5bf40ab3fcc2f529cbb1e024))
+
+    - **SPMD**
+
+      - check pwr mgmt status for SPMC framework response ([8723eaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8723eaf2fea9d09526fd7e6bc544b9c3103240ac))
+      - fix build failure due to redefinition ([a869e2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a869e2dc4549e86465d485d9ec5d1c18d21c10be))
+      - prevent SIMD context loss ([8f60d99](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f60d99f44f3f75108f7cf707e8d1c8f6ef33be0))
+
+    - **SPM MM**
+
+      - prevent excessive racing ([48426cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48426cff7250486b9a00a2e0e69d53cb5ae6e413))
+
+  - **DRTM**
+
+    - add missing DLME data regions for min size requirement ([a65fa57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65fa57b129713ddaa3cdff048921368f9dacc2e))
+    - adjust Event Log size in DLME ([63d2020](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63d2020f577aadb9f600a7f1a525d427117fd11d))
+    - fix DLME data size check ([28e8f9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28e8f9d93329b45e8dc9bf6ee1f3d14bde9adda2))
+    - sort the address-map in ascending order ([7cf3784](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7cf37848140d3ba29b5967b46acbc5464b0b04b0))
+
+  - **TRNG**
+
+    - allow FEAT_RNG_TRAP in dynamic fashion ([bc30945](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc30945bb660c5be04d82bfa95f5b9caaffba3ef))
+
+  - **ERRATA ABI**
+
+    - add support for handling split workarounds ([bbff267](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bbff267b6f2777483a37781850dd1be01c16b937))
+
+- **Libraries**
+
+  - **CPU Support**
+
+    - add missing add_erratum_entry ([a74b009](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a74b0094163b0efc5525131c5b807aaea2591e9e))
+    - avoid SME related loss of context on powerdown ([45c7328](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45c7328c0b94d043745b4a44c2e14e1a77f5c347))
+    - clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset ([c9f352c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9f352c362a8d114a055bb9206c5b6391ec3b96a))
+    - declare reset errata correctly ([5cba510](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cba510ee31c520c6bd3254a4fd791d411d02152))
+    - drop esb from the Neoverse N1 ([e75eea7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e75eea749a59ba67c3eb3dfba41bd8d6770cc708))
+    - fix a typo in errata doc ([845213e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/845213ed0ddb08be79f621990db1314f4988d2e5))
+    - fix clang compilation issue ([bdaf0d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdaf0d9ba71c1fd17f5d35f8fd2a6205136116a3))
+    - remove errata setting PF_MODE to conservative ([ac9f4b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac9f4b4da6f6ef695a25aa2ed525281a89d40bf9))
+    - workaround for accessing ICH_VMCR_EL2 ([7455cd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7455cd1721ec3b8671d6a2fae879f86ecfe497fb))
+    - workaround for Cortex-A710 erratum 3701772 ([463b5b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/463b5b4a46552887c4fb70536d20f315f889add1))
+    - workaround for Cortex-A715 erratum 2804830 ([fcf2ab7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf2ab71ac00122bd382973f6e9f08e30b7eca80))
+    - workaround for Cortex-A715 erratum 3699560 ([26437af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26437afde1e7c16a5a05b8c7e0bb062efe63c3cf))
+    - workaround for Cortex-A720 erratum 3699561 ([050c4a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/050c4a38a335c721c2f6ce38c33f1aa6aa328800))
+    - workaround for Cortex-A720-AE erratum 3699562 ([af5ae9a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af5ae9a73f67dc8c9ed493846d031b052b0f22a0))
+    - workaround for Cortex-A725 erratum 3699564 ([d732300](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d732300b86238ac7166bc9bebd667a24dc3ed062))
+    - workaround for Cortex-X2 erratum 3701772 ([ae6c7c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6c7c97d4e0f491854b34628e0fa1038668f8e4))
+    - workaround for Cortex-X3 erratum 3701769 ([77feb74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77feb745e42296c553c33bcaea5be3304168eff3))
+    - workaround for Cortex-X4 erratum 2923985 ([cc46166](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc46166144b9a3746807f1d137ff784da3013e26))
+    - workaround for Cortex-X4 erratum 2957258 ([09c1edb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09c1edb84b9d2e91ce425b4300042751b3899434))
+    - workaround for Cortex-X4 erratum 3701758 ([38401c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38401c5388b5c3127745b758b3dc939d27041d7d))
+    - workaround for Cortex-X925 erratum 2963999 ([29bda25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29bda258d5655d2ac24dda0f73e6b0ec93c3037e))
+    - workaround for Cortex-X925 erratum 3701747 ([511148e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/511148ef5077dfb8f6bc7b9655e4ac19e16c4af0))
+    - workaround for CVE-2024-5660 for Cortex-A710 ([0d7b503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d7b503f8a11237fa129ae7baa2d979d64b9ab68))
+    - workaround for CVE-2024-5660 for Cortex-A77 ([aed3e8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aed3e8b59a034ddcd073f2295cf0ae70a313ccf5))
+    - workaround for CVE-2024-5660 for Cortex-A78 ([c818bf1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c818bf1d60c01e1a8953bf0051987dea4db7c4bf))
+    - workaround for CVE-2024-5660 for Cortex-A78_AE ([902dc0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/902dc0e01ffc5f215eabde8e0428ce462db18a73))
+    - workaround for CVE-2024-5660 for Cortex-A78C ([46a4cad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46a4cadb9d63f4265756d82c9e252d7760c43ae8))
+    - workaround for CVE-2024-5660 for Cortex-X1 ([26293a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26293a746319e7073dd3699be0afcd2277ad1999))
+    - workaround for CVE-2024-5660 for Cortex-X2 ([5b58142](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b58142c460b9d28740c610d51023a444583a10e))
+    - workaround for CVE-2024-5660 for Cortex-X3 ([b0d441b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0d441bdadae3b38e3a670e03341603785b39f3c))
+    - workaround for CVE-2024-5660 for Cortex-X4 ([af65cbb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af65cbb9549765917cf79ab0a819fe58773882ab))
+    - workaround for CVE-2024-5660 for Cortex-X925 ([ebc090f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ebc090fbf47a25a1ef84657d03198fc3a29d28e3))
+    - workaround for CVE-2024-5660 for Neoverse-N2 ([26e0ff9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26e0ff9d5e99b2ea0eedfd202401655ee404e52f))
+    - workaround for CVE-2024-5660 for Neoverse-V1 ([85709f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85709f66194cef32377a32f8e153316648ebb4a9))
+    - workaround for CVE-2024-5660 for Neoverse-V2 ([878464f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/878464f02a043207f29282f05109012152df569b))
+    - workaround for CVE-2024-5660 for Neoverse-V3 ([ad3da01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad3da019904302d9ecfc2cf50dfdd6d672427b5d))
+    - workaround for Neoverse-N2 erratum 3701773 ([adea6e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/adea6e52a782eeabd9027e3ca9a9847a13453cfa))
+    - workaround for Neoverse-N3 erratum 3699563 ([fded839](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fded839285bdbdb72d492a573274abe22edc9311))
+    - workaround for Neoverse-V3 erratum 2970647 ([5f32fd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f32fd2145020b0007b3f12ae6a95b734ff8e6a2))
+    - workaround for Neoverse-V3 erratum 3701767 ([e25fc9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e25fc9df25092be31e7f7a9cc740e8df661a35c1))
+    - workaround for Cortex-A510 erratum 2971420 ([f2bd352](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f2bd35282066f512c26d859aa086cff13955d76b))
+
+  - **EL3 Runtime**
+
+    - add const qualifier ([54c9c68](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54c9c68a49bc7b3aaa29207f798b1973e3cdb542))
+    - add missing curly braces ([858dc35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/858dc35cfde12ddf6250ed393298fa85d01b77d5))
+    - for nested serrors, restore x30 to lower EL address ([0bc3115](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bc3115f6e7b857344c6ac034d74b0fe81d216ed))
+    - replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR ([c722003](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c72200357aed49fd51dc21e45d4396f5402df811))
+    - make sure LTO doesn't garbage collect the handlers ([f8d2a0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f8d2a0e5caa1b57edf9f7a8e09f9c438a7f3b4be))
+
+    - **Context Management**
+
+      - change back owning security state when a feature is disabled ([13f4a25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/13f4a25251cc6ce0230e999f39a4668cff25dcd0))
+      - don't access a field that doesn't exist ([600717f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/600717fe5909e02a9ec9ee08bcb921a66e653d58))
+      - fix context management SYSREG128 write macros ([6595f4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6595f4cb393090992733eb5e73928424b1e9395a))
+
+    - **RAS**
+
+      - fix status synchronous error type fields ([9c17687](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c17687aabc9e64a26575d5662ef273185d9d275))
+      - fix typo in uncorrectable error type UEO ([e5cd3e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5cd3e81d11cb7f9439e5077cf9063e30fc8c2ae))
+
+    - **SIMD**
+
+      - fix base register in fpregs_context_* ([09ada2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09ada2f8d63fabd1bb01494c2466f647441107b1))
+
+  - **PSCI**
+
+    - add const qualifier ([7b97084](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b970841ad1c9925e72c170734ca30016813743d))
+    - add missing curly braces ([c7b0a28](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7b0a28d32ba78a1bec8fe1f9edbcdc215bf7b1a))
+    - avoid altering function parameters ([e64cdee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e64cdee4dad610e8f4efb873e133a5fffdea397c))
+    - check if a core is the last one in a requested power level ([71d4e03](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71d4e03444f689210803323b437ee15d537fc6ea))
+    - initialise variables ([382ba74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/382ba743a81c9b61d2ab794a22e37af0ac6128fe))
+    - modify variable conflicting with external function ([0839cfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0839cfc980998d24740e41b44164de39b70079a1))
+
+  - **ROMlib**
+
+    - romlib build without MbedTLS ([e4a070e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4a070e3d6dd0af0e74184333b9238e70c9a7075))
+
+  - **SMCCC**
+
+    - properly set RAS feature bit ([04b80c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04b80c187db3e8d5f0aec6987f1cb2fca2df952d))
+    - register PMUv3p5 and PMUv3p7 bits with the FEATURE_AVAILABILITY call ([2bec665](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2bec665f464b1c211eac594b333656b1dfa4b3da))
+
+  - **Translation Tables**
+
+    - zeromem to clear all tables ([aaacde4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aaacde46826df1dd4a119b2a31ff626adbce5653))
+    - remove xlat_mpu ([23302d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/23302d4a53700a7e6b80a897626bee0d67fad028))
+
+  - **C Standard Library**
+
+    - add const qualifier ([b71d082](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b71d0827aeef53d0ad561da212a7deb102f48c45))
+    - explicitly check operators precedence ([277d7dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/277d7dd6c192f350bc80ccbb65c36562e59f8e07))
+    - make sure __init functions are garbage collected ([53644fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53644fa8221b5c7b726beeda78b253f39abe479b))
+    - remove __Nonnull type specifier ([7ce483e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ce483e17cf14ee285a348d0f0081c89793d010b))
+    - typecast expressions to match data type ([dd0d433](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd0d433197d470e1f50ab28f128ff336e021799f))
+    - typecast operands to match data type ([26cc285](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26cc2854609978fcd6b0450e750b3b319b2468fa))
+
+  - **Locks**
+
+    - add missing curly braces ([bd7ad5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd7ad5e684aafd12c9c5873e4776c4a14e5e5dc0))
+
+  - **PSA**
+
+    - guard Crypto APIs with CRYPTO_SUPPORT ([8a41106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a41106c83961029c2d251f390c091d398c100a6))
+    - increase psa-mbedtls heap size for rsa ([52d2934](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52d293456097beef6a3346b244d4e84f78ef2615))
+
+  - **Firmware Handoff**
+
+    - correct 8-bit modulo csum calculation ([5ca0241](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ca0241c7ac7fc07188281058e052044e8f9ec36))
+    - fix message formatting of hex values ([24e1ae2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24e1ae2f0ed3e2c2be680aad6e88313661bf57ee))
+    - fix register convention in opteed ([c0688c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0688c55bb8b924f1b660ffca1b33bd65cab9990))
+    - remove XFERLIST_TB_FW_CONFIG ([18be2db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18be2dbe001162b424e52072dee74c9b7613a4f2))
+
+- **Drivers**
+
+  - **Console**
+
+    - add missing curly braces ([9ded5e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ded5e8d8be4a5f1f3219742c3790c13156378d8))
+    - typecast expressions to match data type ([97eefd9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/97eefd9989aeb2ce2093e873ceab535df9559a59))
+
+  - **Delay Timer**
+
+    - create unique variable name ([472cccb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/472cccb5f94e26ad72b8a52ab2614203230be20f))
+
+  - **MMC**
+
+    - fix the length of the ocr defines ([e02d365](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e02d365ad9c4102cadb2d8886e3aed327a7512c9))
+    - fix the length of the response type ([7b4b3f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b4b3f243ad3ef099de9aa09a526e7ecccc09c04))
+
+  - **GUID Partition Tables Support**
+
+    - fix MBR header load ([2fac89d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fac89d1267e81e1f4bf0eacf9ea8dbacf80aacb))
+    - initialise the mbr_entry variable ([ec48d52](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec48d52e7890d8e27d1b4419a6a8952d7db777cc))
+
+  - **Arm**
+
+    - add missing curly braces ([03c6bb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03c6bb0e3822e05da002c69086357c81f853d6f5))
+    - align essential type categories ([bec4a2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bec4a2c9c3919c4a3012c7a10f4fa75a861f8150))
+    - typecast expression to match data type ([0f76d0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f76d0d57ec700b835e1715200f4520fde1c11c4))
+    - typecast expressions to match data type ([edecc70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/edecc70331ec5e7583972f66f0e8dc6cf039c686))
+
+    - **GIC**
+
+      - quote the correct flag on error ([df21ca0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df21ca08e65b2aeb575e54b155fce1e32908eae6))
+
+      - **GICv3**
+
+        - do not assume redistributors are powered down ([57f2d00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57f2d009fb198181c53f768233f76087ab918ce1))
+
+    - **SMMU**
+
+      - set root port CR0 GPCEN before ACCESSEN ([8cc9724](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8cc972421faf02cfdd4fea1a21fabe6e9d96e2a3))
+
+  - **Renesas**
+
+    - **R-Car3**
+
+      - disable A/B loader support by default ([1a57115](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a5711519a8e685d3db43620623f0f616317cfe9))
+
+  - **ST**
+
+    - **ST PMIC**
+
+      - remove deadcode from STPMIC2 driver ([bdbbf48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdbbf48f4db6fa64079efcd284955a3bf629b705))
+
+- **Miscellaneous**
+
+  - **AArch32**
+
+    - avoid using r12 to store boot params ([af61b50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af61b50c1077b6d936c8ed741c1d0b8e43eb2b19))
+
+  - **FDTs**
+
+    - **ST**
+
+      - **STM32MP1**
+
+        - re-enable RTC clock ([33573ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33573ea6842198cfdb5b3fdd320db9e2045855e9))
+
+        - **STM32MP15**
+
+          - update clocks config for prtt1x board family ([5aeb003](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5aeb0031558b4a9ccff9f097ae651d42d7b850a2))
+
+      - **STM32MP2**
+
+        - fix SDMMC slew rate ([575d6dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/575d6dd7af3644f7c3c9cb34e3fb57d951695023))
+
+  - **Security**
+
+    - add CVE-2024-7881 mitigation to Cortex-X3 ([b0521a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0521a164a8d61c95968e728df9af52be1a48553))
+    - add CVE-2024-7881 mitigation to Cortex-X4 ([6ce6aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ce6acac911f11979a6cd2ee9cc9041f189c6ec7))
+    - add CVE-2024-7881 mitigation to Cortex-X925 ([520c220](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/520c2207b96d31adf508edc068bb97cd01d98da4))
+    - add CVE-2024-7881 mitigation to Neoverse-V2 ([56bb1d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56bb1d172ccee56e984559de69e8ebd8683d491b))
+    - add CVE-2024-7881 mitigation to Neoverse-V3 ([037a15f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/037a15f5c72e856b8739a2159bd0fe1fe69e1d5b))
+    - add support in cpu_ops for CVE-2024-7881 ([4caef42](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4caef42a94b4efe97b09764a7257f701ab7ff3b8))
+    - apply SMCCC_ARCH_WORKAROUND_4 to affected cpus ([8ae6b1a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ae6b1ad6c9c57b09b6d4e7ae3cbdf3aed6455b1))
+    - enable WORKAROUND_CVE_2024_7881 build option ([2372179](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2372179484741aa81d5451b20748520677205c71))
+
+  - **SDEI**
+
+    - return SDEI_EINVAL if signaling state is incorrect ([b142ede](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b142ede74ceb5fc0b2908d0e7e8e2b2b27b6b1f6))
+
+  - **TBBR**
+
+    - remove tbbr_cot_bl1_r64.c ([a2328f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2328f2eac83aa9bc10f89d9141ab9bd66338400))
+
+- **Documentation**
+
+  - fix the indent and the build command for MT8188 ([cef56a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cef56a5c6b42b4518af8c48f48a8790542ce3930))
+  - put INIT_UNUSED_NS_EL2 docs back ([4557c0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4557c0c001ba296328e6292a5a2c973581fbeb47))
+  - update the instrumentation procedure ([9b65ffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b65ffefd673fb2781b808024d13039151c17668))
+
+- **Build System**
+
+  - do not force PLAT in plat_helpers.mk ([422b181](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/422b181faf2fd740e08cf881880015ea47b0cb67))
+  - enable fp during fp save/restore ([5141de1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5141de14432aba7a775c0dd19ecba766d224ec39))
+  - handle invalid spd build options ([a0effb9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0effb91897ff41871cbe2366a54c6e2339246d8))
+  - include platform mk earlier ([696ed16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/696ed16877a121d07a766af5bb4f8d73a8ac01ae))
+  - run sp_mk_gen.py with poetry ([dd81623](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd816235771e19df1fd04ef2c6f1c6d11e429fd5))
+  - update clang target for aarch64 ([af8947f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af8947fe17d3a29a47573ab0537d121d3653b53e))
+
+- **Tools**
+
+  - change data type to size_t for doimage ([fbf6555](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbf6555790ad6de635ebf9e5581c840496166306))
+
+  - **NXP Tools**
+
+    - fix create_pbl buildroot build ([634c7d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/634c7d8172b7965cf4f5d7d6470a25956ac06ab4))
+    - fix2 create_pbl buildroot build ([bfe7f80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfe7f8018947a960c287f6d8f5ac1efece7261b4))
+
+  - **Certificate Creation Tool**
+
+    - add default keysize to Brainpool ECDSA ([0da16fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0da16fe32f41387f4ad32e96a939c67a3dc8e611))
+    - load openSSL configuration before PKCS11 operations ([785c2c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/785c2c3e8671aa69269bccd3ee968bebd3777a9f))
+
+  - **Firmware Encryption Tool**
+
+    - put build_msg under LOG_LEVEL flag ([7640df6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7640df6f1ef392d664d16aa4d49c67a24421adce))
+
+  - **Renesas Tools**
+
+    - **R-Car Layout Tool**
+
+      - fix tool build ([72f4b70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72f4b70e8e8e656d88bda77605f73076474f5a55))
+
+  - **Transfer List Compiler**
+
+    - add void entries to align data ([03c2660](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03c2660f7556957262c41032064716414572833c))
+    - pass the flags from client interface ([537a25e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/537a25ef7ff6fc95221c70c9543404049143353d))
+    - relax entry addition from YAML files ([f0e15dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0e15ddca303322764e17524396cb2da2c1c5ccc))
+
+- **Dependencies**
+
+  - remove deprecated husky commands ([b47dddd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b47dddd061e92054c3b2096fc8aa9688bfef68d6))
+
 ## [2.12.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.11.0..refs/tags/v2.12.0) (2024-11-19)
 
 The threat model for context management and the asymmetric CPU extension support
@@ -10792,7 +11989,7 @@
 
 ______________________________________________________________________
 
-*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.*
 
 [mbed tls releases]: https://tls.mbed.org/tech-updates/releases
 [pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193

diff --git a/docs/components/activity-monitors.rst b/docs/components/activity-monitors.rst
index 4c33d42..d25fcb1 100644
--- a/docs/components/activity-monitors.rst
+++ b/docs/components/activity-monitors.rst

@@ -21,7 +21,9 @@
 
 As a security precaution, Trusted Firmware-A does not enable these by default.
 Instead, platforms must configure their auxiliary counters through the
-``plat_amu_aux_enables`` platform hook.
+``plat_amu_aux_enables`` platform hook. This is a per-core array indexed with
+``plat_my_core_pos()``. A core's value will be written verbatim into
+``AMCNTENSET1_EL0``.
 
 --------------
 

diff --git a/docs/components/context-management-library.rst b/docs/components/context-management-library.rst
index 8cb1ace..cef6fba 100644
--- a/docs/components/context-management-library.rst
+++ b/docs/components/context-management-library.rst

@@ -106,7 +106,6 @@
 	#define FEAT_STATE_DISABLED     	0
 	#define FEAT_STATE_ENABLED      	1
 	#define FEAT_STATE_CHECK        	2
-	#define FEAT_STATE_CHECK_ASYMMETRIC	3
 
 A pattern is established for feature enablement behavior.
 Each feature must support the 3 possible values with rigid semantics.
@@ -120,15 +119,15 @@
 - **FEAT_STATE_CHECK** - same as ``FEAT_STATE_ALWAYS`` except that the feature's
   existence will be checked at runtime. Default on dynamic platforms (example: FVP).
 
-- **FEAT_STATE_CHECK_ASYMMETRIC** - same as ``FEAT_STATE_CHECK`` except that the feature's
-  existence is asymmetric across cores, which requires the feature existence is checked
-  during warmboot path also. Note that only limited number of features can be asymmetric.
-
  .. note::
-   Only limited number of features can be ``FEAT_STATE_CHECK_ASYMMETRIC`` this is due to
-   the fact that Operating systems are designed for SMP systems.
-   There are no clear guidelines what kind of mismatch is allowed but following pointers
-   can help making a decision
+
+   In general, it is assumed that all cores will support the same set of
+   architectural features (features will be symmetrical). However, there are
+   cases where this is impractical to achieve. Only some features can be
+   mismatched among cores and this is the exception rather than the rule. This
+   is due to the fact that Operating systems are designed for SMP systems. There
+   are no clear guidelines what kind of mismatch is allowed but following
+   pointers can help in making a decision:
 
     - All mandatory features must be symmetric.
     - Any feature that impacts the generation of page tables must be symmetric.
@@ -136,8 +135,9 @@
     - Features related with profiling, debug and trace could be asymmetric
     - Migration of vCPU/tasks between CPUs should not cause an error
 
-    Whenever there is asymmetric feature support is added for a feature TF-A need to add
-    feature specific code in context management code.
+   TF-A caters for mismatched features, however, this is not regularly tested
+   for all features and may not work as expected, even without considering OS
+   support.
 
  .. note::
    ``FEAT_RAS`` is an exception here, as it impacts the execution of EL3 and
@@ -345,9 +345,9 @@
 
 |Context Init WarmBoot|
 
-The primary CPU initializes the Non-Secure context for the secondary CPU while
-restoring re-entry information for the Non-Secure world.
-It initialises via ``cm_init_context_by_index(target_idx, ep )``.
+The primary CPU writes the entrypoint for the secondary CPU. When the secondary
+wakes up it initialises its own context via ``cm_init_my_context( ep )`` using
+the provided entrypoint.
 
 ``psci_warmboot_entrypoint()`` is the warm boot entrypoint procedure.
 During the warm bootup process, secondary CPUs have their secure context

diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
index 2b6382b..34290f8 100644
--- a/docs/components/ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst

@@ -29,8 +29,13 @@
 
 - uuid [mandatory]
    - value type: <prop-encoded-array>
-   - An array consisting of 4 <u32> values, identifying the UUID of the service
-     implemented by this partition. The UUID format is described in RFC 4122.
+   - An array of comma separated tuples each consisting of 4 <u32> values,
+     identifying the UUID of the services implemented by this partition.
+     The UUID format is described in RFC 4122.
+   - These 4 <u32> values are packed similar to the UUID register mapping
+     specified in section '5.3 Unique Identification format', SMC Calling
+     Convention, DEN0028, v1.6 G BET0
+     (https://developer.arm.com/documentation/den0028/latest/).
 
 - id
    - value type: <u32>

diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index dfdabc6..6a07271 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst

@@ -52,7 +52,7 @@
   - ``RES0``: Bit 31 of the version number is reserved 0 as to maintain
     consistency with the versioning schemes used in other parts of RMM.
 
-This document specifies the 0.5 version of Boot Interface ABI and RMM-EL3
+This document specifies the 0.6 version of Boot Interface ABI and RMM-EL3
 services specification and the 0.5 version of the Boot Manifest.
 
 .. _rmm_el3_boot_interface:
@@ -719,6 +719,263 @@
    ``E_RMM_OK``,No errors detected
 
 
+RMM_IDE_KEY_PROG command
+=========================
+
+Set the key/IV info at Root port for an IDE stream as part of Device Assignment flow. This
+command is available from v0.6 of the RMM-EL3 interface.
+
+Please refer to `IDE-KM RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_
+for description of the IDE setup sequence and how this will be invoked by RMM.
+
+The key is 256 bits and IV is 96 bits. The caller needs
+to call this SMC to program this key to the Rx, Tx ports and for each sub-stream
+corresponding to a single keyset.
+
+FID
+---
+
+``0xC40001B7``
+
+Input values
+------------
+
+.. csv-table:: Input values for RMM_IDE_KEY_PROG
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   fid,x0,[63:0],UInt64,Command FID
+   ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
+   rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
+   "Keyset[12]:
+   Dir[11]:
+   Substream[10:8]:
+   StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream informationKey set: can be 0 or 1unused bits MBZ.
+   KeqQW0,x4,[63:0],UInt64,Quad word of key [63:0]
+   KeqQW1,x5,[63:0],UInt64,Quad word of key [127:64]
+   KeqQW2,x6,[63:0],UInt64,Quad word of key [191:128]
+   KeqQW3,x7,[63:0],UInt64,Quad word of key [255:192]
+   IFVQW0,x8,[63:0],UInt64,Quad word of IV [63:0]
+   IFVQW1,x9,[63:0],UInt64,Quad word of IV [95:64]
+   request_id,x10,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
+   cookie,x11,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
+
+
+Output values
+-------------
+
+.. csv-table:: Output values for RMM_IDE_KEY_PROG
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   Result,x0,[63:0],Error Code,Command return status
+
+Failure conditions
+------------------
+
+The table below shows all the possible error codes returned in ``Result`` upon
+a failure. The errors are ordered by condition check.
+
+.. csv-table:: Failure conditions for RMM_IDE_KEY_PROG
+   :header: "ID", "Condition"
+   :widths: 1 5
+
+   ``E_RMM_OK``,The Key programming is successful.
+   ``E_RMM_FAULT``,The Key programming is not successful.
+   ``E_RMM_INVAL``,The Key programming arguments are incorrect.
+   ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
+   ``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
+   ``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
+
+
+RMM_IDE_KEY_SET_GO command
+==========================
+
+Activate the IDE stream at Root Port once the keys have been programmed as part of
+Device Assignment flow. This command is available from v0.6 of the RMM-EL3 interface.
+
+Please refer to `IDE-KM RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_
+for description of the IDE setup sequence and info on how this will be invoked by RMM.
+
+The caller(RMM) needs to ensure the EL3_IDE_KEY_PROG() call had succeeded prior to this call.
+
+FID
+---
+
+``0xC40001B8``
+
+Input values
+------------
+
+.. csv-table:: Input values for RMM_IDE_KEY_SET_GO
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   fid,x0,[63:0],UInt64,Command FID
+   ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
+   rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
+   "Keyset[12]:
+   Dir[11]:
+   Substream[10:8]:
+   StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
+   request_id,x4,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
+   cookie,x5,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
+
+
+Output values
+-------------
+
+.. csv-table:: Output values for RMM_IDE_KEY_SET_GO
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   Result,x0,[63:0],Error Code,Command return status
+
+Failure conditions
+------------------
+
+The table below shows all the possible error codes returned in ``Result`` upon
+a failure. The errors are ordered by condition check.
+
+.. csv-table:: Failure conditions for RMM_IDE_KEY_SET_GO
+   :header: "ID", "Condition"
+   :widths: 1 5
+
+   ``E_RMM_OK``,The Key set go is successful.
+   ``E_RMM_FAULT``,The Key set go is not successful.
+   ``E_RMM_INVAL``,Incorrect arguments.
+   ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
+   ``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
+   ``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
+
+
+RMM_IDE_KEY_SET_STOP command
+============================
+
+Deactivate the IDE stream at Root Port as part of Device Assignment flow. This command is
+available from v0.6 of the RMM-EL3 interface.
+
+Please refer to `IDE-KM RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_
+for description of the IDE setup sequence and info on how this will be invoked by RMM.
+
+This SMC is used to tear down an IDE Stream.
+
+FID
+---
+
+``0xC40001B9``
+
+Input values
+------------
+
+.. csv-table:: Input values for RMM_IDE_KEY_SET_STOP
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   fid,x0,[63:0],UInt64,Command FID
+   ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
+   rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
+   "Keyset[12]:
+   Dir[11]:
+   Substream[10:8]:
+   StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
+   request_id,x4,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
+   cookie,x5,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
+
+
+Output values
+-------------
+
+.. csv-table:: Output values for RMM_IDE_KEY_SET_STOP
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   Result,x0,[63:0],Error Code,Command return status
+
+Failure conditions
+------------------
+
+The table below shows all the possible error codes returned in ``Result`` upon
+a failure. The errors are ordered by condition check.
+
+.. csv-table:: Failure conditions for RMM_IDE_KEY_SET_STOP
+   :header: "ID", "Condition"
+   :widths: 1 5
+
+   ``E_RMM_OK``,The Key set stop is successful.
+   ``E_RMM_FAULT``,The Key set stop is not successful.
+   ``E_RMM_INVAL``,Incorrect arguments.
+   ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
+   ``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
+   ``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
+
+
+RMM_IDE_KM_PULL_RESPONSE command
+================================
+
+Retrieve the response from Root Port to a previous non-blocking IDE-KM SMC request as part of
+Device Assignment flow. This command is available from v0.6 of the RMM-EL3 interface.
+
+Please refer to `IDE-KM RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_
+for description of the IDE setup sequence and info on how this will be invoked by RMM.
+
+The response from this call could correspond to any of the last pending requests and the
+RMM needs to identify the request and populate the response. For blocking calls, this SMC
+always returns E_RMM_UNK.
+
+FID
+---
+
+``0xC40001BA``
+
+Input values
+------------
+
+.. csv-table:: Input values for RMM_IDE_KM_PULL_RESPONSE
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   fid,x0,[63:0],UInt64,Command FID
+   ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
+   rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
+
+
+Output values
+-------------
+
+.. csv-table:: Output values for RMM_IDE_KM_PULL_RESPONSE
+   :header: "Name", "Register", "Field", "Type", "Description"
+   :widths: 1 1 1 1 5
+
+   Result,x0,[63:0],Error Code,Command return status
+   Result,x1,[63:0],Error Code,Retrieved response corresponding to previous IDE_KM requests.
+   Result,x2,[63:0],value,passthrough from requested SMC
+   Result,x3,[63:0],value,passthrough from requested SMC
+
+Failure conditions
+------------------
+
+The table below shows all the possible error codes returned in ``Result`` upon
+a failure. The errors are ordered by condition check.
+
+.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE(x0)
+   :header: "ID", "Condition"
+   :widths: 1 5
+
+   ``E_RMM_OK``,Response is retrieved successfully.
+   ``E_RMM_INVAL``,Arguments to pull response SMC is not correct.
+   ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
+   ``E_RMM_AGAIN``,IDE-KM response queue is empty and no response is available.
+
+.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE(x1)
+   :header: "ID", "Condition"
+   :widths: 1 5
+
+   ``E_RMM_OK``,The previous request was successful.
+   ``E_RMM_FAULT``,The previous request was not successful.
+   ``E_RMM_INVAL``,Arguments to previous request were incorrect.
+   ``E_RMM_UNK``,Previous request returned unknown error.
+
 RMM-EL3 world switch register save restore convention
 _____________________________________________________
 
@@ -768,47 +1025,53 @@
 RMM-EL3 Boot Manifest structure
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The RMM-EL3 Boot Manifest v0.4 structure contains platform boot information passed
-from EL3 to RMM. The size of the Boot Manifest is 112 bytes.
+The RMM-EL3 Boot Manifest v0.5 structure contains platform boot information passed
+from EL3 to RMM. The size of the Boot Manifest is 160 bytes.
 
 The members of the RMM-EL3 Boot Manifest structure are shown in the following
 table:
 
-+--------------------+--------+-------------------+----------------------------------------------+
-|   Name             | Offset |       Type        |            Description                       |
-+====================+========+===================+==============================================+
-| version            |   0    |      uint32_t     | Boot Manifest version                        |
-+--------------------+--------+-------------------+----------------------------------------------+
-| padding            |   4    |      uint32_t     | Reserved, set to 0                           |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_data          |   8    |     uintptr_t     | Pointer to Platform Data section             |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_dram          |   16   |    memory_info    | NS DRAM Layout Info structure                |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_console       |   40   |   console_list    | List of consoles available to RMM            |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_ncoh_region   |   64   |    memory_info    | Device non-coherent ranges Info structure    |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_coh_region    |   88   |    memory_info    | Device coherent ranges Info structure        |
-+--------------------+--------+-------------------+----------------------------------------------+
++-------------------+--------+-------------------+----------------------------------------------+
+|        Name       | Offset |       Type        |                 Description                  |
++===================+========+===================+==============================================+
+| version           |   0    |      uint32_t     | Boot Manifest version                        |
++-------------------+--------+-------------------+----------------------------------------------+
+| padding           |   4    |      uint32_t     | Reserved, set to 0                           |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_data         |   8    |      uint64_t     | Pointer to Platform Data section             |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_dram         |   16   |    memory_info    | NS DRAM Layout Info structure                |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_console      |   40   |   console_list    | List of consoles available to RMM            |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_ncoh_region  |   64   |    memory_info    | Device non-coherent ranges Info structure    |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_coh_region   |   88   |    memory_info    | Device coherent ranges Info structure        |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_smmu         |   112  |     smmu_list     | List of SMMUs available to RMM               |
+|                   |        |                   | (from Boot Manifest v0.5)                    |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_root_complex |   136  | root_complex_list | List of PCIe root complexes available to RMM |
+|                   |        |                   | (from Boot Manifest v0.5)                    |
++-------------------+--------+-------------------+----------------------------------------------+
 
 .. _memory_info_struct:
 
 Memory Info structure
-~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~
 
 Memory Info structure contains information about platform memory layout.
 The members of this structure are shown in the table below:
 
-+-----------+--------+----------------+----------------------------------------+
-|   Name    | Offset |     Type       |               Description              |
-+===========+========+================+========================================+
-| num_banks |   0    |   uint64_t     | Number of memory banks/device regions  |
-+-----------+--------+----------------+----------------------------------------+
-| banks     |   8    |  memory_bank * | Pointer to 'memory_bank'[] array       |
-+-----------+--------+----------------+----------------------------------------+
-| checksum  |   16   |   uint64_t     | Checksum                               |
-+-----------+--------+----------------+----------------------------------------+
++-----------+--------+---------------+----------------------------------------+
+|   Name    | Offset |     Type      |              Description               |
++===========+========+===============+========================================+
+| num_banks |   0    |    uint64_t   | Number of memory banks/device regions  |
++-----------+--------+---------------+----------------------------------------+
+| banks     |   8    | memory_bank * | Pointer to 'memory_bank'[] array       |
++-----------+--------+---------------+----------------------------------------+
+| checksum  |   16   |    uint64_t   | Checksum                               |
++-----------+--------+---------------+----------------------------------------+
 
 Checksum is calculated as two's complement sum of 'num_banks', 'banks' pointer
 and memory banks data array pointed by it.
@@ -820,13 +1083,13 @@
 
 Memory Bank structure contains information about each memory bank/device region:
 
-+-----------+--------+----------------+--------------------------------------------+
-|   Name    | Offset |     Type       |                Description                 |
-+===========+========+================+============================================+
-|   base    |   0    |   uintptr_t    | Base address                               |
-+-----------+--------+----------------+--------------------------------------------+
-|   size    |   8    |   uint64_t     | Size of memory bank/device region in bytes |
-+-----------+--------+----------------+--------------------------------------------+
++------+--------+----------+--------------------------------------------+
+| Name | Offset |   Type   |                Description                 |
++======+========+==========+============================================+
+| base |   0    | uint64_t | Base address                               |
++------+--------+----------+--------------------------------------------+
+| size |   8    | uint64_t | Size of memory bank/device region in bytes |
++------+--------+----------+--------------------------------------------+
 
 .. _console_list_struct:
 
@@ -836,15 +1099,15 @@
 Console List structure contains information about the available consoles for RMM.
 The members of this structure are shown in the table below:
 
-+--------------+--------+----------------+-------------------------------------+
-|   Name       | Offset |     Type       |               Description           |
-+==============+========+================+=====================================+
-| num_consoles |   0    |   uint64_t     | Number of consoles                  |
-+--------------+--------+----------------+-------------------------------------+
-| consoles     |   8    | console_info * | Pointer to 'console_info'[] array   |
-+--------------+--------+----------------+-------------------------------------+
-| checksum     |   16   |   uint64_t     | Checksum                            |
-+--------------+--------+----------------+-------------------------------------+
++--------------+--------+----------------+-----------------------------------+
+|   Name       | Offset |     Type       |           Description             |
++==============+========+================+===================================+
+| num_consoles |   0    |   uint64_t     | Number of consoles                |
++--------------+--------+----------------+-----------------------------------+
+| consoles     |   8    | console_info * | Pointer to 'console_info'[] array |
++--------------+--------+----------------+-----------------------------------+
+| checksum     |   16   |   uint64_t     | Checksum                          |
++--------------+--------+----------------+-----------------------------------+
 
 Checksum is calculated as two's complement sum of 'num_consoles', 'consoles'
 pointer and the consoles array pointed by it.
@@ -856,21 +1119,144 @@
 
 Console Info structure contains information about each Console available to RMM.
 
-+-----------+--------+---------------+-----------------------------------------+
-|   Name    | Offset |     Type      |               Description               |
-+===========+========+===============+=========================================+
-| base      |   0    |   uintptr_t   | Console Base address                    |
-+-----------+--------+---------------+-----------------------------------------+
-| map_pages |   8    |   uint64_t    | Num of pages to map for console MMIO    |
-+-----------+--------+---------------+-----------------------------------------+
-| name      |   16   |   char[8]     | Name of console                         |
-+-----------+--------+---------------+-----------------------------------------+
-| clk_in_hz |   24   |   uint64_t    | UART clock (in Hz) for console          |
-+-----------+--------+---------------+-----------------------------------------+
-| baud_rate |   32   |   uint64_t    | Baud rate                               |
-+-----------+--------+---------------+-----------------------------------------+
-| flags     |   40   |   uint64_t    | Additional flags (RES0)                 |
-+-----------+--------+---------------+-----------------------------------------+
++-----------+--------+----------+--------------------------------------+
+|   Name    | Offset |   Type   |             Description              |
++===========+========+==========+======================================+
+| base      |   0    | uint64_t | Console Base address                 |
++-----------+--------+----------+--------------------------------------+
+| map_pages |   8    | uint64_t | Num of pages to map for console MMIO |
++-----------+--------+----------+--------------------------------------+
+| name      |   16   | char[8]  | Name of console                      |
++-----------+--------+----------+--------------------------------------+
+| clk_in_hz |   24   | uint64_t | UART clock (in Hz) for console       |
++-----------+--------+----------+--------------------------------------+
+| baud_rate |   32   | uint64_t | Baud rate                            |
++-----------+--------+----------+--------------------------------------+
+| flags     |   40   | uint64_t | Additional flags (RES0)              |
++-----------+--------+----------+--------------------------------------+
+
+.. _smmu_list_struct:
+
+SMMU List structure
+~~~~~~~~~~~~~~~~~~~
+
+SMMU List structure contains information about SMMUs available for RMM.
+The members of this structure are shown in the table below:
+
++-----------+--------+-------------+--------------------------------+
+|    Name   | Offset |     Type    |          Description           |
++===========+========+=============+================================+
+| num_smmus |   0    |   uint64_t  | Number of SMMUs                |
++-----------+--------+-------------+--------------------------------+
+| smmus     |   8    | smmu_info * | Pointer to 'smmu_info'[] array |
++-----------+--------+-------------+--------------------------------+
+| checksum  |   16   |   uint64_t  | Checksum                       |
++-----------+--------+-------------+--------------------------------+
+
+.. _smmu_info_struct:
+
+SMMU Info structure
+~~~~~~~~~~~~~~~~~~~
+
+SMMU Info structure contains information about each SMMU available to RMM.
+
++-------------+--------+----------+-------------------------------+
+|    Name     | Offset |   Type   |          Description          |
++=============+========+==========+===============================+
+| smmu_base   |   0    | uint64_t | SMMU Base address             |
++-------------+--------+----------+-------------------------------+
+| smmu_r_base |   8    | uint64_t | SMMU Realm Pages base address |
++-------------+--------+----------+-------------------------------+
+
+.. _root_complex_list_struct:
+
+Root Complex List structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Root Complex List structure contains information about PCIe root complexes available for RMM.
+The members of this structure are shown in the table below.
+
++------------------+--------+---------------------+-------------------------------------+
+|       Name       | Offset |        Type         |           Description               |
++==================+========+=====================+=====================================+
+| num_root_complex |   0    |      uint64_t       | Number of root complexes            |
++------------------+--------+---------------------+-------------------------------------+
+| rc_info_version  |   8    |      uint32_t       | Root Complex Info structure version |
++------------------+--------+---------------------+-------------------------------------+
+| padding          |   12   |      uint32_t       | Reserved, set to 0                  |
++------------------+--------+---------------------+-------------------------------------+
+| root_complex     |   16   | root_complex_info * | Pointer to 'root_complex'[] array   |
++------------------+--------+---------------------+-------------------------------------+
+| checksum         |   24   |      uint64_t       | Checksum                            |
++------------------+--------+---------------------+-------------------------------------+
+
+The checksum calculation of Root Complex List structure includes all data structures
+referenced by 'root_complex_info' pointer.
+
+.. _root_complex_info_struct:
+
+Root Complex Info structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Root Complex Info structure contains information about each PCIe root complex available to RMM.
+The table below describes the members of this structure as per v0.1.
+
++-----------------+--------+------------------+-------------------------------------+
+|    Name         | Offset |       Type       |               Description           |
++=================+========+==================+=====================================+
+| ecam_base       |   0    |     uint64_t     | PCIe ECAM Base address              |
++-----------------+--------+------------------+-------------------------------------+
+| segment         |   8    |     uint8_t      | PCIe segment identifier             |
++-----------------+--------+------------------+-------------------------------------+
+| padding[3]      |   9    |     uint8_t      | Reserved, set to 0                  |
++-----------------+--------+------------------+-------------------------------------+
+| num_root_ports  |   12   |     uint32_t     | Number of root ports                |
++-----------------+--------+------------------+-------------------------------------+
+| root_ports      |   16   | root_port_info * | Pointer to 'root_port_info'[] array |
++-----------------+--------+------------------+-------------------------------------+
+
+The Root Complex Info structure version uses the same numbering scheme as described in
+:ref:`rmm_el3_ifc_versioning`.
+
+.. _root_port_info_struct:
+
+Root Port Info structure
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Root Complex Info structure contains information about each root port in PCIe root complex.
+
++------------------+--------+--------------------+---------------------------------------+
+|      Name        | Offset |       Type         |              Description              |
++==================+========+====================+=======================================+
+| root_port_id     |   0    |     uint16_t       | Root Port identifier                  |
++------------------+--------+--------------------+---------------------------------------+
+| padding          |   2    |     uint16_t       | Reserved, set to 0                    |
++------------------+--------+--------------------+---------------------------------------+
+| num_bdf_mappings |   4    |     uint32_t       | Number of BDF mappings                |
++------------------+--------+--------------------+---------------------------------------+
+| bdf_mappings     |   8    | bdf_mapping_info * | Pointer to 'bdf_mapping_info'[] array |
++------------------+--------+--------------------+---------------------------------------+
+
+.. _bdf_mapping_info_struct:
+
+BDF Mapping Info structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+BDF Mapping Info structure contains information about each Device-Bus-Function (BDF) mapping
+for PCIe root port.
+
++--------------+--------+----------+------------------------------------------------------+
+|     Name     | Offset |   Type   |                     Description                      |
++==============+========+==========+======================================================+
+| mapping_base |   0    | uint16_t | Base of BDF mapping (inclusive)                      |
++--------------+--------+----------+------------------------------------------------------+
+| mapping_top  |   2    | uint16_t | Top of BDF mapping (exclusive)                       |
++--------------+--------+----------+------------------------------------------------------+
+| mapping_off  |   4    | uint16_t | Mapping offset, as per Arm Base System Architecture: |
+|              |        |          | StreamID = RequesterID[N-1:0] + (1<<N)*Constant_B    |
++--------------+--------+----------+------------------------------------------------------+
+| smmu_idx     |   6    | uint16_t | SMMU index in 'smmu_info'[] array                    |
++--------------+--------+----------+------------------------------------------------------+
 
 .. _el3_token_sign_request_struct:
 

diff --git a/docs/components/ven-el3-service.rst b/docs/components/ven-el3-service.rst
index 13449ba..8be1b39 100644
--- a/docs/components/ven-el3-service.rst
+++ b/docs/components/ven-el3-service.rst

@@ -32,9 +32,13 @@
 +-----------------------------------+ Measurement Framework | | 2 - 15 are reserved for future expansion. |
 | 0xC7000020 - 0xC700002F (SMC64)   | (PMF)                 |                                             |
 +-----------------------------------+-----------------------+---------------------------------------------+
-| 0x87000030 - 0x8700FFFF (SMC32)   | Reserved              | | reserved for future expansion             |
+| 0x87000030 - 0x8700003F (SMC32)   | ACS (Architecture     | | 0 in use.                                 |
++-----------------------------------+ Compliance Suite) SMC | | 1 - 15 are reserved for future expansion. |
+| 0xC7000030 - 0xC700003F (SMC64)   | handler               |                                             |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000040 - 0x8700FFFF (SMC32)   | Reserved              | | reserved for future expansion             |
 +-----------------------------------+                       |                                             |
-| 0xC7000030 - 0xC700FFFF (SMC64)   |                       |                                             |
+| 0xC7000040 - 0xC700FFFF (SMC64)   |                       |                                             |
 +-----------------------------------+-----------------------+---------------------------------------------+
 
 Source definitions for vendor-specific EL3 Monitor Service Calls used by TF-A are located in
@@ -45,6 +49,8 @@
 +============================+============================+================================+
 |                          1 |                          0 | Added Debugfs and PMF services.|
 +----------------------------+----------------------------+--------------------------------+
+|                          1 |                          1 | Added ACS SMC handler services.|
++----------------------------+----------------------------+--------------------------------+
 
 *Table 1: Showing different versions of Vendor-specific service and changes done with each version*
 
@@ -71,8 +77,16 @@
 The optional DebugFS interface is accessed through Vendor specific EL3 service. Refer
 to :ref:`DebugFS interface` documentation for further details and usage.
 
+Architecture Compliance Suite (ACS) SMC handler
+-----------------------------------------------
+
+The Architecture Compliance Suite (ACS) SMC handler allows callers to branch
+to their ACS EL3 code based on their respective use-cases.
+For more details on System ACS, `System ACS`_.
+
 --------------
 
-*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.*
 
+.. _System ACS: https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite
 .. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest

diff --git a/docs/components/xlat-tables-lib-v2-design.rst b/docs/components/xlat-tables-lib-v2-design.rst
index cac32f5..c7fd5a2 100644
--- a/docs/components/xlat-tables-lib-v2-design.rst
+++ b/docs/components/xlat-tables-lib-v2-design.rst

@@ -10,7 +10,7 @@
 More specifically, some use cases that this library aims to support are:
 
 #. Statically allocate translation tables and populate them (at run-time) based
-   upon a description of the memory layout. The memory layout is typically
+   on a description of the memory layout. The memory layout is typically
    provided by the platform port as a list of memory regions;
 
 #. Support for generating translation tables pertaining to a different
@@ -26,28 +26,22 @@
 #. Support for changing memory attributes of memory regions at run-time.
 
 
-About version 1, version 2 and MPU libraries
---------------------------------------------
+About version 1 and version 2
+-----------------------------
 
 This document focuses on version 2 of the library, whose sources are available
 in the ``lib/xlat_tables_v2`` directory. Version 1 of the library can still be
 found in ``lib/xlat_tables`` directory but it is less flexible and doesn't
-support dynamic mapping. ``lib/xlat_mpu``, which configures Arm's MPU
-equivalently, is also addressed here. The ``lib/xlat_mpu`` is experimental,
-meaning that its API may change. It currently strives for consistency and
-code-reuse with xlat_tables_v2.  Future versions may be more MPU-specific (e.g.,
-removing all mentions of virtual addresses). Although potential bug fixes will
-be applied to all versions of the xlat_* libs, future feature enhancements will
-focus on version 2 and might not be back-ported to version 1 and MPU versions.
-Therefore, it is recommended to use version 2, especially for new platform
-ports (unless the platform uses an MPU).
+support dynamic mapping. Although potential bug fixes will be applied to both
+versions, future features enhancements will focus on version 2 and might not be
+back-ported to version 1. Therefore, it is recommended to use version 2,
+especially for new platform ports.
 
-However, please note that version 2 and the MPU version are still in active
-development and is not considered stable yet. Hence, compatibility breaks might
-be introduced.
+However, please note that version 2 is still in active development and is not
+considered stable yet. Hence, compatibility breaks might be introduced.
 
 From this point onwards, this document will implicitly refer to version 2 of the
-library, unless stated otherwise.
+library.
 
 
 Design concepts and interfaces
@@ -108,16 +102,6 @@
 library will choose the mapping granularity for this region as it sees fit (more
 details can be found in `The memory mapping algorithm`_ section below).
 
-The MPU library also uses ``struct mmap_region`` to specify translations, but
-the MPU's translations are limited to specification of valid addresses and
-access permissions.  If the requested virtual and physical addresses mismatch
-the system will panic. Being register-based for deterministic memory-reference
-timing, the MPU hardware does not involve memory-resident translation tables.
-
-Currently, the MPU library is also limited to MPU translation at EL2 with no
-MMU translation at other ELs.  These limitations, however, are expected to be
-overcome in future library versions.
-
 Translation Context
 ~~~~~~~~~~~~~~~~~~~
 
@@ -231,8 +215,7 @@
 The ``MAP_REGION()`` and ``MAP_REGION_FLAT()`` macros do not allow specifying a
 mapping granularity, which leaves the library implementation free to choose
 it. However, in cases where a specific granularity is required, the
-``MAP_REGION2()`` macro might be used instead. Using ``MAP_REGION_FLAT()`` only
-to define regions for the MPU library is strongly recommended.
+``MAP_REGION2()`` macro might be used instead.
 
 As explained earlier in this document, when the dynamic mapping feature is
 disabled, there is no notion of dynamic regions. Conceptually, there are only
@@ -391,9 +374,6 @@
 refer to the comments in the source code of the core module for more details
 about the sorting algorithm in use.
 
-This mapping algorithm does not apply to the MPU library, since the MPU hardware
-directly maps regions by "base" and "limit" (bottom and top) addresses.
-
 TLB maintenance operations
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -410,11 +390,6 @@
 is deferred to the ``enable_mmu*()`` family of functions, just before the MMU is
 turned on.
 
-Regarding enabling and disabling memory management, for the MPU library, to
-reduce confusion, calls to enable or disable the MPU use ``mpu`` in their names
-in place of ``mmu``. For example, the ``enable_mmu_el2()`` call is changed to
-``enable_mpu_el2()``.
-
 TLB invalidation is not required when adding dynamic regions either. Dynamic
 regions are not allowed to overlap existing memory region. Therefore, if the
 dynamic mapping request is deemed legitimate, it automatically concerns memory
@@ -437,6 +412,6 @@
 
 --------------
 
-*Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.*
 
 .. |Alignment Example| image:: ../resources/diagrams/xlat_align.png

diff --git a/docs/conf.py b/docs/conf.py
index 3a7264f..6e08030 100644
--- a/docs/conf.py
+++ b/docs/conf.py

@@ -1,6 +1,6 @@
 # -*- coding: utf-8 -*-
 #
-# Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,8 +14,8 @@
 
 project = "Trusted Firmware-A"
 author = "Trusted Firmware-A contributors"
-version = "2.12.0"
-release = "2.12.0"
+version = "2.13.0"
+release = "2.13.0"
 
 # -- General configuration ---------------------------------------------------
 

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 6562139..e11f8c0 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst

@@ -311,10 +311,6 @@
 -  ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
    CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
 
--  ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
-   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
-   is still open.
-
 -  ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
    CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
    is present in r0p0 but there is no workaround. It is still open.
@@ -377,10 +373,6 @@
   Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
   fixed in r0p1.
 
-- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
-  Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
-  it is still open.
-
 - ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to
   Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
   it is still open.
@@ -505,10 +497,6 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
    CPU.  It is still open.
 
--  ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
-   CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
-   It is still open.
-
 -  ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
    CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
    issue is present in r0p0 as well but there is no workaround for that
@@ -545,10 +533,6 @@
 
 For Neoverse V2, the following errata build flags are defined :
 
--  ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2
-   CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
-   open.
-
 -  ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2
    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
    r0p2.
@@ -589,6 +573,18 @@
 
 For Cortex-A710, the following errata build flags are defined :
 
+-  ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has
+   been fixed in r2p0.
+
+-  ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+   It has been fixed in r2p0.
+
+-  ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+   It has been fixed in r2p0.
+
 -  ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
    r2p0 of the CPU. It is still open.
@@ -609,10 +605,6 @@
    Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
    is still open.
 
--  ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
-   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
-   and r2p1 of the CPU and is still open.
-
 -  ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
    of the CPU and is fixed in r2p1.
@@ -686,9 +678,6 @@
 -  ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
 
--  ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
-   CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
-
 -  ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
 
@@ -752,10 +741,6 @@
    CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
    it is still open.
 
--  ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
-   CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU,
-   it is still open.
-
 -  ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
    CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
 
@@ -806,10 +791,6 @@
 
 For Cortex-X3, the following errata build flags are defined :
 
-- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3
-  CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
-  the CPU and is still open.
-
 - ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3
   CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
   is fixed in r1p1.
@@ -1080,6 +1061,12 @@
    please note that this workaround results in increased DSU power consumption
    on idle.
 
+-  ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the
+   affected DSU-120 configurations. This erratum applies to some r2p0
+   implementations and is fixed in r2p1. The affected r2p0 implementations
+   are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit
+   and making sure it's clear.
+
 CPU Specific optimizations
 --------------------------
 

diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index cf8cbc7..669bd96 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst

@@ -1056,6 +1056,18 @@
 integrating PSCI library with AArch32 EL3 Runtime Software can be found
 at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
 
+DSU driver
+----------
+
+Platforms that include a DSU (DynamIQ Shared Unit) can define
+the ``USE_DSU_DRIVER`` build flag to enable the DSU driver.
+This driver is responsible for configuring DSU-related powerdown
+and power feature settings using ``dsu_driver_init()`` and for
+preserving the context of DSU PMU system registers.
+
+To support the DSU driver, platforms must define the ``plat_dsu_data``
+structure.
+
 .. _firmware_design_sel1_spd:
 
 Secure-EL1 Payloads and Dispatchers
@@ -2599,6 +2611,9 @@
 section section can be reclaimed for any data which is accessed after cold
 boot initialization and it is upto the platform to make the decision.
 
+Please note that this will disable inlining for any functions with the __init
+attribute.
+
 .. _firmware_design_pmf:
 
 Performance Measurement Framework

diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 1f76770..a9d2fa9 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst

@@ -231,9 +231,9 @@
    - Public key data size is passed as the third argument to this function.
    - This function must return 0 on success, a signed integer error code
      otherwise.
-   - In TC2 platform, this function is used to calculate the hash of the given
-     key and forward this hash to |RSE| alongside the measurement of the image
-     which the key signs.
+   - In Total Compute platform, this function is used to calculate the hash
+     of the given key and forward this hash to |RSE| alongside the measurement
+     of the image which the key signs.
 
 --------------
 

diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index b5814bb..f99840b 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst

@@ -113,12 +113,16 @@
 -  ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
    and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
    If enabled, it is needed to use a compiler that supports the option
-   ``-mbranch-protection``. Selects the branch protection features to use:
--  0: Default value turns off all types of branch protection
+   ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR``
+   and ``ARM_ARCH_MAJOR``) option will control which instructions will be
+   emitted (HINT space or not). Selects the branch protection features to use:
+-  0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED)
 -  1: Enables all types of branch protection features
 -  2: Return address signing to its standard level
 -  3: Extend the signing to include leaf functions
 -  4: Turn on branch target identification mechanism
+-  5: Enables all types of branch protection features, only if present in
+   hardware (FEAT_STATE_CHECK).
 
    The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
    and resulting PAuth/BTI features.
@@ -136,6 +140,8 @@
    +-------+--------------+-------+-----+
    |   4   |     bti      |   N   |  Y  |
    +-------+--------------+-------+-----+
+   |   5   |   dynamic    |   Y   |  Y  |
+   +-------+--------------+-------+-----+
 
    This option defaults to 0.
    Note that Pointer Authentication is enabled for Non-secure world
@@ -198,11 +204,13 @@
 -  ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
    Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
    to be included when saving and restoring the CPU context as part of world
-   switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT``
-   mechanism. Default value is 0.
+   switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag
+   can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value
+   is 0.
 
    Note that Pointer Authentication is enabled for Non-secure world irrespective
-   of the value of this flag if the CPU supports it.
+   of the value of this flag if the CPU supports it. Alternatively, when
+   ``BRANCH_PROTECTION`` is enabled, this flag is superseded.
 
 -  ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the
    SVE registers to be included when saving and restoring the CPU context. Note
@@ -397,6 +405,12 @@
    flag can take values 0 to 2, to align  with the ``ENABLE_FEAT``
    mechanism. Default value is ``0``.
 
+-  ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR``
+   extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4
+   onwards. This feature requires PAUTH to be enabled via the
+   ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align
+   with the ``ENABLE_FEAT`` mechanism. Default value is ``0``.
+
 -  ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
    ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
    flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
@@ -467,6 +481,11 @@
    the values 0 to 2, to align  with the ``ENABLE_FEAT`` mechanism.
    Default value is ``0``.
 
+ - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU
+   interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually
+   exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported.
+   Default value is ``0``.
+
 -  ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE
    (Translation Hardening Extension) at EL2 and below, setting the bit
    SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1
@@ -1100,6 +1119,11 @@
    (Coherent memory region is included) or 0 (Coherent memory region is
    excluded). Default is 1.
 
+-  ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver.
+   The DSU driver allows save/restore of DSU PMU registers through
+   ``PRESERVE_DSU_PMU_REGS`` build option and allows platforms to
+   configure powerdown and power settings of DSU.
+
 -  ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
    firmware configuration framework. This will move the io_policies into a
    configuration device tree, instead of static structure in the code base.
@@ -1182,11 +1206,6 @@
    cluster platforms). If this option is enabled, then warm boot path
    enables D-caches immediately after enabling MMU. This option defaults to 0.
 
--  ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
-   tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
-   default value of this flag is ``no``. Note this option must be enabled only
-   for ARM architecture greater than Armv8.5-A.
-
 -  ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
    speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
    The default value of this flag is ``0``.
@@ -1280,11 +1299,38 @@
   This option should only be enabled on a need basis if there is a use case for
   reading characters from the console.
 
-GICv3 driver options
+GIC driver options
 --------------------
 
-GICv3 driver files are included using directive:
+The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is
+a numeric option that can take the following values:
 
+ - ``0``: generic GIC driver not enabled. Any support is entirely in platform
+   code. Strongly discouraged for GIC based interrupt controllers.
+
+ - ``1``: enable the use of the generic GIC driver but do not include any files
+   or function definitions. It is then the platform's responsibility to provide
+   these. This is useful if the platform either has a custom GIC implementation
+   or an alternative interrupt controller design. Use of this option is strongly
+   discouraged for standard GIC implementations.
+
+ - ``2``: use the GICv2 driver
+
+ - ``3``: use the GICv3 driver. See the next section on how to further configure
+   it. Use this option for GICv4 implementations.
+ - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``.
+
+ For GIC driver versions other than ``1``, deciding when to save and restore GIC
+ context on a power domain state transition, as well as any GIC actions outside
+ of the PSCI library's visibility are the platform's responsibility. The driver
+ provides implementations of all necessary subroutines, they only need to be
+ called as appropriate.
+
+GICv3 driver options
+~~~~~~~~~~~~~~~~~~~~
+
+``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The
+old (deprecated) way of included them is using the directive:
 ``include drivers/arm/gic/v3/gicv3.mk``
 
 The driver can be configured with the following options set in the platform
@@ -1456,6 +1502,9 @@
    per the `PSA Crypto API specification`_. This feature is only supported if
    using MbedTLS 3.x version. It is disabled (``0``) by default.
 
+-  ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware
+   activation as per the specification. This option defaults to 0.
+
 -  ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware
    Handoff using Transfer List defined in `Firmware Handoff specification`_.
    This defaults to ``0``. Current implementation follows the Firmware Handoff
@@ -1469,6 +1518,11 @@
    information using HOB defined in `Platform Initialization specification`_.
    This defaults to ``0``.
 
+-  ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC
+   handler code to handle SMC calls from the Architecture Compliance Suite. The
+   handler is intentionally empty to reserve the SMC section and allow
+   project-specific implementations in future ACS use cases.
+
 Firmware update options
 ~~~~~~~~~~~~~~~~~~~~~~~
 

diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index 54e29dd..e11da77 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst

@@ -42,7 +42,7 @@
 
 .. code:: shell
 
-   poetry run make doc
+   make doc
 
 Output from the build process will be placed in: ``docs/build/html``.
 
@@ -55,7 +55,7 @@
 
 .. code:: shell
 
-   poetry run make -C docs help
+   make -C docs help
 
 To build the documentation in PDF format, additionally ensure that the following
 packages are installed:
@@ -80,9 +80,10 @@
 Building rendered documentation from Poetry's virtual environment
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The command ``poetry run`` used in the steps above executes the input command
-from inside the project's virtual environment. The easiest way to activate this
-virtual environment is with the ``poetry shell`` command.
+If Poetry is installed, the ``doc`` target wraps its build steps with ``poetry
+run``, which runs the specified command within the project's virtual
+environment. The easiest way to activate this environment manually is by using
+the ``poetry shell`` command.
 
 Running ``poetry shell`` from the directory containing this project, activates
 the same virtual environment. This creates a sub-shell through which you can
@@ -91,7 +92,7 @@
 .. code:: shell
 
     poetry shell
-    make doc
+    make -C docs html
 
 Type ``exit`` to deactivate the virtual environment and exit this new shell. For
 other use cases, please see the official `Poetry`_ documentation.
@@ -121,7 +122,7 @@
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
 
 .. _Sphinx: http://www.sphinx-doc.org/en/master/
 .. _Poetry: https://python-poetry.org/docs/

diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 768e4fe..66c278e 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst

@@ -27,11 +27,11 @@
         Program          Min supported version
 ======================== =====================
 Arm Compiler             6.23
-Arm GNU Compiler         13.3
+Arm GNU Compiler         14.2
 Clang/LLVM               18.1.8
 Device Tree Compiler     1.6.1
 GNU make                 3.81
-mbed TLS\ [#f1]_         3.6.2
+mbed TLS\ [#f1]_         3.6.3
 Node.js [#f2]_           16
 OpenSSL                  1.0.0
 Poetry                   1.3.2
@@ -51,7 +51,7 @@
 AArch64 builds, the respective targets required are ``arm-none-eabi`` and
 ``aarch64-none-elf``.
 
-Testing has been performed with version 13.3.Rel1 (gcc 13.3) of the Arm
+Testing has been performed with version 14.2.Rel1 (GCC 14.2) of the Arm
 GNU compiler, which can be installed from the `Arm Developer website`_.
 
 In addition, a native compiler is required to build supporting tools.
@@ -182,6 +182,44 @@
 You can read more about Git hooks in the *githooks* page of the Git
 documentation, available `here <https://git-scm.com/docs/githooks>`_.
 
+.. _git_submodules:
+
+Cloning Additional Git Submodules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Some dependencies in TF-A, such as Transfer List Library ``libtl``, are managed
+using Git submodules. Submodules allow external repositories to be included
+within the main project while maintaining their own commit history.
+
+Initial Clone with Submodules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+If you're cloning the repository for the first time, run the following commands
+to initialize and fetch all submodules:
+
+.. code-block:: bash
+
+   git clone --recurse-submodules "https://git.trustedfirmware.org/TF-A/trusted-firmware-a"
+
+This ensures all submodules (including ``libtl``) are correctly checked out.
+
+Updating Submodules
+^^^^^^^^^^^^^^^^^^^
+
+If the project updates the reference to a submodule (e.g., points to a new
+commit of ``libtl``), you can update your local copy by running:
+
+.. code-block:: bash
+
+   git pull
+   git submodule update --init --recursive
+
+To fetch the latest commits from all submodules, you can use:
+
+.. code-block:: bash
+
+   git submodule update --remote
+
 --------------
 
 *Copyright (c) 2021-2025, Arm Limited. All rights reserved.*

diff --git a/docs/license.rst b/docs/license.rst
index e35b9bb..05458b9 100644
--- a/docs/license.rst
+++ b/docs/license.rst

@@ -119,6 +119,15 @@
    -  ``include/lib/hob/mmram.h``
    -  ``include/lib/hob/mpinfo.h``
 
+- Some source files originating from the `mbed OS`_ project.
+  These files are licensed under the Apache License, Version 2.0, which is a
+  permissive license compatible with BSD-3-Clause. Any contributions to this
+  code must also be made under the terms of `Apache License 2.0`_.
+  These files are:
+
+   -  ``tools/memory/memory/mapsummary.py``
+   -  ``tools/memory/memory/mapsummary_flamegraph.hmtl``
+
 .. _FreeBSD: http://www.freebsd.org
 .. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
 .. _SCC: http://www.simple-cc.org/
@@ -126,3 +135,4 @@
 .. _Apache License 2.0: https://www.apache.org/licenses/LICENSE-2.0.txt
 .. _pydevicetree: https://pypi.org/project/pydevicetree/
 .. _edk2: https://github.com/tianocore/edk2
+.. _mbed OS: https://github.com/ARMmbed/mbed-os/

diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 9640a24..45c1922 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst

@@ -31,40 +31,14 @@
 
 The following source trees and binaries were used:
 
-- `TF-A v2.12-rc0`_
-- `TFTF v2.12-rc0`_
+- `TF-A v2.13-rc0`_
+- `TFTF v2.13-rc0`_
 
 Please see the Runtime Instrumentation :ref:`Testing Methodology
 <Runtime Instrumentation Methodology>`
-page for more details.
-
-Procedure
----------
-
-#. Build TFTF with runtime instrumentation enabled:
-
-    .. code:: shell
-
-        make CROSS_COMPILE=aarch64-none-elf- PLAT=juno \
-            TESTS=runtime-instrumentation all
-
-#. Fetch Juno's SCP binary from TF-A's archive:
-
-    .. code:: shell
-
-        curl --fail --connect-timeout 5 --retry 5 -sLS -o scp_bl2.bin \
-            https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/juno/release/juno-bl2.bin
-
-#. Build TF-A with the following build options:
-
-    .. code:: shell
-
-        make CROSS_COMPILE=aarch64-none-elf- PLAT=juno \
-            BL33="/path/to/tftf.bin" SCP_BL2="scp_bl2.bin" \
-            ENABLE_RUNTIME_INSTRUMENTATION=1 fiptool all fip
-
-#. Load the following images onto the development board: ``fip.bin``,
-   ``scp_bl2.bin``.
+page for more details. The tests were ran using the
+`tf-psci-lava-instr/juno-enable-runtime-instr,juno-instrumentation:juno-tftf`
+configuration in CI.
 
 Results
 -------
@@ -73,6 +47,25 @@
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
+        parallel (v2.13)
+
+    +---------+------+------------------+-------------------+--------------------+
+    | Cluster | Core |    Powerdown     |       Wakeup      |    Cache Flush     |
+    +---------+------+------------------+-------------------+--------------------+
+    |    0    |  0   | 333.0 (-52.92%)  |  23.92 (-40.11%)  |       138.88       |
+    +---------+------+------------------+-------------------+--------------------+
+    |    0    |  1   | 630.9 (+145.95%) |  253.72 (-46.56%) | 136.94 (+1987.50%) |
+    +---------+------+------------------+-------------------+--------------------+
+    |    1    |  0   | 184.74 (+71.92%) |  23.16 (-95.39%)  | 80.24 (+1283.45%)  |
+    +---------+------+------------------+-------------------+--------------------+
+    |    1    |  1   |      481.14      |  18.56 (-88.25%)  |  76.5 (+1520.76%)  |
+    +---------+------+------------------+-------------------+--------------------+
+    |    1    |  2   | 933.88 (+67.76%) | 289.58 (+189.64%) | 76.34 (+1510.55%)  |
+    +---------+------+------------------+-------------------+--------------------+
+    |    1    |  3   |     1112.48      | 238.42 (+753.94%) |       76.38        |
+    +---------+------+------------------+-------------------+--------------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
         parallel (v2.12)
 
     +---------+------+-------------------+------------------+--------------------+
@@ -92,23 +85,23 @@
     +---------+------+-------------------+------------------+--------------------+
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
-        parallel (v2.11)
+        serial (v2.13)
 
-    +---------+------+-------------------+--------------------+-------------+
-    | Cluster | Core |     Powerdown     |       Wakeup       | Cache Flush |
-    +---------+------+-------------------+--------------------+-------------+
-    |    0    |  0   |  112.98 (-53.44%) |  26.16 (-89.33%)   |     5.48    |
-    +---------+------+-------------------+--------------------+-------------+
-    |    0    |  1   |       411.18      | 438.88 (+1572.56%) |    138.54   |
-    +---------+------+-------------------+--------------------+-------------+
-    |    1    |  0   | 261.82 (+150.88%) | 474.06 (+1649.30%) |     5.6     |
-    +---------+------+-------------------+--------------------+-------------+
-    |    1    |  1   |  714.76 (+86.84%) |       26.44        |     4.48    |
-    +---------+------+-------------------+--------------------+-------------+
-    |    1    |  2   |       862.66      |  149.34 (-45.00%)  |     4.38    |
-    +---------+------+-------------------+--------------------+-------------+
-    |    1    |  3   |      1045.12      |  98.12 (-55.76%)   |    79.74    |
-    +---------+------+-------------------+--------------------+-------------+
+    +---------+------+------------------+-----------------+-------------------+
+    | Cluster | Core |    Powerdown     |      Wakeup     |    Cache Flush    |
+    +---------+------+------------------+-----------------+-------------------+
+    |    0    |  0   |      244.08      | 24.48 (-40.00%) |       137.64      |
+    +---------+------+------------------+-----------------+-------------------+
+    |    0    |  1   |      244.2       | 23.84 (-41.57%) |       137.86      |
+    +---------+------+------------------+-----------------+-------------------+
+    |    1    |  0   |      294.78      |      23.54      |       76.62       |
+    +---------+------+------------------+-----------------+-------------------+
+    |    1    |  1   | 180.1 (+74.72%)  |      21.14      | 77.12 (+1533.90%) |
+    +---------+------+------------------+-----------------+-------------------+
+    |    1    |  2   | 180.54 (+75.25%) |       20.8      | 76.76 (+1554.31%) |
+    +---------+------+------------------+-----------------+-------------------+
+    |    1    |  3   | 180.6 (+75.44%)  |       21.2      | 76.86 (+1542.31%) |
+    +---------+------+------------------+-----------------+-------------------+
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
         serial (v2.12)
@@ -129,29 +122,29 @@
     |    1    |  3   |   100.96  |      22.54      |     4.38    |
     +---------+------+-----------+-----------------+-------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
-        serial (v2.11)
-
-    +---------+------+-----------+--------+-------------+
-    | Cluster | Core | Powerdown | Wakeup | Cache Flush |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |   244.42  | 27.42  |    138.12   |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  1   |   245.02  | 27.34  |    138.08   |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |   297.66  |  26.2  |    77.68    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  1   |   108.02  | 21.94  |     4.52    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  2   |   107.48  | 21.88  |     4.46    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  3   |   107.52  | 21.86  |     4.46    |
-    +---------+------+-----------+--------+-------------+
-
 ``CPU_SUSPEND`` to power level 0
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
+        parallel (v2.13)
+
+    +---------+------+-------------------+-----------------+-------------+
+    | Cluster | Core |     Powerdown     |      Wakeup     | Cache Flush |
+    +---------+------+-------------------+-----------------+-------------+
+    |    0    |  0   |       703.06      | 16.86 (-47.87%) |     7.98    |
+    +---------+------+-------------------+-----------------+-------------+
+    |    0    |  1   |       851.88      |  16.4 (-49.41%) |     8.04    |
+    +---------+------+-------------------+-----------------+-------------+
+    |    1    |  0   |  407.4 (+58.99%)  |  15.1 (-26.20%) |     7.2     |
+    +---------+------+-------------------+-----------------+-------------+
+    |    1    |  1   |  110.98 (-72.67%) |      15.46      |     6.56    |
+    +---------+------+-------------------+-----------------+-------------+
+    |    1    |  2   |       554.54      |       15.4      |     6.94    |
+    +---------+------+-------------------+-----------------+-------------+
+    |    1    |  3   | 258.96 (+143.06%) | 15.56 (-25.05%) |     6.64    |
+    +---------+------+-------------------+-----------------+-------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
         parallel (v2.12)
 
     +--------------------------------------------------------------------+
@@ -172,24 +165,23 @@
     |    1    |  3   | 523.36 (+391.23%) |       19.0      |     7.3     |
     +---------+------+-------------------+-----------------+-------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
-        parallel (v2.11)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.13)
 
-    +---------+------+-------------------+--------+-------------+
-    | Cluster | Core |     Powerdown     | Wakeup | Cache Flush |
-    +---------+------+-------------------+--------+-------------+
-    |    0    |  0   |       704.46      | 19.28  |     7.86    |
-    +---------+------+-------------------+--------+-------------+
-    |    0    |  1   |       853.66      | 18.78  |     7.82    |
-    +---------+------+-------------------+--------+-------------+
-    |    1    |  0   | 556.52 (+425.51%) | 19.06  |     7.82    |
-    +---------+------+-------------------+--------+-------------+
-    |    1    |  1   |  113.28 (-70.47%) | 19.28  |     7.48    |
-    +---------+------+-------------------+--------+-------------+
-    |    1    |  2   |  260.62 (-50.22%) |  19.8  |     7.26    |
-    +---------+------+-------------------+--------+-------------+
-    |    1    |  3   |  408.16 (+66.94%) | 19.82  |     7.38    |
-    +---------+------+-------------------+--------+-------------+
+    +---------+------+-----------+-----------------+-------------+
+    | Cluster | Core | Powerdown |      Wakeup     | Cache Flush |
+    +---------+------+-----------+-----------------+-------------+
+    |    0    |  0   |   106.12  |  17.1 (-48.24%) |     5.26    |
+    +---------+------+-----------+-----------------+-------------+
+    |    0    |  1   |   106.88  | 17.06 (-47.08%) |     5.28    |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  0   |   294.36  |       15.6      |     4.56    |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  1   |   103.26  |      15.44      |     4.46    |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  2   |   103.7   |      15.26      |     4.5     |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  3   |   103.68  |      15.72      |     4.5     |
+    +---------+------+-----------+-----------------+-------------+
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.12)
 
@@ -209,30 +201,30 @@
     |    1    |  3   |   97.52   |      19.46      |     4.26    |
     +---------+------+-----------+-----------------+-------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
-
-    +---------+------+-----------+--------+-------------+
-    | Cluster | Core | Powerdown | Wakeup | Cache Flush |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |   106.78  |  19.2  |     5.32    |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  1   |   107.44  | 19.64  |     5.44    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |   295.82  | 19.14  |     4.34    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  1   |   104.34  | 19.18  |     4.28    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  2   |   103.96  | 19.34  |     4.4     |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  3   |   104.32  | 19.18  |     4.34    |
-    +---------+------+-----------+--------+-------------+
-
 ``CPU_OFF`` on all non-lead CPUs
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 ``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
 core to the deepest power level.
 
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.13)
+
+    +---------+------+-----------+-----------------+-------------+
+    | Cluster | Core | Powerdown |      Wakeup     | Cache Flush |
+    +---------+------+-----------+-----------------+-------------+
+    |    0    |  0   |   243.02  | 26.42 (-39.51%) |    137.58   |
+    +---------+------+-----------+-----------------+-------------+
+    |    0    |  1   |   244.24  | 26.32 (-38.93%) |    137.88   |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  0   |   182.36  |      23.66      |     78.0    |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  1   |   108.18  |      22.68      |     4.42    |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  2   |   108.34  |      21.72      |     4.24    |
+    +---------+------+-----------+-----------------+-------------+
+    |    1    |  3   |   108.22  |      21.68      |     4.34    |
+    +---------+------+-----------+-----------------+-------------+
+
 .. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.12)
 
     +---------+------+-----------+-----------------+-------------+
@@ -251,27 +243,27 @@
     |    1    |  3   |   101.08  |      26.74      |     4.4     |
     +---------+------+-----------+-----------------+-------------+
 
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
-
-    +---------+------+-----------+--------+-------------+
-    | Cluster | Core | Powerdown | Wakeup | Cache Flush |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |   243.62  | 29.84  |    137.66   |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  1   |   243.88  | 29.54  |    137.8    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |   183.26  | 26.22  |    77.76    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  1   |   107.64  | 26.74  |     4.34    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  2   |   107.52  |  25.9  |     4.32    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  3   |   107.74  |  25.8  |     4.34    |
-    +---------+------+-----------+--------+-------------+
-
 ``CPU_VERSION`` in parallel
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.13)
+
+    +-------------+--------+--------------+
+    |   Cluster   |  Core  |   Latency    |
+    +-------------+--------+--------------+
+    |      0      |   0    |     1.0      |
+    +-------------+--------+--------------+
+    |      0      |   1    |     1.06     |
+    +-------------+--------+--------------+
+    |      1      |   0    |     0.6      |
+    +-------------+--------+--------------+
+    |      1      |   1    |     1.0      |
+    +-------------+--------+--------------+
+    |      1      |   2    |     0.98     |
+    +-------------+--------+--------------+
+    |      1      |   3    |     1.0      |
+    +-------------+--------+--------------+
+
 .. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.12)
 
     +-------------+--------+--------------+
@@ -290,24 +282,6 @@
     |      1      |   3    |     0.92     |
     +-------------+--------+--------------+
 
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.11)
-
-    +-------------+--------+--------------+
-    |   Cluster   |  Core  |   Latency    |
-    +-------------+--------+--------------+
-    |      0      |   0    |     1.26     |
-    +-------------+--------+--------------+
-    |      0      |   1    |     0.96     |
-    +-------------+--------+--------------+
-    |      1      |   0    |     0.54     |
-    +-------------+--------+--------------+
-    |      1      |   1    |     0.94     |
-    +-------------+--------+--------------+
-    |      1      |   2    |     0.92     |
-    +-------------+--------+--------------+
-    |      1      |   3    |     1.02     |
-    +-------------+--------+--------------+
-
 Annotated Historic Results
 --------------------------
 
@@ -526,9 +500,9 @@
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.*
 
 .. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
 .. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
-.. _TF-A v2.12-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.12-rc0
-.. _TFTF v2.12-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.12-rc0
+.. _TF-A v2.13-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.13-rc0
+.. _TFTF v2.13-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.13-rc0

diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index 178d8e6..196cdb1 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst

@@ -4,87 +4,16 @@
 For this test we used the N1 System Development Platform (`N1SDP`_), which
 contains an SoC consisting of two dual-core Arm N1 clusters.
 
-The following source trees and binaries were used:
+The following source trees were used:
 
-- `TF-A v2.12-rc0`_
-- `TFTF v2.12-rc0`_
-- SCP/MCP `Prebuilt Images`_
+- `TF-A v2.13-rc0`_
+- `TFTF v2.13-rc0`_
 
 Please see the Runtime Instrumentation :ref:`Testing Methodology
-<Runtime Instrumentation Methodology>` page for more details.
-
-Procedure
----------
-
-#. Build TFTF with runtime instrumentation enabled:
-
-    .. code:: shell
-
-        make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
-            TESTS=runtime-instrumentation all
-
-#. Build TF-A with the following build options:
-
-    .. code:: shell
-
-        make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
-            ENABLE_RUNTIME_INSTRUMENTATION=1 fiptool all
-
-#. Fetch the SCP firmware images:
-
-    .. code:: shell
-
-        curl --fail --connect-timeout 5 --retry 5 \
-            -sLS -o build/n1sdp/release/scp_rom.bin \
-            https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-bl1.bin
-        curl --fail --connect-timeout 5 \
-            --retry 5 -sLS -o build/n1sdp/release/scp_ram.bin \
-            https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-bl2.bin
-
-#. Fetch the MCP firmware images:
-
-    .. code:: shell
-
-        curl --fail --connect-timeout 5 --retry 5 \
-            -sLS -o build/n1sdp/release/mcp_rom.bin \
-            https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-mcp-bl1.bin
-        curl --fail --connect-timeout 5 --retry 5 \
-            -sLS -o build/n1sdp/release/mcp_ram.bin \
-            https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-mcp-bl2.bin
-
-#. Using the fiptool, create a new FIP package and append the SCP ram image onto
-   it.
-
-    .. code:: shell
-
-        ./tools/fiptool/fiptool create --blob \
-                uuid=cfacc2c4-15e8-4668-82be-430a38fad705,file=build/n1sdp/release/bl1.bin \
-                --scp-fw build/n1sdp/release/scp_ram.bin build/n1sdp/release/scp_fw.bin
-
-#. Append the MCP image to the FIP.
-
-    .. code:: shell
-
-        ./tools/fiptool/fiptool create \
-            --blob uuid=54464222-a4cf-4bf8-b1b6-cee7dade539e,file=build/n1sdp/release/mcp_ram.bin \
-            build/n1sdp/release/mcp_fw.bin
-
-#. Then, add TFTF as the Non-Secure workload in the FIP image:
-
-    .. code:: shell
-
-        make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
-            ENABLE_RUNTIME_INSTRUMENTATION=1 SCP_BL2=/dev/null \
-            BL33=<path/to/tftf.bin>  fip
-
-#. Load the following images onto the development board: ``fip.bin``,
-   ``scp_rom.bin``, ``scp_ram.bin``, ``mcp_rom.bin``, and ``mcp_ram.bin``.
-
-.. note::
-
-    These instructions presume you have a complete firmware stack. The N1SDP
-    `user guide`_ provides a detailed explanation on how to get setup from
-    scratch.
+<Runtime Instrumentation Methodology>` page for more details. The tests were ran
+using the
+`tf-psci-lava-instr/n1sdp-runtime-instrumentation,n1sdp-runtime-instrumentation:n1sdp-fip.tftf-firmware`
+configuration in CI.
 
 Results
 -------
@@ -92,6 +21,20 @@
 ``CPU_SUSPEND`` to deepest power level
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.13)
+
+    +---------+------+----------------+-----------------+----------------+
+    | Cluster | Core |   Powerdown    |      Wakeup     |  Cache Flush   |
+    +---------+------+----------------+-----------------+----------------+
+    |    0    |  0   |      3.32      | 13.42 (-45.40%) | 0.28 (-69.57%) |
+    +---------+------+----------------+-----------------+----------------+
+    |    0    |  0   | 4.02 (-35.78%) | 18.14 (-52.88%) |      0.28      |
+    +---------+------+----------------+-----------------+----------------+
+    |    1    |  0   | 2.7 (-27.42%)  | 17.38 (-49.36%) |      0.26      |
+    +---------+------+----------------+-----------------+----------------+
+    |    1    |  0   |      2.96      | 10.86 (-73.64%) |      0.26      |
+    +---------+------+----------------+-----------------+----------------+
+
 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.12)
 
     +---------+------+----------------+--------+----------------+
@@ -106,19 +49,19 @@
     |    1    |  0   |      3.28      | 42.36  |      0.3       |
     +---------+------+----------------+--------+----------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.11)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.13)
 
-    +---------+------+----------------+--------+----------------+
-    | Cluster | Core |   Powerdown    | Wakeup |  Cache Flush   |
-    +---------+------+----------------+--------+----------------+
-    |    0    |  0   | 3.0 (+41.51%)  | 23.14  | 1.2 (+185.71%) |
-    +---------+------+----------------+--------+----------------+
-    |    0    |  0   |      4.6       | 35.86  |      0.3       |
-    +---------+------+----------------+--------+----------------+
-    |    1    |  0   | 3.68 (+33.33%) | 33.36  |      0.3       |
-    +---------+------+----------------+--------+----------------+
-    |    1    |  0   | 3.7 (+40.15%)  |  38.1  |      0.28      |
-    +---------+------+----------------+--------+----------------+
+    +---------+------+-----------+-----------------+----------------+
+    | Cluster | Core | Powerdown |      Wakeup     |  Cache Flush   |
+    +---------+------+-----------+-----------------+----------------+
+    |    0    |  0   |    1.62   | 10.14 (-58.10%) |      0.3       |
+    +---------+------+-----------+-----------------+----------------+
+    |    0    |  0   |    1.86   | 10.62 (-56.44%) | 0.28 (-26.32%) |
+    +---------+------+-----------+-----------------+----------------+
+    |    1    |  0   |    1.8    | 10.16 (-57.84%) |      0.32      |
+    +---------+------+-----------+-----------------+----------------+
+    |    1    |  0   |    2.16   |  10.6 (-56.84%) | 0.5 (+56.25%)  |
+    +---------+------+-----------+-----------------+----------------+
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.12)
 
@@ -134,23 +77,23 @@
     |    1    |  0   |    2.24   | 23.84  |     0.36    |
     +---------+------+-----------+--------+-------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.11)
-
-    +---------+------+-----------+--------+-------------+
-    | Cluster | Core | Powerdown | Wakeup | Cache Flush |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |    1.7    | 22.46  |     0.3     |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |    2.28   |  22.5  |     0.3     |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |    2.14   |  21.5  |     0.32    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |    2.24   | 22.66  |     0.3     |
-    +---------+------+-----------+--------+-------------+
-
 ``CPU_SUSPEND`` to power level 0
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.13)
+
+    +---------+------+----------------+-----------------+---------------+
+    | Cluster | Core |   Powerdown    |      Wakeup     |  Cache Flush  |
+    +---------+------+----------------+-----------------+---------------+
+    |    0    |  0   | 0.8 (-57.45%)  | 11.98 (-61.75%) |      0.26     |
+    +---------+------+----------------+-----------------+---------------+
+    |    0    |  0   | 1.54 (-30.63%) | 16.44 (-53.74%) |      0.26     |
+    +---------+------+----------------+-----------------+---------------+
+    |    1    |  0   | 1.62 (-30.77%) |  16.1 (-53.92%) |      0.3      |
+    +---------+------+----------------+-----------------+---------------+
+    |    1    |  0   |      1.8       | 10.54 (-55.30%) | 0.2 (-33.33%) |
+    +---------+------+----------------+-----------------+---------------+
+
 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.12)
 
     +---------+------+-----------+--------+----------------+
@@ -165,19 +108,19 @@
     |    1    |  0   |    2.08   | 23.38  |      0.28      |
     +---------+------+-----------+--------+----------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.11)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.13)
 
-    +---------+------+----------------+--------+-------------+
-    | Cluster | Core |   Powerdown    | Wakeup | Cache Flush |
-    +---------+------+----------------+--------+-------------+
-    |    0    |  0   | 0.94 (-37.33%) | 30.36  |     0.3     |
-    +---------+------+----------------+--------+-------------+
-    |    0    |  0   |      2.12      | 33.12  |     0.28    |
-    +---------+------+----------------+--------+-------------+
-    |    1    |  0   |      2.08      | 32.56  |     0.3     |
-    +---------+------+----------------+--------+-------------+
-    |    1    |  0   |      2.14      | 21.92  |     0.28    |
-    +---------+------+----------------+--------+-------------+
+    +---------+------+----------------+-----------------+----------------+
+    | Cluster | Core |   Powerdown    |      Wakeup     |  Cache Flush   |
+    +---------+------+----------------+-----------------+----------------+
+    |    0    |  0   |      1.44      |  9.9 (-58.05%)  |      0.3       |
+    +---------+------+----------------+-----------------+----------------+
+    |    0    |  0   | 1.74 (-25.64%) |  10.4 (-56.23%) | 0.28 (-33.33%) |
+    +---------+------+----------------+-----------------+----------------+
+    |    1    |  0   |      1.8       | 10.04 (-57.71%) |      0.34      |
+    +---------+------+----------------+-----------------+----------------+
+    |    1    |  0   |      1.96      | 10.46 (-56.23%) |      0.44      |
+    +---------+------+----------------+-----------------+----------------+
 
 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.12)
 
@@ -193,26 +136,26 @@
     |    1    |  0   |    2.16   | 23.92  |      0.34      |
     +---------+------+-----------+--------+----------------+
 
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
-
-    +---------+------+-----------+--------+-------------+
-    | Cluster | Core | Powerdown | Wakeup | Cache Flush |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |    1.64   | 21.88  |     0.34    |
-    +---------+------+-----------+--------+-------------+
-    |    0    |  0   |    2.42   | 21.76  |     0.34    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |    2.02   | 21.14  |     0.32    |
-    +---------+------+-----------+--------+-------------+
-    |    1    |  0   |    2.18   |  22.3  |     0.34    |
-    +---------+------+-----------+--------+-------------+
-
 ``CPU_OFF`` on all non-lead CPUs
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 ``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
 core to the deepest power level.
 
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.13)
+
+    +---------+------+-----------+-----------------+---------------+
+    | Cluster | Core | Powerdown |      Wakeup     |  Cache Flush  |
+    +---------+------+-----------+-----------------+---------------+
+    |    0    |  0   |    1.64   | 10.24 (-57.72%) |      0.3      |
+    +---------+------+-----------+-----------------+---------------+
+    |    0    |  0   |   13.92   |  17.7 (-43.74%) |      0.3      |
+    +---------+------+-----------+-----------------+---------------+
+    |    1    |  0   |   13.54   | 16.74 (-44.90%) | 0.3 (-37.50%) |
+    +---------+------+-----------+-----------------+---------------+
+    |    1    |  0   |   14.12   | 18.28 (-41.93%) | 0.3 (-44.44%) |
+    +---------+------+-----------+-----------------+---------------+
+
 .. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.12)
 
     +---------+------+-----------+--------+----------------+
@@ -227,22 +170,21 @@
     |    1    |  0   |   14.18   | 31.82  |      0.68      |
     +---------+------+-----------+--------+----------------+
 
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
-
-    +---------+------+-----------+--------+----------------+
-    | Cluster | Core | Powerdown | Wakeup |  Cache Flush   |
-    +---------+------+-----------+--------+----------------+
-    |    0    |  0   |    1.96   | 22.44  |      0.38      |
-    +---------+------+-----------+--------+----------------+
-    |    0    |  0   |   13.76   | 30.34  |      0.26      |
-    +---------+------+-----------+--------+----------------+
-    |    1    |  0   |   13.46   | 28.28  |      0.24      |
-    +---------+------+-----------+--------+----------------+
-    |    1    |  0   |   13.84   | 30.06  | 0.28 (-60.00%) |
-    +---------+------+-----------+--------+----------------+
-
 ``CPU_VERSION`` in parallel
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.13)
+
+    +----------+------+-------------------+
+    | Cluster  | Core |      Latency      |
+    +----------+------+-------------------+
+    |    0     |  0   |        0.12       |
+    +----------+------+-------------------+
+    |    0     |  0   |   0.2 (-28.57%)   |
+    +----------+------+-------------------+
+    |    1     |  0   |        0.2        |
+    +----------+------+-------------------+
+    |    1     |  0   |   0.24 (-25.00%)  |
+    +----------+------+-------------------+
 
 .. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.12)
 
@@ -258,26 +200,11 @@
     |    1     |  0   |        0.26       |
     +----------+------+-------------------+
 
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.11)
-
-    +-------------+--------+--------------+
-    |   Cluster   |  Core  |   Latency    |
-    +-------------+--------+--------------+
-    |      0      |   0    |     0.12     |
-    +-------------+--------+--------------+
-    |      0      |   0    |     0.24     |
-    +-------------+--------+--------------+
-    |      1      |   0    |     0.2      |
-    +-------------+--------+--------------+
-    |      1      |   0    |     0.26     |
-    +-------------+--------+--------------+
-
 --------------
 
-*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2025, Arm Limited. All rights reserved.*
 
-.. _TF-A v2.12-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.12-rc0
-.. _TFTF v2.12-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.12-rc0
+.. _TF-A v2.13-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.13-rc0
+.. _TFTF v2.13-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.13-rc0
 .. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
-.. _Prebuilt Images:  https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/
 .. _N1SDP: https://developer.arm.com/documentation/101489/latest

diff --git a/docs/plat/arm/fvp/fvp-build-options.rst b/docs/plat/arm/fvp/fvp-build-options.rst
index 79dc0dc..3d87494 100644
--- a/docs/plat/arm/fvp/fvp-build-options.rst
+++ b/docs/plat/arm/fvp/fvp-build-options.rst

@@ -27,6 +27,7 @@
 
    -  ``FVP_GICV2`` : The GICv2 only driver is selected
    -  ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
+   -  ``FVP_GICV5`` : The GICv5 only driver is selected
 
 -  ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
    to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
@@ -41,6 +42,9 @@
    HW_CONFIG blob instead of the DTS file. This option is useful to override
    the default HW_CONFIG selected by the build system.
 
+-  ``FVP_HW_CONFIG_ADDR`` : Specify the memory address in which to load the
+   HW_CONFIG. The default value is ``0x82000000``.
+
 -  ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
    inactive/fused CPU cores as read-only. The default value of this option
    is ``0``, which means the redistributor pages of all CPU cores are marked

diff --git a/docs/plat/arm/fvp/fvp-specific-configs.rst b/docs/plat/arm/fvp/fvp-specific-configs.rst
index 0f51e4b..9608969 100644
--- a/docs/plat/arm/fvp/fvp-specific-configs.rst
+++ b/docs/plat/arm/fvp/fvp-specific-configs.rst

@@ -241,6 +241,34 @@
    (Default) For use with Foundation FVP with Base memory map configuration
    and Linux GICv3 support.
 
+GICv5 Support
+^^^^^^^^^^^^^
+
+GICv5 support in TF-A is currently **experimental** and provided only for early
+development and testing purposes. A simplified build configuration is available
+to allow booting the Linux kernel as a BL33 payload on the FVP platform.
+
+Key notes:
+
+- The support is **not production-ready** and is intended to assist with
+  upstream kernel development and validation.
+- The device tree bindings are **not finalized**; support has been validated
+  only with a **custom device tree**.
+- Use this configuration at your own discretion, understanding that the design
+  and register usage may change in future revisions.
+
+This configuration is **temporary** and may be removed once full GICv5 support
+is integrated upstream.
+
+.. code:: shell
+
+    make PLAT=fvp DEBUG=1                       \
+    CTX_INCLUDE_AARCH32_REGS=0                  \
+    FVP_USE_GIC_DRIVER=FVP_GICV5                \
+    ARM_LINUX_KERNEL_AS_BL33=1                  \
+    PRELOADED_BL33_BASE=0x84000000              \
+    FVP_HW_CONFIG_DTS=<PROVIDE_YOUR_OWN_DT>     \
+
 --------------
 
 *Copyright (c) 2019-2024, Arm Limited. All rights reserved.*

diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index 0ce1905..9535005 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst

@@ -1,8 +1,16 @@
 Fixed Virtual Platform (FVP) Support
 ------------------------------------
 
-This section lists the supported Arm |FVP| platforms. Please refer to the FVP
-documentation for a detailed description of the model parameter options.
+An |FVP| provides a complete simulation of an Arm system. This is a generic term
+used for all kinds of vastly different and incompatible systems. One category of
+these systems are the ``FVP_Base`` family of FVPs. These are entirely virtual
+platforms, largely used for early feature development. They offer a large
+degrees of customisation but share a lot of similarities. The ``fvp`` platform
+in TF-A supports these platforms only. Despite the generic name, other FVPs (eg
+FVP_TC4) have their own dedicated TF-A platforms and will not work with this one.
+
+Please refer to each FVP's documentation for a detailed description of the model
+parameter options.
 
 The latest version of the AArch64 build of TF-A has been tested on the following
 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
@@ -41,9 +49,6 @@
 -  ``FVP_Base_Neoverse-N1``
 -  ``FVP_Base_Neoverse-N2``
 -  ``FVP_Base_Neoverse-V1``
--  ``FVP_BaseR_AEMv8R``
--  ``FVP_RD_1_AE``
--  ``FVP_TC4``
 
 The latest version of the AArch32 build of TF-A has been tested on the
 following Arm FVPs without shifted affinities, and that do not support threaded
@@ -58,9 +63,8 @@
    is not compatible with legacy GIC configurations. Therefore this FVP does not
    support these legacy GIC configurations.
 
-The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
-FVP website`_. The Cortex-A models listed above are also available to download
-from `Arm's website`_.
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the
+`Arm's website`_ for download options of all FVPs.
 
 .. note::
    The build numbers quoted above are those reported by launching the FVP
@@ -94,7 +98,5 @@
 
 *Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
 
-.. _Arm's website: `FVP models`_
-.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Arm's website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
 .. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
-.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms

diff --git a/docs/plat/arm/fvp_r/index.rst b/docs/plat/arm/fvp_r/index.rst
deleted file mode 100644
index 8af16ba..0000000
--- a/docs/plat/arm/fvp_r/index.rst
+++ /dev/null

@@ -1,46 +0,0 @@
-ARM V8-R64 Fixed Virtual Platform (FVP)
-=======================================
-
-Some of the features of Armv8-R AArch64 FVP platform referenced in Trusted
-Boot R-class include:
-
-- Secure World Support Only
-- EL2 as Maximum EL support (No EL3)
-- MPU Support only at EL2
-- MPU or MMU Support at EL0/EL1
-- AArch64 Support Only
-- Trusted Board Boot
-
-Further information on v8-R64 FVP is available at `info <https://developer.arm.com/documentation/ddi0600/latest/>`_
-
-Boot Sequence
--------------
-
-BL1 –> BL33
-
-The execution begins from BL1 which loads the BL33 image, a boot-wrapped (bootloader + Operating System)
-Operating System, from FIP to DRAM.
-
-Build Procedure
-~~~~~~~~~~~~~~~
-
--  Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
-   Set the CROSS_COMPILE environment variable to point to the toolchain folder.
-
--  Build TF-A:
-
-   .. code:: shell
-
-      make PLAT=fvp_r BL33=<path_to_os.bin> all fip
-
-   Enable TBBR by adding the following options to the make command:
-
-   .. code:: shell
-
-      MBEDTLS_DIR=<path_to_mbedtls_directory>  \
-      TRUSTED_BOARD_BOOT=1 \
-      GENERATE_COT=1 \
-      ARM_ROTPK_LOCATION=devel_rsa  \
-      ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
-
-*Copyright (c) 2021, Arm Limited. All rights reserved.*

diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index 35c0c59..652337e 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst

@@ -7,7 +7,6 @@
 
    juno/index
    fvp/index
-   fvp_r/index
    fvp-ve/index
    tc/index
    arm_fpga/index
@@ -22,4 +21,4 @@
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*

diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 1e37696..e241f57 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst

@@ -56,7 +56,7 @@
 
 #. Obtain SCP binaries (Juno)
 
-   This version of TF-A is tested with SCP version 2.15.0 on Juno. You can
+   This version of TF-A is tested with SCP version 2.14.0 on Juno. You can
    download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
    from `TF-A downloads page`_. Alternatively, you can `build
    the binaries from source`_.
@@ -241,11 +241,11 @@
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
 
 .. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
 .. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
-.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.15.0/juno/
+.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.14.0/juno/
 .. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
 .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
 .. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en

diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
index 467738c..d57b48e 100644
--- a/docs/plat/arm/tc/index.rst
+++ b/docs/plat/arm/tc/index.rst

@@ -17,12 +17,8 @@
 the Total Compute platform number. The platforms support the CPU variants
 listed as below:
 
--  TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
--  TC1 has support for Cortex A510, Cortex A715 and Cortex X3. (Note TC1 is now deprecated)
--  TC2 has support for Cortex A520, Cortex A720 and Cortex x4. (Note TC2 is now deprecated)
 -  TC3 has support for Cortex A520, Cortex A725 and Cortex x925.
 
-
 Boot Sequence
 -------------
 
@@ -59,6 +55,6 @@
 
 --------------
 
-*Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2020-2025, Arm Limited. All rights reserved.*
 
 .. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads

diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 0b53d1d..a30f55d 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst

@@ -22,6 +22,7 @@
    mt8183
    mt8186
    mt8188
+   mt8189
    mt8192
    mt8195
    mt8196
@@ -63,8 +64,6 @@
    currently have associated documentation:
 
    - Arm Neoverse N1 System Development Platform (N1SDP)
-   - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
-   - Arm SGI-575
    - MediaTek MT8173 SoCs
 
 Deprecated platforms
@@ -73,10 +72,25 @@
 +----------------+----------------+--------------------+--------------------+
 |    Platform    |     Vendor     | Deprecated version |  Deleted version   |
 +================+================+====================+====================+
-|      TC2       |      Arm       |        2.12        |         TBD        |
+|      TC2       |      Arm       |        2.12        |         2.13       |
+|                |                |                    |                    |
++----------------+----------------+--------------------+--------------------+
+|     fvp_r      |      Arm       |        2.13        |         2.13       |
+|                |                |                    |                    |
++----------------+----------------+--------------------+--------------------+
+|    SGI-575     |      Arm       |        2.13        |         2.13       |
+|                |                |                    |                    |
++----------------+----------------+--------------------+--------------------+
+|   RD-N1-Edge   |      Arm       |        2.13        |         2.13       |
+|                |                |                    |                    |
++----------------+----------------+--------------------+--------------------+
+|     RD-V1      |      Arm       |        2.13        |         2.13       |
+|                |                |                    |                    |
++----------------+----------------+--------------------+--------------------+
+|    RD-V1-MC    |      Arm       |        2.13        |         2.13       |
 |                |                |                    |                    |
 +----------------+----------------+--------------------+--------------------+
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*

diff --git a/docs/plat/mt8189.rst b/docs/plat/mt8189.rst
new file mode 100644
index 0000000..81aa129
--- /dev/null
+++ b/docs/plat/mt8189.rst

@@ -0,0 +1,22 @@
+MediaTek 8189
+=============
+
+MediaTek 8189 (MT8189) is a 64-bit ARM SoC introduced by MediaTek in 2024.
+The chip incorporates eight cores - six Cortex-A55 cores, two Cortex-A78
+cores.
+Cortex-A55 can operate at up to 2.0 GHz.
+Cortex-A78 can operate at up to 3.0 GHz.
+
+Boot Sequence
+-------------
+
+::
+
+    Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
+
+How to Build
+------------
+
+.. code:: shell
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8189 DEBUG=1 COREBOOT=1

diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 87bb6a5..e64b989 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst

@@ -12,6 +12,43 @@
 STM32MP2 Versions
 -----------------
 
+Here are the variants for STM32MP2:
+- STM32MP21
+- STM32MP23
+- STM32MP25
+
+STM32MP21 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC
+- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Basic + Cortex-A35 @ 1.2GHz
+- C      Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D      Basic + Cortex-A35 @ 1.5GHz
+- F      Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP23 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP23 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - H264 - 3D GPU - AI / NN - LVDS / DSI
+- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Basic + Cortex-A35 @ 1.2GHz
+- C      Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D      Basic + Cortex-A35 @ 1.5GHz
+- F      Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP25 Versions
+~~~~~~~~~~~~~~~~~~
 The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
 
 - STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
@@ -70,6 +107,10 @@
 
 - | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
   | Default: 1
+- | ``STM32MP21``: to select STM32MP21 variant configuration.
+  | Default: 0
+- | ``STM32MP23``: to select STM32MP23 variant configuration.
+  | Default: 0
 - | ``STM32MP25``: to select STM32MP25 variant configuration.
   | Default: 1
 
@@ -154,4 +195,4 @@
 .. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
 .. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
 
-*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
+*Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved*

diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst
index d22a46d..acb67a6 100644
--- a/docs/plat/xilinx-versal-net.rst
+++ b/docs/plat/xilinx-versal-net.rst

@@ -24,6 +24,11 @@
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31
 ```
 
+To build TF-A with SDEI_SUPPORT:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SDEI_SUPPORT=1 bl31
+```
+
 Xilinx Versal NET platform specific build options
 -------------------------------------------------
 

diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
index 7185d91..a654a0b 100644
--- a/docs/plat/xilinx-versal.rst
+++ b/docs/plat/xilinx-versal.rst

@@ -59,6 +59,57 @@
     -   `6`   : SGI 6 (Default)
     -   `7`   : SGI 7
 
+Configurable Stack Size
+-----------------------
+
+The stack size in TF-A for the Versal platform is configurable.
+The custom package can define the desired stack size as per the requirement in
+the makefile as follows:
+
+.. code-block:: shell
+
+    PLATFORM_STACK_SIZE := <value>
+
+    $(eval $(call add_define,PLATFORM_STACK_SIZE))
+
+CUSTOM SIP Service Support
+--------------------------
+
+- Dedicated SMC FID ``VERSAL_SIP_SVC_CUSTOM(0x82002000)`` (32-bit) /
+  ``(0xC2002000)`` (64-bit) is used by a custom package for providing
+  CUSTOM SIP service.
+
+- By default, the platform provides a bare minimum definition for
+  ``custom_smc_handler`` in this service.
+
+- To use this service, the custom package should implement its own SMC handler
+  named ``custom_smc_handler``. Once the custom package is included in the
+  TF-A build, its definition of ``custom_smc_handler`` is enabled.
+
+Custom Package Makefile Fragment Inclusion in TF-A Build
+--------------------------------------------------------
+
+- Custom package is not directly part of the TF-A source.
+
+- ``<CUSTOM_PKG_PATH>`` is the location where the user clones a
+  custom package locally.
+
+- The custom package must implement a makefile fragment named
+  ``custom_pkg.mk`` so it can be included in the TF-A build.
+
+- ``custom_pkg.mk`` should specify all the rules to include custom package
+  specific header files, dependent libraries, and source files that are
+  required to be part of the TF-A build.
+
+- When ``<CUSTOM_PKG_PATH>`` is specified in the TF-A build command,
+  ``custom_pkg.mk`` is included from ``<CUSTOM_PKG_PATH>``.
+
+- Example TF-A build command:
+
+.. code-block:: shell
+
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=versal RESET_TO_BL31=1 bl31 CUSTOM_PKG_PATH=<...>
+
 # PLM->TF-A Parameter Passing
 ------------------------------
 The PLM populates a data structure with image information for the TF-A. The TF-A

diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 327c67b..4157659 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst

@@ -2460,6 +2460,163 @@
 The function returns E_RMM_OK on success, RMM_E_INVAL if arguments are invalid and
 E_RMM_UNK if the SMC is not implemented or if interface version is < 0.4.
 
+Function : plat_rmmd_el3_ide_key_program() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint64_t, uint64_t, uint64_t, struct rp_ide_key_info_t *, uint64_t, uint64_t
+    Return   : int
+
+This function sets the key/IV info for an IDE stream at the Root port. The key is 256 bits
+and IV is 96 bits. The caller calls this SMC to program this key to the Rx and Tx ports
+and for each substream corresponding to a single keyset. The platform should validate
+the arguments `Ecam address` and `Rootport ID` before acting on it. The arguments `request ID`
+and `cookie` are to be ignored for blocking mode and are pass-through to the response for
+non-blocking mode.
+
+The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs.
+Depending on the expected latency for IDE-KM interface, the platform should choose blocking
+or non-blocking semantics. More details about IDE Setup flow can be found
+in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_.
+
+The parameters of the function are:
+
+    arg0 - The ecam address, to access and configure PCI devices in a system.
+
+    arg1 - The rootport ID used to identify the PCIe rootport of a connected device.
+
+    arg2 - The IDE stream info associated with a physical device, this parameter packs the
+    the keyset, direction, substream and stream ID info.
+
+    arg3 - Structure with key and IV info.
+
+    arg4 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode.
+
+    arg5 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking
+    mode.
+
+The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT
+if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned
+only for non-blocking mode if the IDE-KM interface is busy or the request queue is full.
+E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking
+mode.
+
+Function : plat_rmmd_el3_ide_key_set_go() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
+    Return   : int
+
+This function activates the IDE stream at the Root Port once all the keys have been
+programmed. The platform should validate the arguments `Ecam address` and `Rootport ID`
+before acting on it. The arguments `request ID` and `cookie` are to be ignored for blocking
+mode and are pass-through to the response for non-blocking mode.
+
+The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs.
+Depending on the expected latency for IDE-KM interface, the platform should choose blocking
+or non-blocking semantics. More details about IDE Setup flow can be found
+in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_.
+
+The parameters of the function are:
+
+    arg0 - The ecam address, to access and configure PCI devices in a system.
+
+    arg1 - The rootport ID used to identify the PCIe rootport of a connected device.
+
+    arg2 - The IDE stream info associated with a physical device, this parameter packs the
+    the keyset, direction, substream and stream ID info.
+
+    arg3 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode.
+
+    arg4 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking
+    mode.
+
+The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT
+if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned
+only for non-blocking mode if the IDE-KM interface is busy or the request queue is full.
+E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking
+mode.
+
+Function : plat_rmmd_el3_ide_key_set_stop() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
+    Return   : int
+
+This function stops the IDE stream and is used to tear down the IDE stream at Root Port.
+The platform should validate the arguments `Ecam address` and `Rootport ID` before acting
+on it. The arguments `request ID` and `cookie` are to be ignored for blocking
+mode and are pass-through to the response for non-blocking mode.
+
+The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs.
+Depending on the expected latency for IDE-KM interface, the platform should choose blocking
+or non-blocking semantics. More details about IDE Setup flow can be found
+in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_.
+
+The parameters of the function are:
+
+    arg0 - The ecam address, to access and configure PCI devices in a system.
+
+    arg1 - The rootport ID used to identify the PCIe rootport of a connected device.
+
+    arg2 - The IDE stream info associated with a physical device, this parameter packs the
+    the keyset, direction, substream and stream ID info.
+
+    arg3 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode.
+
+    arg4 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking
+    mode.
+
+The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT
+if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned
+only for non-blocking mode if the IDE-KM interface is busy or the request queue is full.
+E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking
+mode.
+
+Function : plat_rmmd_el3_ide_km_pull_response() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint64_t, uint64_t, uint64_t *, uint64_t *, uint64_t *
+    Return   : int
+
+This function retrieves a reponse for any of the prior non-blocking IDE-KM requests. The
+caller has to identify the request and populate the accurate response. For blocking calls,
+this function always returns E_RMM_UNK.
+
+The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs.
+Depending on the expected latency for IDE-KM interface, the platform should choose blocking
+or non-blocking semantics. More details about IDE Setup flow can be found
+in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_.
+
+The parameters of the function are:
+
+    arg0 - The ecam address, to access and configure PCI devices in a system.
+
+    arg1 - The rootport ID used to identify the PCIe rootport of a connected device.
+
+    arg2 - Retrieved response corresponding to the previous IDE_KM request.
+
+    arg3 - returns the passthrough request ID of the retrieved response.
+
+    arg4 - returns the passthrough cookie of the retrieved response.
+
+The function returns E_RMM_OK if response is retrieved successfully, E_RMM_INVAL if arguments
+to this function are invalid, E_RMM_UNK if response retrieval failed for an unknown error or
+IDE-KM interface is having blocking semantics, E_RMM_AGAIN if the response queue is empty.
+
+The `arg2` return parameter can return the following values:
+E_RMM_OK - The previous request was successful.
+E_RMM_FAULT - The previous request was not successful.
+E_RMM_INVAL - Arguments to previous request were incorrect.
+E_RMM_UNK - Previous request returned Unknown error.
+
 Function : bl31_plat_enable_mmu [optional]
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -3771,6 +3928,58 @@
 Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer
 to :ref:`Measured Boot Design` for more details.
 
+Live Firmware Activation Interface
+----------------------------------
+
+Function : plat_lfa_get_components()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : plat_lfa_component_info_t **
+    Return   : int
+
+This platform API provides the list of LFA components available for activation.
+It populates a pointer to an array of ``plat_lfa_component_info_t`` structures,
+which contain information about each component (like UUID, ID, etc.). It returns
+0 on success, or a standard error code on failure.
+
+Function : is_plat_lfa_activation_pending()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint32_t
+    Return   : bool
+
+This platform API checks if the specified LFA component, identified
+by its ``lfa_component_id``, is available for activation. It returns
+true if available, otherwise false.
+
+Function : plat_lfa_cancel()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint32_t
+    Return   : int
+
+This platform API allows the platform to cancel an ongoing update or activation
+process for the specified ``lfa_component_id``. It returns 0 on success or
+a standard error code on failure.
+
+Function : plat_lfa_load_auth_image()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint32_t
+    Return   : int
+
+The platform uses this API to load, authenticate and measure the component
+specified by ``lfa_component_id``. It should return 0 on success or appropriate
+error codes for load/authentication failures.
+
 --------------
 
 *Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.*

diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst
index c287599..97b4b44 100644
--- a/docs/process/commit-style.rst
+++ b/docs/process/commit-style.rst

@@ -36,6 +36,9 @@
 
     [optional footer(s)]
 
+Note that the type, the scope and the first letter of the description (also
+called subject by the commitlint checker) must be lower case.
+
 The following example commit message demonstrates the use of the
 ``refactor`` type and the ``amu`` scope:
 
@@ -144,7 +147,7 @@
 
 --------------
 
-*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.*
 
 .. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
 .. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html

diff --git a/docs/sbom.cdx.json b/docs/sbom.cdx.json
new file mode 100644
index 0000000..795e5d5
--- /dev/null
+++ b/docs/sbom.cdx.json

@@ -0,0 +1,47 @@
+{
+  "bomFormat": "CycloneDX",
+  "specVersion": "1.6",
+  "version": 1,
+  "metadata": {
+    "authors": [
+      {
+        "name": "@VCS_SBOM_AUTHORS@"
+      }
+    ]
+  },
+  "components": [
+    {
+      "type": "library",
+      "bom-ref": "pkg:github/TrustedFirmware-A/trusted-firmware-a@@VCS_TAG@",
+      "cpe": "cpe:2.3:a:trustedfirmware.org:trusted-firmware-a:@VCS_TAG@:*:*:*:*:*:*:*",
+      "name": "trusted-firmware-a",
+      "version": "@VCS_VERSION@",
+      "description": "Reference implementation of secure software for Arm A-Profile architectures",
+      "authors": [
+        {
+          "name": "@VCS_AUTHORS@"
+        }
+      ],
+      "supplier": {
+        "name": "trustedfirmware.org"
+      },
+      "licenses": [
+        {
+          "license": {
+            "id": "BSD-3-Clause"
+          }
+        }
+      ],
+      "externalReferences": [
+        {
+          "type": "vcs",
+          "url": "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
+        },
+        {
+          "type": "vcs",
+          "url": "https://github.com/TrustedFirmware-A/trusted-firmware-a"
+        }
+      ]
+    }
+  ]
+}

diff --git a/docs/threat_model/firmware_threat_model/index.rst b/docs/threat_model/firmware_threat_model/index.rst
index ce1752f..89205de 100644
--- a/docs/threat_model/firmware_threat_model/index.rst
+++ b/docs/threat_model/firmware_threat_model/index.rst

@@ -29,13 +29,12 @@
 
    threat_model
    threat_model_el3_spm
-   threat_model_fvp_r
    threat_model_rse_interface
    threat_model_arm_cca
    threat_model_fw_update_and_recovery
 
 --------------
 
-*Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.*
 
 .. _STRIDE threat modeling technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model

diff --git a/docs/threat_model/firmware_threat_model/threat_model_fvp_r.rst b/docs/threat_model/firmware_threat_model/threat_model_fvp_r.rst
deleted file mode 100644
index 0b71bf0..0000000
--- a/docs/threat_model/firmware_threat_model/threat_model_fvp_r.rst
+++ /dev/null

@@ -1,99 +0,0 @@
-fvp_r-Platform Threat Model
-***************************
-
-************************
-Introduction
-************************
-This document provides a threat model for TF-A fvp_r platform.
-
-************************
-Target of Evaluation
-************************
-In this threat model, the target of evaluation is the fvp_r platform of Trusted
-Firmware for A-class Processors (TF-A).  The fvp_r platform provides limited
-support of AArch64 R-class Processors (v8-R64).
-
-This is a delta document, only pointing out differences from the general TF-A
-threat-model document, :ref:`Generic Threat Model`
-
-BL1 Only
-========
-The most fundamental difference between the threat model for the current fvp_r
-implementation compared to the general TF-A threat model, is that fvp_r is
-currently limited to BL1 only.  Any threats from the general TF-A threat model
-unrelated to BL1 are therefore not relevant to the fvp_r implementation.
-
-The fvp_r BL1 implementation directly loads a customer/partner-defined runtime
-system.  The threat model for that runtime system, being partner-defined, is
-out-of-scope for this threat-model.
-
-Relatedly, all exceptions, synchronous and asynchronous, are disabled during BL1
-execution.  So, any references to exceptions are not relevant.
-
-EL3 is Unsupported and All Secure
-=================================
-v8-R64 cores do not support EL3, and (essentially) all operation is defined as
-Secure-mode.  Therefore:
-
-    - Any threats regarding NS operation are not relevant.
-
-    - Any mentions of SMCs are also not relevant.
-
-    - Anything otherwise-relevant code running in EL3 is instead run in EL2.
-
-MPU instead of MMU
-==================
-v8-R64 cores, running in EL2, use an MPU for memory management, rather than an
-MMU.  The MPU in the fvp_r implementation is configured to function effectively
-identically with the MMU for the usual BL1 implementation.  There are
-memory-map differences, but the MPU configuration is functionally equivalent.
-
-No AArch32 Support
-==================
-Another substantial difference between v8-A and v8-R64 cores is that v8-R64 does
-not support AArch32.  However, this is not believed to have any threat-modeling
-ramifications.
-
-
-Threat Assessment
-=================
-For this section, please reference the Threat Assessment under the general TF-A
-threat-model document, :ref:`Generic Threat Model`
-
-The following threats from that document are still relevant to the fvp_r
-implementation:
-
-    - ID 01:  An attacker can mangle firmware images to execute arbitrary code.
-
-    - ID 03:  An attacker can use Time-of-Check-Time-of-Use (TOCTOU) attack to
-      bypass image authentication during the boot process.
-
-    - ID 04:  An attacker with physical access can execute arbitrary image by
-      bypassing the signature verification stage using clock- or power-glitching
-      techniques.
-
-    - ID 05:  Information leak via UART logs such as crashes
-
-    - ID 06:  An attacker can read sensitive data and execute arbitrary code
-      through the external debug and trace interface.
-
-    - ID 08:  Memory corruption due to memory overflows and lack of boundary
-      checking when accessing resources could allow an attacker to execute 
-      arbitrary code, modify some state variable to change the normal flow of
-      the program, or leak sensitive.
-
-    - ID 11:  Misconfiguration of the Memory Protection Unit (MPU) may allow
-      normal world software to access sensitive data or execute arbitrary code.
-      Arguably, MPUs having fewer memory regions, there may be a temptation to
-      share memory regions, making this a greater threat.  However, since the
-      fvp_r implementation is limited to BL1, since BL1's regions are fixed,
-      and since the MPU configuration is equivalent with that for the fvp
-      platform and others, this is not expected to be a concern.
-
-    - ID 15:  Improper handling of input data received over a UART interface may
-      allow an attacker to tamper with TF-A execution environment.
-
-
---------------
-
-*Copyright (c) 2021-2024, Arm Limited. All rights reserved.*

diff --git a/docs/tools/memory-layout-tool.rst b/docs/tools/memory-layout-tool.rst
index d9c358d..0a447c5 100644
--- a/docs/tools/memory-layout-tool.rst
+++ b/docs/tools/memory-layout-tool.rst

@@ -41,7 +41,7 @@
 
 .. code:: shell
 
-    $ poetry run memory -s
+    $ poetry run memory symbols
     build-path: build/fvp/release
     Virtual Address Map:
                +------------__BL1_RAM_END__------------+---------------------------------------+
@@ -116,14 +116,14 @@
 Memory Footprint
 ~~~~~~~~~~~~~~~~
 
-The tool enables users to view static memory consumption. When the options
-``-f``, or ``--footprint`` are provided, the script analyses the ELF binaries in
-the build path to generate a table (per memory type), showing memory allocation
-and usage. This is the default output generated by the tool.
+The tool enables users to view static memory consumption. When the ``footprint``
+command is provided, the script analyses the ELF binaries in the build path to
+generate a table (per memory type), showing memory allocation and usage. This is
+the default output generated by the tool.
 
 .. code:: shell
 
-    $ poetry run memory -f
+    $ poetry run memory footprint
     build-path: build/fvp/release
     +----------------------------------------------------------------------------+
     |                         Memory Usage (bytes) [RAM]                         |
@@ -150,13 +150,13 @@
 Memory Tree
 ~~~~~~~~~~~
 
-A hierarchical view of the memory layout can be produced by passing the option
-``-t`` or ``--tree`` to the tool. This gives the start, end, and size of each
-module, their ELF segments as well as sections.
+A hierarchical view of the memory layout can be produced by passing the ``tree``
+command to the tool. This gives the start, end, and size of each module, their
+ELF segments as well as sections.
 
 .. code:: shell
 
-    $ poetry run memory -t
+    $ poetry run memory tree
     build-path: build/fvp/release
     name                                       start        end       size
     bl1                                            0    400c000    400c000
@@ -209,7 +209,7 @@
 
 .. code::
 
-    $ poetry run memory -t --depth 2
+    $ poetry run memory tree --depth 2
     build-path: build/fvp/release
     name                          start        end       size
     bl1                               0    400c000    400c000
@@ -229,6 +229,169 @@
     ├── 00                      4003000    4010000       d000
     └── 01                      4010000    4021000      11000
 
+Memory Summary
+~~~~~~~~~~~~~~
+
+The tool provides a by-translation-unit summary of the sizes (``text``, ``bss``,
+``data``) contributed by each translation unit or group of translation units.
+For example, to print a table of an FVP build, with a path depth of 3:
+
+.. code::
+
+   $ poetry run memory summary build/fvp/debug/bl1/bl1.map  -d 3
+    | Module                                 |         .text |       .data |          .bss |
+    |----------------------------------------|---------------|-------------|---------------|
+    | [fill]                                 |   3204(+3204) |       0(+0) |       97(+97) |
+    | bl1/aem_generic.o                      |         0(+0) |       0(+0) |         0(+0) |
+    | bl1/arm_bl1_fwu.o                      |     224(+224) |     80(+80) |         0(+0) |
+    | bl1/arm_bl1_setup.o                    |     608(+608) |       0(+0) |       17(+17) |
+    | bl1/arm_common.o                       |     116(+116) |       0(+0) |         0(+0) |
+    | bl1/arm_console.o                      |     116(+116) |       0(+0) |       40(+40) |
+    | bl1/arm_dev_rotpk.o                    |         0(+0) |       0(+0) |         0(+0) |
+    | bl1/arm_dyn_cfg.o                      |     276(+276) |       0(+0) |   7184(+7184) |
+    | bl1/arm_dyn_cfg_helpers.o              |     364(+364) |       0(+0) |         0(+0) |
+    | bl1/arm_err.o                          |       12(+12) |       0(+0) |         0(+0) |
+    | bl1/arm_fconf_io.o                     |         0(+0) |   952(+952) |         0(+0) |
+    | bl1/arm_helpers.o                      |       44(+44) |       0(+0) |         0(+0) |
+    | bl1/arm_io_storage.o                   |     480(+480) |       0(+0) |       32(+32) |
+    | bl1/auth_mod.o                         |   1288(+1288) |       0(+0) |         0(+0) |
+    | bl1/backtrace.o                        |     444(+444) |       0(+0) |         0(+0) |
+    | bl1/bl1_arch_setup.o                   |       16(+16) |       0(+0) |         0(+0) |
+    | bl1/bl1_context_mgmt.o                 |     340(+340) |       0(+0) |   1392(+1392) |
+    | bl1/bl1_entrypoint.o                   |     236(+236) |       0(+0) |         0(+0) |
+    | bl1/bl1_exceptions.o                   |   2240(+2240) |       0(+0) |         0(+0) |
+    | bl1/bl1_fwu.o                          |   2188(+2188) |     44(+44) |         0(+0) |
+    | bl1/bl1_main.o                         |     620(+620) |       0(+0) |         0(+0) |
+    | bl1/bl_common.o                        |     772(+772) |       0(+0) |         4(+4) |
+    | bl1/board_arm_helpers.o                |       44(+44) |       0(+0) |         0(+0) |
+    | bl1/board_arm_trusted_boot.o           |       44(+44) |     16(+16) |         0(+0) |
+    | bl1/cache_helpers.o                    |     112(+112) |       0(+0) |         0(+0) |
+    | bl1/cci.o                              |     408(+408) |       0(+0) |       24(+24) |
+    | bl1/context.o                          |     348(+348) |       0(+0) |         0(+0) |
+    | bl1/context_mgmt.o                     |   1692(+1692) |       0(+0) |       48(+48) |
+    | bl1/cortex_a35.o                       |       96(+96) |       0(+0) |         0(+0) |
+    | bl1/cortex_a53.o                       |     248(+248) |       0(+0) |         0(+0) |
+    | bl1/cortex_a57.o                       |     384(+384) |       0(+0) |         0(+0) |
+    | bl1/cortex_a72.o                       |     356(+356) |       0(+0) |         0(+0) |
+    | bl1/cortex_a73.o                       |     304(+304) |       0(+0) |         0(+0) |
+    | bl1/cpu_helpers.o                      |     200(+200) |       0(+0) |         0(+0) |
+    | bl1/crypto_mod.o                       |     380(+380) |       0(+0) |         0(+0) |
+    | bl1/debug.o                            |     224(+224) |       0(+0) |         0(+0) |
+    | bl1/delay_timer.o                      |       64(+64) |       0(+0) |         8(+8) |
+    | bl1/enable_mmu.o                       |     112(+112) |       0(+0) |         0(+0) |
+    | bl1/errata_report.o                    |     564(+564) |       0(+0) |         0(+0) |
+    | bl1/fconf.o                            |     148(+148) |       0(+0) |         0(+0) |
+    | bl1/fconf_dyn_cfg_getter.o             |     656(+656) |     32(+32) |     144(+144) |
+    | bl1/fconf_tbbr_getter.o                |     332(+332) |       0(+0) |       24(+24) |
+    | bl1/fdt_wrappers.o                     |     452(+452) |       0(+0) |         0(+0) |
+    | bl1/fvp_bl1_setup.o                    |     168(+168) |       0(+0) |         0(+0) |
+    | bl1/fvp_common.o                       |     512(+512) |       0(+0) |         8(+8) |
+    | bl1/fvp_cpu_pwr.o                      |     136(+136) |       0(+0) |         0(+0) |
+    | bl1/fvp_err.o                          |       44(+44) |       0(+0) |         0(+0) |
+    | bl1/fvp_helpers.o                      |     148(+148) |       0(+0) |         0(+0) |
+    | bl1/fvp_io_storage.o                   |     228(+228) |       0(+0) |       16(+16) |
+    | bl1/fvp_trusted_boot.o                 |     292(+292) |       0(+0) |         0(+0) |
+    | bl1/generic_delay_timer.o              |     136(+136) |       0(+0) |       16(+16) |
+    | bl1/img_parser_mod.o                   |     588(+588) |       0(+0) |       20(+20) |
+    | bl1/io_fip.o                           |   1332(+1332) |       0(+0) |     100(+100) |
+    | bl1/io_memmap.o                        |     736(+736) |     16(+16) |       32(+32) |
+    | bl1/io_semihosting.o                   |     648(+648) |     16(+16) |         0(+0) |
+    | bl1/io_storage.o                       |   1268(+1268) |       0(+0) |     104(+104) |
+    | bl1/mbedtls_common.o                   |     208(+208) |       0(+0) |         4(+4) |
+    | bl1/mbedtls_crypto.o                   |     636(+636) |       0(+0) |         0(+0) |
+    | bl1/mbedtls_x509_parser.o              |   1588(+1588) |       0(+0) |     120(+120) |
+    | bl1/misc_helpers.o                     |     392(+392) |       0(+0) |         0(+0) |
+    | bl1/multi_console.o                    |     528(+528) |       1(+1) |         8(+8) |
+    | bl1/pl011_console.o                    |     308(+308) |       0(+0) |         0(+0) |
+    | bl1/plat_bl1_common.o                  |     208(+208) |       0(+0) |         0(+0) |
+    | bl1/plat_bl_common.o                   |       40(+40) |       0(+0) |         0(+0) |
+    | bl1/plat_common.o                      |       48(+48) |       0(+0) |         8(+8) |
+    | bl1/plat_log_common.o                  |       48(+48) |       0(+0) |         0(+0) |
+    | bl1/plat_tbbr.o                        |     128(+128) |       0(+0) |         0(+0) |
+    | bl1/platform_helpers.o                 |       12(+12) |       0(+0) |         0(+0) |
+    | bl1/platform_up_stack.o                |       16(+16) |       0(+0) |         0(+0) |
+    | bl1/semihosting.o                      |     352(+352) |       0(+0) |         0(+0) |
+    | bl1/semihosting_call.o                 |         8(+8) |       0(+0) |         0(+0) |
+    | bl1/smmu_v3.o                          |     296(+296) |       0(+0) |         0(+0) |
+    | bl1/sp805.o                            |       64(+64) |       0(+0) |         0(+0) |
+    | bl1/tbbr_cot_bl1.o                     |         0(+0) |     48(+48) |     156(+156) |
+    | bl1/tbbr_cot_common.o                  |         0(+0) |   144(+144) |     306(+306) |
+    | bl1/tbbr_img_desc.o                    |         0(+0) |   768(+768) |         0(+0) |
+    | bl1/tf_log.o                           |     200(+200) |       4(+4) |         0(+0) |
+    | bl1/xlat_tables_arch.o                 |     736(+736) |       0(+0) |         0(+0) |
+    | bl1/xlat_tables_context.o              |     192(+192) |     96(+96) |   1296(+1296) |
+    | bl1/xlat_tables_core.o                 |   2112(+2112) |       0(+0) |         0(+0) |
+    | bl1/xlat_tables_utils.o                |         8(+8) |       0(+0) |         0(+0) |
+    | lib/libc.a/assert.o                    |       48(+48) |       0(+0) |         0(+0) |
+    | lib/libc.a/exit.o                      |       64(+64) |       0(+0) |         8(+8) |
+    | lib/libc.a/memchr.o                    |       44(+44) |       0(+0) |         0(+0) |
+    | lib/libc.a/memcmp.o                    |       52(+52) |       0(+0) |         0(+0) |
+    | lib/libc.a/memcpy.o                    |       32(+32) |       0(+0) |         0(+0) |
+    | lib/libc.a/memmove.o                   |       52(+52) |       0(+0) |         0(+0) |
+    | lib/libc.a/memset.o                    |     140(+140) |       0(+0) |         0(+0) |
+    | lib/libc.a/printf.o                    |   1532(+1532) |       0(+0) |         0(+0) |
+    | lib/libc.a/snprintf.o                  |   1748(+1748) |       0(+0) |         0(+0) |
+    | lib/libc.a/strcmp.o                    |       44(+44) |       0(+0) |         0(+0) |
+    | lib/libc.a/strlen.o                    |       28(+28) |       0(+0) |         0(+0) |
+    | lib/libfdt.a/fdt.o                     |   1460(+1460) |       0(+0) |         0(+0) |
+    | lib/libfdt.a/fdt_ro.o                  |   1392(+1392) |       0(+0) |         0(+0) |
+    | lib/libfdt.a/fdt_wip.o                 |     244(+244) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/asn1parse.o           |     956(+956) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/bignum.o              |   6796(+6796) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/bignum_core.o         |   3252(+3252) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/constant_time.o       |     280(+280) |       0(+0) |         8(+8) |
+    | lib/libmbedtls.a/md.o                  |     504(+504) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/memory_buffer_alloc.o |   1264(+1264) |       0(+0) |       40(+40) |
+    | lib/libmbedtls.a/oid.o                 |     752(+752) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/pk.o                  |     872(+872) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/pk_wrap.o             |     848(+848) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/pkparse.o             |     516(+516) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/platform.o            |       92(+92) |     24(+24) |         0(+0) |
+    | lib/libmbedtls.a/platform_util.o       |       96(+96) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/rsa.o                 |   6588(+6588) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/rsa_alt_helpers.o     |   2340(+2340) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/sha256.o              |   1448(+1448) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/x509.o                |   1028(+1028) |       0(+0) |         0(+0) |
+    | Subtotals                              | 69632(+69632) | 2241(+2241) | 11264(+11264) |
+    Total Static RAM memory (data + bss): 13505(+13505) bytes
+    Total Flash memory (text + data): 71873(+71873) bytes
+
+A delta between two images can be generated by passing the ``--old`` option with
+a path to the previous map file.
+
+For example:
+
+.. code::
+
+    $ poetry run memory summary ../maps/fvp-tbb-mbedtls/bl1.map --old ../maps/fvp-tbb-mbedtls/bl1.map.old -d 1
+    | Module    |         .text |    .data |         .bss |
+    |-----------|---------------|----------|--------------|
+    | [fill]    |    780(-2424) |    0(+0) |    321(+224) |
+    | bl1       |   32024(+108) | 2217(+0) |    11111(+0) |
+    | lib       | 45020(+10508) |   24(+0) |  1880(+1824) |
+    | Subtotals |  77824(+8192) | 2241(+0) | 13312(+2048) |
+    Total Static RAM memory (data + bss): 15553(+2048) bytes
+    Total Flash memory (text + data): 80065(+8192) bytes
+
+Note that since the old map file includes the required suffix, specifying the
+``--old`` argument is optional here.
+
+Under some circumstances, some executables are padded to meet certain
+alignments, such as a 4KB page boundary, and excluding that padding can provide
+more helpful diffs. Taking the last example, and adding the ``-e`` argument
+yields such a summary:
+
+.. code::
+
+    $ poetry run memory summary ../maps/fvp-tbb-mbedtls/bl1.map --old ../maps/fvp-tbb-mbedtls/bl1.map.old  -d 1 -e
+    | Module    |         .text |    .data |         .bss |
+    |-----------|---------------|----------|--------------|
+    | bl1       |   32024(+108) | 2217(+0) |    11111(+0) |
+    | lib       | 45020(+10508) |   24(+0) |  1880(+1824) |
+    | Subtotals | 77044(+10616) | 2241(+0) | 12991(+1824) |
+    Total Static RAM memory (data + bss): 15232(+1824) bytes
+    Total Flash memory (text + data): 79285(+10616) bytes
+
 --------------
 
 *Copyright (c) 2023-2025, Arm Limited. All rights reserved.*

diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index 40d2efd..ae2b9bb 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c

@@ -143,7 +143,7 @@
 	 * rest of bits are write ignore
 	 */
 	mmio_write_32(cci_base +
-		      SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
+		      SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
 		      DVM_EN_BIT | SNOOP_EN_BIT);
 
 	/*
@@ -171,7 +171,7 @@
 	 * rest of bits are write ignore.
 	 */
 	mmio_write_32(cci_base +
-		      SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG,
+		      SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
 		      ~(DVM_EN_BIT | SNOOP_EN_BIT));
 
 	/*

diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c
index b310ff4..74d9fad 100644
--- a/drivers/arm/css/scp/css_pm_scmi.c
+++ b/drivers/arm/css/scp/css_pm_scmi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -309,10 +309,11 @@
 	 */
 	mmio_write_64(PLAT_ARM_TRUSTED_MAILBOX_BASE, 0U);
 
+	unsigned int core_pos = plat_my_core_pos();
 	/*
 	 * Send powerdown request to online secondary core(s)
 	 */
-	ret = psci_stop_other_cores(plat_my_core_pos(), 0, css_raise_pwr_down_interrupt);
+	ret = psci_stop_other_cores(core_pos, 0, css_raise_pwr_down_interrupt);
 	if (ret != PSCI_E_SUCCESS) {
 		ERROR("Failed to powerdown secondary core(s)\n");
 	}
@@ -321,8 +322,8 @@
 	 * Disable GIC CPU interface to prevent pending interrupt from waking
 	 * up the AP from WFI.
 	 */
-	plat_arm_gic_cpuif_disable();
-	plat_arm_gic_redistif_off();
+	gic_cpuif_disable(core_pos);
+	gic_pcpu_off(core_pos);
 
 	/*
 	 * Issue SCMI command. First issue a graceful

diff --git a/drivers/arm/css/scp/css_pm_scpi.c b/drivers/arm/css/scp/css_pm_scpi.c
index 02be070..781b216 100644
--- a/drivers/arm/css/scp/css_pm_scpi.c
+++ b/drivers/arm/css/scp/css_pm_scpi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -121,12 +121,6 @@
 {
 	uint32_t response;
 
-	/*
-	 * Disable GIC CPU interface to prevent pending interrupt
-	 * from waking up the AP from WFI.
-	 */
-	plat_arm_gic_cpuif_disable();
-
 	/* Send the power down request to the SCP */
 	response = scpi_sys_power_state(scpi_system_shutdown);
 
@@ -143,12 +137,6 @@
 {
 	uint32_t response;
 
-	/*
-	 * Disable GIC CPU interface to prevent pending interrupt
-	 * from waking up the AP from WFI.
-	 */
-	plat_arm_gic_cpuif_disable();
-
 	/* Send the system reset request to the SCP */
 	response = scpi_sys_power_state(scpi_system_reboot);
 

diff --git a/drivers/arm/css/dsu/dsu.c b/drivers/arm/dsu/dsu.c
similarity index 83%
rename from drivers/arm/css/dsu/dsu.c
rename to drivers/arm/dsu/dsu.c
index f0e8df1..dea89c5 100644
--- a/drivers/arm/css/dsu/dsu.c
+++ b/drivers/arm/dsu/dsu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,7 +10,9 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
-#include <drivers/arm/css/dsu.h>
+#include <drivers/arm/dsu.h>
+#include <dsu_def.h>
+#include <lib/utils_def.h>
 
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
@@ -133,3 +135,30 @@
 	restore_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
 }
 
+void dsu_driver_init(const dsu_driver_data_t *plat_driver_data)
+{
+	uint64_t actlr_el3 = read_actlr_el3();
+	uint64_t pwrctlr = read_clusterpwrctlr_el1();
+	uint64_t pwrdn = read_clusterpwrdn_el1();
+
+	/* enable access to power control registers. */
+	actlr_el3 |= ACTLR_EL3_PWREN_BIT;
+	write_actlr_el3(actlr_el3);
+
+	UPDATE_REG_FIELD(CLUSTERPWRCTLR_FUNCRET, pwrctlr,
+			plat_driver_data->clusterpwrctlr_funcret);
+
+	UPDATE_REG_FIELD(CLUSTERPWRCTLR_CACHEPWR, pwrctlr,
+			plat_driver_data->clusterpwrctlr_cachepwr);
+
+	write_clusterpwrctlr_el1(pwrctlr);
+
+	UPDATE_REG_FIELD(CLUSTERPWRDN_PWRDN, pwrdn,
+			plat_driver_data->clusterpwrdwn_pwrdn);
+
+	UPDATE_REG_FIELD(CLUSTERPWRDN_MEMRET, pwrdn,
+			plat_driver_data->clusterpwrdwn_memret);
+
+	write_clusterpwrdn_el1(pwrdn);
+}
+

diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk
new file mode 100644
index 0000000..8b28f21
--- /dev/null
+++ b/drivers/arm/gic/gic.mk

@@ -0,0 +1,44 @@
+#
+# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+GIC_REVISIONS_ := 1 2 3 5
+ifeq ($(filter $(USE_GIC_DRIVER),$(GIC_REVISIONS_)),)
+$(error USE_GIC_DRIVER can only be one of $(GIC_REVISIONS_))
+endif
+
+ifeq (${USE_GIC_DRIVER},2)
+include drivers/arm/gic/v2/gicv2.mk
+GIC_SOURCES	:=	${GICV2_SOURCES}			\
+			drivers/arm/gic/v2/gicv2_base.c	\
+			plat/common/plat_gicv2.c
+else ifeq (${USE_GIC_DRIVER},3)
+include drivers/arm/gic/v3/gicv3.mk
+GIC_SOURCES	:=	${GICV3_SOURCES}			\
+			drivers/arm/gic/v3/gicv3_base.c	\
+			plat/common/plat_gicv3.c
+else ifeq (${USE_GIC_DRIVER},5)
+ifneq (${ENABLE_FEAT_GCIE},1)
+$(error USE_GIC_DRIVER=5 requires ENABLE_FEAT_GCIE=1)
+endif
+$(warning GICv5 support is experimental!)
+GIC_SOURCES	:=	drivers/arm/gicv5/gicv5_iri.c		\
+			plat/common/plat_gicv5.c
+endif
+
+ifneq (${ENABLE_FEAT_GCIE},0)
+GIC_SOURCES	+=	drivers/arm/gicv5/gicv5_cpuif.c		\
+			drivers/arm/gicv5/gicv5_main.c
+endif
+
+ifeq ($(ARCH),aarch64)
+BL31_SOURCES	+=	${GIC_SOURCES}
+else
+BL32_SOURCES	+=	${GIC_SOURCES}
+endif
+
+$(eval $(call add_defines,\
+	USE_GIC_DRIVER \
+))

diff --git a/drivers/arm/gic/v2/gicdv2_helpers.c b/drivers/arm/gic/v2/gicdv2_helpers.c
index db9ba87..464bb34 100644
--- a/drivers/arm/gic/v2/gicdv2_helpers.c
+++ b/drivers/arm/gic/v2/gicdv2_helpers.c

@@ -8,6 +8,7 @@
 
 #include <drivers/arm/gic_common.h>
 #include <lib/mmio.h>
+#include <lib/utils_def.h>
 
 #include "../common/gic_common_private.h"
 
@@ -256,7 +257,7 @@
 	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
+	gicd_write_igroupr(base, id, reg_val | BIT_32(bit_num));
 }
 
 void gicd_clr_igroupr(uintptr_t base, unsigned int id)
@@ -264,35 +265,35 @@
 	unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
 	unsigned int reg_val = gicd_read_igroupr(base, id);
 
-	gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
+	gicd_write_igroupr(base, id, reg_val & ~BIT_32(bit_num));
 }
 
 void gicd_set_isenabler(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
 
-	gicd_write_isenabler(base, id, (1U << bit_num));
+	gicd_write_isenabler(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_icenabler(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
 
-	gicd_write_icenabler(base, id, (1U << bit_num));
+	gicd_write_icenabler(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_ispendr(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
 
-	gicd_write_ispendr(base, id, (1U << bit_num));
+	gicd_write_ispendr(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_icpendr(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
 
-	gicd_write_icpendr(base, id, (1U << bit_num));
+	gicd_write_icpendr(base, id, BIT_32(bit_num));
 }
 
 unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
@@ -307,19 +308,19 @@
 {
 	unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
 
-	gicd_write_isactiver(base, id, (1U << bit_num));
+	gicd_write_isactiver(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_icactiver(uintptr_t base, unsigned int id)
 {
 	unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
 
-	gicd_write_icactiver(base, id, (1U << bit_num));
+	gicd_write_icactiver(base, id, BIT_32(bit_num));
 }
 
 void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
 {
-	uint8_t val = pri & GIC_PRI_MASK;
+	uint8_t val = (uint8_t)(pri & GIC_PRI_MASK);
 
 	mmio_write_8(base + GICD_IPRIORITYR + id, val);
 }

diff --git a/plat/arm/common/arm_gicv2.c b/drivers/arm/gic/v2/gicv2_base.c
similarity index 74%
copy from plat/arm/common/arm_gicv2.c
copy to drivers/arm/gic/v2/gicv2_base.c
index 80a845f..c51c195 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/drivers/arm/gic/v2/gicv2_base.c

@@ -1,24 +1,19 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <platform_def.h>
 
+#include <drivers/arm/gic.h>
 #include <drivers/arm/gicv2.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
-/******************************************************************************
- * The following functions are defined as weak to allow a platform to override
- * the way the GICv2 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
+#if USE_GIC_DRIVER != 2
+#error "This file should only be used with USE_GIC_DRIVER=2"
+#endif
 
 /******************************************************************************
  * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
@@ -43,23 +38,16 @@
 /******************************************************************************
  * ARM common helper to initialize the GICv2 only driver.
  *****************************************************************************/
-void plat_arm_gic_driver_init(void)
+void __init gic_init(unsigned int cpu_idx)
 {
 	gicv2_driver_init(&arm_gic_data);
-}
-
-void plat_arm_gic_init(void)
-{
 	gicv2_distif_init();
-	gicv2_pcpu_distif_init();
-	gicv2_set_pe_target_mask(plat_my_core_pos());
-	gicv2_cpuif_enable();
 }
 
 /******************************************************************************
  * ARM common helper to enable the GICv2 CPU interface
  *****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
+void gic_cpuif_enable(unsigned int cpu_idx)
 {
 	gicv2_cpuif_enable();
 }
@@ -67,7 +55,7 @@
 /******************************************************************************
  * ARM common helper to disable the GICv2 CPU interface
  *****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
+void gic_cpuif_disable(unsigned int cpu_idx)
 {
 	gicv2_cpuif_disable();
 }
@@ -75,7 +63,7 @@
 /******************************************************************************
  * ARM common helper to initialize the per cpu distributor interface in GICv2
  *****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
+void gic_pcpu_init(unsigned int cpu_idx)
 {
 	gicv2_pcpu_distif_init();
 	gicv2_set_pe_target_mask(plat_my_core_pos());
@@ -85,29 +73,23 @@
  * Stubs for Redistributor power management. Although GICv2 doesn't have
  * Redistributor interface, these are provided for the sake of uniform GIC API
  *****************************************************************************/
-void plat_arm_gic_redistif_on(void)
+void gic_pcpu_off(unsigned int cpu_idx)
 {
 	return;
 }
 
-void plat_arm_gic_redistif_off(void)
-{
-	return;
-}
-
-
 /******************************************************************************
  * ARM common helper to save & restore the GICv3 on resume from system suspend.
  * The normal world currently takes care of saving and restoring the GICv2
  * registers due to legacy reasons. Hence we just initialize the Distributor
  * on resume from system suspend.
  *****************************************************************************/
-void plat_arm_gic_save(void)
+void gic_save(void)
 {
 	return;
 }
 
-void plat_arm_gic_resume(void)
+void gic_resume(void)
 {
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();

diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c
index a9ae0b5..3415499 100644
--- a/drivers/arm/gic/v2/gicv2_helpers.c
+++ b/drivers/arm/gic/v2/gicv2_helpers.c

@@ -11,6 +11,7 @@
 #include <common/interrupt_props.h>
 #include <drivers/arm/gic_common.h>
 #include <drivers/arm/gicv2.h>
+#include <lib/utils_def.h>
 
 #include "../common/gic_common_private.h"
 #include "gicv2_private.h"
@@ -203,7 +204,7 @@
 		}
 
 		/* We have an SGI or a PPI. They are Group0 at reset */
-		sec_ppi_sgi_mask |= (1u << prop_desc->intr_num);
+		sec_ppi_sgi_mask |= BIT_32((uint32_t)prop_desc->intr_num);
 
 		/* Set the priority of this interrupt */
 		gicd_set_ipriorityr(gicd_base, prop_desc->intr_num,

diff --git a/plat/arm/common/arm_gicv3.c b/drivers/arm/gic/v3/gicv3_base.c
similarity index 76%
copy from plat/arm/common/arm_gicv3.c
copy to drivers/arm/gic/v3/gicv3_base.c
index 5becbcd..57f2314 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/drivers/arm/gic/v3/gicv3_base.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,25 +9,18 @@
 
 #include <common/debug.h>
 #include <common/interrupt_props.h>
+#include <drivers/arm/gic.h>
 #include <drivers/arm/gicv3.h>
 #include <lib/utils.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
-/******************************************************************************
- * The following functions are defined as weak to allow a platform to override
- * the way the GICv3 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
-#pragma weak plat_arm_gic_redistif_on
-#pragma weak plat_arm_gic_redistif_off
+#if USE_GIC_DRIVER != 3
+#error "This file should only be used with USE_GIC_DRIVER=3"
+#endif
 
 /* The GICv3 driver only needs to be initialized in EL3 */
-static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
 /* Default GICR base address to be used for GICR probe. */
 static const uintptr_t gicr_base_addrs[2] = {
@@ -79,7 +72,7 @@
 	return plat_arm_calc_core_pos(mpidr);
 }
 
-static const gicv3_driver_data_t arm_gic_data __unused = {
+gicv3_driver_data_t gic_data __unused = {
 	.gicd_base = PLAT_ARM_GICD_BASE,
 	.gicr_base = 0U,
 	.interrupt_props = arm_interrupt_props,
@@ -101,49 +94,29 @@
 	gicr_frames = plat_gicr_frames;
 }
 
-void __init plat_arm_gic_driver_init(void)
-{
-	/*
-	 * The GICv3 driver is initialized in EL3 and does not need
-	 * to be initialized again in SEL1. This is because the S-EL1
-	 * can use GIC system registers to manage interrupts and does
-	 * not need GIC interface base addresses to be configured.
-	 */
-#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
-	(defined(__aarch64__) && defined(IMAGE_BL31))
-	gicv3_driver_init(&arm_gic_data);
-
-	if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
-		ERROR("No GICR base frame found for Primary CPU\n");
-		panic();
-	}
-#endif
-}
-
 /******************************************************************************
  * ARM common helper to initialize the GIC. Only invoked by BL31
  *****************************************************************************/
-void __init plat_arm_gic_init(void)
+void __init gic_init(unsigned int cpu_idx)
 {
+	gicv3_driver_init(&gic_data);
 	gicv3_distif_init();
-	gicv3_rdistif_init(plat_my_core_pos());
-	gicv3_cpuif_enable(plat_my_core_pos());
 }
 
 /******************************************************************************
  * ARM common helper to enable the GIC CPU interface
  *****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
+void gic_cpuif_enable(unsigned int cpu_idx)
 {
-	gicv3_cpuif_enable(plat_my_core_pos());
+	gicv3_cpuif_enable(cpu_idx);
 }
 
 /******************************************************************************
  * ARM common helper to disable the GIC CPU interface
  *****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
+void gic_cpuif_disable(unsigned int cpu_idx)
 {
-	gicv3_cpuif_disable(plat_my_core_pos());
+	gicv3_cpuif_disable(cpu_idx);
 }
 
 /******************************************************************************
@@ -151,7 +124,7 @@
  * corresponding per-cpu redistributor frame as well as initialize the
  * corresponding interface in GICv3.
  *****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
+void gic_pcpu_init(unsigned int cpu_idx)
 {
 	int result;
 	const uintptr_t *plat_gicr_frames = gicr_frames;
@@ -170,26 +143,22 @@
 		ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
 		panic();
 	}
-	gicv3_rdistif_init(plat_my_core_pos());
+	gicv3_rdistif_init(cpu_idx);
 }
 
 /******************************************************************************
  * ARM common helpers to power GIC redistributor interface
  *****************************************************************************/
-void plat_arm_gic_redistif_on(void)
+void gic_pcpu_off(unsigned int cpu_idx)
 {
-	gicv3_rdistif_on(plat_my_core_pos());
-}
-
-void plat_arm_gic_redistif_off(void)
-{
-	gicv3_rdistif_off(plat_my_core_pos());
+	gicv3_rdistif_off(cpu_idx);
 }
 
 /******************************************************************************
- * ARM common helper to save & restore the GICv3 on resume from system suspend
+ * Common helper to save & restore the GICv3 on resume from system suspend. It
+ * is the platform's responsibility to call these.
  *****************************************************************************/
-void plat_arm_gic_save(void)
+void gic_save(void)
 {
 	gicv3_redist_ctx_t * const rdist_context =
 			(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
@@ -222,7 +191,7 @@
 	 */
 }
 
-void plat_arm_gic_resume(void)
+void gic_resume(void)
 {
 	const gicv3_redist_ctx_t *rdist_context =
 			(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);

diff --git a/drivers/arm/gicv5/gicv5_cpuif.c b/drivers/arm/gicv5/gicv5_cpuif.c
new file mode 100644
index 0000000..eb17206
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_cpuif.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+void gic_cpuif_enable(unsigned int cpu_idx)
+{
+}
+
+void gic_cpuif_disable(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_init(unsigned int cpu_idx)
+{
+	gicv5_enable_ppis();
+}
+
+void gic_pcpu_off(unsigned int cpu_idx)
+{
+}
+

diff --git a/drivers/arm/gicv5/gicv5_iri.c b/drivers/arm/gicv5/gicv5_iri.c
new file mode 100644
index 0000000..049f3f0
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_iri.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+#if USE_GIC_DRIVER != 5
+#error "This file should only be used with USE_GIC_DRIVER=5"
+#endif
+
+void __init gic_init(unsigned int cpu_idx)
+{
+	gicv5_driver_init();
+}
+
+void gic_save(void)
+{
+}
+
+void gic_resume(void)
+{
+}

diff --git a/drivers/arm/gicv5/gicv5_main.c b/drivers/arm/gicv5/gicv5_main.c
new file mode 100644
index 0000000..803a96d
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_main.c

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <cdefs.h>
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+
+#include <bl31/interrupt_mgmt.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv5.h>
+
+/*
+ * Check for a bad platform configuration.
+ * Not expected to be called on release builds.
+ */
+static inline bool probe_component(uintptr_t base_addr, uint8_t component)
+{
+	uint32_t aidr = read_iri_aidr(base_addr);
+
+	if (EXTRACT(IRI_AIDR_COMPONENT, aidr) != component) {
+		ERROR("GICv5 frame belongs to wrong component\n");
+		return false;
+	}
+
+	if (EXTRACT(IRI_AIDR_ARCH_MAJOR, aidr) != IRI_AIDR_ARCH_MAJOR_V5) {
+		ERROR("Bad GICv5 major version\n");
+		return false;
+	}
+
+	/* there was a bump in architecture and we've not updated the driver */
+	assert(EXTRACT(IRI_AIDR_ARCH_MINOR, aidr) == IRI_AIDR_ARCH_MINOR_P0);
+
+	return true;
+}
+
+static inline bool iwb_domain_supported(uint32_t idr0, uint8_t domain)
+{
+	return (EXTRACT(IWB_IDR0_DOMAINS, idr0) & (1U << domain)) != 0U;
+}
+
+static void iwb_configure_domainr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+	uint32_t reg_offset = (wire.id % 16U) * 2U;
+	uint32_t reg_index = wire.id / 16U;
+	uint32_t val = read_iwb_wdomainr(base_addr, reg_index) &
+		       ~(IWB_WDOMAINR_DOMAINX_MASK << reg_offset);
+
+	write_iwb_wdomainr(base_addr, reg_index, val | wire.domain << reg_offset);
+}
+
+static void iwb_configure_wtmr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+	uint32_t reg_offset = wire.id % 32U;
+	uint32_t reg_index = wire.id / 32U;
+	uint32_t val = read_iwb_wtmr(base_addr, reg_index) & ~(1U << reg_offset);
+
+	write_iwb_wtmr(base_addr, reg_index, val | wire.tm << reg_offset);
+}
+
+static void iwb_enable(const struct gicv5_iwb *config)
+{
+	uintptr_t base_addr = config->config_frame;
+	uint32_t idr0;
+	uint16_t num_regs;
+
+	assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IWB));
+
+	idr0 = read_iwb_idr0(base_addr);
+	num_regs = EXTRACT(IWB_IDR0_IWRANGE, idr0) + 1U;
+
+	/* initialise all wires as disabled */
+	for (int i = 0U; i < num_regs; i++) {
+		write_iwb_wenabler(base_addr, i, 0U);
+	}
+
+	/* default all wires to the NS domain */
+	for (int i = 0U; i < num_regs * 2; i++) {
+		write_iwb_wdomainr(base_addr, i, 0x55555555);
+	}
+
+	for (uint32_t i = 0U; i < config->num_wires; i++) {
+		assert(iwb_domain_supported(idr0, config->wires[i].domain));
+		assert(config->wires[i].id <= num_regs * 32);
+
+		iwb_configure_domainr(base_addr, config->wires[i]);
+		iwb_configure_wtmr(base_addr, config->wires[i]);
+	}
+
+	write_iwb_cr0(base_addr, IWB_CR0_IWBEN_BIT);
+	WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base_addr);
+	WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base_addr);
+	WAIT_FOR_IDLE_IWB_CR0(base_addr);
+}
+
+static void irs_configure_wire(uintptr_t base_addr, uint32_t wire, uint8_t domain)
+{
+	write_irs_spi_selr(base_addr, wire);
+	WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+
+	write_irs_spi_domainr(base_addr, domain);
+	WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+}
+
+static void irs_enable(const struct gicv5_irs *config)
+{
+	uint32_t spi_base, spi_range;
+	uintptr_t base_addr = config->el3_config_frame;
+
+	spi_base  = EXTRACT(IRS_IDR7_SPI_BASE, read_irs_idr7(base_addr));
+	spi_range = EXTRACT(IRS_IDR6_SPI_IRS_RANGE, read_irs_idr6(base_addr));
+
+	assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IRS));
+
+	if (spi_range == 0U) {
+		assert(config->num_spis == 0U);
+	}
+
+	/* default all wires to the NS domain */
+	for (uint32_t i = spi_base; i < spi_base + spi_range; i++) {
+		irs_configure_wire(base_addr, i, INTDMN_NS);
+	}
+
+	for (uint32_t i = 0U; i < config->num_spis; i++) {
+		assert((config->spis[i].id >= spi_base) &&
+		       (config->spis[i].id < spi_base + spi_range));
+
+		irs_configure_wire(base_addr, config->spis[i].id, config->spis[i].domain);
+
+		/* don't (can't) configure TM of wires for other domains */
+		if (config->spis[i].domain == INTDMN_EL3) {
+			write_irs_spi_cfgr(base_addr, config->spis[i].tm);
+			WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+		}
+	}
+}
+
+void __init gicv5_driver_init(void)
+{
+	for (size_t i = 0U; i < plat_gicv5_driver_data.num_iwbs; i++) {
+		iwb_enable(&plat_gicv5_driver_data.iwbs[i]);
+	}
+
+	for (size_t i = 0U; i < plat_gicv5_driver_data.num_irss; i++) {
+		irs_enable(&plat_gicv5_driver_data.irss[i]);
+	}
+}
+
+/*
+ * There exists a theoretical configuration where FEAT_RME is enabled
+ * without using TrustZone (i.e., no Secure world present). Currently,
+ * there is no reliable mechanism to detect this scenario at runtime.
+ *
+ * TODO: Add support for this configuration in the future if required.
+ */
+bool gicv5_has_interrupt_type(unsigned int type)
+{
+	switch (type) {
+	case INTR_TYPE_EL3:
+	case INTR_TYPE_S_EL1:
+	case INTR_TYPE_NS:
+		return true;
+	case INTR_TYPE_RL:
+		return is_feat_rme_supported();
+	default:
+		return false;
+	}
+}
+
+uint8_t gicv5_get_pending_interrupt_type(void)
+{
+	/* there is no pending interrupt expected */
+	return INTR_TYPE_INVAL;
+}
+
+/* TODO: these will probably end up contexted. Make Linux work for now */
+void gicv5_enable_ppis(void)
+{
+	uint64_t domainr = 0U;
+
+	/* the only ones described in the device tree at the moment */
+	write_icc_ppi_domainr(domainr, PPI_PMUIRQ,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_GICMNT,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTHP,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTV,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTPS,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTP,	INTDMN_NS);
+
+	write_icc_ppi_domainr0_el3(domainr);
+}

diff --git a/drivers/auth/auth.mk b/drivers/auth/auth.mk
new file mode 100644
index 0000000..a23c59b
--- /dev/null
+++ b/drivers/auth/auth.mk

@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+AUTH_SRC_DIR		:= drivers/auth/
+
+AUTH_SOURCES		:= ${AUTH_SRC_DIR}auth_mod.c		\
+			   ${AUTH_SRC_DIR}auth_util.c		\
+			   ${AUTH_SRC_DIR}crypto_mod.c		\
+			   ${AUTH_SRC_DIR}img_parser_mod.c

diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 8c5ff9d..05a8f45 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,7 @@
 #include <common/tbbr/cot_def.h>
 #include <drivers/auth/auth_common.h>
 #include <drivers/auth/auth_mod.h>
+#include <drivers/auth/auth_util.h>
 #include <drivers/auth/crypto_mod.h>
 #include <drivers/auth/img_parser_mod.h>
 #include <drivers/fwu/fwu.h>
@@ -188,6 +189,18 @@
 		return rc;
 	}
 
+	/*
+	 * Set Zero-OID for ROTPK(subject key) as a the certificate
+	 * does not hold Key-OID information for ROTPK.
+	 */
+	if (param->pk->cookie != NULL) {
+		pk_oid = param->pk->cookie;
+	} else {
+		pk_oid = ZERO_OID;
+	}
+
+	set_current_pk_oid(pk_oid);
+
 	/* Get the public key from the parent. If there is no parent (NULL),
 	 * the certificate has been signed with the ROTPK, so we have to get
 	 * the PK from the platform */
@@ -268,16 +281,6 @@
 		}
 
 		/*
-		 * Set Zero-OID for ROTPK(subject key) as a the certificate
-		 * does not hold Key-OID information for ROTPK.
-		 */
-		if (param->pk->cookie != NULL) {
-			pk_oid = param->pk->cookie;
-		} else {
-			pk_oid = ZERO_OID;
-		}
-
-		/*
 		 * Public key is verified at this stage, notify platform
 		 * to measure and publish it.
 		 */

diff --git a/drivers/auth/auth_util.c b/drivers/auth/auth_util.c
new file mode 100644
index 0000000..c12d2c3
--- /dev/null
+++ b/drivers/auth/auth_util.c

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <drivers/auth/auth_util.h>
+
+static const char *current_pk_oid;
+
+const char *get_current_pk_oid(void)
+{
+	return current_pk_oid;
+}
+
+void set_current_pk_oid(const char *pk_oid)
+{
+	current_pk_oid = pk_oid;
+}

diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c
index e36b285..882ca8e 100644
--- a/drivers/auth/crypto_mod.c
+++ b/drivers/auth/crypto_mod.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -187,3 +187,12 @@
 					    key_len, key_flags, iv, iv_len, tag,
 					    tag_len);
 }
+
+/* Perform end of psa crypto usage calls to finish */
+void crypto_mod_finish(void)
+{
+	if (crypto_lib_desc.finish != NULL) {
+		crypto_lib_desc.finish();
+		INFO("Finished using crypto library '%s'\n", crypto_lib_desc.name);
+	}
+}

diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 8fe426b..98a9510 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -417,19 +417,19 @@
 #if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
 #if TF_MBEDTLS_USE_AES_GCM
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
-		    auth_decrypt, NULL);
+		    auth_decrypt, NULL, NULL);
 #else
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
-		    NULL, NULL);
+		    NULL, NULL, NULL);
 #endif
 #elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY
 #if TF_MBEDTLS_USE_AES_GCM
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
-		    auth_decrypt, NULL);
+		    auth_decrypt, NULL, NULL);
 #else
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
-		    NULL, NULL);
+		    NULL, NULL, NULL);
 #endif
 #elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY
-REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL);
+REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL, NULL);
 #endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */

diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 0e4b57e..34987e4 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,8 +21,10 @@
 #include <psa/crypto_values.h>
 
 #include <common/debug.h>
+#include <drivers/auth/auth_util.h>
 #include <drivers/auth/crypto_mod.h>
 #include <drivers/auth/mbedtls/mbedtls_common.h>
+#include <drivers/auth/mbedtls/mbedtls_psa_crypto.h>
 #include <plat/common/platform.h>
 
 #define LIB_NAME		"mbed TLS PSA"
@@ -36,6 +38,9 @@
 #define SIZE_OF_ASN1_LEN	1U
 #define SIZE_OF_ASN1_TAG	1U
 
+/* Global cache for keys */
+key_cache_t key_cache[MAX_CACHED_KEYS] = {0};
+
 #if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
 CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
 /*
@@ -103,6 +108,49 @@
 
 #if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
 CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+/* Destroy all psa key ids created in a loop */
+static void destroy_key_ids(void)
+{
+	for (int i = 0; i < MAX_CACHED_KEYS; i++) {
+		if (key_cache[i].valid) {
+			psa_destroy_key(key_cache[i].key_id);
+		}
+	}
+}
+
+/* Retrieve cached key ID, algorithm, and key attributes */
+static bool get_cached_psa_key_info(const char *pk_oid, psa_key_id_t *key_id,
+		psa_algorithm_t *psa_alg, psa_key_attributes_t *psa_key_attr)
+{
+	for (int i = 0; i < MAX_CACHED_KEYS; i++) {
+		if (key_cache[i].valid &&
+				(strlen(key_cache[i].pk_oid) == strlen(pk_oid)) &&
+				(strncmp(key_cache[i].pk_oid, pk_oid, strlen(pk_oid)) == 0)) {
+			*key_id = key_cache[i].key_id;
+			*psa_alg = key_cache[i].psa_alg;
+			*psa_key_attr = key_cache[i].psa_key_attr;
+			return true;
+		}
+	}
+	return false;
+}
+
+/* Store key ID, algorithm, and key attributes in the cache */
+static int cache_psa_key_info(const char *pk_oid, psa_key_id_t key_id, psa_algorithm_t psa_alg,
+		psa_key_attributes_t psa_key_attr)
+{
+	for (int i = 0; i < MAX_CACHED_KEYS; i++) {
+		if (!key_cache[i].valid) {
+			key_cache[i].pk_oid = pk_oid;
+			key_cache[i].key_id = key_id;
+			key_cache[i].psa_alg = psa_alg;
+			key_cache[i].psa_key_attr = psa_key_attr;
+			key_cache[i].valid = true;
+			return CRYPTO_SUCCESS;
+		}
+	}
+	return CRYPTO_ERR_SIGNATURE;
+}
 
 /*
  * NOTE: This has been made internal in mbedtls 3.6.0 and the mbedtls team has
@@ -201,42 +249,53 @@
 	psa_key_id_t psa_key_id;
 	mbedtls_pk_type_t pk_alg;
 	psa_algorithm_t psa_alg;
+	const char *pk_oid = get_current_pk_oid();
 	__unused unsigned char reformatted_sig[ECDSA_SIG_BUFFER_SIZE] = {0};
 	unsigned char *local_sig_ptr;
 	size_t local_sig_len;
 
-	/* Load the key into the PSA key store. */
-	initialize_pk_context(&pk, &pk_initialized);
+	/* Check if key, algorithm, and key attributes are already cached */
+	if (!get_cached_psa_key_info(pk_oid, &psa_key_id, &psa_alg, &psa_key_attr)) {
+		/* Load the key into the PSA key store. */
+		initialize_pk_context(&pk, &pk_initialized);
 
-	p = (unsigned char *) pk_ptr;
-	end = p + pk_len;
-	rc = mbedtls_pk_parse_subpubkey(&p, end, &pk);
-	if (rc != 0) {
-		rc = CRYPTO_ERR_SIGNATURE;
-		goto end2;
+		p = (unsigned char *) pk_ptr;
+		end = p + pk_len;
+		rc = mbedtls_pk_parse_subpubkey(&p, end, &pk);
+		if (rc != 0) {
+			rc = CRYPTO_ERR_SIGNATURE;
+			goto end2;
+		}
+
+		rc = mbedtls_pk_get_psa_attributes(&pk, PSA_KEY_USAGE_VERIFY_MESSAGE,
+				&psa_key_attr);
+		if (rc != 0) {
+			rc = CRYPTO_ERR_SIGNATURE;
+			goto end2;
+		}
+
+		rc = construct_psa_alg(sig_alg, sig_alg_len, &pk_alg, &psa_alg);
+		if (rc != CRYPTO_SUCCESS) {
+			goto end2;
+		}
+		psa_set_key_algorithm(&psa_key_attr, psa_alg);
+
+		rc = mbedtls_pk_import_into_psa(&pk, &psa_key_attr, &psa_key_id);
+		if (rc != 0) {
+			rc = CRYPTO_ERR_SIGNATURE;
+			goto end2;
+		}
+
+		/* Cache the key, algorithm, and key attributes for future use */
+		rc = cache_psa_key_info(pk_oid, psa_key_id, psa_alg, psa_key_attr);
+		if (rc != CRYPTO_SUCCESS) {
+			goto end2;
+		}
+
+		/* Optimize mbedtls heap usage by freeing the pk context now.  */
+		cleanup_pk_context(&pk, &pk_initialized);
 	}
 
-	rc = mbedtls_pk_get_psa_attributes(&pk, PSA_KEY_USAGE_VERIFY_MESSAGE, &psa_key_attr);
-	if (rc != 0) {
-		rc = CRYPTO_ERR_SIGNATURE;
-		goto end2;
-	}
-
-	rc = construct_psa_alg(sig_alg, sig_alg_len, &pk_alg, &psa_alg);
-	if (rc != CRYPTO_SUCCESS) {
-		goto end2;
-	}
-	psa_set_key_algorithm(&psa_key_attr, psa_alg);
-
-	rc = mbedtls_pk_import_into_psa(&pk, &psa_key_attr, &psa_key_id);
-	if (rc != 0) {
-		rc = CRYPTO_ERR_SIGNATURE;
-		goto end2;
-	}
-
-	/* Optimize mbedtls heap usage by freeing the pk context now.  */
-	cleanup_pk_context(&pk, &pk_initialized);
-
 	/* Extract the signature from sig_ptr. */
 	p = (unsigned char *) sig_ptr;
 	end = p + sig_len;
@@ -249,7 +308,7 @@
 
 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
 TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-	if (pk_alg == MBEDTLS_PK_ECDSA) {
+	if (PSA_ALG_IS_ECDSA(psa_alg)) {
 		/* Convert the DER ASN.1 signature to raw format. */
 		size_t key_bits = psa_get_key_bits(&psa_key_attr);
 
@@ -271,16 +330,11 @@
 	psa_status = psa_verify_message(psa_key_id, psa_alg,
 				    data_ptr, data_len,
 				    local_sig_ptr, local_sig_len);
-	if (psa_status == PSA_SUCCESS) {
-		/* The signature has been successfully verified. */
-		rc = CRYPTO_SUCCESS;
-	} else {
-		rc = CRYPTO_ERR_SIGNATURE;
-	}
+
+	rc = (psa_status == PSA_SUCCESS) ? CRYPTO_SUCCESS : CRYPTO_ERR_SIGNATURE;
 
 end1:
-	/* Destroy the key from the PSA subsystem. */
-	psa_destroy_key(psa_key_id);
+	return rc;
 end2:
 	/* Free the pk context, if it is initialized. */
 	cleanup_pk_context(&pk, &pk_initialized);
@@ -365,6 +419,18 @@
 	* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
 	*/
 
+/*
+ * Finish crypto usage by destroying the psa_key_ids
+ */
+static void finish(void)
+{
+#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
+CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+	/* Destroy the psa_key_ids */
+	destroy_key_ids();
+#endif
+}
+
 #if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
 CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
 /*
@@ -524,19 +590,19 @@
 #if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
 #if TF_MBEDTLS_USE_AES_GCM
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
-		    auth_decrypt, NULL);
+		    auth_decrypt, NULL, finish);
 #else
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
-		    NULL, NULL);
+		    NULL, NULL, finish);
 #endif
 #elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY
 #if TF_MBEDTLS_USE_AES_GCM
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
-		    auth_decrypt, NULL);
+		    auth_decrypt, NULL, finish);
 #else
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
-		    NULL, NULL);
+		    NULL, NULL, finish);
 #endif
 #elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY
-REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL);
+REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL, finish);
 #endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */

diff --git a/drivers/auth/tbbr/tbbr_cot_bl1_r64.c b/drivers/auth/tbbr/tbbr_cot_bl1_r64.c
deleted file mode 100644
index 236823a..0000000
--- a/drivers/auth/tbbr/tbbr_cot_bl1_r64.c
+++ /dev/null

@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stddef.h>
-
-#include <mbedtls/version.h>
-
-#include <drivers/auth/auth_mod.h>
-#include <drivers/auth/tbbr_cot_common.h>
-
-#if USE_TBBR_DEFS
-#include <tools_share/tbbr_oid.h>
-#else
-#include <platform_oid.h>
-#endif
-
-#include <platform_def.h>
-
-static unsigned char trusted_world_pk_buf[PK_DER_LEN];
-static unsigned char non_trusted_world_pk_buf[PK_DER_LEN];
-static unsigned char content_pk_buf[PK_DER_LEN];
-static unsigned char nt_fw_config_hash_buf[HASH_DER_LEN];
-
-static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
-		AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID);
-static auth_param_type_desc_t trusted_world_pk = AUTH_PARAM_TYPE_DESC(
-		AUTH_PARAM_PUB_KEY, TRUSTED_WORLD_PK_OID);
-static auth_param_type_desc_t non_trusted_world_pk = AUTH_PARAM_TYPE_DESC(
-		AUTH_PARAM_PUB_KEY, NON_TRUSTED_WORLD_PK_OID);
-static auth_param_type_desc_t nt_fw_content_pk = AUTH_PARAM_TYPE_DESC(
-		AUTH_PARAM_PUB_KEY, NON_TRUSTED_FW_CONTENT_CERT_PK_OID);
-static auth_param_type_desc_t nt_world_bl_hash = AUTH_PARAM_TYPE_DESC(
-		AUTH_PARAM_HASH, NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID);
-static auth_param_type_desc_t nt_fw_config_hash = AUTH_PARAM_TYPE_DESC(
-		AUTH_PARAM_HASH, NON_TRUSTED_FW_CONFIG_HASH_OID);
-/*
- * Trusted key certificate
- */
-static const auth_img_desc_t trusted_key_cert = {
-	.img_id = TRUSTED_KEY_CERT_ID,
-	.img_type = IMG_CERT,
-	.parent = NULL,
-	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
-		[0] = {
-			.type = AUTH_METHOD_SIG,
-			.param.sig = {
-				.pk = &subject_pk,
-				.sig = &sig,
-				.alg = &sig_alg,
-				.data = &raw_data
-			}
-		},
-		[1] = {
-			.type = AUTH_METHOD_NV_CTR,
-			.param.nv_ctr = {
-				.cert_nv_ctr = &trusted_nv_ctr,
-				.plat_nv_ctr = &trusted_nv_ctr
-			}
-		}
-	},
-	.authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
-		[0] = {
-			.type_desc = &trusted_world_pk,
-			.data = {
-				.ptr = (void *)trusted_world_pk_buf,
-				.len = (unsigned int)PK_DER_LEN
-			}
-		},
-		[1] = {
-			.type_desc = &non_trusted_world_pk,
-			.data = {
-				.ptr = (void *)non_trusted_world_pk_buf,
-				.len = (unsigned int)PK_DER_LEN
-			}
-		}
-	}
-};
-/*
- * Non-Trusted Firmware
- */
-static const auth_img_desc_t non_trusted_fw_key_cert = {
-	.img_id = NON_TRUSTED_FW_KEY_CERT_ID,
-	.img_type = IMG_CERT,
-	.parent = &trusted_key_cert,
-	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
-		[0] = {
-			.type = AUTH_METHOD_SIG,
-			.param.sig = {
-				.pk = &non_trusted_world_pk,
-				.sig = &sig,
-				.alg = &sig_alg,
-				.data = &raw_data
-			}
-		},
-		[1] = {
-			.type = AUTH_METHOD_NV_CTR,
-			.param.nv_ctr = {
-				.cert_nv_ctr = &non_trusted_nv_ctr,
-				.plat_nv_ctr = &non_trusted_nv_ctr
-			}
-		}
-	},
-	.authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
-		[0] = {
-			.type_desc = &nt_fw_content_pk,
-			.data = {
-				.ptr = (void *)content_pk_buf,
-				.len = (unsigned int)PK_DER_LEN
-			}
-		}
-	}
-};
-static const auth_img_desc_t non_trusted_fw_content_cert = {
-	.img_id = NON_TRUSTED_FW_CONTENT_CERT_ID,
-	.img_type = IMG_CERT,
-	.parent = &non_trusted_fw_key_cert,
-	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
-		[0] = {
-			.type = AUTH_METHOD_SIG,
-			.param.sig = {
-				.pk = &nt_fw_content_pk,
-				.sig = &sig,
-				.alg = &sig_alg,
-				.data = &raw_data
-			}
-		},
-		[1] = {
-			.type = AUTH_METHOD_NV_CTR,
-			.param.nv_ctr = {
-				.cert_nv_ctr = &non_trusted_nv_ctr,
-				.plat_nv_ctr = &non_trusted_nv_ctr
-			}
-		}
-	},
-	.authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
-		[0] = {
-			.type_desc = &nt_world_bl_hash,
-			.data = {
-				.ptr = (void *)nt_world_bl_hash_buf,
-				.len = (unsigned int)HASH_DER_LEN
-			}
-		},
-		[1] = {
-			.type_desc = &nt_fw_config_hash,
-			.data = {
-				.ptr = (void *)nt_fw_config_hash_buf,
-				.len = (unsigned int)HASH_DER_LEN
-			}
-		}
-	}
-};
-static const auth_img_desc_t bl33_image = {
-	.img_id = BL33_IMAGE_ID,
-	.img_type = IMG_RAW,
-	.parent = &non_trusted_fw_content_cert,
-	.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
-		[0] = {
-			.type = AUTH_METHOD_HASH,
-			.param.hash = {
-				.data = &raw_data,
-				.hash = &nt_world_bl_hash
-			}
-		}
-	}
-};
-
-static const auth_img_desc_t * const cot_desc[] = {
-	[TRUSTED_KEY_CERT_ID]			=	&trusted_key_cert,
-	[NON_TRUSTED_FW_KEY_CERT_ID]		=	&non_trusted_fw_key_cert,
-	[NON_TRUSTED_FW_CONTENT_CERT_ID]	=	&non_trusted_fw_content_cert,
-	[BL33_IMAGE_ID]				=	&bl33_image,
-};
-
-/* Register the CoT in the authentication module */
-REGISTER_COT(cot_desc);

diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index 5ecbaed..59a4a86 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c

@@ -79,8 +79,8 @@
 {
 	int ret;
 
-	if ((c == '\n') &&
-	    ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) {
+	if ((c == (int)'\n') &&
+	    ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0U)) {
 		ret = console->putc('\r', console);
 		if (ret < 0)
 			return ret;

diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 49dfc07..30caeba 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,9 +15,22 @@
 #include <drivers/delay_timer.h>
 #include <drivers/mmc.h>
 #include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 
 #include <imx_usdhc.h>
 
+/* These masks represent the commands which involve a data transfer. */
+#define ADTC_MASK_SD			(BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\
+					 BIT_32(24U) | BIT_32(25U))
+#define ADTC_MASK_ACMD			(BIT_64(51U))
+
+struct imx_usdhc_device_data {
+	uint32_t addr;
+	uint32_t blk_size;
+	uint32_t blks;
+	bool valid;
+};
+
 static void imx_usdhc_initialize(void);
 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
@@ -34,27 +48,85 @@
 };
 
 static imx_usdhc_params_t imx_usdhc_params;
+static struct imx_usdhc_device_data imx_usdhc_data;
+
+static bool imx_usdhc_is_buf_valid(void)
+{
+	return imx_usdhc_data.valid;
+}
+
+static bool imx_usdhc_is_buf_multiblk(void)
+{
+	return imx_usdhc_data.blks > 1U;
+}
+
+static void imx_usdhc_inval_buf_data(void)
+{
+	imx_usdhc_data.valid = false;
+}
+
+static int imx_usdhc_save_buf_data(uintptr_t buf, size_t size)
+{
+	uint32_t block_size;
+	uint64_t blks;
+
+	if (size <= MMC_BLOCK_SIZE) {
+		block_size = (uint32_t)size;
+	} else {
+		block_size = MMC_BLOCK_SIZE;
+	}
+
+	if (buf > UINT32_MAX) {
+		return -EOVERFLOW;
+	}
+
+	imx_usdhc_data.addr = (uint32_t)buf;
+	imx_usdhc_data.blk_size = block_size;
+	blks = size / block_size;
+	imx_usdhc_data.blks = (uint32_t)blks;
+
+	imx_usdhc_data.valid = true;
+
+	return 0;
+}
+
+static void imx_usdhc_write_buf_data(void)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	uint32_t addr, blks, blk_size;
+
+	addr = imx_usdhc_data.addr;
+	blks = imx_usdhc_data.blks;
+	blk_size = imx_usdhc_data.blk_size;
+
+	mmio_write_32(reg_base + DSADDR, addr);
+	mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) |
+		      BLKATT_BLKSIZE(blk_size));
+}
 
 #define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
-static void imx_usdhc_set_clk(int clk)
+static void imx_usdhc_set_clk(unsigned int clk)
 {
-	int div = 1;
-	int pre_div = 1;
 	unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
 	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	unsigned int pre_div = 1U, div = 1U;
 
 	assert(clk > 0);
 
 	while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
 		pre_div *= 2;
 
-	while (sdhc_clk / div > clk && div < 16)
+	while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) {
 		div++;
+	}
 
 	pre_div >>= 1;
 	div -= 1;
 	clk = (pre_div << 8) | (div << 4);
 
+	while ((mmio_read_32(reg_base + PSTATE) & PSTATE_SDSTB) == 0U) {
+	}
+
 	mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
 	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
 	udelay(10000);
@@ -107,15 +179,87 @@
 
 #define FSL_CMD_RETRIES	1000
 
+static bool is_data_transfer_to_card(const struct mmc_cmd *cmd)
+{
+	unsigned int cmd_idx = cmd->cmd_idx;
+
+	return (cmd_idx == MMC_CMD(24)) || (cmd_idx == MMC_CMD(25));
+}
+
+static bool is_data_transfer_cmd(const struct mmc_cmd *cmd)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	unsigned int cmd_idx = cmd->cmd_idx;
+	uint32_t xfer_type;
+
+	xfer_type = mmio_read_32(reg_base + XFERTYPE);
+
+	if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) {
+		return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL;
+	}
+
+	if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) {
+		return true;
+	}
+
+	return false;
+}
+
+static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype)
+{
+	*xfertype = XFERTYPE_CMD(cmd->cmd_idx);
+
+	switch (cmd->resp_type) {
+	case MMC_RESPONSE_R2:
+		*xfertype |= XFERTYPE_RSPTYP_136;
+		*xfertype |= XFERTYPE_CCCEN;
+		break;
+	case MMC_RESPONSE_R4:
+		*xfertype |= XFERTYPE_RSPTYP_48;
+		break;
+	case MMC_RESPONSE_R6:
+		*xfertype |= XFERTYPE_RSPTYP_48;
+		*xfertype |= XFERTYPE_CICEN;
+		*xfertype |= XFERTYPE_CCCEN;
+		break;
+	case MMC_RESPONSE_R1B:
+		*xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+		*xfertype |= XFERTYPE_CICEN;
+		*xfertype |= XFERTYPE_CCCEN;
+		break;
+	case MMC_RESPONSE_NONE:
+		break;
+	default:
+		ERROR("Invalid CMD response: %u\n", cmd->resp_type);
+		return -EINVAL;
+	}
+
+	if (data) {
+		*xfertype |= XFERTYPE_DPSEL;
+	}
+
+	return 0;
+}
+
 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
 {
 	uintptr_t reg_base = imx_usdhc_params.reg_base;
-	unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
 	unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
+	unsigned int mixctl = 0;
 	unsigned int cmd_retries = 0;
+	uint32_t xfertype;
+	bool data;
+	int err = 0;
 
 	assert(cmd);
 
+	data = is_data_transfer_cmd(cmd);
+
+	err = get_xfr_type(cmd, data, &xfertype);
+	if (err != 0) {
+		return err;
+	}
+
 	/* clear all irq status */
 	mmio_write_32(reg_base + INTSTAT, 0xffffffff);
 
@@ -128,56 +272,23 @@
 		;
 
 	mmio_write_32(reg_base + INTSIGEN, 0);
-	udelay(1000);
-
-	switch (cmd->cmd_idx) {
-	case MMC_CMD(12):
-		xfertype |= XFERTYPE_CMDTYP_ABORT;
-		break;
-	case MMC_CMD(18):
-		multiple = 1;
-		/* for read op */
-		/* fallthrough */
-	case MMC_CMD(17):
-	case MMC_CMD(8):
-		mixctl |= MIXCTRL_DTDSEL;
-		data = 1;
-		break;
-	case MMC_CMD(25):
-		multiple = 1;
-		/* for data op flag */
-		/* fallthrough */
-	case MMC_CMD(24):
-		data = 1;
-		break;
-	default:
-		break;
-	}
-
-	if (multiple) {
-		mixctl |= MIXCTRL_MSBSEL;
-		mixctl |= MIXCTRL_BCEN;
-	}
 
 	if (data) {
-		xfertype |= XFERTYPE_DPSEL;
 		mixctl |= MIXCTRL_DMAEN;
 	}
 
-	if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
-		xfertype |= XFERTYPE_RSPTYP_48;
-	else if (cmd->resp_type & MMC_RSP_136)
-		xfertype |= XFERTYPE_RSPTYP_136;
-	else if (cmd->resp_type & MMC_RSP_BUSY)
-		xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+	if (!is_data_transfer_to_card(cmd)) {
+		mixctl |= MIXCTRL_DTDSEL;
+	}
 
-	if (cmd->resp_type & MMC_RSP_CMD_IDX)
-		xfertype |= XFERTYPE_CICEN;
+	if ((cmd->cmd_idx != MMC_CMD(55)) && imx_usdhc_is_buf_valid()) {
+		if (imx_usdhc_is_buf_multiblk()) {
+			mixctl |= MIXCTRL_MSBSEL | MIXCTRL_BCEN;
+		}
 
-	if (cmd->resp_type & MMC_RSP_CRC)
-		xfertype |= XFERTYPE_CCCEN;
-
-	xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+		imx_usdhc_write_buf_data();
+		imx_usdhc_inval_buf_data();
+	}
 
 	/* Send the command */
 	mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
@@ -269,17 +380,13 @@
 
 static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
 {
-	uintptr_t reg_base = imx_usdhc_params.reg_base;
-
-	mmio_write_32(reg_base + DSADDR, buf);
-	mmio_write_32(reg_base + BLKATT,
-		      (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
-
-	return 0;
+	flush_dcache_range(buf, size);
+	return imx_usdhc_save_buf_data(buf, size);
 }
 
 static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
 {
+	inv_dcache_range(buf, size);
 	return 0;
 }
 
@@ -291,13 +398,24 @@
 void imx_usdhc_init(imx_usdhc_params_t *params,
 		    struct mmc_device_info *mmc_dev_info)
 {
+	int ret __maybe_unused;
+
 	assert((params != 0) &&
 	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
-	       (params->clk_rate > 0) &&
 	       ((params->bus_width == MMC_BUS_WIDTH_1) ||
 		(params->bus_width == MMC_BUS_WIDTH_4) ||
 		(params->bus_width == MMC_BUS_WIDTH_8)));
 
+#if PLAT_XLAT_TABLES_DYNAMIC
+	ret = mmap_add_dynamic_region(params->reg_base, params->reg_base,
+				      PAGE_SIZE,
+				      MT_DEVICE | MT_RW | MT_SECURE);
+	if (ret != 0) {
+		ERROR("Failed to map the uSDHC registers\n");
+		panic();
+	}
+#endif
+
 	memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
 	mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
 		 params->flags, mmc_dev_info);

diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
index e063316..bb0ef01 100644
--- a/drivers/imx/usdhc/imx_usdhc.h
+++ b/drivers/imx/usdhc/imx_usdhc.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,8 +12,8 @@
 
 typedef struct imx_usdhc_params {
 	uintptr_t	reg_base;
-	int		clk_rate;
-	int		bus_width;
+	unsigned int	clk_rate;
+	unsigned int	bus_width;
 	unsigned int	flags;
 } imx_usdhc_params_t;
 
@@ -20,115 +21,119 @@
 		    struct mmc_device_info *mmc_dev_info);
 
 /* iMX MMC registers definition */
-#define DSADDR			0x000
-#define BLKATT			0x004
-#define CMDARG			0x008
-#define CMDRSP0			0x010
-#define CMDRSP1			0x014
-#define CMDRSP2			0x018
-#define CMDRSP3			0x01c
+#define DSADDR			0x000U
+#define BLKATT			0x004U
+#define BLKATT_BLKCNT(x)	(((x) << 16U) & GENMASK_32(31U, 16U))
+#define BLKATT_BLKSIZE(x)	((x) & GENMASK_32(12U, 0U))
+#define CMDARG			0x008U
+#define CMDRSP0			0x010U
+#define CMDRSP1			0x014U
+#define CMDRSP2			0x018U
+#define CMDRSP3			0x01cU
 
-#define XFERTYPE		0x00c
-#define XFERTYPE_CMD(x)		(((x) & 0x3f) << 24)
-#define XFERTYPE_CMDTYP_ABORT	(3 << 22)
-#define XFERTYPE_DPSEL		BIT(21)
-#define XFERTYPE_CICEN		BIT(20)
-#define XFERTYPE_CCCEN		BIT(19)
-#define XFERTYPE_RSPTYP_136	BIT(16)
-#define XFERTYPE_RSPTYP_48	BIT(17)
-#define XFERTYPE_RSPTYP_48_BUSY	(BIT(16) | BIT(17))
+#define XFERTYPE		0x00cU
+#define XFERTYPE_CMD(x)		(((x) & 0x3fU) << 24U)
+#define XFERTYPE_GET_CMD(x)	(((x) & GENMASK_32(29U, 24U)) >> 24U)
+#define XFERTYPE_CMDTYP_ABORT	(3U << 22U)
+#define XFERTYPE_DPSEL		BIT_32(21U)
+#define XFERTYPE_CICEN		BIT_32(20U)
+#define XFERTYPE_CCCEN		BIT_32(19U)
+#define XFERTYPE_RSPTYP_136	BIT_32(16U)
+#define XFERTYPE_RSPTYP_48	BIT_32(17U)
+#define XFERTYPE_RSPTYP_48_BUSY	(BIT_32(16U) | BIT_32(17U))
 
-#define PSTATE			0x024
-#define PSTATE_DAT0		BIT(24)
-#define PSTATE_DLA		BIT(2)
-#define PSTATE_CDIHB		BIT(1)
-#define PSTATE_CIHB		BIT(0)
+#define PSTATE			0x024U
+#define PSTATE_DAT0		BIT_32(24U)
+#define PSTATE_SDSTB		BIT_32(3U)
+#define PSTATE_DLA		BIT_32(2U)
+#define PSTATE_CDIHB		BIT_32(1U)
+#define PSTATE_CIHB		BIT_32(0U)
 
-#define PROTCTRL		0x028
-#define PROTCTRL_LE		BIT(5)
-#define PROTCTRL_WIDTH_4	BIT(1)
-#define PROTCTRL_WIDTH_8	BIT(2)
-#define PROTCTRL_WIDTH_MASK	0x6
+#define PROTCTRL		0x028U
+#define PROTCTRL_LE		BIT_32(5U)
+#define PROTCTRL_WIDTH_4	BIT_32(1U)
+#define PROTCTRL_WIDTH_8	BIT_32(2U)
+#define PROTCTRL_WIDTH_MASK	0x6U
 
-#define SYSCTRL			0x02c
-#define SYSCTRL_RSTD		BIT(26)
-#define SYSCTRL_RSTC		BIT(25)
-#define SYSCTRL_RSTA		BIT(24)
-#define SYSCTRL_CLOCK_MASK	0x0000fff0
-#define SYSCTRL_TIMEOUT_MASK	0x000f0000
-#define SYSCTRL_TIMEOUT(x)	((0xf & (x)) << 16)
+#define SYSCTRL			0x02cU
+#define SYSCTRL_RSTD		BIT_32(26U)
+#define SYSCTRL_RSTC		BIT_32(25U)
+#define SYSCTRL_RSTA		BIT_32(24U)
+#define SYSCTRL_CLOCK_MASK	GENMASK_32(15U, 4U)
+#define SYSCTRL_TIMEOUT_MASK	GENMASK_32(19U, 16U)
+#define SYSCTRL_TIMEOUT(x)	((0xfU & (x)) << 16U)
 
-#define INTSTAT			0x030
-#define INTSTAT_DMAE		BIT(28)
-#define INTSTAT_DEBE		BIT(22)
-#define INTSTAT_DCE		BIT(21)
-#define INTSTAT_DTOE		BIT(20)
-#define INTSTAT_CIE		BIT(19)
-#define INTSTAT_CEBE		BIT(18)
-#define INTSTAT_CCE		BIT(17)
-#define INTSTAT_DINT		BIT(3)
-#define INTSTAT_BGE		BIT(2)
-#define INTSTAT_TC		BIT(1)
-#define INTSTAT_CC		BIT(0)
+#define INTSTAT			0x030U
+#define INTSTAT_DMAE		BIT_32(28U)
+#define INTSTAT_DEBE		BIT_32(22U)
+#define INTSTAT_DCE		BIT_32(21U)
+#define INTSTAT_DTOE		BIT_32(20U)
+#define INTSTAT_CIE		BIT_32(19U)
+#define INTSTAT_CEBE		BIT_32(18U)
+#define INTSTAT_CCE		BIT_32(17U)
+#define INTSTAT_DINT		BIT_32(3U)
+#define INTSTAT_BGE		BIT_32(2U)
+#define INTSTAT_TC		BIT_32(1U)
+#define INTSTAT_CC		BIT_32(0U)
 #define CMD_ERR			(INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
 #define DATA_ERR		(INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
 				 INTSTAT_DTOE)
 #define DATA_COMPLETE		(INTSTAT_DINT | INTSTAT_TC)
 
-#define INTSTATEN		0x034
-#define INTSTATEN_DEBE		BIT(22)
-#define INTSTATEN_DCE		BIT(21)
-#define INTSTATEN_DTOE		BIT(20)
-#define INTSTATEN_CIE		BIT(19)
-#define INTSTATEN_CEBE		BIT(18)
-#define INTSTATEN_CCE		BIT(17)
-#define INTSTATEN_CTOE		BIT(16)
-#define INTSTATEN_CINT		BIT(8)
-#define INTSTATEN_BRR		BIT(5)
-#define INTSTATEN_BWR		BIT(4)
-#define INTSTATEN_DINT		BIT(3)
-#define INTSTATEN_TC		BIT(1)
-#define INTSTATEN_CC		BIT(0)
+#define INTSTATEN		0x034U
+#define INTSTATEN_DEBE		BIT_32(22U)
+#define INTSTATEN_DCE		BIT_32(21U)
+#define INTSTATEN_DTOE		BIT_32(20U)
+#define INTSTATEN_CIE		BIT_32(19U)
+#define INTSTATEN_CEBE		BIT_32(18U)
+#define INTSTATEN_CCE		BIT_32(17U)
+#define INTSTATEN_CTOE		BIT_32(16U)
+#define INTSTATEN_CINT		BIT_32(8U)
+#define INTSTATEN_BRR		BIT_32(5U)
+#define INTSTATEN_BWR		BIT_32(4U)
+#define INTSTATEN_DINT		BIT_32(3U)
+#define INTSTATEN_TC		BIT_32(1U)
+#define INTSTATEN_CC		BIT_32(0U)
 #define EMMC_INTSTATEN_BITS	(INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
 				 INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
 				 INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
 				 INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
 				 INTSTATEN_DEBE)
 
-#define INTSIGEN		0x038
+#define INTSIGEN		0x038U
 
-#define WATERMARKLEV		0x044
-#define WMKLV_RD_MASK		0xff
-#define WMKLV_WR_MASK		0x00ff0000
+#define WATERMARKLEV		0x044U
+#define WMKLV_RD_MASK		GENMASK_32(7U, 0U)
+#define WMKLV_WR_MASK		GENMASK_32(23U, 16U)
 #define WMKLV_MASK		(WMKLV_RD_MASK | WMKLV_WR_MASK)
 
-#define MIXCTRL			0x048
-#define MIXCTRL_MSBSEL		BIT(5)
-#define MIXCTRL_DTDSEL		BIT(4)
-#define MIXCTRL_DDREN		BIT(3)
-#define MIXCTRL_AC12EN		BIT(2)
-#define MIXCTRL_BCEN		BIT(1)
-#define MIXCTRL_DMAEN		BIT(0)
-#define MIXCTRL_DATMASK		0x7f
+#define MIXCTRL			0x048U
+#define MIXCTRL_MSBSEL		BIT_32(5U)
+#define MIXCTRL_DTDSEL		BIT_32(4U)
+#define MIXCTRL_DDREN		BIT_32(3U)
+#define MIXCTRL_AC12EN		BIT_32(2U)
+#define MIXCTRL_BCEN		BIT_32(1U)
+#define MIXCTRL_DMAEN		BIT_32(0U)
+#define MIXCTRL_DATMASK		0x7fU
 
-#define DLLCTRL			0x060
+#define DLLCTRL			0x060U
 
-#define CLKTUNECTRLSTS		0x068
+#define CLKTUNECTRLSTS		0x068U
 
-#define VENDSPEC		0x0c0
-#define VENDSPEC_RSRV1		BIT(29)
-#define VENDSPEC_CARD_CLKEN	BIT(14)
-#define VENDSPEC_PER_CLKEN	BIT(13)
-#define VENDSPEC_AHB_CLKEN	BIT(12)
-#define VENDSPEC_IPG_CLKEN	BIT(11)
-#define VENDSPEC_AC12_CHKBUSY	BIT(3)
-#define VENDSPEC_EXTDMA		BIT(0)
+#define VENDSPEC		0x0c0U
+#define VENDSPEC_RSRV1		BIT_32(29U)
+#define VENDSPEC_CARD_CLKEN	BIT_32(14U)
+#define VENDSPEC_PER_CLKEN	BIT_32(13U)
+#define VENDSPEC_AHB_CLKEN	BIT_32(12U)
+#define VENDSPEC_IPG_CLKEN	BIT_32(11U)
+#define VENDSPEC_AC12_CHKBUSY	BIT_32(3U)
+#define VENDSPEC_EXTDMA		BIT_32(0U)
 #define VENDSPEC_INIT		(VENDSPEC_RSRV1	| VENDSPEC_CARD_CLKEN | \
 				 VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
 				 VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
 				 VENDSPEC_EXTDMA)
 
-#define MMCBOOT			0x0c4
+#define MMCBOOT			0x0c4U
 
 #define mmio_clrsetbits32(addr, clear, set)	mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
 #define mmio_clrbits32(addr, clear)		mmio_write_32(addr, mmio_read_32(addr) & ~(clear))

diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index f12da0e..117ac73 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c

@@ -12,7 +12,6 @@
 #include <drivers/marvell/amb_adec.h>
 #include <drivers/marvell/iob.h>
 #include <drivers/marvell/mochi/cp110_setup.h>
-#include <drivers/rambus/trng_ip_76.h>
 
 #include <efuse_def.h>
 #include <plat_marvell.h>
@@ -107,13 +106,6 @@
 #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK		0xFFFF
 #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT		0x1F
 
-/*******************************************************************************
- * TRNG Configuration
- ******************************************************************************/
-#define MVEBU_TRNG_BASE					(0x760000)
-#define MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD		MVEBU_AP_LDX_220_189_EFUSE_OFFS
-#define MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET		13	/* LD0[202] */
-
 enum axi_attr {
 	AXI_ADUNIT_ATTR = 0,
 	AXI_COMUNIT_ATTR,
@@ -388,36 +380,6 @@
 	init_amb_adec(base);
 }
 
-static void cp110_trng_init(uintptr_t base)
-{
-	static bool done;
-	int ret;
-	uint32_t reg_val, efuse;
-
-	/* Set access to LD0 */
-	reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
-	reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
-	mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
-
-	/* Obtain the AP LD0 bit defining TRNG presence */
-	efuse = mmio_read_32(MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD);
-	efuse >>= MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET;
-	efuse &= 1;
-
-	if (efuse == 0) {
-		VERBOSE("TRNG is not present, skipping");
-		return;
-	}
-
-	if (!done) {
-		ret = eip76_rng_probe(base + MVEBU_TRNG_BASE);
-		if (ret != 0) {
-			ERROR("Failed to init TRNG @ 0x%lx\n", base);
-			return;
-		}
-		done = true;
-	}
-}
 void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
 {
 	INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
@@ -445,9 +407,6 @@
 
 	/* Reset RTC if needed */
 	cp110_rtc_init(cp110_base);
-
-	/* TRNG init - for CP0 only */
-	cp110_trng_init(cp110_base);
 }
 
 /* Do the minimal setup required to configure the CP in BLE */

diff --git a/drivers/marvell/trng.c b/drivers/marvell/trng.c
new file mode 100644
index 0000000..34a3e38
--- /dev/null
+++ b/drivers/marvell/trng.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2025, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mvebu_def.h>
+
+/* Bind to first CP110's EIP-76 engine only */
+#define CP110_TRNG_REGS_BASE		(MVEBU_CP_REGS_BASE(0) + 0x760000U)
+
+/* EIP-76 Register Definitions */
+#define CP110_TRNG_OUTPUT_REG(n)	(CP110_TRNG_REGS_BASE + ((n) * 0x4U))
+#define CP110_TRNG_STAT_N_ACK_REG	(CP110_TRNG_REGS_BASE + 0x10U)
+#define CP110_TRNG_CONTROL_REG		(CP110_TRNG_REGS_BASE + 0x14U)
+#define CP110_TRNG_CONFIG_REG		(CP110_TRNG_REGS_BASE + 0x18U)
+#define CP110_TRNG_FRO_ENABLE_REG	(CP110_TRNG_REGS_BASE + 0x20U)
+#define CP110_TRNG_FRO_DETUNE_REG	(CP110_TRNG_REGS_BASE + 0x24U)
+
+/* CP110_TRNG_STAT_N_ACK_REG */
+#define CP110_TRNG_READY		BIT(0)
+
+/* CP110_TRNG_CONTROL_REG */
+#define CP110_TRNG_EN			BIT(10)
+
+/* CP110_TRNG_CONFIG_REG */
+#define CP110_TRNG_NOISE_BLOCKS_SHIFT	0U
+#define CP110_TRNG_NOISE_BLOCKS_MASK	(0xFFU << CP110_TRNG_NOISE_BLOCKS_SHIFT)
+#define CP110_TRNG_SAMPLE_CYCLES_SHIFT	16U
+#define CP110_TRNG_SAMPLE_CYCLES_MASK	(0xFFU << CP110_TRNG_SAMPLE_CYCLES_SHIFT)
+
+/* CP110_TRNG_FRO_ENABLE_REG */
+#define CP110_TRNG_FRO_EN_SHIFT		0U
+#define CP110_TRNG_FRO_EN_MASK		(0xFFFFFFU << CP110_TRNG_FRO_EN_SHIFT)
+
+#define CP110_TRNG_MAX_OUTPUTS		4U
+
+/* maximum busy wait */
+#define CP110_TRNG_MAX_RETRIES		3U
+
+static void mv_trng_init(void)
+{
+	uint32_t val;
+
+	val = (0x5U << CP110_TRNG_NOISE_BLOCKS_SHIFT) & CP110_TRNG_NOISE_BLOCKS_MASK;
+	val |= (0x22U << CP110_TRNG_SAMPLE_CYCLES_SHIFT) & CP110_TRNG_SAMPLE_CYCLES_MASK;
+	mmio_write_32(CP110_TRNG_CONFIG_REG, val);
+
+	mmio_write_32(CP110_TRNG_FRO_DETUNE_REG, 0U);
+	mmio_write_32(CP110_TRNG_FRO_ENABLE_REG, CP110_TRNG_FRO_EN_MASK);
+
+	mmio_write_32(CP110_TRNG_CONTROL_REG, CP110_TRNG_EN);
+}
+
+int mv_trng_get_random32(uint32_t *rand, uint8_t num)
+{
+	uint32_t val;
+	uint8_t i;
+
+	if (num > CP110_TRNG_MAX_OUTPUTS) {
+		return -1;
+	}
+
+	val = mmio_read_32(CP110_TRNG_CONTROL_REG);
+	if ((val & CP110_TRNG_EN) != 0U) {
+		/* Flush the staled output data */
+		val = mmio_read_32(CP110_TRNG_STAT_N_ACK_REG);
+		if ((val & CP110_TRNG_READY) != 0U) {
+			mmio_write_32(CP110_TRNG_STAT_N_ACK_REG, CP110_TRNG_READY);
+		}
+	} else {
+		mv_trng_init();
+		/* Necessary delay for the warm-up */
+		udelay(200U);
+	}
+
+
+	for (i = 0U; i < CP110_TRNG_MAX_RETRIES; i++) {
+		val = mmio_read_32(CP110_TRNG_STAT_N_ACK_REG);
+		if ((val & CP110_TRNG_READY) != 0U) {
+			break;
+		}
+		udelay(1U);
+	}
+
+	if (i == CP110_TRNG_MAX_RETRIES) {
+		return -1;
+	}
+
+	for (i = 0U; i < num; i++) {
+		rand[i] = mmio_read_32(CP110_TRNG_OUTPUT_REG(i));
+	}
+
+	return 0;
+}

diff --git a/drivers/measured_boot/event_log/event_handoff.c b/drivers/measured_boot/event_log/event_handoff.c
new file mode 100644
index 0000000..238ea27
--- /dev/null
+++ b/drivers/measured_boot/event_log/event_handoff.c

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <common/debug.h>
+#include <drivers/measured_boot/event_log/event_handoff.h>
+
+#include <platform_def.h>
+
+static uint8_t *get_log_ptr(struct transfer_list_entry *te, size_t offset)
+{
+	uint8_t *base_ptr = transfer_list_entry_data(te);
+
+	if (base_ptr == NULL) {
+		return NULL;
+	}
+
+	return base_ptr + offset;
+}
+
+uint8_t *transfer_list_event_log_extend(struct transfer_list_header *tl,
+					size_t req_size, size_t *free)
+{
+	struct transfer_list_entry *existing_entry;
+	struct transfer_list_entry *new_entry;
+	uint8_t *old_data;
+	size_t existing_offset;
+	size_t old_size;
+
+	if (tl == NULL || free == NULL || req_size == 0) {
+		ERROR("Invalid arguments to event log extend.\n");
+		return NULL;
+	}
+
+	existing_entry = transfer_list_find(tl, TL_TAG_TPM_EVLOG);
+	existing_offset = EVENT_LOG_RESERVED_BYTES;
+
+	if (existing_entry != NULL) {
+		existing_offset = existing_entry->data_size;
+
+		if (transfer_list_set_data_size(tl, existing_entry,
+						req_size + existing_offset)) {
+			VERBOSE("TPM event log entry resized: new space %zu bytes at offset %zu\n",
+				req_size, existing_offset);
+
+			*free = existing_entry->data_size - existing_offset;
+
+			return get_log_ptr(existing_entry, existing_offset);
+		}
+	}
+
+	/* Add new entry (resize failed or no existing entry) */
+	new_entry = transfer_list_add(tl, TL_TAG_TPM_EVLOG,
+				      req_size + existing_offset, NULL);
+
+	if (new_entry == NULL) {
+		ERROR("Failed to add TPM event log entry to transfer list.\n");
+		return NULL;
+	}
+
+	VERBOSE("New TPM event log entry added at %p\n",
+		transfer_list_entry_data(new_entry));
+
+	if (existing_entry != NULL) {
+		old_data = transfer_list_entry_data(existing_entry);
+		old_size = existing_offset;
+
+		VERBOSE("Copying existing event log (%zu bytes) to new entry at %p\n",
+			old_size, transfer_list_entry_data(new_entry));
+
+		memmove(transfer_list_entry_data(new_entry), old_data,
+			old_size);
+
+		transfer_list_rem(tl, existing_entry);
+	}
+
+	*free = new_entry->data_size - existing_offset;
+
+	return get_log_ptr(new_entry, existing_offset);
+}
+
+uint8_t *transfer_list_event_log_finish(struct transfer_list_header *tl,
+					uintptr_t cursor)
+{
+	uintptr_t entry_data_base;
+	size_t final_log_size;
+	struct transfer_list_entry *entry;
+
+	entry = transfer_list_find(tl, TL_TAG_TPM_EVLOG);
+	entry_data_base = (uintptr_t)transfer_list_entry_data(entry);
+
+	if (cursor < entry_data_base ||
+	    cursor >= entry_data_base + entry->data_size) {
+		ERROR("Invalid cursor: outside event log bounds.\n");
+		return NULL;
+	}
+
+	final_log_size = cursor - entry_data_base;
+
+	if (!transfer_list_set_data_size(tl, entry, final_log_size)) {
+		ERROR("Unable to resize event log TE.\n");
+		return NULL;
+	}
+
+	transfer_list_update_checksum(tl);
+
+	VERBOSE("TPM event log finalized: trimmed to %zu bytes",
+		final_log_size - EVENT_LOG_RESERVED_BYTES);
+
+	/* Ensure changes are visible to the next stage. */
+	flush_dcache_range((uintptr_t)tl, tl->size);
+
+	return get_log_ptr(entry, EVENT_LOG_RESERVED_BYTES);
+}

diff --git a/drivers/measured_boot/event_log/event_log.c b/drivers/measured_boot/event_log/event_log.c
index 6f2898d..761ff29 100644
--- a/drivers/measured_boot/event_log/event_log.c
+++ b/drivers/measured_boot/event_log/event_log.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,12 +7,9 @@
 #include <assert.h>
 #include <errno.h>
 #include <string.h>
-#include <arch_helpers.h>
 
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/event_log/event_log.h>
+#include "crypto_mod.h"
+#include "event_log.h"
 
 #if TPM_ALG_ID == TPM_ALG_SHA512
 #define	CRYPTO_MD_ID	CRYPTO_MD_SHA512
@@ -75,34 +72,25 @@
 	}
 };
 
-/*
- * Record a measurement as a TCG_PCR_EVENT2 event
- *
- * @param[in] hash		Pointer to hash data of TCG_DIGEST_SIZE bytes
- * @param[in] event_type	Type of Event, Various Event Types are
- * 				mentioned in tcg.h header
- * @param[in] metadata_ptr	Pointer to event_log_metadata_t structure
- *
- * There must be room for storing this new event into the event log buffer.
- */
-void event_log_record(const uint8_t *hash, uint32_t event_type,
+int event_log_record(const uint8_t *hash, uint32_t event_type,
 		      const event_log_metadata_t *metadata_ptr)
 {
 	void *ptr = log_ptr;
 	uint32_t name_len = 0U;
 
-	assert(hash != NULL);
-	assert(metadata_ptr != NULL);
 	/* event_log_buf_init() must have been called prior to this. */
-	assert(log_ptr != NULL);
+	if (hash == NULL || metadata_ptr == NULL || log_ptr == NULL) {
+		return -EINVAL;
+	}
 
 	if (metadata_ptr->name != NULL) {
 		name_len = (uint32_t)strlen(metadata_ptr->name) + 1U;
 	}
 
 	/* Check for space in Event Log buffer */
-	assert(((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) <
-	       log_end);
+	if (((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) > log_end) {
+		return -ENOMEM;
+	}
 
 	/*
 	 * As per TCG specifications, firmware components that are measured
@@ -145,38 +133,42 @@
 	/* End of event data */
 	log_ptr = (uint8_t *)((uintptr_t)ptr +
 			offsetof(event2_data_t, event) + name_len);
+
+	return 0;
 }
 
-void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish)
+int event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish)
 {
-	assert(event_log_start != NULL);
-	assert(event_log_finish > event_log_start);
+	if (event_log_start == NULL || event_log_finish == NULL ||
+	    event_log_start > event_log_finish) {
+		return -EINVAL;
+	}
 
 	log_ptr = event_log_start;
 	log_end = (uintptr_t)event_log_finish;
+
+	return 0;
 }
 
-/*
- * Initialise Event Log global variables, used during the recording
- * of various payload measurements into the Event Log buffer
- *
- * @param[in] event_log_start		Base address of Event Log buffer
- * @param[in] event_log_finish		End address of Event Log buffer,
- * 					it is a first byte past end of the
- * 					buffer
- */
-void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish)
+int event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish)
 {
-	event_log_buf_init(event_log_start, event_log_finish);
+	return event_log_buf_init(event_log_start, event_log_finish);
 }
 
-void event_log_write_specid_event(void)
+int event_log_write_specid_event(void)
 {
-	void *ptr = log_ptr;
+	void *ptr;
 
 	/* event_log_buf_init() must have been called prior to this. */
-	assert(log_ptr != NULL);
-	assert(((uintptr_t)log_ptr + ID_EVENT_SIZE) < log_end);
+	if (log_ptr == NULL) {
+		return -EFAULT;
+	}
+
+	if (((uintptr_t)log_ptr + ID_EVENT_SIZE) > log_end) {
+		return -ENOMEM;
+	}
+
+	ptr = log_ptr;
 
 	/*
 	 * Add Specification ID Event first
@@ -199,21 +191,26 @@
 	((id_event_struct_data_t *)ptr)->vendor_info_size = 0;
 	log_ptr = (uint8_t *)((uintptr_t)ptr +
 			offsetof(id_event_struct_data_t, vendor_info));
+
+	return 0;
 }
 
-/*
- * Initialises Event Log by writing Specification ID and
- * Startup Locality events
- */
-void event_log_write_header(void)
+int event_log_write_header(void)
 {
 	const char locality_signature[] = TCG_STARTUP_LOCALITY_SIGNATURE;
 	void *ptr;
+	int rc;
 
-	event_log_write_specid_event();
+	rc = event_log_write_specid_event();
+	if (rc < 0) {
+		return rc;
+	}
+
+	if (((uintptr_t)log_ptr + LOC_EVENT_SIZE) > log_end) {
+		return -ENOMEM;
+	}
 
 	ptr = log_ptr;
-	assert(((uintptr_t)log_ptr + LOC_EVENT_SIZE) < log_end);
 
 	/*
 	 * The Startup Locality event should be placed in the log before
@@ -250,6 +247,8 @@
 	 */
 	((startup_locality_event_t *)ptr)->startup_locality = 0U;
 	log_ptr = (uint8_t *)((uintptr_t)ptr + sizeof(startup_locality_event_t));
+
+	return 0;
 }
 
 int event_log_measure(uintptr_t data_base, uint32_t data_size,
@@ -260,18 +259,6 @@
 				    (void *)data_base, data_size, hash_data);
 }
 
-/*
- * Calculate and write hash of image, configuration data, etc.
- * to Event Log.
- *
- * @param[in] data_base		Address of data
- * @param[in] data_size		Size of data
- * @param[in] data_id		Data ID
- * @param[in] metadata_ptr	Event Log metadata
- * @return:
- *	0 = success
- *    < 0 = error
- */
 int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
 				 uint32_t data_id,
 				 const event_log_metadata_t *metadata_ptr)
@@ -279,14 +266,18 @@
 	unsigned char hash_data[CRYPTO_MD_MAX_SIZE];
 	int rc;
 
-	assert(metadata_ptr != NULL);
+	if (metadata_ptr == NULL) {
+		return -EINVAL;
+	}
 
 	/* Get the metadata associated with this image. */
-	while ((metadata_ptr->id != EVLOG_INVALID_ID) &&
-		(metadata_ptr->id != data_id)) {
+	while (metadata_ptr->id != data_id) {
+		if (metadata_ptr->id == EVLOG_INVALID_ID) {
+			return -EINVAL;
+		}
+
 		metadata_ptr++;
 	}
-	assert(metadata_ptr->id != EVLOG_INVALID_ID);
 
 	/* Measure the payload with algorithm selected by EventLog driver */
 	rc = event_log_measure(data_base, data_size, hash_data);
@@ -294,18 +285,14 @@
 		return rc;
 	}
 
-	event_log_record(hash_data, EV_POST_CODE, metadata_ptr);
+	rc = event_log_record(hash_data, EV_POST_CODE, metadata_ptr);
+	if (rc != 0) {
+		return rc;
+	}
 
 	return 0;
 }
 
-/*
- * Get current Event Log buffer size i.e. used space of Event Log buffer
- *
- * @param[in]  event_log_start		Base Pointer to Event Log buffer
- *
- * @return: current Size of Event Log buffer
- */
 size_t event_log_get_cur_size(uint8_t *event_log_start)
 {
 	assert(event_log_start != NULL);

diff --git a/drivers/measured_boot/event_log/event_log.mk b/drivers/measured_boot/event_log/event_log.mk
index 9e0d6c4..09c15da 100644
--- a/drivers/measured_boot/event_log/event_log.mk
+++ b/drivers/measured_boot/event_log/event_log.mk

@@ -4,6 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+EVENT_LOG_SRC_DIR	:= drivers/measured_boot/event_log/
+
 # Default log level to dump the event log (LOG_LEVEL_INFO)
 EVENT_LOG_LEVEL         ?= 40
 
@@ -40,7 +42,13 @@
         EVENT_LOG_LEVEL \
 )))
 
-EVENT_LOG_SRC_DIR	:= drivers/measured_boot/event_log/
+INCLUDES		+= -Iinclude/drivers/measured_boot/event_log \
+				-Iinclude/drivers/auth
 
 EVENT_LOG_SOURCES	:= ${EVENT_LOG_SRC_DIR}event_log.c		\
 			   ${EVENT_LOG_SRC_DIR}event_print.c
+
+
+ifeq (${TRANSFER_LIST}, 1)
+EVENT_LOG_SOURCES	+= ${EVENT_LOG_SRC_DIR}/event_handoff.c
+endif

diff --git a/drivers/measured_boot/event_log/event_print.c b/drivers/measured_boot/event_log/event_print.c
index e2ba174..234a694 100644
--- a/drivers/measured_boot/event_log/event_print.c
+++ b/drivers/measured_boot/event_log/event_print.c

@@ -1,24 +1,31 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdio.h>
 #include <string.h>
 
 #include <common/debug.h>
-#include <drivers/measured_boot/event_log/event_log.h>
+#include "event_log.h"
 
-#if LOG_LEVEL >= EVENT_LOG_LEVEL
-
-/*
- * Print TCG_EfiSpecIDEventStruct
+/**
+ * Print a TCG_EfiSpecIDEventStruct entry from the event log.
  *
- * @param[in/out] log_addr	Pointer to Event Log
- * @param[in/out] log_size	Pointer to Event Log size
+ * This function extracts and prints a TCG_EfiSpecIDEventStruct
+ * entry from the event log for debugging or auditing purposes.
+ *
+ * @param[in,out] log_addr  Pointer to the current position in the Event Log.
+ *                          Updated to the next entry after processing.
+ * @param[in,out] log_size  Pointer to the remaining Event Log size.
+ *                          Updated to reflect the remaining bytes.
+ *
+ * @return 0 on success, or a negative error code on failure.
  */
-static void id_event_print(uint8_t **log_addr, size_t *log_size)
+static int event_log_print_id_event(uint8_t **log_addr, size_t *log_size)
 {
 	unsigned int i;
 	uint8_t info_size, *info_size_ptr;
@@ -27,12 +34,11 @@
 	id_event_algorithm_size_t *alg_ptr;
 	uint32_t event_size, number_of_algorithms;
 	size_t digest_len;
-#if ENABLE_ASSERTIONS
 	const uint8_t *end_ptr = (uint8_t *)((uintptr_t)*log_addr + *log_size);
-	bool valid = true;
-#endif
 
-	assert(*log_size >= sizeof(id_event_headers_t));
+	if (*log_size < sizeof(id_event_headers_t)) {
+		return -EINVAL;
+	}
 
 	/* The fields of the event log header are defined to be PCRIndex of 0,
 	 * EventType of EV_NO_ACTION, Digest of 20 bytes of 0, and
@@ -40,10 +46,14 @@
 	 */
 	LOG_EVENT("TCG_EfiSpecIDEvent:\n");
 	LOG_EVENT("  PCRIndex           : %u\n", event->header.pcr_index);
-	assert(event->header.pcr_index == (uint32_t)PCR_0);
+	if (event->header.pcr_index != (uint32_t)PCR_0) {
+		return -EINVAL;
+	}
 
 	LOG_EVENT("  EventType          : %u\n", event->header.event_type);
-	assert(event->header.event_type == EV_NO_ACTION);
+	if (event->header.event_type != EV_NO_ACTION) {
+		return -EINVAL;
+	}
 
 	LOG_EVENT("  Digest             :");
 	for (i = 0U; i < sizeof(event->header.digest); ++i) {
@@ -54,18 +64,12 @@
 			(void)printf("\n");
 			LOG_EVENT("\t\t      :");
 		}
-#if ENABLE_ASSERTIONS
-		if (val != 0U) {
-			valid = false;
-		}
-#endif
 	}
+
 	if ((i & U(0xF)) != 0U) {
 		(void)printf("\n");
 	}
 
-	assert(valid);
-
 	/* EventSize */
 	event_size = event->header.event_size;
 	LOG_EVENT("  EventSize          : %u\n", event_size);
@@ -90,7 +94,9 @@
 
 	/* Size of DigestSizes[] */
 	digest_len = number_of_algorithms * sizeof(id_event_algorithm_size_t);
-	assert(((uintptr_t)alg_ptr + digest_len) <= (uintptr_t)end_ptr);
+	if (digest_len > (uintptr_t)end_ptr - (uintptr_t)alg_ptr) {
+		return -EFAULT;
+	}
 
 	LOG_EVENT("  DigestSizes        :\n");
 	for (i = 0U; i < number_of_algorithms; ++i) {
@@ -110,7 +116,7 @@
 		default:
 			(void)printf("?\n");
 			ERROR("Algorithm 0x%x not found\n", algorithm_id);
-			assert(false);
+			return -ENOENT;
 		}
 
 		LOG_EVENT("       DigestSize    : %u\n",
@@ -119,17 +125,24 @@
 
 	/* Address of VendorInfoSize */
 	info_size_ptr = (uint8_t *)((uintptr_t)alg_ptr + digest_len);
-	assert((uintptr_t)info_size_ptr <= (uintptr_t)end_ptr);
+	if ((uintptr_t)info_size_ptr > (uintptr_t)end_ptr) {
+		return -EFAULT;
+	}
 
 	info_size = *info_size_ptr++;
 	LOG_EVENT("  VendorInfoSize     : %u\n", info_size);
 
 	/* Check VendorInfo end address */
-	assert(((uintptr_t)info_size_ptr + info_size) <= (uintptr_t)end_ptr);
+	if (((uintptr_t)info_size_ptr + info_size) > (uintptr_t)end_ptr) {
+		return -EFAULT;
+	}
 
 	/* Check EventSize */
-	assert(event_size == (sizeof(id_event_struct_t) +
-				digest_len + info_size));
+	if (event_size !=
+	    (sizeof(id_event_struct_t) + digest_len + info_size)) {
+		return -EFAULT;
+	}
+
 	if (info_size != 0U) {
 		LOG_EVENT("  VendorInfo         :");
 		for (i = 0U; i < info_size; ++i) {
@@ -140,24 +153,33 @@
 
 	*log_size -= (uintptr_t)info_size_ptr - (uintptr_t)*log_addr;
 	*log_addr = info_size_ptr;
+
+	return 0;
 }
 
-/*
- * Print TCG_PCR_EVENT2
+/**
+ * Print a TCG_PCR_EVENT2 entry from the event log.
  *
- * @param[in/out] log_addr	Pointer to Event Log
- * @param[in/out] log_size	Pointer to Event Log size
+ * This function extracts and prints a TCG_PCR_EVENT2 structure
+ * from the event log for debugging or auditing purposes.
+ *
+ * @param[in,out] log_addr  Pointer to the current position in the Event Log.
+ *                          Updated to the next entry after processing.
+ * @param[in,out] log_size  Pointer to the remaining Event Log size.
+ *                          Updated to reflect the remaining bytes.
+ *
+ * @return 0 on success, or a negative error code on failure.
  */
-static void event2_print(uint8_t **log_addr, size_t *log_size)
+static int event_log_print_pcr_event2(uint8_t **log_addr, size_t *log_size)
 {
 	uint32_t event_size, count;
 	size_t sha_size, digests_size = 0U;
 	void *ptr = *log_addr;
-#if ENABLE_ASSERTIONS
 	const uint8_t *end_ptr = (uint8_t *)((uintptr_t)*log_addr + *log_size);
-#endif
 
-	assert(*log_size >= sizeof(event2_header_t));
+	if (*log_size < sizeof(event2_header_t)) {
+		return -EINVAL;
+	}
 
 	LOG_EVENT("PCR_Event2:\n");
 	LOG_EVENT("  PCRIndex           : %u\n",
@@ -166,16 +188,25 @@
 			((event2_header_t *)ptr)->event_type);
 
 	count = ((event2_header_t *)ptr)->digests.count;
+	if (count < 1U) {
+		LOG_EVENT("Invalid Digests Count      : %u\n", count);
+		return -EINVAL;
+	}
+
 	LOG_EVENT("  Digests Count      : %u\n", count);
 
 	/* Address of TCG_PCR_EVENT2.Digests[] */
 	ptr = (uint8_t *)ptr + sizeof(event2_header_t);
-	assert(((uintptr_t)ptr <= (uintptr_t)end_ptr) && (count != 0U));
+	if ((uintptr_t)ptr > (uintptr_t)end_ptr) {
+		return -EFAULT;
+	}
 
 	for (unsigned int i = 0U; i < count; ++i) {
 		/* Check AlgorithmId address */
-		assert(((uintptr_t)ptr +
-			offsetof(tpmt_ha, digest)) <= (uintptr_t)end_ptr);
+		if (((uintptr_t)ptr + offsetof(tpmt_ha, digest)) >
+		    (uintptr_t)end_ptr) {
+			return -EFAULT;
+		}
 
 		LOG_EVENT("    #%u AlgorithmId   : SHA", i);
 		switch (((tpmt_ha *)ptr)->algorithm_id) {
@@ -193,14 +224,16 @@
 			break;
 		default:
 			(void)printf("?\n");
-			ERROR("Algorithm 0x%x not found\n",
+			printf("Algorithm 0x%x not found\n",
 				((tpmt_ha *)ptr)->algorithm_id);
-			panic();
+			return -ENOENT;
 		}
 
 		/* End of Digest[] */
 		ptr = (uint8_t *)((uintptr_t)ptr + offsetof(tpmt_ha, digest));
-		assert(((uintptr_t)ptr + sha_size) <= (uintptr_t)end_ptr);
+		if (((uintptr_t)ptr + sha_size) > (uintptr_t)end_ptr) {
+			return -EFAULT;
+		}
 
 		/* Total size of all digests */
 		digests_size += sha_size;
@@ -218,7 +251,10 @@
 	}
 
 	/* TCG_PCR_EVENT2.EventSize */
-	assert(((uintptr_t)ptr + offsetof(event2_data_t, event)) <= (uintptr_t)end_ptr);
+	if (((uintptr_t)ptr + offsetof(event2_data_t, event)) >
+	    (uintptr_t)end_ptr) {
+		return -EFAULT;
+	}
 
 	event_size = ((event2_data_t *)ptr)->event_size;
 	LOG_EVENT("  EventSize          : %u\n", event_size);
@@ -227,7 +263,9 @@
 	ptr = (uint8_t *)((uintptr_t)ptr + offsetof(event2_data_t, event));
 
 	/* End of TCG_PCR_EVENT2.Event[EventSize] */
-	assert(((uintptr_t)ptr + event_size) <= (uintptr_t)end_ptr);
+	if (((uintptr_t)ptr + event_size) > (uintptr_t)end_ptr) {
+		return -EFAULT;
+	}
 
 	if ((event_size == sizeof(startup_locality_event_t)) &&
 	     (strcmp((const char *)ptr, TCG_STARTUP_LOCALITY_SIGNATURE) == 0)) {
@@ -241,25 +279,30 @@
 
 	*log_size -= (uintptr_t)ptr + event_size - (uintptr_t)*log_addr;
 	*log_addr = (uint8_t *)ptr + event_size;
-}
-#endif	/* LOG_LEVEL >= EVENT_LOG_LEVEL */
 
-/*
- * Print Event Log
- *
- * @param[in]	log_addr	Pointer to Event Log
- * @param[in]	log_size	Event Log size
- */
-void dump_event_log(uint8_t *log_addr, size_t log_size)
+	return 0;
+}
+
+int event_log_dump(uint8_t *log_addr, size_t log_size)
 {
-#if LOG_LEVEL >= EVENT_LOG_LEVEL
-	assert(log_addr != NULL);
+	int rc;
+
+	if (log_addr == NULL) {
+		return -EINVAL;
+	}
 
 	/* Print TCG_EfiSpecIDEvent */
-	id_event_print(&log_addr, &log_size);
+	rc = event_log_print_id_event(&log_addr, &log_size);
+
+	if (rc < 0) {
+		return rc;
+	}
 
 	while (log_size != 0U) {
-		event2_print(&log_addr, &log_size);
+		rc = event_log_print_pcr_event2(&log_addr, &log_size);
+		if (rc < 0) {
+			return rc;
+		}
 	}
-#endif
+	return 0;
 }

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b51e744..93a958c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c

@@ -437,7 +437,7 @@
 	int ret;
 
 	/* CMD0: reset to IDLE */
-	ret = mmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
+	ret = mmc_send_cmd(MMC_CMD(0), 0, MMC_RESPONSE_NONE, NULL);
 	if (ret != 0) {
 		return ret;
 	}

diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 92182a0..ac9d99a 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c

@@ -19,7 +19,7 @@
 #define S32CC_DDR_PLL_VCO_FREQ		(1600U * MHZ)
 #define S32CC_DDR_PLL_PHI0_FREQ		(800U * MHZ)
 #define S32CC_PERIPH_DFS_PHI3_FREQ	(800U * MHZ)
-#define S32CC_USDHC_FREQ		(400U * MHZ)
+#define S32CC_USDHC_FREQ		(200U * MHZ)
 
 static int setup_fxosc(void)
 {

diff --git a/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c b/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
index 408d974..f607d8b 100644
--- a/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
+++ b/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c

@@ -120,4 +120,4 @@
 /*
  * Register crypto library descriptor
  */
-REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, NULL, NULL);
+REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, NULL, NULL, NULL);

diff --git a/drivers/nxp/crypto/caam/src/rng.c b/drivers/nxp/crypto/caam/src/rng.c
index 58430db..0331040 100644
--- a/drivers/nxp/crypto/caam/src/rng.c
+++ b/drivers/nxp/crypto/caam/src/rng.c

@@ -41,7 +41,7 @@
 	if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) {
 		*state_handle = 0;
 		ret_code = 1;
-	} else if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) {
+	} else if (rdsta & RNG_STATE1_HANDLE_INSTANTIATED) {
 		*state_handle = 1;
 		ret_code = 1;
 	}

diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index c4f7493..564d29d 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,11 +75,6 @@
 
 	memcpy(&tmp, mbr_sector + MBR_PRIMARY_ENTRY_OFFSET, sizeof(tmp));
 
-	if (tmp.first_lba != 1) {
-		VERBOSE("MBR header may have an invalid first LBA\n");
-		return -EINVAL;
-	}
-
 	if ((tmp.sector_nums == 0) || (tmp.sector_nums == UINT32_MAX)) {
 		VERBOSE("MBR header entry has an invalid number of sectors\n");
 		return -EINVAL;
@@ -399,7 +394,7 @@
 int load_partition_table(unsigned int image_id)
 {
 	uintptr_t dev_handle, image_handle, image_spec = 0;
-	mbr_entry_t mbr_entry;
+	mbr_entry_t mbr_entry = {0};
 	int result;
 
 	result = plat_get_image_source(image_id, &dev_handle, &image_spec);
@@ -421,6 +416,11 @@
 		goto out;
 	}
 	if (mbr_entry.type == PARTITION_TYPE_GPT) {
+		if (mbr_entry.first_lba != 1U) {
+			VERBOSE("MBR header may have an invalid first LBA\n");
+			return -EINVAL;
+		}
+
 		result = load_primary_gpt(image_handle, mbr_entry.first_lba);
 		if (result != 0) {
 			io_close(image_handle);

diff --git a/drivers/rambus/trng_ip_76.c b/drivers/rambus/trng_ip_76.c
deleted file mode 100644
index 8de12e9..0000000
--- a/drivers/rambus/trng_ip_76.c
+++ /dev/null

@@ -1,249 +0,0 @@
-/*
- * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
- *
- * Based on Linux kernel omap-rng.c - RNG driver for TI OMAP CPU family
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * Mostly based on original driver:
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <drivers/rambus/trng_ip_76.h>
-#include <lib/mmio.h>
-#include <lib/spinlock.h>
-#include <lib/utils.h>
-
-#define RNG_REG_STATUS_RDY			(1 << 0)
-
-#define RNG_REG_INTACK_RDY_MASK			(1 << 0)
-
-#define RNG_CONTROL_ENABLE_TRNG_MASK		(1 << 10)
-
-#define RNG_CONFIG_NOISE_BLOCKS(val)		((0xff & (val)) << 0)
-#define RNG_CONFIG_NOISE_BLK_VAL		0x5
-
-#define RNG_CONFIG_SAMPLE_CYCLES(val)		((0xff & (val)) << 16)
-#define RNG_CONFIG_SAMPLE_CYCLES_VAL		0x22
-
-#define RNG_REG_FRO_ENABLE_MASK			0xffffff
-#define RNG_REG_FRO_DETUNE_MASK			0x0
-
-#define EIP76_RNG_OUTPUT_SIZE			0x10
-#define EIP76_RNG_WAIT_ROUNDS			10
-
-#define RNG_HW_IS_EIP76(ver)			((ver) & (0xff == 0x4C))
-#define RNG_HW_VER_MAJOR(ver)			(((ver) & (0xf << 24)) >> 24)
-#define RNG_HW_VER_MINOR(ver)			(((ver) & (0xf << 20)) >> 20)
-#define RNG_HW_VER_PATCH(ver)			(((ver) & (0xf << 16)) >> 16)
-
-
-enum {
-	RNG_OUTPUT_0_REG = 0,
-	RNG_OUTPUT_1_REG,
-	RNG_OUTPUT_2_REG,
-	RNG_OUTPUT_3_REG,
-	RNG_STATUS_REG,
-	RNG_INTMASK_REG,
-	RNG_INTACK_REG,
-	RNG_CONTROL_REG,
-	RNG_CONFIG_REG,
-	RNG_ALARMCNT_REG,
-	RNG_FROENABLE_REG,
-	RNG_FRODETUNE_REG,
-	RNG_ALARMMASK_REG,
-	RNG_ALARMSTOP_REG,
-	RNG_REV_REG
-};
-
-static uint16_t reg_map_eip76[] = {
-	[RNG_OUTPUT_0_REG]	= 0x0,
-	[RNG_OUTPUT_1_REG]	= 0x4,
-	[RNG_OUTPUT_2_REG]	= 0x8,
-	[RNG_OUTPUT_3_REG]	= 0xc,
-	[RNG_STATUS_REG]	= 0x10,
-	[RNG_INTACK_REG]	= 0x10,
-	[RNG_CONTROL_REG]	= 0x14,
-	[RNG_CONFIG_REG]	= 0x18,
-	[RNG_ALARMCNT_REG]	= 0x1c,
-	[RNG_FROENABLE_REG]	= 0x20,
-	[RNG_FRODETUNE_REG]	= 0x24,
-	[RNG_ALARMMASK_REG]	= 0x28,
-	[RNG_ALARMSTOP_REG]	= 0x2c,
-	[RNG_REV_REG]		= 0x7c,
-};
-
-struct eip76_rng_dev {
-	uintptr_t	base;
-	uint16_t	*regs;
-};
-
-/* Locals */
-static struct eip76_rng_dev eip76_dev;
-static spinlock_t rng_lock;
-
-static inline uint32_t eip76_rng_read(struct eip76_rng_dev *dev, uint16_t reg)
-{
-	return mmio_read_32(dev->base + dev->regs[reg]);
-}
-
-static inline void eip76_rng_write(struct eip76_rng_dev *dev,
-				   uint16_t reg, uint32_t val)
-{
-	mmio_write_32(dev->base + dev->regs[reg], val);
-}
-
-static void eip76_rng_init(struct eip76_rng_dev *dev)
-{
-	uint32_t val;
-
-	/* Return if RNG is already running. */
-	if (eip76_rng_read(dev, RNG_CONTROL_REG) &
-			   RNG_CONTROL_ENABLE_TRNG_MASK) {
-		return;
-	}
-
-	/*  This field sets the number of 512-bit blocks of raw Noise Source
-	 * output data that must be processed by either the Conditioning
-	 * Function or the SP 800-90 DRBG ‘BC_DF’ functionality to yield
-	 * a ‘full entropy’ output value. As according to [SP 800-90B draft]
-	 * the amount of entropy input to this functionality must be twice
-	 * the amount that is output and the 8-bit samples output by the Noise
-	 * Source are supposed to have one bit of entropy each, the settings
-	 * for this field are as follows:
-	 * - SHA-1 Conditioning Function:
-	 *  generates 160 bits output, requiring 2560 sample bits,
-	 *  equivalent to 5 blocks of raw Noise Source input.
-	 * - SHA-256 Conditioning Function:
-	 *  generates 256 bits output, requiring 4096 sample bits, equivalent
-	 *  to 8 blocks of raw Noise Source input. Note that two blocks of 256
-	 *  bits are needed to start or re-seed the SP 800-90 DRBG
-	 *  (in the EIP-76d-*-SHA2 configurations)
-	 * - SP 800-90 DRBG ‘BC_DF’ functionality:
-	 *  generates 384 bits output, requiring 6144 sample bits, equivalent
-	 *  to 12 blocks of raw Noise Source input.
-	 *  This field can only be modified when ‘enable_trng’ in TRNG_CONTROL
-	 *  is ‘0’ or when either of the ‘test_known_noise’ or ‘test_cond_func’
-	 *  bits in TRNG_TEST is ‘1’. Value 0 in this field selects 256 blocks
-	 *  of 512 bits to be processed.
-	 */
-	val = RNG_CONFIG_NOISE_BLOCKS(RNG_CONFIG_NOISE_BLK_VAL);
-
-	/* This field sets the number of FRO samples that are XOR-ed together
-	 * into one bit to be shifted into the main shift register.
-	 * This value must be such that there is at least one bit of entropy
-	 * (in total) in each 8 bits that are shifted.
-	 * This field can only be modified when ‘enable_trng’ in TRNG_CONTROL
-	 * is ‘0’ or when either of the ‘test_known_noise’ or ‘test_cond_func’
-	 * bits in TRNG_TEST is ‘1’. Value 0 in this field selects 65536 FRO
-	 * samples to be XOR-ed together
-	 */
-	val |= RNG_CONFIG_SAMPLE_CYCLES(RNG_CONFIG_SAMPLE_CYCLES_VAL);
-	eip76_rng_write(dev, RNG_CONFIG_REG, val);
-
-	/* Enable all available FROs */
-	eip76_rng_write(dev, RNG_FRODETUNE_REG, RNG_REG_FRO_DETUNE_MASK);
-	eip76_rng_write(dev, RNG_FROENABLE_REG, RNG_REG_FRO_ENABLE_MASK);
-
-	/* Enable TRNG */
-	eip76_rng_write(dev, RNG_CONTROL_REG, RNG_CONTROL_ENABLE_TRNG_MASK);
-}
-
-int32_t eip76_rng_read_rand_buf(void *data, bool wait)
-{
-	uint32_t i, present;
-
-	if (!eip76_dev.base) /* not initialized */
-		return -1;
-
-	for (i = 0; i < EIP76_RNG_WAIT_ROUNDS; i++) {
-		present = eip76_rng_read(&eip76_dev, RNG_STATUS_REG) &
-					 RNG_REG_STATUS_RDY;
-		if (present || !wait) {
-			break;
-		}
-
-		udelay(10);
-	}
-
-	if (present != 0U) {
-		return 0;
-	}
-
-	memcpy(data,
-	       (void *)(eip76_dev.base + eip76_dev.regs[RNG_OUTPUT_0_REG]),
-	       EIP76_RNG_OUTPUT_SIZE);
-
-	eip76_rng_write(&eip76_dev, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
-
-	return EIP76_RNG_OUTPUT_SIZE;
-}
-
-int32_t eip76_rng_probe(uintptr_t base_addr)
-{
-	uint32_t ver;
-
-	eip76_dev.base = base_addr;
-	eip76_dev.regs = reg_map_eip76;
-
-	eip76_rng_init(&eip76_dev);
-
-	ver = eip76_rng_read(&eip76_dev, RNG_REV_REG);
-
-	INFO("%s Random Number Generator HW ver. %01x.%01x.%01x\n",
-	     RNG_HW_IS_EIP76(ver) ? "TRNG-IP-76" : "Unknown",
-	     RNG_HW_VER_MAJOR(ver), RNG_HW_VER_MINOR(ver),
-	     RNG_HW_VER_PATCH(ver));
-
-	return 0;
-}
-
-int32_t eip76_rng_get_random(uint8_t *data, uint32_t len)
-{
-	static uint8_t rand[EIP76_RNG_OUTPUT_SIZE];
-	static uint8_t pos;
-	uint32_t i;
-	int32_t ret = 0;
-
-	if (!data)
-		return -1;
-
-	spin_lock(&rng_lock);
-
-	for (i = 0; i < len; i++) {
-		if (pos >= EIP76_RNG_OUTPUT_SIZE) {
-			pos = 0;
-		}
-
-		if (pos != 0U) {
-			ret = eip76_rng_read_rand_buf(rand, true);
-		}
-
-		/* Only advance FIFO index if it is non zero or
-		 * the update from TRNG HW was successful
-		 */
-		if (pos || ret > 0) {
-			data[i] = rand[pos++];
-			ret = 0;
-		} else {
-			ret = -1;
-			break;
-		}
-	}
-
-	spin_unlock(&rng_lock);
-
-	return ret;
-}

diff --git a/drivers/renesas/common/scif/scif.S b/drivers/renesas/common/scif/scif.S
index 72b5b4b..22ade9b 100644
--- a/drivers/renesas/common/scif/scif.S
+++ b/drivers/renesas/common/scif/scif.S

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,18 +9,13 @@
 #include <asm_macros.S>
 #include <console_macros.S>
 #include <drivers/renesas/rcar/console/console.h>
+#include <platform_def.h>
 
 #define SCIF_INTERNAL_CLK	0
 #define SCIF_EXTARNAL_CLK	1
 #define SCIF_CLK		SCIF_INTERNAL_CLK
 
-/* product register */
-#define PRR			(0xFFF00044)
-#define PRR_PRODUCT_MASK	(0x00007F00)
-#define PRR_CUT_MASK		(0x000000FF)
 #define PRR_PRODUCT_H3_VER_10	(0x00004F00)
-#define PRR_PRODUCT_E3		(0x00005700)
-#define PRR_PRODUCT_D3		(0x00005800)
 
 /* module stop */
 #define CPG_BASE		(0xE6150000)
@@ -60,7 +56,6 @@
 #endif
 
 /* mode pin */
-#define RST_MODEMR		(0xE6160060)
 #define MODEMR_MD12		(0x00001000)
 
 #define SCSMR_CA_MASK		(1 << 7)

diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c
index 3fdaf16..03d8928 100644
--- a/drivers/st/bsec/bsec3.c
+++ b/drivers/st/bsec/bsec3.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,18 +30,6 @@
 #define BSEC_OTP_BANK_SHIFT		U(5)
 #define BSEC_TIMEOUT_VALUE		U(0x800000) /* ~7sec @1.2GHz */
 
-/* Magic use to indicated valid SHADOW = 'B' 'S' 'E' 'C' */
-#define BSEC_MAGIC			U(0x42534543)
-
-#define OTP_MAX_SIZE			(STM32MP2_OTP_MAX_ID + U(1))
-
-struct bsec_shadow {
-	uint32_t magic;
-	uint32_t state;
-	uint32_t value[OTP_MAX_SIZE];
-	uint32_t status[OTP_MAX_SIZE];
-};
-
 static uint32_t otp_bank(uint32_t otp)
 {
 	if (otp > STM32MP2_OTP_MAX_ID) {
@@ -167,7 +155,7 @@
 		ERROR("BSEC reset critical error 0x%x\n", status);
 		panic();
 	}
-	if ((status & BSEC_OTPSR_FUSEOK) != BSEC_OTPSR_FUSEOK) {
+	if ((status & BSEC_OTPSR_INIT_DONE) != BSEC_OTPSR_INIT_DONE) {
 		ERROR("BSEC reset critical error 0x%x\n", status);
 		panic();
 	}
@@ -467,8 +455,8 @@
 	uint32_t status = bsec_get_status();
 	uint32_t bsec_sr = mmio_read_32(BSEC_BASE + BSEC_SR);
 
-	if ((status & BSEC_OTPSR_FUSEOK) == BSEC_OTPSR_FUSEOK) {
-		/* NVSTATE is only valid if FUSEOK */
+	if ((status & BSEC_OTPSR_INIT_DONE) == BSEC_OTPSR_INIT_DONE) {
+		/* NVSTATE is only valid if INIT_DONE */
 		uint32_t nvstates = (bsec_sr & BSEC_SR_NVSTATE_MASK) >> BSEC_SR_NVSTATE_SHIFT;
 
 		if (nvstates == BSEC_SR_NVSTATE_OPEN) {

diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
index 12839f1..1266e00 100644
--- a/drivers/st/clk/clk-stm32mp2.c
+++ b/drivers/st/clk/clk-stm32mp2.c

@@ -105,7 +105,9 @@
 	_SPDIFSYMB,
 	_CK_PLL1,
 	_CK_PLL2,
+#if !STM32MP21
 	_CK_PLL3,
+#endif /* !STM32MP21 */
 	_CK_PLL4,
 	_CK_PLL5,
 	_CK_PLL6,
@@ -180,6 +182,9 @@
 	_CK_ICN_APB2,
 	_CK_ICN_APB3,
 	_CK_ICN_APB4,
+#if STM32MP21
+	_CK_ICN_APB5,
+#endif /* STM32MP21 */
 	_CK_ICN_APBDBG,
 	_CK_BKPSRAM,
 	_CK_BSEC,
@@ -200,51 +205,82 @@
 	_CK_GPIOG,
 	_CK_GPIOH,
 	_CK_GPIOI,
+#if !STM32MP21
 	_CK_GPIOJ,
 	_CK_GPIOK,
+#endif /* !STM32MP21 */
 	_CK_GPIOZ,
+#if STM32MP21
+	_CK_HASH1,
+	_CK_HASH2,
+#else /* STM32MP21 */
 	_CK_HASH,
+#endif /* STM32MP21 */
 	_CK_I2C1,
 	_CK_I2C2,
+#if !STM32MP23
 	_CK_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
 	_CK_I2C4,
 	_CK_I2C5,
 	_CK_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
 	_CK_I2C7,
 	_CK_I2C8,
+#endif /* !STM32MP21 */
 	_CK_IWDG1,
 	_CK_IWDG2,
 	_CK_OSPI1,
+#if !STM32MP21
 	_CK_OSPI2,
 	_CK_OSPIIOM,
+#endif /* !STM32MP21 */
 	_CK_PKA,
 	_CK_RETRAM,
+#if STM32MP21
+	_CK_RNG1,
+	_CK_RNG2,
+#else /* STM32MP21 */
 	_CK_RNG,
+#endif /* STM32MP21 */
 	_CK_RTC,
 	_CK_SAES,
 	_CK_SDMMC1,
 	_CK_SDMMC2,
 	_CK_SRAM1,
+#if !STM32MP21
 	_CK_SRAM2,
+#endif /* !STM32MP21 */
 	_CK_STGEN,
 	_CK_SYSCPU1,
 	_CK_SYSRAM,
 	_CK_UART4,
 	_CK_UART5,
 	_CK_UART7,
+#if STM32MP25
 	_CK_UART8,
 	_CK_UART9,
+#endif /* STM32MP25 */
 	_CK_USART1,
 	_CK_USART2,
 	_CK_USART3,
 	_CK_USART6,
+#if STM32MP21
+	_CK_USBHEHCI,
+	_CK_USBHOHCI,
+#else /* STM32MP21 */
 	_CK_USB2EHCI,
 	_CK_USB2OHCI,
+#endif /* STM32MP21 */
 	_CK_USB2PHY1,
 	_CK_USB2PHY2,
+#if !STM32MP21
 	_CK_USB3DR,
 	_CK_USB3PCIEPHY,
 	_CK_USBTC,
+#endif /* !STM32MP21 */
 
 	CK_LAST
 };
@@ -271,6 +307,7 @@
 	_CK_FLEXGEN_58, _CK_HSE
 };
 
+#if !STM32MP21
 static const uint16_t usb3pciphy_src[] = {
 	_CK_FLEXGEN_34, _CK_HSE
 };
@@ -278,6 +315,7 @@
 static const uint16_t d3per_src[] = {
 	_CK_MSI, _CK_LSI, _CK_LSE
 };
+#endif /* !STM32MP21 */
 
 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
 	.id_parents	= src,\
@@ -290,7 +328,7 @@
 	},\
 }
 
-static const struct parent_cfg parent_mp25[] = {
+static const struct parent_cfg parent_mp2[] = {
 	MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
 	MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
 	MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
@@ -303,8 +341,10 @@
 	MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
 	MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
 	MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
+#if !STM32MP21
 	MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
 	MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
+#endif /* !STM32MP21 */
 };
 
 /* GATES */
@@ -324,15 +364,26 @@
 	GATE_SYSRAM,
 	GATE_RETRAM,
 	GATE_SRAM1,
+#if !STM32MP21
 	GATE_SRAM2,
+#endif /* !STM32MP21 */
 
 	GATE_DDRPHYC,
 	GATE_SYSCPU1,
 	GATE_CRC,
+#if !STM32MP21
 	GATE_OSPIIOM,
+#endif /* !STM32MP21 */
 	GATE_BKPSRAM,
+#if STM32MP21
+	GATE_HASH1,
+	GATE_HASH2,
+	GATE_RNG1,
+	GATE_RNG2,
+#else /* STM32MP21 */
 	GATE_HASH,
 	GATE_RNG,
+#endif /* STM32MP21 */
 	GATE_CRYP1,
 	GATE_CRYP2,
 	GATE_SAES,
@@ -347,18 +398,27 @@
 	GATE_GPIOG,
 	GATE_GPIOH,
 	GATE_GPIOI,
+#if !STM32MP21
 	GATE_GPIOJ,
 	GATE_GPIOK,
+#endif /* !STM32MP21 */
 	GATE_GPIOZ,
 	GATE_RTC,
 
 	GATE_DDRCP,
 
 	/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+	GATE_USBHOHCI,
+	GATE_USBHEHCI,
+#else /* STM32MP21 */
 	GATE_USB2OHCI,
 	GATE_USB2EHCI,
+#endif /* STM32MP21 */
 
+#if !STM32MP21
 	GATE_USB3DR,
+#endif /* !STM32MP21 */
 
 	GATE_BSEC,
 	GATE_IWDG1,
@@ -373,22 +433,34 @@
 	GATE_UART5,
 	GATE_I2C1,
 	GATE_I2C2,
+#if !STM32MP23
 	GATE_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
 	GATE_I2C5,
 	GATE_I2C4,
 	GATE_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
 	GATE_I2C7,
+#endif /* !STM32MP21 */
 	GATE_USART1,
 	GATE_USART6,
 	GATE_UART7,
+#if STM32MP25
 	GATE_UART8,
 	GATE_UART9,
+#endif /* STM32MP25 */
 	GATE_STGEN,
+#if !STM32MP21
 	GATE_USB3PCIEPHY,
 	GATE_USBTC,
 	GATE_I2C8,
+#endif /* !STM32MP21 */
 	GATE_OSPI1,
+#if !STM32MP21
 	GATE_OSPI2,
+#endif /* !STM32MP21 */
 	GATE_FMC,
 	GATE_SDMMC1,
 	GATE_SDMMC2,
@@ -403,30 +475,57 @@
 	.set_clr	= (_offset_clr),\
 }
 
-static const struct gate_cfg gates_mp25[LAST_GATE] = {
+static const struct gate_cfg gates_mp2[LAST_GATE] = {
 	GATE_CFG(GATE_LSE,		RCC_BDCR,		0,	0),
+#if STM32MP21
+	GATE_CFG(GATE_LSI,		RCC_LSICR,		0,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_LSI,		RCC_BDCR,		9,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_RTCCK,		RCC_BDCR,		20,	0),
 	GATE_CFG(GATE_HSI,		RCC_OCENSETR,		0,	1),
 	GATE_CFG(GATE_HSE,		RCC_OCENSETR,		8,	1),
+#if STM32MP21
+	GATE_CFG(GATE_MSI,		RCC_OCENSETR,		2,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_MSI,		RCC_D3DCR,		0,	0),
+#endif /* STM32MP21 */
 
+#if STM32MP21
+	GATE_CFG(GATE_LSI_RDY,		RCC_LSICR,		1,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_LSI_RDY,		RCC_BDCR,		10,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_LSE_RDY,		RCC_BDCR,		2,	0),
+#if STM32MP21
+	GATE_CFG(GATE_MSI_RDY,		RCC_OCRDYR,		2,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_MSI_RDY,		RCC_D3DCR,		2,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_HSE_RDY,		RCC_OCRDYR,		8,	0),
 	GATE_CFG(GATE_HSI_RDY,		RCC_OCRDYR,		0,	0),
 	GATE_CFG(GATE_SYSRAM,		RCC_SYSRAMCFGR,		1,	0),
 	GATE_CFG(GATE_RETRAM,		RCC_RETRAMCFGR,		1,	0),
 	GATE_CFG(GATE_SRAM1,		RCC_SRAM1CFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_SRAM2,		RCC_SRAM2CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_DDRPHYC,		RCC_DDRPHYCAPBCFGR,	1,	0),
 	GATE_CFG(GATE_SYSCPU1,		RCC_SYSCPU1CFGR,	1,	0),
 	GATE_CFG(GATE_CRC,		RCC_CRCCFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_OSPIIOM,		RCC_OSPIIOMCFGR,	1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_BKPSRAM,		RCC_BKPSRAMCFGR,	1,	0),
+#if STM32MP21
+	GATE_CFG(GATE_HASH1,		RCC_HASH1CFGR,		1,	0),
+	GATE_CFG(GATE_HASH2,		RCC_HASH2CFGR,		1,	0),
+	GATE_CFG(GATE_RNG1,		RCC_RNG1CFGR,		1,	0),
+	GATE_CFG(GATE_RNG2,		RCC_RNG2CFGR,		1,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_HASH,		RCC_HASHCFGR,		1,	0),
 	GATE_CFG(GATE_RNG,		RCC_RNGCFGR,		1,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_CRYP1,		RCC_CRYP1CFGR,		1,	0),
 	GATE_CFG(GATE_CRYP2,		RCC_CRYP2CFGR,		1,	0),
 	GATE_CFG(GATE_SAES,		RCC_SAESCFGR,		1,	0),
@@ -440,16 +539,23 @@
 	GATE_CFG(GATE_GPIOG,		RCC_GPIOGCFGR,		1,	0),
 	GATE_CFG(GATE_GPIOH,		RCC_GPIOHCFGR,		1,	0),
 	GATE_CFG(GATE_GPIOI,		RCC_GPIOICFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_GPIOJ,		RCC_GPIOJCFGR,		1,	0),
 	GATE_CFG(GATE_GPIOK,		RCC_GPIOKCFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_GPIOZ,		RCC_GPIOZCFGR,		1,	0),
 	GATE_CFG(GATE_RTC,		RCC_RTCCFGR,		1,	0),
 	GATE_CFG(GATE_DDRCP,		RCC_DDRCPCFGR,		1,	0),
 
 	/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+	GATE_CFG(GATE_USBHOHCI,		RCC_USBHCFGR,		1,	0),
+	GATE_CFG(GATE_USBHEHCI,		RCC_USBHCFGR,		1,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_USB2OHCI,		RCC_USB2CFGR,		1,	0),
 	GATE_CFG(GATE_USB2EHCI,		RCC_USB2CFGR,		1,	0),
 	GATE_CFG(GATE_USB3DR,		RCC_USB3DRCFGR,		1,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_BSEC,		RCC_BSECCFGR,		1,	0),
 	GATE_CFG(GATE_IWDG1,		RCC_IWDG1CFGR,		1,	0),
 	GATE_CFG(GATE_IWDG2,		RCC_IWDG2CFGR,		1,	0),
@@ -461,22 +567,34 @@
 	GATE_CFG(GATE_UART5,		RCC_UART5CFGR,		1,	0),
 	GATE_CFG(GATE_I2C1,		RCC_I2C1CFGR,		1,	0),
 	GATE_CFG(GATE_I2C2,		RCC_I2C2CFGR,		1,	0),
+#if !STM32MP23
 	GATE_CFG(GATE_I2C3,		RCC_I2C3CFGR,		1,	0),
+#endif /* !STM32MP23 */
+#if STM32MP25
 	GATE_CFG(GATE_I2C5,		RCC_I2C5CFGR,		1,	0),
 	GATE_CFG(GATE_I2C4,		RCC_I2C4CFGR,		1,	0),
 	GATE_CFG(GATE_I2C6,		RCC_I2C6CFGR,		1,	0),
+#endif /* STM32MP25 */
+#if !STM32MP21
 	GATE_CFG(GATE_I2C7,		RCC_I2C7CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_USART1,		RCC_USART1CFGR,		1,	0),
 	GATE_CFG(GATE_USART6,		RCC_USART6CFGR,		1,	0),
 	GATE_CFG(GATE_UART7,		RCC_UART7CFGR,		1,	0),
+#if STM32MP25
 	GATE_CFG(GATE_UART8,		RCC_UART8CFGR,		1,	0),
 	GATE_CFG(GATE_UART9,		RCC_UART9CFGR,		1,	0),
+#endif /* STM32MP25 */
 	GATE_CFG(GATE_STGEN,		RCC_STGENCFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_USB3PCIEPHY,	RCC_USB3PCIEPHYCFGR,	1,	0),
 	GATE_CFG(GATE_USBTC,		RCC_USBTCCFGR,		1,	0),
 	GATE_CFG(GATE_I2C8,		RCC_I2C8CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_OSPI1,		RCC_OSPI1CFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_OSPI2,		RCC_OSPI2CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_FMC,		RCC_FMCCFGR,		1,	0),
 	GATE_CFG(GATE_SDMMC1,		RCC_SDMMC1CFGR,		1,	0),
 	GATE_CFG(GATE_SDMMC2,		RCC_SDMMC2CFGR,		1,	0),
@@ -499,11 +617,14 @@
 		.bitrdy	= _bitrdy,\
 }
 
-static const struct div_cfg dividers_mp25[] = {
+static const struct div_cfg dividers_mp2[] = {
 	DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
+#if STM32MP21
+	DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
+#endif /* STM32MP21 */
 	DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
 	DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
@@ -520,7 +641,7 @@
 	NB_OSCILLATOR
 };
 
-static struct clk_oscillator_data stm32mp25_osc_data[] = {
+static struct clk_oscillator_data stm32mp2_osc_data[] = {
 	OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
 		   NULL, NULL, NULL),
 
@@ -551,7 +672,7 @@
 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
 {
 	if (id < NB_OSCILLATOR) {
-		return stm32mp25_osc_data[id].name;
+		return stm32mp2_osc_data[id].name;
 	}
 
 	return NULL;
@@ -590,10 +711,12 @@
 		.reg_pllxcfgr1 = (_reg),\
 	}
 
-static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = {
+static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = {
 	CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
 	CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
+#if !STM32MP21
 	CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
+#endif /* !STM32MP21 */
 	CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
 	CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
 	CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
@@ -603,7 +726,7 @@
 
 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
 {
-	return &stm32mp25_clk_pll[idx];
+	return &stm32mp2_clk_pll[idx];
 }
 
 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
@@ -958,6 +1081,7 @@
 #define RCC_16_MHZ	UL(16000000)
 
 #ifdef IMAGE_BL2
+#if !STM32MP21
 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
 				      unsigned long prate)
 {
@@ -982,12 +1106,16 @@
 
 	return ret;
 }
+#endif /* !STM32MP21 */
 #endif /* IMAGE_BL2 */
 
 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
 						   int id __unused,
 						   unsigned long prate __unused)
 {
+#if STM32MP21
+	return RCC_16_MHZ;
+#else /* STM32MP21 */
 	uintptr_t address = priv->base + RCC_BDCR;
 
 	if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
@@ -995,6 +1123,7 @@
 	} else {
 		return RCC_16_MHZ;
 	}
+#endif /* STM32MP21 */
 }
 
 static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
@@ -1039,10 +1168,10 @@
 	STM32_OSC_MSI_OPS,
 	STM32_RTC_OPS,
 
-	MP25_LAST_OPS
+	MP2_LAST_OPS
 };
 
-static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = {
+static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = {
 	[NO_OPS] =  NULL,
 	[FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
 	[GATE_OPS] = &clk_gate_ops,
@@ -1061,7 +1190,7 @@
 	[STM32_RTC_OPS] = &clk_stm32_rtc_ops
 };
 
-static const struct clk_stm32 stm32mp25_clk[CK_LAST] = {
+static const struct clk_stm32 stm32mp2_clk[CK_LAST] = {
 	CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
 
 	/* ROOT CLOCKS */
@@ -1081,7 +1210,9 @@
 	CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
 
 	CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
+#if !STM32MP21
 	CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
+#endif /* !STM32MP21 */
 	CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
 	CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
 	CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
@@ -1158,21 +1289,35 @@
 	STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
 	STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
 	STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
+#if STM32MP21
+	STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5),
+#endif /* STM32MP21 */
 	STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
 
 	/* KERNEL CLOCK */
 	STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
 	STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
 	STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
+#if !STM32MP21
 	STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
+#endif /* !STM32MP21 */
 
 	STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
 	STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
 	STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
+#if !STM32MP21
 	STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
+#if STM32MP21
+	STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1),
+	STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2),
+	STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1),
+	STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2),
+#else /* STM32MP21 */
 	STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
 	STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
+#endif /* STM32MP21 */
 	STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
 	STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
 	STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
@@ -1187,18 +1332,27 @@
 	STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
 	STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
 	STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
+#if !STM32MP21
 	STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
 	STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
 	STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC),
 
 	STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP),
 
 	/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+	STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI),
+	STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI),
+#else /* STM32MP21 */
 	STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
 	STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
+#endif /* STM32MP21 */
 
+#if !STM32MP21
 	STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
+#endif /* !STM32MP21 */
 
 	STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
 	STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
@@ -1211,24 +1365,41 @@
 	STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
 	STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
 	STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
+#if STM32MP21
+	STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1),
+	STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2),
+	STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1),
+	STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6),
+	STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7),
+	STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3),
+#else /* STM32MP21 */
 	STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
 	STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
+#if STM32MP25
 	STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
 	STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
 	STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
 	STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
+#endif /* STM32MP25 */
 	STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
 	STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
 	STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
 	STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
+#if STM32MP25
 	STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
 	STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
+#endif /* STM32MP25 */
+#endif /* STM32MP21 */
 	STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
+#if !STM32MP21
 	STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
 	STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
 	STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
+#if !STM32MP21
 	STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
 	STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
 	STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
@@ -1240,7 +1411,9 @@
 	CLKSRC_CA35SS,
 	CLKSRC_PLL1,
 	CLKSRC_PLL2,
+#if !STM32MP21
 	CLKSRC_PLL3,
+#endif /* !STM32MP21 */
 	CLKSRC_PLL4,
 	CLKSRC_PLL5,
 	CLKSRC_PLL6,
@@ -1656,6 +1829,11 @@
 	int err;
 
 	for (i = _PLL1; i < _PLL_NB; i++) {
+#if STM32MP21
+		if (i == _PLL3) {
+			continue;
+		}
+#endif
 		err = clk_stm32_pll_init(priv, i);
 		if (err) {
 			return err;
@@ -1886,6 +2064,7 @@
 
 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
 {
+#if !STM32MP21
 	struct stm32_clk_platdata *pdata = priv->pdata;
 	struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
 	int err;
@@ -1896,6 +2075,7 @@
 			    osci->freq / 1000000U);
 		panic();
 	}
+#endif /* !STM32MP21 */
 
 	_clk_stm32_enable(priv, _CK_MSI);
 }
@@ -2204,6 +2384,11 @@
 		int subnode = 0;
 		int err = 0;
 
+#if STM32MP21
+		if (i == _PLL3) {
+			continue;
+		}
+#endif
 		snprintf(name, sizeof(name), "st,pll-%u", i + 1);
 
 		subnode = fdt_subnode_offset(fdt, node, name);
@@ -2266,49 +2451,53 @@
 }
 #endif /* IMAGE_BL2 */
 
-static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
+static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR];
 
-static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB];
+static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB];
 
 #define DT_FLEXGEN_CLK_MAX	64
-static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
+static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX];
 
+#if STM32MP21
+#define DT_BUS_CLK_MAX		7
+#else /* STM32MP21 */
 #define DT_BUS_CLK_MAX		6
-static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
+#endif /* STM32MP21 */
+static uint32_t mp2_busclk[DT_BUS_CLK_MAX];
 
 #define DT_KERNEL_CLK_MAX	20
-static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
+static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX];
 
-static struct stm32_clk_platdata stm32mp25_pdata = {
-	.osci = mp25_osci,
+static struct stm32_clk_platdata stm32mp2_pdata = {
+	.osci = mp2_osci,
 	.nosci = NB_OSCILLATOR,
-	.pll = mp25_pll,
+	.pll = mp2_pll,
 	.npll = _PLL_NB,
-	.flexgen = mp25_flexgen,
+	.flexgen = mp2_flexgen,
 	.nflexgen = DT_FLEXGEN_CLK_MAX,
-	.busclk	= mp25_busclk,
+	.busclk	= mp2_busclk,
 	.nbusclk = DT_BUS_CLK_MAX,
-	.kernelclk = mp25_kernelclk,
+	.kernelclk = mp2_kernelclk,
 	.nkernelclk = DT_KERNEL_CLK_MAX,
 };
 
-static uint8_t refcounts_mp25[CK_LAST];
+static uint8_t refcounts_mp2[CK_LAST];
 
-static struct stm32_clk_priv stm32mp25_clock_data = {
+static struct stm32_clk_priv stm32mp2_clock_data = {
 	.base		= RCC_BASE,
-	.num		= ARRAY_SIZE(stm32mp25_clk),
-	.clks		= stm32mp25_clk,
-	.parents	= parent_mp25,
-	.nb_parents	= ARRAY_SIZE(parent_mp25),
-	.gates		= gates_mp25,
-	.nb_gates	= ARRAY_SIZE(gates_mp25),
-	.div		= dividers_mp25,
-	.nb_div		= ARRAY_SIZE(dividers_mp25),
-	.osci_data	= stm32mp25_osc_data,
-	.nb_osci_data	= ARRAY_SIZE(stm32mp25_osc_data),
-	.gate_refcounts	= refcounts_mp25,
-	.pdata		= &stm32mp25_pdata,
-	.ops_array	= ops_array_mp25,
+	.num		= ARRAY_SIZE(stm32mp2_clk),
+	.clks		= stm32mp2_clk,
+	.parents	= parent_mp2,
+	.nb_parents	= ARRAY_SIZE(parent_mp2),
+	.gates		= gates_mp2,
+	.nb_gates	= ARRAY_SIZE(gates_mp2),
+	.div		= dividers_mp2,
+	.nb_div		= ARRAY_SIZE(dividers_mp2),
+	.osci_data	= stm32mp2_osc_data,
+	.nb_osci_data	= ARRAY_SIZE(stm32mp2_osc_data),
+	.gate_refcounts	= refcounts_mp2,
+	.pdata		= &stm32mp2_pdata,
+	.ops_array	= ops_array_mp2,
 };
 
 int stm32mp2_clk_init(void)
@@ -2317,13 +2506,13 @@
 	int ret;
 
 #ifdef IMAGE_BL2
-	ret = stm32_clk_parse_fdt(&stm32mp25_pdata);
+	ret = stm32_clk_parse_fdt(&stm32mp2_pdata);
 	if (ret != 0) {
 		return ret;
 	}
 #endif
 
-	ret = clk_stm32_init(&stm32mp25_clock_data, base);
+	ret = clk_stm32_init(&stm32mp2_clock_data, base);
 	if (ret != 0) {
 		return ret;
 	}

diff --git a/drivers/st/crypto/stm32_saes.c b/drivers/st/crypto/stm32_saes.c
index f4da571..547ff89 100644
--- a/drivers/st/crypto/stm32_saes.c
+++ b/drivers/st/crypto/stm32_saes.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -211,9 +211,11 @@
 	uint64_t timeout;
 
 	/* Reset IP */
-	mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
-	udelay(SAES_RESET_DELAY);
-	mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+	if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) != _SAES_SR_BUSY) {
+		mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+		udelay(SAES_RESET_DELAY);
+		mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+	}
 
 	timeout = timeout_init_us(SAES_TIMEOUT_US);
 	while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {

diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
index a2a4082..8efb7cf 100644
--- a/drivers/st/ddr/stm32mp2_ddr_helpers.c
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -363,8 +363,6 @@
 	mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
 		      RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
 
-	/* TODO: check if ddr_sr_exit_loop() is needed here */
-
 	return 0;
 }
 
@@ -390,13 +388,6 @@
 	return ddr_sr_exit_loop();
 }
 
-uint32_t ddr_get_io_calibration_val(void)
-{
-	/* TODO create related service */
-
-	return 0U;
-}
-
 int ddr_sr_entry(bool standby)
 {
 	int ret = -EINVAL;

diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c
index 95f05e7..2b0e317 100644
--- a/drivers/st/ddr/stm32mp2_ram.c
+++ b/drivers/st/ddr/stm32mp2_ram.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -142,9 +142,6 @@
 			ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret);
 			panic();
 		}
-
-		/* TODO Restore area overwritten by training */
-		//stm32_restore_ddr_training_area();
 	} else {
 		size_t retsize;
 

diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c
index 98968d5..4aa5c73 100644
--- a/drivers/st/ddr/stm32mp_ddr.c
+++ b/drivers/st/ddr/stm32mp_ddr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -44,7 +44,7 @@
 			      ddr_registers[type].name, i);
 			panic();
 		} else {
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
 			if (desc[i].qd) {
 				stm32mp_ddr_start_sw_done(priv->ctl);
 			}
@@ -52,7 +52,7 @@
 			value = *((uint32_t *)((uintptr_t)param +
 					       desc[i].par_offset));
 			mmio_write_32(ptr, value);
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
 			if (desc[i].qd) {
 				stm32mp_ddr_wait_sw_done_ack(priv->ctl);
 			}
@@ -277,9 +277,9 @@
 	/* Toggle rfshctl3.refresh_update_level */
 	rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);
 	if ((rfshctl3 & refresh_update_level) == refresh_update_level) {
-		mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
-	} else {
 		mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
+	} else {
+		mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
 		refresh_update_level = 0U;
 	}
 
@@ -293,7 +293,7 @@
 		if (timeout_elapsed(timeout)) {
 			panic();
 		}
-	} while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) != refresh_update_level);
+	} while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) == refresh_update_level);
 
 	VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);
 }

diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 44d7c09..2d64de3 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c

@@ -282,7 +282,7 @@
 
 	clk_disable(clock);
 
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
 	if (status == DT_SECURE) {
 		stm32mp_register_secure_gpio(bank, pin);
 #if !IMAGE_BL2

diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
index 74451d7..3d78c20 100644
--- a/drivers/st/iwdg/stm32_iwdg.c
+++ b/drivers/st/iwdg/stm32_iwdg.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,7 +33,6 @@
 	uintptr_t base;
 	unsigned long clock;
 	uint8_t flags;
-	int num_irq;
 };
 
 static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE];

diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 66988d7..e07d9e7 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c

@@ -129,7 +129,7 @@
 #define DT_SDMMC2_COMPAT		"st,stm32-sdmmc2"
 #endif
 
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
 #define SDMMC_FIFO_SIZE			64U
 #else
 #define SDMMC_FIFO_SIZE			1024U

diff --git a/drivers/st/pmic/stm32mp_pmic2.c b/drivers/st/pmic/stm32mp_pmic2.c
index c19d36a..fcf3fd9 100644
--- a/drivers/st/pmic/stm32mp_pmic2.c
+++ b/drivers/st/pmic/stm32mp_pmic2.c

@@ -493,7 +493,5 @@
 		panic();
 	}
 
-#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
 	stpmic2_dump_regulators(pmic2);
-#endif
 }

diff --git a/drivers/st/pmic/stpmic2.c b/drivers/st/pmic/stpmic2.c
index 7f233db..b3af3e0 100644
--- a/drivers/st/pmic/stpmic2.c
+++ b/drivers/st/pmic/stpmic2.c

@@ -434,9 +434,9 @@
 	return -EPERM;
 }
 
-#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
 void stpmic2_dump_regulators(struct pmic_handle_s *pmic)
 {
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
 	size_t i;
 	char const *name;
 
@@ -456,8 +456,8 @@
 		VERBOSE("PMIC regul %s: %s, %dmV\n",
 			name, state ? "EN" : "DIS", val);
 	}
-}
 #endif
+}
 
 int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val)
 {

diff --git a/drivers/st/regulator/regulator_fixed.c b/drivers/st/regulator/regulator_fixed.c
index 6c9d3b1..6b14b5d 100644
--- a/drivers/st/regulator/regulator_fixed.c
+++ b/drivers/st/regulator/regulator_fixed.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,7 +21,6 @@
 
 struct fixed_data {
 	char name[FIXED_NAME_LEN];
-	uint16_t volt;
 	struct regul_description desc;
 };
 

diff --git a/drivers/ti/ipc/mailbox.c b/drivers/ti/ipc/mailbox.c
new file mode 100644
index 0000000..65458a5
--- /dev/null
+++ b/drivers/ti/ipc/mailbox.c

@@ -0,0 +1,145 @@
+/*
+ * Texas Instruments Mailbox Driver
+ *
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdlib.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/utils.h>
+#include <lib/utils_def.h>
+#include <ti_sci_transport.h>
+
+#include <platform_def.h>
+
+/*
+ * TI_MAILBOX_RX/TX_BASE and the MAILBOX_MAX_MESSAGE_SIZE values are expected
+ * to come from platform specific header file ie. platform_def.h
+ */
+
+#define TI_MAILBOX_SYSC		UL(0x10)
+#define TI_MAILBOX_MSG		UL(0x40)
+#define TI_MAILBOX_FIFO_STATUS	UL(0x80)
+#define TI_MAILBOX_MSG_STATUS		UL(0xc0)
+
+/*
+ * Function to poll for mailbox rx messages
+ * IRQ model is currently not in scope of this driver
+ */
+static int8_t ti_mailbox_poll_rx_status(void)
+{
+	uint32_t num_messages_pending = 0U;
+	uint32_t retry_count = 100U;
+
+	/*
+	 * Keep polling till we get a message for 100 times
+	 * with intervals of 10 milliseconds.
+	 */
+	while (num_messages_pending == 0U) {
+		num_messages_pending = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS);
+		if (retry_count-- == 0U) {
+			return -ETIMEDOUT;
+		}
+		mdelay(10);
+	}
+	return 0;
+}
+
+int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id)
+{
+	/* MSG_STATUS tells us how many pending messages */
+	uint32_t try_count = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS);
+
+	/* Run the loop till the status register is cleared */
+	while (mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS) != 0U) {
+		WARN("Clearing message from mailbox FIFO\n");
+		/* The act of reading the mailbox msg itself clears it */
+		mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG);
+		/*
+		 * The try_count is kept independent of the value of the status register
+		 * because if at any point a new mailbox message arrives while this loop
+		 * is in progress, we would want to know that message arrived and not clear
+		 * it. We would rather print the error than clear the message thus indicating
+		 * that the system is probably in a bad/async state.
+		 */
+		if (!(try_count--)) {
+			ERROR("Could not clear all messages from mailbox FIFO\n");
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg)
+{
+	uint32_t num_bytes;
+	void *dst_ptr = (void *)MAILBOX_TX_START_REGION;
+
+	assert(msg != NULL);
+
+	num_bytes = msg->len;
+
+	/*
+	 * Only a simple check because even if there's 1 pending message
+	 * we will be in a bad state if we try to send another message
+	 * due to the absence of any interrupt or buffer mgmt model.
+	 */
+	if (mmio_read_32(TI_MAILBOX_TX_BASE + TI_MAILBOX_FIFO_STATUS)) {
+		ERROR("Mailbox FIFO has pending messages!\n");
+		return -EINVAL;
+	}
+
+	if (num_bytes > MAILBOX_MAX_MESSAGE_SIZE) {
+		ERROR("message length %lu > max msg size\n", msg->len);
+		return -EINVAL;
+	}
+
+	/*
+	 * Move the buffer contents into the SRAM to be accessed by TIFS
+	 */
+	memmove(dst_ptr, msg->buf, num_bytes);
+
+	mmio_write_32(TI_MAILBOX_TX_BASE + TI_MAILBOX_MSG, (uint64_t)(void *)dst_ptr);
+
+	return 0;
+}
+
+int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg)
+{
+	uint32_t num_bytes;
+	uint64_t rcv_addr;
+
+	assert(msg != NULL);
+
+	num_bytes = msg->len;
+
+	if (ti_mailbox_poll_rx_status() == -ETIMEDOUT) {
+		ERROR("Timeout waiting for receive\n");
+		return -ETIMEDOUT;
+	}
+
+	rcv_addr = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG);
+
+	if (rcv_addr != MAILBOX_RX_START_REGION) {
+		ERROR("message address %lu is not valid\n", rcv_addr);
+		return -EINVAL;
+	}
+
+	if (num_bytes > MAILBOX_MAX_MESSAGE_SIZE) {
+		ERROR("message length %lu > max msg size\n", msg->len);
+		return -EINVAL;
+	}
+
+	memmove(msg->buf, (uint8_t *)(rcv_addr), num_bytes);
+
+	return 0;
+}

diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c b/drivers/ti/ipc/sec_proxy.c
similarity index 83%
rename from plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
rename to drivers/ti/ipc/sec_proxy.c
index fb27336..55396f6 100644
--- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
+++ b/drivers/ti/ipc/sec_proxy.c

@@ -2,7 +2,7 @@
  * Texas Instruments K3 Secure Proxy Driver
  *   Based on Linux and U-Boot implementation
  *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - http://www.ti.com/
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,7 +18,7 @@
 #include <lib/utils.h>
 #include <lib/utils_def.h>
 
-#include "sec_proxy.h"
+#include <ti_sci_transport.h>
 
 /* SEC PROXY RT THREAD STATUS */
 #define RT_THREAD_STATUS			(0x0)
@@ -97,32 +97,12 @@
 		.data_end_offset = 0x3C,
 	},
 	.threads = {
-#if !K3_SEC_PROXY_LITE
-		SP_THREAD(SP_NOTIFY),
-		SP_THREAD(SP_RESPONSE),
-		SP_THREAD(SP_HIGH_PRIORITY),
-		SP_THREAD(SP_LOW_PRIORITY),
-		SP_THREAD(SP_NOTIFY_RESP),
-#else
-		SP_THREAD(SP_RESPONSE),
-		SP_THREAD(SP_HIGH_PRIORITY),
-#endif /* K3_SEC_PROXY_LITE */
+		SP_THREAD(RX_SECURE_TRANSPORT_CHANNEL_ID),
+		SP_THREAD(TX_SECURE_TRANSPORT_CHANNEL_ID),
 	},
 };
 
 /**
- * struct sec_msg_hdr - Message header for secure messages and responses
- * @checksum:	CRC of message for integrity checking
- */
-union sec_msg_hdr {
-	struct {
-		uint16_t checksum;
-		uint16_t reserved;
-	} __packed;
-	uint32_t data;
-};
-
-/**
  * k3_sec_proxy_verify_thread() - Verify thread status before
  *				  sending/receiving data
  * @spt: Pointer to Secure Proxy thread description
@@ -170,13 +150,13 @@
 }
 
 /**
- * k3_sec_proxy_clear_rx_thread() - Clear Secure Proxy thread
+ * ti_sci_transport_clear_rx_thread() - Clear Secure Proxy thread
  *
  * @id: Channel Identifier
  *
  * Return: 0 if all goes well, else appropriate error message
  */
-int k3_sec_proxy_clear_rx_thread(enum k3_sec_proxy_chan_id id)
+int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id)
 {
 	struct k3_sec_proxy_thread *spt = &spm.threads[id];
 
@@ -208,16 +188,15 @@
 }
 
 /**
- * k3_sec_proxy_send() - Send data over a Secure Proxy thread
+ * ti_sci_transport_send() - Send data over a Secure Proxy thread
  * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
+ * @msg: Pointer to ti_sci_msg
  *
  * Return: 0 if all goes well, else appropriate error message
  */
-int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_msg *msg)
+int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg)
 {
 	struct k3_sec_proxy_thread *spt = &spm.threads[id];
-	union sec_msg_hdr secure_header;
 	int num_words, trail_bytes, i, ret;
 	uintptr_t data_reg;
 
@@ -228,19 +207,13 @@
 	}
 
 	/* Check the message size */
-	if (msg->len + sizeof(secure_header) > spm.desc.max_msg_size) {
+	if (msg->len > spm.desc.max_msg_size) {
 		ERROR("Thread %s message length %lu > max msg size\n",
 		      spt->name, msg->len);
 		return -EINVAL;
 	}
 
-	/* TODO: Calculate checksum */
-	secure_header.checksum = 0;
-
-	/* Send the secure header */
 	data_reg = spm.desc.data_start_offset;
-	mmio_write_32(spt->data + data_reg, secure_header.data);
-	data_reg += sizeof(uint32_t);
 
 	/* Send whole words */
 	num_words = msg->len / sizeof(uint32_t);
@@ -281,16 +254,15 @@
 }
 
 /**
- * k3_sec_proxy_recv() - Receive data from a Secure Proxy thread
+ * ti_sci_transport_recv() - Receive data from a Secure Proxy thread
  * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
+ * @msg: Pointer to ti_sci_msg
  *
  * Return: 0 if all goes well, else appropriate error message
  */
-int k3_sec_proxy_recv(enum k3_sec_proxy_chan_id id, struct k3_sec_proxy_msg *msg)
+int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg)
 {
 	struct k3_sec_proxy_thread *spt = &spm.threads[id];
-	union sec_msg_hdr secure_header;
 	uintptr_t data_reg;
 	int num_words, trail_bytes, i, ret;
 
@@ -300,10 +272,7 @@
 		return ret;
 	}
 
-	/* Read secure header */
 	data_reg = spm.desc.data_start_offset;
-	secure_header.data = mmio_read_32(spt->data + data_reg);
-	data_reg += sizeof(uint32_t);
 
 	/* Read whole words */
 	num_words = msg->len / sizeof(uint32_t);
@@ -332,9 +301,6 @@
 	if (data_reg <= spm.desc.data_end_offset)
 		mmio_read_32(spt->data + spm.desc.data_end_offset);
 
-	/* TODO: Verify checksum */
-	(void)secure_header.checksum;
-
 	VERBOSE("Message successfully received from thread %s\n", spt->name);
 
 	return 0;

diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/drivers/ti/ti_sci/ti_sci.c
similarity index 98%
rename from plat/ti/k3/common/drivers/ti_sci/ti_sci.c
rename to drivers/ti/ti_sci/ti_sci.c
index 5c6ba6b..f0813e5 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/drivers/ti/ti_sci/ti_sci.c

@@ -2,7 +2,7 @@
  * Texas Instruments System Control Interface Driver
  *   Based on Linux and U-Boot implementation
  *
- * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
 #include <lib/bakery_lock.h>
 
 #include <common/debug.h>
-#include <sec_proxy.h>
+#include <ti_sci_transport.h>
 
 #include "ti_sci_protocol.h"
 #include "ti_sci.h"
@@ -34,8 +34,8 @@
  * @rx_message:	Receive message
  */
 struct ti_sci_xfer {
-	struct k3_sec_proxy_msg tx_message;
-	struct k3_sec_proxy_msg rx_message;
+	struct ti_sci_msg tx_message;
+	struct ti_sci_msg rx_message;
 };
 
 /**
@@ -69,6 +69,9 @@
 		return -ERANGE;
 
 	hdr = (struct ti_sci_msg_hdr *)tx_buf;
+
+	/* TODO: Calculate checksum */
+	hdr->sec_hdr.checksum = 0;
 	hdr->seq = ++message_sequence;
 	hdr->type = msg_type;
 	hdr->host = TI_SCI_HOST_ID;
@@ -95,8 +98,8 @@
  *
  * Return: 0 if all goes well, else appropriate error message
  */
-static int ti_sci_get_response(struct k3_sec_proxy_msg *msg,
-			       enum k3_sec_proxy_chan_id chan)
+static int ti_sci_get_response(struct ti_sci_msg *msg,
+			       enum ti_sci_transport_chan_id chan)
 {
 	struct ti_sci_msg_hdr *hdr;
 	unsigned int retry = 5;
@@ -104,7 +107,7 @@
 
 	for (; retry > 0; retry--) {
 		/* Receive the response */
-		ret = k3_sec_proxy_recv(chan, msg);
+		ret = ti_sci_transport_recv(chan, msg);
 		if (ret) {
 			ERROR("Message receive failed (%d)\n", ret);
 			return ret;
@@ -133,6 +136,9 @@
 	if (!(hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK))
 		return -ENODEV;
 
+	/* TODO: Verify checksum */
+	(void)hdr->sec_hdr.checksum;
+
 	return 0;
 }
 
@@ -145,21 +151,21 @@
  */
 static int ti_sci_do_xfer(struct ti_sci_xfer *xfer)
 {
-	struct k3_sec_proxy_msg *tx_msg = &xfer->tx_message;
-	struct k3_sec_proxy_msg *rx_msg = &xfer->rx_message;
+	struct ti_sci_msg *tx_msg = &xfer->tx_message;
+	struct ti_sci_msg *rx_msg = &xfer->rx_message;
 	int ret;
 
 	bakery_lock_get(&ti_sci_xfer_lock);
 
 	/* Clear any spurious messages in receive queue */
-	ret = k3_sec_proxy_clear_rx_thread(SP_RESPONSE);
+	ret = ti_sci_transport_clear_rx_thread(RX_SECURE_TRANSPORT_CHANNEL_ID);
 	if (ret) {
 		ERROR("Could not clear response queue (%d)\n", ret);
 		goto unlock;
 	}
 
 	/* Send the message */
-	ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, tx_msg);
+	ret = ti_sci_transport_send(TX_SECURE_TRANSPORT_CHANNEL_ID, tx_msg);
 	if (ret) {
 		ERROR("Message sending failed (%d)\n", ret);
 		goto unlock;
@@ -167,7 +173,7 @@
 
 	/* Get the response if requested */
 	if (rx_msg->len != 0U) {
-		ret = ti_sci_get_response(rx_msg, SP_RESPONSE);
+		ret = ti_sci_get_response(rx_msg, RX_SECURE_TRANSPORT_CHANNEL_ID);
 		if (ret != 0U) {
 			ERROR("Failed to get response (%d)\n", ret);
 			goto unlock;

diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h b/drivers/ti/ti_sci/ti_sci.h
similarity index 99%
rename from plat/ti/k3/common/drivers/ti_sci/ti_sci.h
rename to drivers/ti/ti_sci/ti_sci.h
index 06d1f8d..1f19632 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
+++ b/drivers/ti/ti_sci/ti_sci.h

@@ -2,7 +2,7 @@
  * Texas Instruments System Control Interface API
  *   Based on Linux and U-Boot implementation
  *
- * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/drivers/ti/ti_sci/ti_sci_protocol.h
similarity index 98%
rename from plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
rename to drivers/ti/ti_sci/ti_sci_protocol.h
index cc71eac..bdd2462 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/drivers/ti/ti_sci/ti_sci_protocol.h

@@ -5,7 +5,7 @@
  * The system works in a message response protocol
  * See: http://processors.wiki.ti.com/index.php/TISCI for details
  *
- * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -54,6 +54,17 @@
 #define TISCI_MSG_WAIT_PROC_BOOT_STATUS	0xc401
 
 /**
+ * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
+ *				  via secure transport.
+ * @checksum:	crc16 checksum for the entire message
+ * @reserved:	Reserved for future use.
+ */
+struct ti_sci_secure_msg_hdr {
+	uint16_t checksum;
+	uint16_t reserved;
+} __packed;
+
+/**
  * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
  * @type:	Type of messages: One of TI_SCI_MSG* values
  * @host:	Host of the message
@@ -61,6 +72,7 @@
  * @flags:	Flag for the message
  */
 struct ti_sci_msg_hdr {
+	struct ti_sci_secure_msg_hdr sec_hdr;
 	uint16_t type;
 	uint8_t host;
 	uint8_t seq;

diff --git a/drivers/ti/ti_sci/ti_sci_transport.h b/drivers/ti/ti_sci/ti_sci_transport.h
new file mode 100644
index 0000000..13d0fb5
--- /dev/null
+++ b/drivers/ti/ti_sci/ti_sci_transport.h

@@ -0,0 +1,74 @@
+/*
+ * Texas Instruments SCI Transport Protocol Header
+ *
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TI_SCI_TRANSPORT_H
+#define TI_SCI_TRANSPORT_H
+
+#include <stdint.h>
+
+/**
+ * enum ti_sci_transport_chan_id - Secure Proxy thread IDs
+ *
+ * These are the available IDs used in ti_sci_transport_{send,recv}()
+ */
+enum ti_sci_transport_chan_id {
+#if !K3_SEC_PROXY_LITE
+	RX_SECURE_TRANSPORT_CHANNEL_ID = 1,
+	TX_SECURE_TRANSPORT_CHANNEL_ID,
+#else
+	RX_SECURE_TRANSPORT_CHANNEL_ID = 8,
+	/*
+	 * Note: TISCI documentation indicates "low priority", but in reality
+	 * with a single thread, there is no low or high priority.. This usage
+	 * is more appropriate for TF-A since we can reduce the churn as a
+	 * result.
+	 */
+	TX_SECURE_TRANSPORT_CHANNEL_ID,
+#endif /* K3_SEC_PROXY_LITE */
+};
+
+/**
+ * struct ti_sci_msg - Secure proxy message structure
+ * @len: Length of data in the Buffer
+ * @buf: Buffer pointer
+ *
+ * This is the structure for data used in ti_sci_transport_{send,recv}()
+ */
+struct ti_sci_msg {
+	size_t len;
+	uint8_t *buf;
+};
+
+/**
+ * ti_sci_transport_clear_rx_thread() - Clear a receive Secure Proxy thread
+ * @id: Channel Identifier
+ * @msg: Pointer to ti_sci_msg
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id);
+
+/**
+ * ti_sci_transport_send() - Send data over mailbox/ Secure Proxy thread
+ * @id: Channel Identifier
+ * @msg: Pointer to ti_sci_msg
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg);
+
+/**
+ * ti_sci_transport_recv() - Receive data from a Secure Proxy thread/ mailbox
+ * @id: Channel Identifier
+ * @msg: Pointer to ti_sci_msg
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg);
+
+#endif /* TI_SCI_TRANSPORT_H */

diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
index 95ea2a1..2a128d8 100644
--- a/fdts/fvp-base-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi

@@ -29,9 +29,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-#if (ENABLE_RME == 1)
 		bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
-#endif
 	};
 
 	aliases {

diff --git a/fdts/stm32mp151a-prtt1a.dts b/fdts/stm32mp151a-prtt1a.dts
index 9742dcb..d1a8268 100644
--- a/fdts/stm32mp151a-prtt1a.dts
+++ b/fdts/stm32mp151a-prtt1a.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
  * Copyright (C) 2023, Protonic Holland - All Rights Reserved
- * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2024-2025, STMicroelectronics - All Rights Reserved
  * Author: David Jander <david@protonic.nl>
  */
 /dts-v1/;
@@ -71,29 +71,9 @@
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P
 		CLK_MCU_PLL3P
-		CLK_PLL12_HSE
-		CLK_PLL3_HSE
-		CLK_PLL4_HSE
 		CLK_RTC_LSI
 		CLK_MCO1_DISABLED
 		CLK_MCO2_DISABLED
-	>;
-
-	st,clkdiv = <
-		1 /*MPU*/
-		0 /*AXI*/
-		0 /*MCU*/
-		1 /*APB1*/
-		1 /*APB2*/
-		1 /*APB3*/
-		1 /*APB4*/
-		2 /*APB5*/
-		23 /*RTC*/
-		0 /*MCO1*/
-		0 /*MCO2*/
-	>;
-
-	st,pkcs = <
 		CLK_CKPER_HSE
 		CLK_FMC_ACLK
 		CLK_QSPI_ACLK
@@ -131,35 +111,76 @@
 		CLK_LPTIM45_LSI
 	>;
 
-	/* VCO = 1300.0 MHz => P = 650 (CPU) */
-	pll1: st,pll@0 {
-		compatible = "st,stm32mp1-pll";
-		reg = <0>;
-		cfg = <2 80 0 0 0 PQR(1,0,0)>;
-		frac = <0x800>;
+	st,clkdiv = <
+		DIV(DIV_MPU, 1)
+		DIV(DIV_AXI, 0)
+		DIV(DIV_MCU, 0)
+		DIV(DIV_APB1, 1)
+		DIV(DIV_APB2, 1)
+		DIV(DIV_APB3, 1)
+		DIV(DIV_APB4, 1)
+		DIV(DIV_APB5, 2)
+		DIV(DIV_RTC, 23)
+		DIV(DIV_MCO1, 0)
+		DIV(DIV_MCO2, 0)
+	>;
+
+	st,pll_vco {
+		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
+			src = <CLK_PLL12_HSE>;
+			divmn = <2 65>;
+			frac = <0x1400>;
+		};
+
+		pll3_vco_417Mhz: pll3-vco-417Mhz {
+			src = <CLK_PLL3_HSE>;
+			divmn = <1 33>;
+			frac = <0x1a04>;
+		};
+
+		pll4_vco_480Mhz: pll4-vco-480Mhz {
+			src = <CLK_PLL4_HSE>;
+			divmn = <1 39>;
+		};
 	};
 
 	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 	pll2: st,pll@1 {
 		compatible = "st,stm32mp1-pll";
 		reg = <1>;
-		cfg = <2 65 1 0 0 PQR(1,1,1)>;
-		frac = <0x1400>;
+
+		st,pll = <&pll2_cfg1>;
+
+		pll2_cfg1: pll2_cfg1 {
+			st,pll_vco = <&pll2_vco_1066Mhz>;
+			st,pll_div_pqr = <1 0 0>;
+		};
 	};
 
 	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 	pll3: st,pll@2 {
 		compatible = "st,stm32mp1-pll";
 		reg = <2>;
-		cfg = <1 33 1 16 36 PQR(1,1,1)>;
-		frac = <0x1a04>;
+
+		st,pll = <&pll3_cfg1>;
+
+		pll3_cfg1: pll3_cfg1 {
+			st,pll_vco = <&pll3_vco_417Mhz>;
+			st,pll_div_pqr = <1 16 36>;
+		};
 	};
 
 	/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
 	pll4: st,pll@3 {
 		compatible = "st,stm32mp1-pll";
 		reg = <3>;
-		cfg = <1 39 3 11 4 PQR(1,1,1)>;
+
+		st,pll = <&pll4_cfg1>;
+
+		pll4_cfg1: pll4_cfg1 {
+			st,pll_vco = <&pll4_vco_480Mhz>;
+			st,pll_div_pqr = <3 11 4>;
+		};
 	};
 };
 

diff --git a/fdts/stm32mp153c-lxa-fairytux2-fw-config.dts b/fdts/stm32mp153c-lxa-fairytux2-fw-config.dts
new file mode 100644
index 0000000..9ee09e9
--- /dev/null
+++ b/fdts/stm32mp153c-lxa-fairytux2-fw-config.dts

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE	0x20000000 /* 512MB */
+#include "stm32mp15-fw-config.dtsi"

diff --git a/fdts/stm32mp153c-lxa-fairytux2.dts b/fdts/stm32mp153c-lxa-fairytux2.dts
new file mode 100644
index 0000000..0729ae3
--- /dev/null
+++ b/fdts/stm32mp153c-lxa-fairytux2.dts

@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
+ * Copyright (C) 2024 Leonard Goehrs, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "stm32mp153.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-osd32.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+
+/ {
+	model = "Linux Automation GmbH FairyTux 2";
+	compatible = "lxa,stm32mp153c-fairytux-2", "oct,stm32mp15xx-osd32", "st,stm32mp153";
+
+	aliases {
+		mmc1 = &sdmmc2;
+		serial0 = &uart4;
+	};
+
+	chosen {
+		stdout-path = &uart4;
+	};
+
+	led-controller-0 {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "fairytux:green:status";
+			gpios = <&gpioa 13 1>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	reg_3v3: regulator_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&v3v3>;
+	};
+};
+
+&pinctrl {
+	fairytux_sdmmc2_d47_pins_b: fairytux-sdmmc2-d47-1 {
+		pins {
+			pinmux = <STM32_PINMUX('A', 8, AF9)>,  /* SDMMC2_D4 */
+				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+				 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+			slew-rate = <1>;
+			drive-push-pull;
+			bias-disable;
+		};
+	};
+};
+
+/* VCO = 624 MHz => P = 208, Q = 48, R = 104 */
+&pll3 {
+	st,pll = <&pll3_cfg2>;
+
+	pll3_cfg2: pll3-cfg2 {
+		st,pll_vco = <&pll3_vco_624Mhz>;
+		st,pll_div_pqr = <2 12 5>;
+	};
+};
+
+/* VCO = 750.0 MHz => P = 125, Q = 75, R = 62.5 */
+&pll4 {
+	st,pll = <&pll4_cfg2>;
+
+	pll4_cfg2: pll4-cfg2 {
+		st,pll_vco = <&pll4_vco_750Mhz>;
+		st,pll_div_pqr = <5 9 11>;
+	};
+};
+
+&rcc {
+	/* change parent clocks */
+	st,clksrc = <
+		CLK_MPU_PLL1P
+		CLK_AXI_PLL2P
+		CLK_MCU_PLL3P
+		CLK_RTC_LSE
+		CLK_MCO1_DISABLED
+		CLK_MCO2_DISABLED
+		CLK_CKPER_HSE
+		CLK_FMC_ACLK
+		CLK_QSPI_ACLK
+		CLK_ETH_PLL4P
+		CLK_SDMMC12_PLL3R
+		CLK_DSI_DSIPLL
+		CLK_STGEN_HSE
+		CLK_USBPHY_HSE
+		CLK_SPI2S1_PLL3Q
+		CLK_SPI2S23_PLL3Q
+		CLK_SPI45_HSI
+		CLK_SPI6_HSI
+		CLK_I2C46_HSI
+		CLK_SDMMC3_DISABLED
+		CLK_USBO_USBPHY
+		CLK_ADC_CKPER
+		CLK_CEC_DISABLED
+		CLK_I2C12_HSI
+		CLK_I2C35_HSI
+		CLK_UART1_HSI
+		CLK_UART24_HSI
+		CLK_UART35_HSI
+		CLK_UART6_HSI
+		CLK_UART78_HSI
+		CLK_SPDIF_DISABLED
+		CLK_FDCAN_PLL3Q
+		CLK_SAI1_DISABLED
+		CLK_SAI2_DISABLED
+		CLK_SAI3_DISABLED
+		CLK_SAI4_DISABLED
+		CLK_RNG1_LSI
+		CLK_RNG2_LSI
+		CLK_LPTIM1_PCLK1
+		CLK_LPTIM23_PCLK3
+		CLK_LPTIM45_LSE
+	>;
+
+	st,pll_vco {
+		pll3_vco_624Mhz: pll3-vco-624Mhz {
+			src = <CLK_PLL3_HSE>;
+			divmn = <1 51>;
+		};
+
+		pll4_vco_750Mhz: pll4-vco-750Mhz {
+			src = <CLK_PLL4_HSE>;
+			divmn = <3 124>;
+		};
+	};
+};
+
+&sdmmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2_b4_pins_a &fairytux_sdmmc2_d47_pins_b>;
+	bus-width = <8>;
+	mmc-ddr-3_3v;
+	no-1-8-v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	st,neg-edge;
+	vmmc-supply = <&reg_3v3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins_a>;
+	status = "okay";
+};

diff --git a/fdts/stm32mp157c-lxa-tac-fw-config.dts b/fdts/stm32mp157c-lxa-tac-fw-config.dts
new file mode 100644
index 0000000..9ee09e9
--- /dev/null
+++ b/fdts/stm32mp157c-lxa-tac-fw-config.dts

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE	0x20000000 /* 512MB */
+#include "stm32mp15-fw-config.dtsi"

diff --git a/fdts/stm32mp157c-lxa-tac.dts b/fdts/stm32mp157c-lxa-tac.dts
new file mode 100644
index 0000000..a9e894c
--- /dev/null
+++ b/fdts/stm32mp157c-lxa-tac.dts

@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-osd32.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+
+/ {
+	model = "Linux Automation Test Automation Controller (TAC)";
+	compatible = "lxa,stm32mp157c-tac", "oct,stm32mp15xx-osd32", "st,stm32mp157";
+
+	aliases {
+		mmc1 = &sdmmc2;
+		serial0 = &uart4;
+	};
+
+
+	chosen {
+		stdout-path = &uart4;
+	};
+
+	led-controller-0 {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "tac:green:user1";
+			gpios = <&gpiof 10 1>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	reg_3v3: regulator_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&v3v3>;
+	};
+};
+
+&pinctrl {
+	tac_sdmmc2_d47_pins_b: tac-sdmmc2-d47-1 {
+		pins {
+			pinmux = <STM32_PINMUX('A', 8, AF9)>,  /* SDMMC2_D4 */
+				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+				 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+			slew-rate = <1>;
+			drive-push-pull;
+			bias-disable;
+		};
+	};
+};
+
+/* VCO = 624 MHz => P = 208, Q = 48, R = 104 */
+&pll3 {
+	st,pll = <&pll3_cfg2>;
+
+	pll3_cfg2: pll3-cfg2 {
+		st,pll_vco = <&pll3_vco_624Mhz>;
+		st,pll_div_pqr = <2 12 5>;
+	};
+};
+
+/* VCO = 750.0 MHz => P = 125, Q = 75, R = 62.5 */
+&pll4 {
+	st,pll = <&pll4_cfg2>;
+
+	pll4_cfg2: pll4-cfg2 {
+		st,pll_vco = <&pll4_vco_750Mhz>;
+		st,pll_div_pqr = <5 9 11>;
+	};
+};
+
+&rcc {
+	/* change parent clocks */
+	st,clksrc = <
+		CLK_MPU_PLL1P
+		CLK_AXI_PLL2P
+		CLK_MCU_PLL3P
+		CLK_RTC_LSE
+		CLK_MCO1_DISABLED
+		CLK_MCO2_DISABLED
+		CLK_CKPER_HSE
+		CLK_FMC_ACLK
+		CLK_QSPI_ACLK
+		CLK_ETH_PLL4P
+		CLK_SDMMC12_PLL3R
+		CLK_DSI_DSIPLL
+		CLK_STGEN_HSE
+		CLK_USBPHY_HSE
+		CLK_SPI2S1_PLL3Q
+		CLK_SPI2S23_PLL3Q
+		CLK_SPI45_HSI
+		CLK_SPI6_HSI
+		CLK_I2C46_HSI
+		CLK_SDMMC3_DISABLED
+		CLK_USBO_USBPHY
+		CLK_ADC_CKPER
+		CLK_CEC_DISABLED
+		CLK_I2C12_HSI
+		CLK_I2C35_HSI
+		CLK_UART1_HSI
+		CLK_UART24_HSI
+		CLK_UART35_HSI
+		CLK_UART6_HSI
+		CLK_UART78_HSI
+		CLK_SPDIF_DISABLED
+		CLK_FDCAN_PLL3Q
+		CLK_SAI1_DISABLED
+		CLK_SAI2_DISABLED
+		CLK_SAI3_DISABLED
+		CLK_SAI4_DISABLED
+		CLK_RNG1_LSI
+		CLK_RNG2_LSI
+		CLK_LPTIM1_PCLK1
+		CLK_LPTIM23_PCLK3
+		CLK_LPTIM45_LSE
+	>;
+
+	st,pll_vco {
+		pll3_vco_624Mhz: pll3-vco-624Mhz {
+			src = <CLK_PLL3_HSE>;
+			divmn = <1 51>;
+		};
+
+		pll4_vco_750Mhz: pll4-vco-750Mhz {
+			src = <CLK_PLL4_HSE>;
+			divmn = <3 124>;
+		};
+	};
+};
+
+&sdmmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2_b4_pins_a &tac_sdmmc2_d47_pins_b>;
+	bus-width = <8>;
+	mmc-ddr-3_3v;
+	no-1-8-v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	st,neg-edge;
+	vmmc-supply = <&reg_3v3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins_a>;
+	status = "okay";
+};

diff --git a/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi b/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
index 674cb3d..223761f 100644
--- a/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
+++ b/fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi

@@ -1,21 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
- * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
  */
 
 /*
  * STM32MP25 DDR4 board configuration
  * DDR4 2x8Gbits 2x16bits 1200MHz
  *
- * version     1
- * package     1        Package selection (14x14 and 18x18)
- * memclk      1200MHz  (2x DFI clock) + range check
- * Speed_Bin   Worse    from JEDEC
- * width       32       32: full width / 16: half width
- * ranks       1        Single or Dual rank
- * density     8Gbits   (per 16bit device)
- * Addressing  RBC      row/bank interleaving
- * RDBI        No       Read DBI
+ * version      2
+ * package      1        Package selection (14x14 and 18x18)
+ * memclk       1200MHz  (2x DFI clock) + range check
+ * Speed_Bin    Worse    from JEDEC
+ * device_width 16       x16 by default
+ * width        32       32: full width / 16: half width
+ * density      8Gbits   (per device)
+ * Addressing   RBC      row/bank interleaving
+ * RDBI         No       Read DBI
  */
 
 #define DDR_MEM_NAME	"DDR4 2x8Gbits 2x16bits 1200MHz"
@@ -49,6 +49,7 @@
 #define DDR_INIT7 0x00000C16
 #define DDR_DIMMCTL 0x00000000
 #define DDR_RANKCTL 0x0000066F
+#define DDR_RANKCTL1 0x0000000D
 #define DDR_DRAMTMG0 0x11152815
 #define DDR_DRAMTMG1 0x0004051E
 #define DDR_DRAMTMG2 0x0609060D
@@ -94,31 +95,34 @@
 #define DDR_ADDRMAP11 0x00000007
 #define DDR_ODTCFG 0x06000618
 #define DDR_ODTMAP 0x00000001
-#define DDR_SCHED 0x00000F00
+#define DDR_SCHED 0x80001B00
 #define DDR_SCHED1 0x00000000
-#define DDR_PERFHPR1 0x0F000001
-#define DDR_PERFLPR1 0x0F000080
-#define DDR_PERFWR1 0x01000200
+#define DDR_PERFHPR1 0x04000200
+#define DDR_PERFLPR1 0x08000080
+#define DDR_PERFWR1 0x08000400
+#define DDR_SCHED3 0x04040208
+#define DDR_SCHED4 0x08400810
 #define DDR_DBG0 0x00000000
 #define DDR_DBG1 0x00000000
 #define DDR_DBGCMD 0x00000000
 #define DDR_SWCTL 0x00000000
+#define DDR_SWCTLSTATIC 0x00000000
 #define DDR_POISONCFG 0x00000000
 #define DDR_PCCFG 0x00000000
-#define DDR_PCFGR_0 0x00004100
+#define DDR_PCFGR_0 0x00704100
 #define DDR_PCFGW_0 0x00004100
 #define DDR_PCTRL_0 0x00000000
-#define DDR_PCFGQOS0_0 0x00200007
-#define DDR_PCFGQOS1_0 0x01000100
-#define DDR_PCFGWQOS0_0 0x00000C07
-#define DDR_PCFGWQOS1_0 0x02000200
-#define DDR_PCFGR_1 0x00004100
+#define DDR_PCFGQOS0_0 0x0021000C
+#define DDR_PCFGQOS1_0 0x01000080
+#define DDR_PCFGWQOS0_0 0x01100C07
+#define DDR_PCFGWQOS1_0 0x04000200
+#define DDR_PCFGR_1 0x00704100
 #define DDR_PCFGW_1 0x00004100
 #define DDR_PCTRL_1 0x00000000
-#define DDR_PCFGQOS0_1 0x00200007
-#define DDR_PCFGQOS1_1 0x01000180
-#define DDR_PCFGWQOS0_1 0x00000C07
-#define DDR_PCFGWQOS1_1 0x04000400
+#define DDR_PCFGQOS0_1 0x00100007
+#define DDR_PCFGQOS1_1 0x01000080
+#define DDR_PCFGWQOS0_1 0x01100C07
+#define DDR_PCFGWQOS1_1 0x04000200
 
 #define DDR_UIB_DRAMTYPE 0x00000000
 #define DDR_UIB_DIMMTYPE 0x00000004

diff --git a/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi
index 3917dc6..32424d0 100644
--- a/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi
+++ b/fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi

@@ -7,7 +7,7 @@
  * STM32MP25 LPDDR4 board configuration
  * LPDDR4 1x16Gbits 1x32bits 1200MHz
  *
- * version       1
+ * version       2
  * memclk        1200MHz  (2x DFI clock)
  * width         32       32: full width / 16: half width
  * ranks         1        Single or Dual rank
@@ -46,10 +46,11 @@
 #define DDR_INIT3 0x00C40024
 #define DDR_INIT4 0x00310008
 #define DDR_INIT5 0x00100004
-#define DDR_INIT6 0x00660050
-#define DDR_INIT7 0x00050019
+#define DDR_INIT6 0x00660047
+#define DDR_INIT7 0x00050047
 #define DDR_DIMMCTL 0x00000000
 #define DDR_RANKCTL 0x0000066F
+#define DDR_RANKCTL1 0x00000011
 #define DDR_DRAMTMG0 0x1718141A
 #define DDR_DRAMTMG1 0x00050524
 #define DDR_DRAMTMG2 0x060C1111
@@ -95,25 +96,28 @@
 #define DDR_ADDRMAP11 0x00000007
 #define DDR_ODTCFG 0x04000400
 #define DDR_ODTMAP 0x00000000
-#define DDR_SCHED 0x00001B00
+#define DDR_SCHED 0x80001B00
 #define DDR_SCHED1 0x00000000
 #define DDR_PERFHPR1 0x04000200
 #define DDR_PERFLPR1 0x08000080
 #define DDR_PERFWR1 0x08000400
+#define DDR_SCHED3 0x04040208
+#define DDR_SCHED4 0x08400810
 #define DDR_DBG0 0x00000000
 #define DDR_DBG1 0x00000000
 #define DDR_DBGCMD 0x00000000
 #define DDR_SWCTL 0x00000000
+#define DDR_SWCTLSTATIC 0x00000000
 #define DDR_POISONCFG 0x00000000
 #define DDR_PCCFG 0x00000000
-#define DDR_PCFGR_0 0x00004100
+#define DDR_PCFGR_0 0x00704100
 #define DDR_PCFGW_0 0x00004100
 #define DDR_PCTRL_0 0x00000000
 #define DDR_PCFGQOS0_0 0x0021000C
 #define DDR_PCFGQOS1_0 0x01000080
 #define DDR_PCFGWQOS0_0 0x01100C07
 #define DDR_PCFGWQOS1_0 0x04000200
-#define DDR_PCFGR_1 0x00004100
+#define DDR_PCFGR_1 0x00704100
 #define DDR_PCFGW_1 0x00004100
 #define DDR_PCTRL_1 0x00000000
 #define DDR_PCFGQOS0_1 0x00100007
@@ -148,8 +152,8 @@
 #define DDR_UIA_EXTCALRESVAL 0x00000000
 #define DDR_UIA_IS2TTIMING_0 0x00000000
 #define DDR_UIA_ODTIMPEDANCE_0 0x00000035
-#define DDR_UIA_TXIMPEDANCE_0 0x0000003C
-#define DDR_UIA_ATXIMPEDANCE 0x0000001E
+#define DDR_UIA_TXIMPEDANCE_0 0x00000028
+#define DDR_UIA_ATXIMPEDANCE 0x00000028
 #define DDR_UIA_MEMALERTEN 0x00000000
 #define DDR_UIA_MEMALERTPUIMP 0x00000000
 #define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
@@ -157,7 +161,7 @@
 #define DDR_UIA_DISDYNADRTRI_0 0x00000001
 #define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
 #define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
-#define DDR_UIA_WDQSEXT 0x00000000
+#define DDR_UIA_WDQSEXT 0x00000001
 #define DDR_UIA_CALINTERVAL 0x00000009
 #define DDR_UIA_CALONCE 0x00000000
 #define DDR_UIA_LP4RL_0 0x00000004
@@ -193,9 +197,9 @@
 #define DDR_UIM_MR5_0 0x00000000
 #define DDR_UIM_MR6_0 0x00000000
 #define DDR_UIM_MR11_0 0x00000066
-#define DDR_UIM_MR12_0 0x00000050
+#define DDR_UIM_MR12_0 0x00000047
 #define DDR_UIM_MR13_0 0x00000008
-#define DDR_UIM_MR14_0 0x00000019
+#define DDR_UIM_MR14_0 0x00000047
 #define DDR_UIM_MR22_0 0x00000005
 
 #define DDR_UIS_SWIZZLE_0 0x00000003

diff --git a/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi
index 53d6b7d..0df2a4d 100644
--- a/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi
+++ b/fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi

@@ -161,7 +161,7 @@
 #define DDR_UIA_DISDYNADRTRI_0 0x00000001
 #define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
 #define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
-#define DDR_UIA_WDQSEXT 0x00000000
+#define DDR_UIA_WDQSEXT 0x00000001
 #define DDR_UIA_CALINTERVAL 0x00000009
 #define DDR_UIA_CALONCE 0x00000000
 #define DDR_UIA_LP4RL_0 0x00000004

diff --git a/fdts/stm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi b/fdts/stm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi
new file mode 100644
index 0000000..4fafcd1
--- /dev/null
+++ b/fdts/stm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi

@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+/*
+ * STM32MP25 LPDDR4 board configuration
+ * LPDDR4 2x16Gbits 1x32bits 1200MHz
+ *
+ * version       2
+ * memclk        1200MHz  (2x DFI clock)
+ * width         32       32: full width / 16: half width
+ * ranks         2        Single or Dual rank
+ * density       16Gbits  (per 16bit channel)
+ * Addressing    RBC      row/bank interleaving
+ * DBI-RD        No       Read DBI
+ * DBI-WR        No       Write DBI
+ * RPST          1.5      Read postamble (ck)
+ * Per_bank_ref  Yes
+ */
+
+#define DDR_MEM_NAME	"LPDDR4 2x16Gbits 1x32bits 1200MHz"
+#define DDR_MEM_SPEED	1200000
+#define DDR_MEM_SIZE	0x100000000
+
+#define DDR_MSTR 0x03080020
+#define DDR_MRCTRL0 0x00000030
+#define DDR_MRCTRL1 0x00000000
+#define DDR_MRCTRL2 0x00000000
+#define DDR_DERATEEN 0x00000203
+#define DDR_DERATEINT 0x0124f800
+#define DDR_DERATECTL 0x00000000
+#define DDR_PWRCTL 0x00000100
+#define DDR_PWRTMG 0x00130001
+#define DDR_HWLPCTL 0x00000002
+#define DDR_RFSHCTL0 0x00210014
+#define DDR_RFSHCTL1 0x00000000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x81240072
+#define DDR_RFSHTMG1 0x00360000
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_CRCPARCTL1 0x00001000
+#define DDR_INIT0 0xc0020002
+#define DDR_INIT1 0x00010002
+#define DDR_INIT2 0x00000d00
+#define DDR_INIT3 0x00c40024
+#define DDR_INIT4 0x00310008
+#define DDR_INIT5 0x00100004
+#define DDR_INIT6 0x00660047
+#define DDR_INIT7 0x001d0047
+#define DDR_DIMMCTL 0x00000000
+#define DDR_RANKCTL 0x0000066f
+#define DDR_RANKCTL1 0x00000011
+#define DDR_DRAMTMG0 0x1718141a
+#define DDR_DRAMTMG1 0x00050524
+#define DDR_DRAMTMG2 0x060c1111
+#define DDR_DRAMTMG3 0x0090900c
+#define DDR_DRAMTMG4 0x0b04060b
+#define DDR_DRAMTMG5 0x02030909
+#define DDR_DRAMTMG6 0x02020007
+#define DDR_DRAMTMG7 0x00000302
+#define DDR_DRAMTMG8 0x03034405
+#define DDR_DRAMTMG9 0x0004040d
+#define DDR_DRAMTMG10 0x001c180a
+#define DDR_DRAMTMG11 0x440c021c
+#define DDR_DRAMTMG12 0x1a020010
+#define DDR_DRAMTMG13 0x0b100002
+#define DDR_DRAMTMG14 0x000000e9
+#define DDR_DRAMTMG15 0x00000000
+#define DDR_ZQCTL0 0x22580012
+#define DDR_ZQCTL1 0x01e0493e
+#define DDR_ZQCTL2 0x00000000
+#define DDR_DFITMG0 0x0395820a
+#define DDR_DFITMG1 0x000a0303
+#define DDR_DFILPCFG0 0x07f04111
+#define DDR_DFILPCFG1 0x000000f0
+#define DDR_DFIUPD0 0x4040000c
+#define DDR_DFIUPD1 0x0040007f
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIMISC 0x00000041
+#define DDR_DFITMG2 0x0000150a
+#define DDR_DFITMG3 0x00000000
+#define DDR_DBICTL 0x00000001
+#define DDR_DFIPHYMSTR 0x80000001
+#define DDR_ADDRMAP0 0x00000004
+#define DDR_ADDRMAP1 0x00090909
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001f1f
+#define DDR_ADDRMAP5 0x080f0808
+#define DDR_ADDRMAP6 0x08080808
+#define DDR_ADDRMAP7 0x00000f08
+#define DDR_ADDRMAP8 0x00003f3f
+#define DDR_ADDRMAP9 0x08080808
+#define DDR_ADDRMAP10 0x08080808
+#define DDR_ADDRMAP11 0x00000008
+#define DDR_ODTCFG 0x04000400
+#define DDR_ODTMAP 0x00000000
+#define DDR_SCHED 0x80001b00
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x04000200
+#define DDR_PERFLPR1 0x08000080
+#define DDR_PERFWR1 0x08000400
+#define DDR_SCHED3 0x04040208
+#define DDR_SCHED4 0x08400810
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_SWCTL 0x00000000
+#define DDR_SWCTLSTATIC 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000000
+#define DDR_PCFGR_0 0x00704100
+#define DDR_PCFGW_0 0x00004100
+#define DDR_PCTRL_0 0x00000000
+#define DDR_PCFGQOS0_0 0x0021000c
+#define DDR_PCFGQOS1_0 0x01000080
+#define DDR_PCFGWQOS0_0 0x01100c07
+#define DDR_PCFGWQOS1_0 0x04000200
+#define DDR_PCFGR_1 0x00704100
+#define DDR_PCFGW_1 0x00004100
+#define DDR_PCTRL_1 0x00000000
+#define DDR_PCFGQOS0_1 0x00100007
+#define DDR_PCFGQOS1_1 0x01000080
+#define DDR_PCFGWQOS0_1 0x01100c07
+#define DDR_PCFGWQOS1_1 0x04000200
+#define DDR_UIB_DRAMTYPE 0x00000002
+#define DDR_UIB_DIMMTYPE 0x00000004
+#define DDR_UIB_LP4XMODE 0x00000000
+#define DDR_UIB_NUMDBYTE 0x00000004
+#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000002
+#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000002
+#define DDR_UIB_NUMANIB 0x00000008
+#define DDR_UIB_NUMRANK_DFI0 0x00000002
+#define DDR_UIB_NUMRANK_DFI1 0x00000002
+#define DDR_UIB_DRAMDATAWIDTH 0x00000010
+#define DDR_UIB_NUMPSTATES 0x00000001
+#define DDR_UIB_FREQUENCY_0 0x000004b0
+#define DDR_UIB_PLLBYPASS_0 0x00000000
+#define DDR_UIB_DFIFREQRATIO_0 0x00000001
+#define DDR_UIB_DFI1EXISTS 0x00000001
+#define DDR_UIB_TRAIN2D 0x00000000
+#define DDR_UIB_HARDMACROVER 0x00000003
+#define DDR_UIB_READDBIENABLE_0 0x00000000
+#define DDR_UIB_DFIMODE 0x00000000
+#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000
+#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000001
+#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000001
+#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000
+#define DDR_UIA_EXTCALRESVAL 0x00000000
+#define DDR_UIA_IS2TTIMING_0 0x00000000
+#define DDR_UIA_ODTIMPEDANCE_0 0x00000035
+#define DDR_UIA_TXIMPEDANCE_0 0x00000028
+#define DDR_UIA_ATXIMPEDANCE 0x00000028
+#define DDR_UIA_MEMALERTEN 0x00000000
+#define DDR_UIA_MEMALERTPUIMP 0x00000000
+#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
+#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000
+#define DDR_UIA_DISDYNADRTRI_0 0x00000001
+#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000a
+#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
+#define DDR_UIA_WDQSEXT 0x00000001
+#define DDR_UIA_CALINTERVAL 0x00000009
+#define DDR_UIA_CALONCE 0x00000000
+#define DDR_UIA_LP4RL_0 0x00000004
+#define DDR_UIA_LP4WL_0 0x00000004
+#define DDR_UIA_LP4WLS_0 0x00000000
+#define DDR_UIA_LP4DBIRD_0 0x00000000
+#define DDR_UIA_LP4DBIWR_0 0x00000000
+#define DDR_UIA_LP4NWR_0 0x00000004
+#define DDR_UIA_LP4LOWPOWERDRV 0x00000000
+#define DDR_UIA_DRAMBYTESWAP 0x00000000
+#define DDR_UIA_RXENBACKOFF 0x00000000
+#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000
+#define DDR_UIA_SNPSUMCTLOPT 0x00000000
+#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000
+#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000f
+#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000f
+#define DDR_UIA_TXSLEWRISEAC 0x0000000f
+#define DDR_UIA_TXSLEWFALLAC 0x0000000f
+#define DDR_UIA_DISABLERETRAINING 0x00000000
+#define DDR_UIA_DISABLEPHYUPDATE 0x00000001
+#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000
+#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001
+#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000
+#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000
+#define DDR_UIA_PHYVREF 0x00000014
+#define DDR_UIA_SEQUENCECTRL_0 0x0000131f
+#define DDR_UIM_MR0_0 0x00000000
+#define DDR_UIM_MR1_0 0x000000c4
+#define DDR_UIM_MR2_0 0x00000024
+#define DDR_UIM_MR3_0 0x00000031
+#define DDR_UIM_MR4_0 0x00000000
+#define DDR_UIM_MR5_0 0x00000000
+#define DDR_UIM_MR6_0 0x00000000
+#define DDR_UIM_MR11_0 0x00000066
+#define DDR_UIM_MR12_0 0x00000047
+#define DDR_UIM_MR13_0 0x00000008
+#define DDR_UIM_MR14_0 0x00000047
+#define DDR_UIM_MR22_0 0x0000001d
+#define DDR_UIS_SWIZZLE_0 0x00000003
+#define DDR_UIS_SWIZZLE_1 0x00000002
+#define DDR_UIS_SWIZZLE_2 0x00000000
+#define DDR_UIS_SWIZZLE_3 0x00000001
+#define DDR_UIS_SWIZZLE_4 0x00000006
+#define DDR_UIS_SWIZZLE_5 0x00000007
+#define DDR_UIS_SWIZZLE_6 0x00000005
+#define DDR_UIS_SWIZZLE_7 0x00000004
+#define DDR_UIS_SWIZZLE_8 0x00000005
+#define DDR_UIS_SWIZZLE_9 0x00000004
+#define DDR_UIS_SWIZZLE_10 0x00000007
+#define DDR_UIS_SWIZZLE_11 0x00000006
+#define DDR_UIS_SWIZZLE_12 0x00000000
+#define DDR_UIS_SWIZZLE_13 0x00000003
+#define DDR_UIS_SWIZZLE_14 0x00000002
+#define DDR_UIS_SWIZZLE_15 0x00000001
+#define DDR_UIS_SWIZZLE_16 0x00000005
+#define DDR_UIS_SWIZZLE_17 0x00000007
+#define DDR_UIS_SWIZZLE_18 0x00000006
+#define DDR_UIS_SWIZZLE_19 0x00000004
+#define DDR_UIS_SWIZZLE_20 0x00000000
+#define DDR_UIS_SWIZZLE_21 0x00000001
+#define DDR_UIS_SWIZZLE_22 0x00000003
+#define DDR_UIS_SWIZZLE_23 0x00000002
+#define DDR_UIS_SWIZZLE_24 0x00000007
+#define DDR_UIS_SWIZZLE_25 0x00000004
+#define DDR_UIS_SWIZZLE_26 0x00000005
+#define DDR_UIS_SWIZZLE_27 0x00000006
+#define DDR_UIS_SWIZZLE_28 0x00000002
+#define DDR_UIS_SWIZZLE_29 0x00000003
+#define DDR_UIS_SWIZZLE_30 0x00000001
+#define DDR_UIS_SWIZZLE_31 0x00000000
+#define DDR_UIS_SWIZZLE_32 0x00000000
+#define DDR_UIS_SWIZZLE_33 0x00000001
+#define DDR_UIS_SWIZZLE_34 0x00000002
+#define DDR_UIS_SWIZZLE_35 0x00000003
+#define DDR_UIS_SWIZZLE_36 0x00000004
+#define DDR_UIS_SWIZZLE_37 0x00000005
+#define DDR_UIS_SWIZZLE_38 0x00000000
+#define DDR_UIS_SWIZZLE_39 0x00000001
+#define DDR_UIS_SWIZZLE_40 0x00000002
+#define DDR_UIS_SWIZZLE_41 0x00000003
+#define DDR_UIS_SWIZZLE_42 0x00000004
+#define DDR_UIS_SWIZZLE_43 0x00000005
+
+
+#include "stm32mp25-ddr.dtsi"

diff --git a/fdts/stm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi b/fdts/stm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi
new file mode 100644
index 0000000..7dc3b54
--- /dev/null
+++ b/fdts/stm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2025, Ultratronik GmbH
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author: Boerge Struempfel <boerge.struempfel@gmail.com> for Ultratronik GmbH.
+ */
+
+&clk_hse {
+	clock-frequency = <40000000>;
+};
+
+&clk_hsi {
+	clock-frequency = <64000000>;
+};
+
+&clk_lse {
+	clock-frequency = <32768>;
+};
+
+&clk_lsi {
+	clock-frequency = <32000>;
+};
+
+&clk_msi {
+	clock-frequency = <16000000>;
+};
+
+&rcc {
+	st,busclk = <
+		DIV_CFG(DIV_LSMCU, 1)
+		DIV_CFG(DIV_APB1, 0)
+		DIV_CFG(DIV_APB2, 0)
+		DIV_CFG(DIV_APB3, 0)
+		DIV_CFG(DIV_APB4, 0)
+		DIV_CFG(DIV_APBDBG, 0)
+	>;
+
+	st,flexgen = <
+		FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
+		FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
+		FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
+		FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
+		FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
+		FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0)
+		FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
+		FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
+		FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
+		FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
+		FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
+	>;
+
+	st,kerclk = <
+		MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
+		MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
+	>;
+
+	pll1: st,pll-1 {
+		st,pll = <&pll1_cfg_1200Mhz>;
+
+		pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
+			cfg = <30 1 1 1>;
+			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
+		};
+	};
+
+	pll2: st,pll-2 {
+		st,pll = <&pll2_cfg_600Mhz>;
+
+		pll2_cfg_600Mhz: pll2-cfg-600Mhz {
+			cfg = <30 1 1 2>;
+			src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
+		};
+	};
+
+	pll4: st,pll-4 {
+		st,pll = <&pll4_cfg_1200Mhz>;
+
+		pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
+			cfg = <30 1 1 1>;
+			src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
+		};
+	};
+
+	pll5: st,pll-5 {
+		st,pll = <&pll5_cfg_532Mhz>;
+
+		pll5_cfg_532Mhz: pll5-cfg-532Mhz {
+			cfg = <133 5 1 2>;
+			src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
+		};
+	};
+};

diff --git a/fdts/stm32mp257d-ultra-fly-sbc-fw-config.dts b/fdts/stm32mp257d-ultra-fly-sbc-fw-config.dts
new file mode 100644
index 0000000..0bcf0f0
--- /dev/null
+++ b/fdts/stm32mp257d-ultra-fly-sbc-fw-config.dts

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2025, Ultratronik GmbH
+ */
+
+#include "stm32mp25-fw-config.dtsi"
+#include "stm32mp257f-dk-ca35tdcid-fw-config.dtsi"

diff --git a/fdts/stm32mp257d-ultra-fly-sbc.dts b/fdts/stm32mp257d-ultra-fly-sbc.dts
new file mode 100644
index 0000000..2aaa38b
--- /dev/null
+++ b/fdts/stm32mp257d-ultra-fly-sbc.dts

@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2025, Ultratronik GmbH
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author: Boerge Struempfel <boerge.struempfel@gmail.com> for Ultratronik GmbH.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include "stm32mp257.dtsi"
+#include "stm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi"
+#include "stm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxak-pinctrl.dtsi"
+
+/ {
+	model = "Ultratronik Ultra Fly SBC based on STM32MP257D";
+	compatible = "st,stm32mp257d-ultra-fly-sbc", "st,stm32mp257";
+
+	aliases {
+		serial0 = &usart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x1 0x00000000>;
+	};
+};
+
+&ddr {
+	vdd1-supply = <&vdd1_ddr>;
+	vdd2-supply = <&vdd2_ddr>;
+	vddq-supply = <&vdd2_ddr>;
+};
+
+&i2c7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7_pins_a>;
+	i2c-scl-rising-time-ns = <185>;
+	i2c-scl-falling-time-ns = <20>;
+	clock-frequency = <400000>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	pmic2: stpmic@33 {
+		compatible = "st,stpmic2";
+		reg = <0x33>;
+		status = "okay";
+
+		regulators {
+			compatible = "st,stpmic2-regulators";
+
+			vddcpu: buck1 {
+				regulator-name = "vddcpu";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <910000>;
+				regulator-always-on;
+			};
+			vddcore: buck2 {
+				regulator-name = "vddcore";
+				regulator-min-microvolt = <820000>;
+				regulator-max-microvolt = <820000>;
+				regulator-always-on;
+			};
+			vddgpu: buck3 {
+				regulator-name = "vddgpu";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <900000>;
+				regulator-always-on;
+			};
+			vddio_pmic: buck4 {
+				regulator-name = "vddio_pmic";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+			v1v8: buck5 {
+				regulator-name = "v1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+			vdd2_ddr: buck6 {
+				regulator-name = "vdd2_ddr";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+			};
+			v3v3: buck7 {
+				regulator-name = "v3v3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+			vdda1v8_aon: ldo1 {
+				regulator-name = "vdda1v8_aon";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+			vdd_emmc: ldo2 {
+				regulator-name = "vdd_emmc";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+			vdd1_ddr: ldo3 {
+				regulator-name = "vdd1_ddr";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <1000>;
+			};
+			vdd3v3_usb: ldo4 {
+				regulator-name = "vdd3v3_usb";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+			vdd_sdcard: ldo7 {
+				regulator-name = "vdd_sdcard";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+			vddio_sdcard: ldo8 {
+				regulator-name = "vddio_sdcard";
+				st,regulator-bypass-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&pwr {
+	vddio1: vddio1 {
+		vddio1-supply = <&vddio_sdcard>;
+	};
+	vddio2: vddio2 {
+		vddio2-supply = <&v1v8>;
+	};
+	vddio3: vddio3 {
+		vddio3-supply = <&vddio_pmic>;
+	};
+	vddio4: vddio4 {
+		vddio4-supply = <&vddio_pmic>;
+	};
+	vddio: vddio {
+		vdd-supply = <&vddio_pmic>;
+	};
+};
+
+&sdmmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_b4_pins_a>;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&vdd_sdcard>;
+	vqmmc-supply = <&vddio1>;
+	status = "okay";
+};
+
+&sdmmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	st,neg-edge;
+	bus-width = <8>;
+	vmmc-supply = <&vdd_emmc>;
+	vqmmc-supply = <&vddio2>;
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usart1_pins_a>;
+	status = "okay";
+};
+
+&pinctrl {
+	usart1_pins_a: usart1-0 {
+		pins1 {
+			pinmux = <STM32_PINMUX('A', 3, AF6)>; /* USART1_TX */
+			bias-disable;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+		pins2 {
+			pinmux = <STM32_PINMUX('G', 15, AF6)>; /* USART1_RX */
+			bias-disable;
+		};
+	};
+};

diff --git a/fdts/tc2.dts b/fdts/tc2.dts
deleted file mode 100644
index fa16dcd..0000000
--- a/fdts/tc2.dts
+++ /dev/null

@@ -1,287 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <platform_def.h>
-
-#if TARGET_FLAVOUR_FVP
-#define LIT_CAPACITY			406
-#define MID_CAPACITY			912
-#else /* TARGET_FLAVOUR_FPGA */
-#define LIT_CAPACITY			280
-#define MID_CAPACITY			775
-/* this is an area optimized configuration of the big core */
-#define BIG2_CAPACITY			930
-#endif /* TARGET_FLAVOUR_FPGA */
-#define BIG_CAPACITY			1024
-
-#define MHU_TX_ADDR			45000000 /* hex */
-#define MHU_TX_COMPAT			"arm,mhuv2-tx","arm,primecell"
-#define MHU_TX_INT_NAME			"mhu_tx"
-
-#define MHU_RX_ADDR			45010000 /* hex */
-#define MHU_RX_COMPAT			"arm,mhuv2-rx","arm,primecell"
-#define MHU_OFFSET			0x1000
-#define MHU_MBOX_CELLS			2
-#define MHU_RX_INT_NUM			317
-#define MHU_RX_INT_NAME			"mhu_rx"
-
-#define LIT_CPU_PMU_COMPATIBLE		"arm,cortex-a520-pmu"
-#define MID_CPU_PMU_COMPATIBLE		"arm,cortex-a720-pmu"
-#define BIG_CPU_PMU_COMPATIBLE		"arm,cortex-x4-pmu"
-
-#define DSU_MPAM_ADDR			0x1 0x00010000 /* 0x1_0001_0000 */
-
-#define DPU_ADDR			2cc00000
-#define DPU_IRQ				69
-
-#define ETHERNET_ADDR			18000000
-#define ETHERNET_INT			109
-
-#define SYS_REGS_ADDR			1c010000
-
-#define MMC_ADDR			1c050000
-#define MMC_INT_0			107
-#define MMC_INT_1			108
-
-#define RTC_ADDR			1c170000
-#define RTC_INT				100
-
-#define KMI_0_ADDR			1c060000
-#define KMI_0_INT			197
-#define KMI_1_ADDR			1c070000
-#define KMI_1_INT			103
-
-#define VIRTIO_BLOCK_ADDR		1c130000
-#define VIRTIO_BLOCK_INT		204
-
-#include "tc-common.dtsi"
-#if TARGET_FLAVOUR_FVP
-#include "tc-fvp.dtsi"
-#else
-#include "tc-fpga.dtsi"
-#endif /* TARGET_FLAVOUR_FVP */
-#include "tc-base.dtsi"
-
-/ {
-	cpus {
-#if TARGET_FLAVOUR_FPGA
-		cpu-map {
-			cluster0 {
-				core8 {
-					cpu = <&CPU8>;
-				};
-				core9 {
-					cpu = <&CPU9>;
-				};
-				core10 {
-					cpu = <&CPU10>;
-				};
-				core11 {
-					cpu = <&CPU11>;
-				};
-				core12 {
-					cpu = <&CPU12>;
-				};
-				core13 {
-					cpu = <&CPU13>;
-				};
-			};
-		};
-#endif
-
-		CPU2:cpu@200 {
-			clocks = <&scmi_dvfs 0>;
-			capacity-dmips-mhz = <LIT_CAPACITY>;
-		};
-
-		CPU3:cpu@300 {
-			clocks = <&scmi_dvfs 0>;
-			capacity-dmips-mhz = <LIT_CAPACITY>;
-		};
-
-		CPU6:cpu@600 {
-			clocks = <&scmi_dvfs 1>;
-			capacity-dmips-mhz = <MID_CAPACITY>;
-		};
-
-		CPU7:cpu@700 {
-			clocks = <&scmi_dvfs 1>;
-			capacity-dmips-mhz = <MID_CAPACITY>;
-		};
-
-#if TARGET_FLAVOUR_FPGA
-		CPU8:cpu@800 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x800>;
-			enable-method = "psci";
-			clocks = <&scmi_dvfs 1>;
-			capacity-dmips-mhz = <MID_CAPACITY>;
-		};
-
-		CPU9:cpu@900 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x900>;
-			enable-method = "psci";
-			clocks = <&scmi_dvfs 2>;
-			capacity-dmips-mhz = <BIG2_CAPACITY>;
-		};
-
-		CPU10:cpu@A00 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0xA00>;
-			enable-method = "psci";
-			clocks = <&scmi_dvfs 2>;
-			capacity-dmips-mhz = <BIG2_CAPACITY>;
-		};
-
-		CPU11:cpu@B00 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0xB00>;
-			enable-method = "psci";
-			clocks = <&scmi_dvfs 2>;
-			capacity-dmips-mhz = <BIG2_CAPACITY>;
-		};
-
-		CPU12:cpu@C00 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0xC00>;
-			enable-method = "psci";
-			clocks = <&scmi_dvfs 3>;
-			capacity-dmips-mhz = <BIG_CAPACITY>;
-		};
-
-		CPU13:cpu@D00 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0xD00>;
-			enable-method = "psci";
-			clocks = <&scmi_dvfs 3>;
-			capacity-dmips-mhz = <BIG_CAPACITY>;
-		};
-#endif
-	};
-
-#if TARGET_FLAVOUR_FPGA
-	ete8 {
-		compatible = "arm,embedded-trace-extension";
-		cpu = <&CPU8>;
-	};
-
-	ete9 {
-		compatible = "arm,embedded-trace-extension";
-		cpu = <&CPU9>;
-	};
-
-	ete10 {
-		compatible = "arm,embedded-trace-extension";
-		cpu = <&CPU10>;
-	};
-
-	ete11 {
-		compatible = "arm,embedded-trace-extension";
-		cpu = <&CPU11>;
-	};
-
-	ete12 {
-		compatible = "arm,embedded-trace-extension";
-		cpu = <&CPU12>;
-	};
-
-	ete13 {
-		compatible = "arm,embedded-trace-extension";
-		cpu = <&CPU13>;
-	};
-#endif /* TARGET_FLAVOUR_FPGA */
-
-	cmn-pmu {
-		compatible = "arm,ci-700";
-		reg = <0x0 0x50000000 0x0 0x10000000>;
-		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;
-	};
-
-	mbox_db_rx: mhu@MHU_RX_ADDR {
-		arm,mhuv2-protocols = <0 1>;
-	};
-
-	mbox_db_tx: mhu@MHU_TX_ADDR {
-		arm,mhuv2-protocols = <0 1>;
-	};
-
-	firmware {
-		/*
-		 * TC2 does not have a P2A channel, but wiring one was needed to make Linux work
-		 * (by chance). At the time the SCMI driver did not support bidirectional
-		 * mailboxes so as a workaround, the A2P channel was wired for TX communication
-		 * and the synchronous replies would be read asyncrhonously as if coming from
-		 * the P2A channel, while being the actual A2P channel.
-		 *
-		 * This will not work with kernels > 5.15, but keep it around to keep TC2
-		 * working with its target kernel. Newer kernels will still work, but SCMI
-		 * won't as they check that the two regions are distinct.
-		 */
-		scmi {
-			mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>;
-			shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>;
-		};
-	};
-
-	gic: interrupt-controller@GIC_CTRL_ADDR {
-		ppi-partitions {
-			ppi_partition_little: interrupt-partition-0 {
-				affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
-			};
-
-#if TARGET_FLAVOUR_FVP
-			ppi_partition_mid: interrupt-partition-1 {
-				affinity = <&CPU4>, <&CPU5>, <&CPU6>;
-			};
-
-			ppi_partition_big: interrupt-partition-2 {
-				affinity = <&CPU7>;
-			};
-#elif TARGET_FLAVOUR_FPGA
-			ppi_partition_mid: interrupt-partition-1 {
-				affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
-			};
-
-			ppi_partition_big: interrupt-partition-2 {
-				affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
-			};
-#endif
-		};
-	};
-
-	spe-pmu-big {
-		status = "okay";
-	};
-
-	smmu_700: iommu@3f000000 {
-		status = "okay";
-	};
-
-	dp0: display@DPU_ADDR {
-#if TC_SCMI_PD_CTRL_EN
-		power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
-#endif
-		iommus = <&smmu_700 0x100>;
-	};
-
-	gpu: gpu@2d000000 {
-		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
-		interrupt-names = "JOB", "MMU", "GPU";
-		iommus = <&smmu_700 0x200>;
-	};
-};

diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index 243ac15..47a2659 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h

@@ -204,5 +204,9 @@
 static inline bool is_feat_ls64_accdata_present(void) { return false; }
 __attribute__((always_inline))
 static inline bool is_feat_mops_supported(void) { return false; }
+__attribute__((always_inline))
+static inline bool is_feat_bti_supported(void) { return false; }
+__attribute__((always_inline))
+static inline bool is_feat_pauth_supported(void) { return false; }
 
 #endif /* ARCH_FEATURES_H */

diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 67fdead..5506cb1 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h

@@ -91,6 +91,17 @@
 #define SERROR_EXCEPTION	0x180
 
 /*******************************************************************************
+ * Encodings for GICv5 EL3 system registers
+ ******************************************************************************/
+#define ICC_PPI_DOMAINR0_EL3	S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3	S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3	S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3	S3_6_C12_C8_7
+
+#define ICC_PPI_DOMAINR_FIELD_MASK		ULL(0x3)
+#define ICC_PPI_DOMAINR_COUNT			(32)
+
+/*******************************************************************************
  * Definitions for CPU system register interface to GICv3
  ******************************************************************************/
 #define ICC_IGRPEN1_EL1		S3_0_C12_C12_7
@@ -251,7 +262,7 @@
 #define ID_AA64DFR0_PMUVER_SHIFT	U(8)
 #define ID_AA64DFR0_PMUVER_MASK		U(0xf)
 #define ID_AA64DFR0_PMUVER_PMUV3	U(1)
-#define ID_AA64DFR0_PMUVER_PMUV3P8	U(8)
+#define ID_AA64DFR0_PMUVER_PMUV3P9	U(9)
 #define ID_AA64DFR0_PMUVER_IMP_DEF	U(0xf)
 
 /* ID_AA64DFR0_EL1.SEBEP definitions */
@@ -504,6 +515,11 @@
 #define SME2_IMPLEMENTED			ULL(0x2)
 #define SME_NOT_IMPLEMENTED			ULL(0x0)
 
+/* ID_AA64PFR2_EL1 definitions */
+#define ID_AA64PFR2_EL1				S3_0_C0_C4_2
+#define ID_AA64PFR2_EL1_GCIE_SHIFT		12
+#define ID_AA64PFR2_EL1_GCIE_MASK		ULL(0xf)
+
 /* ID_PFR1_EL1 definitions */
 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
@@ -606,6 +622,11 @@
 #define SCTLR_EPAN_BIT		(ULL(1) << 57)
 #define SCTLR_RESET_VAL		SCTLR_EL3_RES1
 
+#define SCTLR2_EnPACM_BIT	(ULL(1) << 7)
+
+/* SCTLR2 currently has no RES1 fields so reset to 0 */
+#define SCTLR2_RESET_VAL	ULL(0)
+
 /* CPACR_EL1 definitions */
 #define CPACR_EL1_FPEN(x)	((x) << 20)
 #define CPACR_EL1_FP_TRAP_EL0	UL(0x1)
@@ -615,7 +636,11 @@
 #define CPACR_EL1_SMEN_MASK	ULL(0x3)
 
 /* SCR definitions */
+#if ENABLE_FEAT_GCIE
+#define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
+#else
 #define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5))
+#endif
 #define SCR_NSE_SHIFT		U(62)
 #define SCR_FGTEN2_BIT		(UL(1) << 59)
 #define SCR_NSE_BIT		(ULL(1) << SCR_NSE_SHIFT)
@@ -664,6 +689,7 @@
 
 /* MDCR_EL3 definitions */
 #define MDCR_EBWE_BIT		(ULL(1) << 43)
+#define MDCR_EnPMS3_BIT		(ULL(1) << 42)
 #define MDCR_E3BREC_BIT		(ULL(1) << 38)
 #define MDCR_E3BREW_BIT		(ULL(1) << 37)
 #define MDCR_EnPMSN_BIT		(ULL(1) << 36)
@@ -696,7 +722,9 @@
 #define MDCR_NSPBE_BIT		(ULL(1) << 11)
 #define MDCR_TDOSA_BIT		(ULL(1) << 10)
 #define MDCR_TDA_BIT		(ULL(1) << 9)
+#define MDCR_EnPM2_BIT		(ULL(1) << 7)
 #define MDCR_TPM_BIT		(ULL(1) << 6)
+#define MDCR_RLTE_BIT		(ULL(1) << 0)
 #define MDCR_EL3_RESET_VAL	MDCR_MTPME_BIT
 
 /* MDCR_EL2 definitions */
@@ -854,6 +882,7 @@
 #define SPSR_PPEND_BIT		BIT(33)
 #define SPSR_EXLOCK_BIT_AARCH64	BIT_64(34)
 #define SPSR_NZCV		(SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT)
+#define SPSR_PACM_BIT_AARCH64	BIT_64(35)
 
 #define DISABLE_ALL_EXCEPTIONS \
 		(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
@@ -1530,6 +1559,7 @@
 /*******************************************************************************
  * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers
  ******************************************************************************/
+#define SCTLR2_EL3		S3_6_C1_C0_3
 #define SCTLR2_EL2		S3_4_C1_C0_3
 #define SCTLR2_EL1		S3_0_C1_C0_3
 
@@ -1546,7 +1576,7 @@
 /*******************************************************************************
  * Definitions for DynamicIQ Shared Unit registers
  ******************************************************************************/
-#define CLUSTERPWRDN_EL1	S3_0_c15_c3_6
+#define CLUSTERPWRDN_EL1	S3_0_C15_C3_6
 
 /*******************************************************************************
  * FEAT_FPMR - Floating point Mode Register

diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 43ff2cc..77355cd 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -146,6 +146,8 @@
  * +----------------------------+
  * |	FEAT_MOPS		|
  * +----------------------------+
+ * |	FEAT_PAUTH_LR		|
+ * +----------------------------+
  */
 
 __attribute__((always_inline))
@@ -176,9 +178,9 @@
 			((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
 			(ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
 
-/* PAUTH */
+/* FEAT_PAUTH: Pointer Authentication */
 __attribute__((always_inline))
-static inline bool is_armv8_3_pauth_present(void)
+static inline bool is_feat_pauth_present(void)
 {
 	uint64_t mask_id_aa64isar1 =
 		(ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
@@ -193,14 +195,45 @@
 	return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
 		is_feat_pacqarma3_present());
 }
+CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH)
+CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS)
+
+/*
+ * FEAT_PAUTH_LR
+ * This feature has a non-standard discovery method so define this function
+ * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This
+ * feature is enabled with ENABLE_PAUTH when present.
+ */
+__attribute__((always_inline))
+static inline bool is_feat_pauth_lr_present(void)
+{
+	/*
+	 * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more
+	 * of these is 0b0110 then the feature is present.
+	 *   1) id_aa64isr1_el1.api
+	 *   2) id_aa64isr1_el1.apa
+	 *   3) id_aa64isr2_el1.apa3
+	 */
+	if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) {
+		return true;
+	}
+	if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) {
+		return true;
+	}
+	if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) {
+		return true;
+	}
+	return false;
+}
+CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR)
 
 /* FEAT_TTST: Small translation tables */
 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
 			ID_AA64MMFR2_EL1_ST_MASK, 1U)
 
 /* FEAT_BTI: Branch target identification */
-CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
-			ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED)
+CREATE_FEATURE_FUNCS(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
+			ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED, ENABLE_BTI)
 
 /* FEAT_MTE2: Memory tagging extension */
 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
@@ -487,4 +520,11 @@
 
 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
 
+/*************************************************************************
+ * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface
+ * extension).
+ ************************************************************************/
+CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT,
+		     ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE)
+
 #endif /* ARCH_FEATURES_H */

diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 569182a..a59c531 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h

@@ -238,7 +238,14 @@
 /*******************************************************************************
  * Strip Pointer Authentication Code
  ******************************************************************************/
-DEFINE_SYSOP_PARAM_FUNC(xpaci)
+static inline u_register_t xpaci(u_register_t arg)
+{
+	__asm__ (".arch armv8.3-a\n"
+		 "xpaci %0\n"
+		 : "+r" (arg));
+
+	return arg;
+}
 
 void flush_dcache_range(uintptr_t addr, size_t size);
 void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
@@ -552,6 +559,12 @@
 DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
 DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
 
+/* GICv5 System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3)
+
 /* GICv3 System Registers */
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
@@ -725,6 +738,7 @@
 /* FEAT_SCTLR2 Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el3, SCTLR2_EL3)
 
 /* FEAT_LS64_ACCDATA Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(accdata_el1, ACCDATA_EL1)

diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index dce07d9..8f1651d 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S

@@ -230,7 +230,7 @@
 	 */
 	.macro	read reg:req
 #if ENABLE_BTI
-	bti	j
+	BTI	j
 #endif
 	mrs	x0, \reg
 	ret
@@ -241,7 +241,7 @@
 	 */
 	.macro	write reg:req
 #if ENABLE_BTI
-	bti	j
+	BTI	j
 #endif
 	msr	\reg, x1
 	ret
@@ -329,7 +329,7 @@
 	.endm
 
 	/*
-	* is_feat_sysreg128_present_asm - Set flags and reg if FEAT_SYSREG128
+	* is_feat_XYZ_present_asm - Set flags and reg if FEAT_XYZ
 	* is enabled at runtime.
 	*
 	* Arguments:
@@ -342,6 +342,20 @@
 	ands	\reg, \reg, #(ID_AA64ISAR2_SYSREG128_MASK << ID_AA64ISAR2_SYSREG128_SHIFT)
 	.endm
 
+	.macro is_feat_pauth_present_asm reg:req, clobber:req
+	mrs	\reg, ID_AA64ISAR1_EL1
+	mov_imm	\clobber, ((ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) \
+			 | (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) \
+			 | (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) \
+			 | (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT))
+	tst	\reg, \clobber
+	.endm
+
+	.macro is_feat_sctlr2_present_asm reg:req
+	mrs	\reg, ID_AA64MMFR3_EL1
+	ands	\reg, \reg, #(ID_AA64MMFR3_EL1_SCTLR2_MASK << ID_AA64MMFR3_EL1_SCTLR2_SHIFT)
+	.endm
+
 .macro call_reset_handler
 #if !(defined(IMAGE_BL2) && ENABLE_RME)
 	/* ---------------------------------------------------------------------

diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S
deleted file mode 100644
index 5db6831..0000000
--- a/include/arch/aarch64/el2_common_macros.S
+++ /dev/null

@@ -1,418 +0,0 @@
-/*
- * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef EL2_COMMON_MACROS_S
-#define EL2_COMMON_MACROS_S
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <context.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-
-#include <platform_def.h>
-
-	/*
-	 * Helper macro to initialise system registers at EL2.
-	 */
-	.macro el2_arch_init_common
-
-	/* ---------------------------------------------------------------------
-	 * SCTLR_EL2 has already been initialised - read current value before
-	 * modifying.
-	 *
-	 * SCTLR_EL2.I: Enable the instruction cache.
-	 *
-	 * SCTLR_EL2.SA: Enable Stack Alignment check. A SP alignment fault
-	 *  exception is generated if a load or store instruction executed at
-	 *  EL2 uses the SP as the base address and the SP is not aligned to a
-	 *  16-byte boundary.
-	 *
-	 * SCTLR_EL2.A: Enable Alignment fault checking. All instructions that
-	 *  load or store one or more registers have an alignment check that the
-	 *  address being accessed is aligned to the size of the data element(s)
-	 *  being accessed.
-	 * ---------------------------------------------------------------------
-	 */
-	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
-	mrs	x0, sctlr_el2
-	orr	x0, x0, x1
-	msr	sctlr_el2, x0
-	isb
-
-	/* ---------------------------------------------------------------------
-	 * Initialise HCR_EL2, setting all fields rather than relying on HW.
-	 * All fields are architecturally UNKNOWN on reset. The following fields
-	 * do not change during the TF lifetime. The remaining fields are set to
-	 * zero here but are updated ahead of transitioning to a lower EL in the
-	 * function cm_init_context_common().
-	 *
-	 * HCR_EL2.TWE: Set to zero so that execution of WFE instructions at
-	 *  EL2, EL1 and EL0 are not trapped to EL2.
-	 *
-	 * HCR_EL2.TWI: Set to zero so that execution of WFI instructions at
-	 *  EL2, EL1 and EL0 are not trapped to EL2.
-	 *
-	 * HCR_EL2.HCD: Set to zero to enable HVC calls at EL1 and above,
-	 *  from both Security states and both Execution states.
-	 *
-	 * HCR_EL2.TEA: Set to one to route External Aborts and SError
-	 * Interrupts to EL2 when executing at any EL.
-	 *
-	 * HCR_EL2.{API,APK}: For Armv8.3 pointer authentication feature,
-	 * disable traps to EL2 when accessing key registers or using
-	 * pointer authentication instructions from lower ELs.
-	 * ---------------------------------------------------------------------
-	 */
-	mov_imm	x0, ((HCR_RESET_VAL | HCR_TEA_BIT) \
-			& ~(HCR_TWE_BIT | HCR_TWI_BIT | HCR_HCD_BIT))
-#if CTX_INCLUDE_PAUTH_REGS
-	/*
-	 * If the pointer authentication registers are saved during world
-	 * switches, enable pointer authentication everywhere, as it is safe to
-	 * do so.
-	 */
-	orr	x0, x0, #(HCR_API_BIT | HCR_APK_BIT)
-#endif  /* CTX_INCLUDE_PAUTH_REGS */
-	msr	hcr_el2, x0
-
-	/* ---------------------------------------------------------------------
-	 * Initialise MDCR_EL2, setting all fields rather than relying on
-	 * hw. Some fields are architecturally UNKNOWN on reset.
-	 *
-	 * MDCR_EL2.TDOSA: Set to zero so that EL2 and EL2 System register
-	 *  access to the powerdown debug registers do not trap to EL2.
-	 *
-	 * MDCR_EL2.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
-	 *  debug registers, other than those registers that are controlled by
-	 *  MDCR_EL2.TDOSA.
-	 *
-	 * MDCR_EL2.TPM: Set to zero so that EL0, EL1, and EL2 System
-	 *  register accesses to all Performance Monitors registers do not trap
-	 *  to EL2.
-	 *
-	 * MDCR_EL2.HPMD: Set to zero so that event counting by the program-
-	 *  mable counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If
-	 *  ARMv8.2 Debug is not implemented this bit does not have any effect
-	 *  on the counters unless there is support for the implementation
-	 *  defined authentication interface
-	 *  ExternalSecureNoninvasiveDebugEnabled().
-	 * ---------------------------------------------------------------------
-	 */
-	mov_imm	x0, ((MDCR_EL2_RESET_VAL | \
-		      MDCR_SPD32(MDCR_SPD32_DISABLE)) \
-		      & ~(MDCR_EL2_HPMD_BIT | MDCR_TDOSA_BIT | \
-		      MDCR_TDA_BIT | MDCR_TPM_BIT))
-
-	msr	mdcr_el2, x0
-
-	/* ---------------------------------------------------------------------
-	 * Initialise PMCR_EL0 setting all fields rather than relying
-	 * on hw. Some fields are architecturally UNKNOWN on reset.
-	 *
-	 * PMCR_EL0.DP: Set to one so that the cycle counter,
-	 *  PMCCNTR_EL0 does not count when event counting is prohibited.
-	 *
-	 * PMCR_EL0.X: Set to zero to disable export of events.
-	 *
-	 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
-	 *  counts on every clock cycle.
-	 * ---------------------------------------------------------------------
-	 */
-	mov_imm	x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_DP_BIT) & \
-		    ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
-
-	msr	pmcr_el0, x0
-
-	/* ---------------------------------------------------------------------
-	 * Enable External Aborts and SError Interrupts now that the exception
-	 * vectors have been setup.
-	 * ---------------------------------------------------------------------
-	 */
-	msr	daifclr, #DAIF_ABT_BIT
-
-	/* ---------------------------------------------------------------------
-	 * Initialise CPTR_EL2, setting all fields rather than relying on hw.
-	 * All fields are architecturally UNKNOWN on reset.
-	 *
-	 * CPTR_EL2.TCPAC: Set to zero so that any accesses to CPACR_EL1 do
-	 * not trap to EL2.
-	 *
-	 * CPTR_EL2.TTA: Set to zero so that System register accesses to the
-	 *  trace registers do not trap to EL2.
-	 *
-	 * CPTR_EL2.TFP: Set to zero so that accesses to the V- or Z- registers
-	 *  by Advanced SIMD, floating-point or SVE instructions (if implemented)
-	 *  do not trap to EL2.
-	 */
-
-	mov_imm x0, (CPTR_EL2_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
-	msr	cptr_el2, x0
-
-	/*
-	 * If Data Independent Timing (DIT) functionality is implemented,
-	 * always enable DIT in EL2
-	 */
-	mrs	x0, id_aa64pfr0_el1
-	ubfx	x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
-	cmp	x0, #DIT_IMPLEMENTED
-	bne	1f
-	mov	x0, #DIT_BIT
-	msr	DIT, x0
-1:
-	.endm
-
-/* -----------------------------------------------------------------------------
- * This is the super set of actions that need to be performed during a cold boot
- * or a warm boot in EL2. This code is shared by BL1 and BL31.
- *
- * This macro will always perform reset handling, architectural initialisations
- * and stack setup. The rest of the actions are optional because they might not
- * be needed, depending on the context in which this macro is called. This is
- * why this macro is parameterised ; each parameter allows to enable/disable
- * some actions.
- *
- *  _init_sctlr:
- *	Whether the macro needs to initialise SCTLR_EL2, including configuring
- *      the endianness of data accesses.
- *
- *  _warm_boot_mailbox:
- *	Whether the macro needs to detect the type of boot (cold/warm). The
- *	detection is based on the platform entrypoint address : if it is zero
- *	then it is a cold boot, otherwise it is a warm boot. In the latter case,
- *	this macro jumps on the platform entrypoint address.
- *
- *  _secondary_cold_boot:
- *	Whether the macro needs to identify the CPU that is calling it: primary
- *	CPU or secondary CPU. The primary CPU will be allowed to carry on with
- *	the platform initialisations, while the secondaries will be put in a
- *	platform-specific state in the meantime.
- *
- *	If the caller knows this macro will only be called by the primary CPU
- *	then this parameter can be defined to 0 to skip this step.
- *
- * _init_memory:
- *	Whether the macro needs to initialise the memory.
- *
- * _init_c_runtime:
- *	Whether the macro needs to initialise the C runtime environment.
- *
- * _exception_vectors:
- *	Address of the exception vectors to program in the VBAR_EL2 register.
- *
- * _pie_fixup_size:
- *	Size of memory region to fixup Global Descriptor Table (GDT).
- *
- *	A non-zero value is expected when firmware needs GDT to be fixed-up.
- *
- * -----------------------------------------------------------------------------
- */
-	.macro el2_entrypoint_common					\
-		_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot,	\
-		_init_memory, _init_c_runtime, _exception_vectors,	\
-		_pie_fixup_size
-
-	.if \_init_sctlr
-		/* -------------------------------------------------------------
-		 * This is the initialisation of SCTLR_EL2 and so must ensure
-		 * that all fields are explicitly set rather than relying on hw.
-		 * Some fields reset to an IMPLEMENTATION DEFINED value and
-		 * others are architecturally UNKNOWN on reset.
-		 *
-		 * SCTLR.EE: Set the CPU endianness before doing anything that
-		 *  might involve memory reads or writes. Set to zero to select
-		 *  Little Endian.
-		 *
-		 * SCTLR_EL2.WXN: For the EL2 translation regime, this field can
-		 *  force all memory regions that are writeable to be treated as
-		 *  XN (Execute-never). Set to zero so that this control has no
-		 *  effect on memory access permissions.
-		 *
-		 * SCTLR_EL2.SA: Set to zero to disable Stack Alignment check.
-		 *
-		 * SCTLR_EL2.A: Set to zero to disable Alignment fault checking.
-		 *
-		 * SCTLR.DSSBS: Set to zero to disable speculation store bypass
-		 *  safe behaviour upon exception entry to EL2.
-		 * -------------------------------------------------------------
-		 */
-		mov_imm	x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
-				| SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
-		msr	sctlr_el2, x0
-		isb
-	.endif /* _init_sctlr */
-
-	.if \_warm_boot_mailbox
-		/* -------------------------------------------------------------
-		 * This code will be executed for both warm and cold resets.
-		 * Now is the time to distinguish between the two.
-		 * Query the platform entrypoint address and if it is not zero
-		 * then it means it is a warm boot so jump to this address.
-		 * -------------------------------------------------------------
-		 */
-		bl	plat_get_my_entrypoint
-		cbz	x0, do_cold_boot
-		br	x0
-
-	do_cold_boot:
-	.endif /* _warm_boot_mailbox */
-
-	.if \_pie_fixup_size
-#if ENABLE_PIE
-		/*
-		 * ------------------------------------------------------------
-		 * If PIE is enabled fixup the Global descriptor Table only
-		 * once during primary core cold boot path.
-		 *
-		 * Compile time base address, required for fixup, is calculated
-		 * using "pie_fixup" label present within first page.
-		 * ------------------------------------------------------------
-		 */
-	pie_fixup:
-		ldr	x0, =pie_fixup
-		and	x0, x0, #~(PAGE_SIZE_MASK)
-		mov_imm	x1, \_pie_fixup_size
-		add	x1, x1, x0
-		bl	fixup_gdt_reloc
-#endif /* ENABLE_PIE */
-	.endif /* _pie_fixup_size */
-
-	/* ---------------------------------------------------------------------
-	 * Set the exception vectors.
-	 * ---------------------------------------------------------------------
-	 */
-	adr	x0, \_exception_vectors
-	msr	vbar_el2, x0
-	isb
-
-	/* ---------------------------------------------------------------------
-	 * It is a cold boot.
-	 * Perform any processor specific actions upon reset e.g. cache, TLB
-	 * invalidations etc.
-	 * ---------------------------------------------------------------------
-	 */
-	call_reset_handler
-
-	el2_arch_init_common
-
-	.if \_secondary_cold_boot
-		/* -------------------------------------------------------------
-		 * Check if this is a primary or secondary CPU cold boot.
-		 * The primary CPU will set up the platform while the
-		 * secondaries are placed in a platform-specific state until the
-		 * primary CPU performs the necessary actions to bring them out
-		 * of that state and allows entry into the OS.
-		 * -------------------------------------------------------------
-		 */
-		bl	plat_is_my_cpu_primary
-		cbnz	w0, do_primary_cold_boot
-
-		/* This is a cold boot on a secondary CPU */
-		bl	plat_secondary_cold_boot_setup
-		/* plat_secondary_cold_boot_setup() is not supposed to return */
-		bl	el2_panic
-	do_primary_cold_boot:
-	.endif /* _secondary_cold_boot */
-
-	/* ---------------------------------------------------------------------
-	 * Initialize memory now. Secondary CPU initialization won't get to this
-	 * point.
-	 * ---------------------------------------------------------------------
-	 */
-
-	.if \_init_memory
-		bl	platform_mem_init
-	.endif /* _init_memory */
-
-	/* ---------------------------------------------------------------------
-	 * Init C runtime environment:
-	 *   - Zero-initialise the NOBITS sections. There are 2 of them:
-	 *       - the .bss section;
-	 *       - the coherent memory section (if any).
-	 *   - Relocate the data section from ROM to RAM, if required.
-	 * ---------------------------------------------------------------------
-	 */
-	.if \_init_c_runtime
-		adrp	x0, __BSS_START__
-		add	x0, x0, :lo12:__BSS_START__
-
-		adrp	x1, __BSS_END__
-		add	x1, x1, :lo12:__BSS_END__
-		sub	x1, x1, x0
-		bl	zeromem
-
-#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && \
-	RESET_TO_BL2 && BL2_IN_XIP_MEM)
-		adrp	x0, __DATA_RAM_START__
-		add	x0, x0, :lo12:__DATA_RAM_START__
-		adrp	x1, __DATA_ROM_START__
-		add	x1, x1, :lo12:__DATA_ROM_START__
-		adrp	x2, __DATA_RAM_END__
-		add	x2, x2, :lo12:__DATA_RAM_END__
-		sub	x2, x2, x0
-		bl	memcpy16
-#endif
-	.endif /* _init_c_runtime */
-
-	/* ---------------------------------------------------------------------
-	 * Use SP_EL0 for the C runtime stack.
-	 * ---------------------------------------------------------------------
-	 */
-	msr	spsel, #0
-
-	/* ---------------------------------------------------------------------
-	 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
-	 * the MMU is enabled. There is no risk of reading stale stack memory
-	 * after enabling the MMU as only the primary CPU is running at the
-	 * moment.
-	 * ---------------------------------------------------------------------
-	 */
-	bl	plat_set_my_stack
-
-#if STACK_PROTECTOR_ENABLED
-	.if \_init_c_runtime
-	bl	update_stack_protector_canary
-	.endif /* _init_c_runtime */
-#endif
-	.endm
-
-	.macro	apply_at_speculative_wa
-#if ERRATA_SPECULATIVE_AT
-	/*
-	 * This function expects x30 has been saved.
-	 * Also, save x29 which will be used in the called function.
-	 */
-	str	x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
-	bl	save_and_update_ptw_el1_sys_regs
-	ldr	x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
-#endif
-	.endm
-
-	.macro	restore_ptw_el1_sys_regs
-#if ERRATA_SPECULATIVE_AT
-	/* -----------------------------------------------------------
-	 * In case of ERRATA_SPECULATIVE_AT, must follow below order
-	 * to ensure that page table walk is not enabled until
-	 * restoration of all EL1 system registers. TCR_EL1 register
-	 * should be updated at the end which restores previous page
-	 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
-	 * ensures that CPU does below steps in order.
-	 *
-	 * 1. Ensure all other system registers are written before
-	 *    updating SCTLR_EL1 using ISB.
-	 * 2. Restore SCTLR_EL1 register.
-	 * 3. Ensure SCTLR_EL1 written successfully using ISB.
-	 * 4. Restore TCR_EL1 register.
-	 * -----------------------------------------------------------
-	 */
-	isb
-	ldp	x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1]
-	msr	sctlr_el1, x28
-	isb
-	msr	tcr_el1, x29
-#endif
-	.endm
-
-#endif /* EL2_COMMON_MACROS_S */

diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 2f2aeaf..ee5d8d9 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S

@@ -32,14 +32,29 @@
 	 *  load or store one or more registers have an alignment check that the
 	 *  address being accessed is aligned to the size of the data element(s)
 	 *  being accessed.
+	 *
+	 * SCTLR_EL3.BT: PAuth instructions are compatible with bti jc
 	 * ---------------------------------------------------------------------
 	 */
-	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+	mov_imm	x1, (SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
 	mrs	x0, sctlr_el3
+#if ENABLE_BTI
+	bic	x0, x0, #SCTLR_BT_BIT
+#endif
 	orr	x0, x0, x1
 	msr	sctlr_el3, x0
 	isb
 
+#if ENABLE_FEAT_SCTLR2
+#if ENABLE_FEAT_SCTLR2 > 1
+	is_feat_sctlr2_present_asm x1
+	beq	feat_sctlr2_not_supported\@
+#endif
+	mov	x1, #SCTLR2_RESET_VAL
+	msr	SCTLR2_EL3, x1
+feat_sctlr2_not_supported\@:
+#endif
+
 #ifdef IMAGE_BL31
 	/* ---------------------------------------------------------------------
 	 * Initialise the per-cpu cache pointer to the CPU.
@@ -50,7 +65,11 @@
 	 * ---------------------------------------------------------------------
 	 */
 	bl	plat_my_core_pos
-	bl	_cpu_data_by_index
+	/* index into the cpu_data */
+	mov_imm	x1, CPU_DATA_SIZE
+	mul	x0, x0, x1
+	adr_l	x1, percpu_data
+	add	x0, x0, x1
 	msr	tpidr_el3, x0
 #endif /* IMAGE_BL31 */
 

diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8b9dfb6..e228495 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,8 @@
 #define INTR_TYPE_S_EL1			U(0)
 #define INTR_TYPE_EL3			U(1)
 #define INTR_TYPE_NS			U(2)
-#define MAX_INTR_TYPES			U(3)
+#define INTR_TYPE_RL			U(3)
+#define MAX_INTR_TYPES			U(4)
 #define INTR_TYPE_INVAL			MAX_INTR_TYPES
 
 /* Interrupt routing modes */

diff --git a/include/bl32/tsp/platform_tsp.h b/include/bl32/tsp/platform_tsp.h
index fe8a2c9..81a1a40 100644
--- a/include/bl32/tsp/platform_tsp.h
+++ b/include/bl32/tsp/platform_tsp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,7 +10,8 @@
 /*******************************************************************************
  * Mandatory TSP functions (only if platform contains a TSP)
  ******************************************************************************/
-void tsp_early_platform_setup(void);
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3);
 void tsp_plat_arch_setup(void);
 void tsp_platform_setup(void);
 

diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h
index a63abf1..bc152e5 100644
--- a/include/bl32/tsp/tsp.h
+++ b/include/bl32/tsp/tsp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -106,7 +106,8 @@
 	tsp_vector_isn_t abort_yield_smc_entry;
 } tsp_vectors_t;
 
-void tsp_setup(void);
+void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+	       u_register_t arg3);
 
 #endif /* __ASSEMBLER__ */
 

diff --git a/include/common/asm_macros_common.S b/include/common/asm_macros_common.S
index fd0ea81..9172b55 100644
--- a/include/common/asm_macros_common.S
+++ b/include/common/asm_macros_common.S

@@ -7,6 +7,20 @@
 #define ASM_MACROS_COMMON_S
 
 	/*
+	 * Provide a wrapper for the "bti" instructions using the more
+	 * compatible "hint" encoding, otherwise older toolchains would reject
+	 * this when not compiled for a BTI capable machine (-march=armv8.5-a).
+	 */
+	.macro	BTI _targets
+	.ifc	\_targets, j
+	hint	#36
+	.endif
+	.ifc	\_targets, jc
+	hint	#38
+	.endif
+	.endm
+
+	/*
 	 * This macro is used to create a function label and place the
 	 * code into a separate text section based on the function name
 	 * to enable elimination of unused code during linking. It also adds
@@ -42,7 +56,7 @@
 	/* When Branch Target Identification is enabled, insert "bti jc"
 	 * instruction to enable indirect calls and branches
 	 */
-	 bti	jc
+	BTI	jc
 #endif
 	.endm
 

diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 2f065ec..db4bb9a 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -199,8 +199,6 @@
 void setup_page_tables(const struct mmap_region *bl_regions,
 			   const struct mmap_region *plat_regions);
 
-void bl_handle_pauth(void);
-
 #endif /*__ASSEMBLER__*/
 
 #endif /* BL_COMMON_H */

diff --git a/include/common/debug.h b/include/common/debug.h
index 0ddb400..6d7f2c6 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h

@@ -32,6 +32,7 @@
 #include <cdefs.h>
 #include <stdarg.h>
 #include <stdbool.h>
+#include <stdint.h>
 #include <stdio.h>
 
 #include <drivers/console.h>
@@ -135,7 +136,7 @@
 
 void tf_log(const char *fmt, ...) __printflike(1, 2);
 void tf_log_newline(const char log_fmt[2]);
-void tf_log_set_max_level(unsigned int log_level);
+void tf_log_set_max_level(uint32_t log_level);
 
 #endif /* __ASSEMBLER__ */
 #endif /* DEBUG_H */

diff --git a/include/common/feat_detect.h b/include/common/feat_detect.h
index b85e1ce..18e6c42 100644
--- a/include/common/feat_detect.h
+++ b/include/common/feat_detect.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,6 +14,5 @@
 #define FEAT_STATE_DISABLED		0
 #define FEAT_STATE_ALWAYS		1
 #define FEAT_STATE_CHECK		2
-#define FEAT_STATE_CHECK_ASYMMETRIC	3
 
 #endif /* FEAT_DETECT_H */

diff --git a/include/drivers/arm/css/css_scp.h b/include/drivers/arm/css/css_scp.h
index 5395546..c3ce1d6 100644
--- a/include/drivers/arm/css/css_scp.h
+++ b/include/drivers/arm/css/css_scp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,8 +45,11 @@
 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
 
+#if !TRANSFER_LIST
 CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
 CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
+#endif /* !TRANSFER_LIST */
+
 #endif
 
 #endif /* CSS_SCP_H */

diff --git a/include/drivers/arm/css/dsu.h b/include/drivers/arm/css/dsu.h
deleted file mode 100644
index 4d7822b..0000000
--- a/include/drivers/arm/css/dsu.h
+++ /dev/null

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DSU_H
-#define DSU_H
-
-#define PMCR_N_MAX			0x1f
-
-#define save_pmu_reg(state, reg) state->reg = read_##reg()
-
-#define restore_pmu_reg(context, reg) write_##reg(context->reg)
-
-typedef struct cluster_pmu_state{
-	uint64_t clusterpmcr;
-	uint64_t clusterpmcntenset;
-	uint64_t clusterpmccntr;
-	uint64_t clusterpmovsset;
-	uint64_t clusterpmselr;
-	uint64_t clusterpmsevtyper;
-	uint64_t counter_val[PMCR_N_MAX];
-	uint64_t counter_type[PMCR_N_MAX];
-} cluster_pmu_state_t;
-
-static inline unsigned int read_cluster_eventctr_num(void)
-{
-	return ((read_clusterpmcr() >> CLUSTERPMCR_N_SHIFT) &
-			CLUSTERPMCR_N_MASK);
-}
-
-
-void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
-
-void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
-
-void cluster_on_dsu_pmu_context_restore(void);
-
-void cluster_off_dsu_pmu_context_save(void);
-
-#endif /* DSU_H */

diff --git a/include/drivers/arm/dsu.h b/include/drivers/arm/dsu.h
new file mode 100644
index 0000000..492babd
--- /dev/null
+++ b/include/drivers/arm/dsu.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DSU_H
+#define DSU_H
+
+#if defined(__aarch64__)
+#include <dsu_def.h>
+
+/*
+ * Power Control Registers enable bit of Auxilary Control register.
+ * ACTLR_EL3_PWREN_BIT definition is same among cores like Cortex-X925,
+ * Cortex-X4, Cortex-A520, Cortex-A725 that are used in a cluster
+ * with DSU.
+ */
+#define ACTLR_EL3_PWREN_BIT		BIT(7)
+
+#define PMCR_N_MAX			0x1f
+
+#define save_pmu_reg(state, reg) state->reg = read_##reg()
+
+#define restore_pmu_reg(context, reg) write_##reg(context->reg)
+
+typedef struct cluster_pmu_state {
+	uint64_t clusterpmcr;
+	uint64_t clusterpmcntenset;
+	uint64_t clusterpmccntr;
+	uint64_t clusterpmovsset;
+	uint64_t clusterpmselr;
+	uint64_t clusterpmsevtyper;
+	uint64_t counter_val[PMCR_N_MAX];
+	uint64_t counter_type[PMCR_N_MAX];
+} cluster_pmu_state_t;
+
+typedef struct dsu_driver_data {
+	uint8_t clusterpwrdwn_pwrdn;
+	uint8_t clusterpwrdwn_memret;
+	uint8_t clusterpwrctlr_cachepwr;
+	uint8_t clusterpwrctlr_funcret;
+} dsu_driver_data_t;
+
+extern const dsu_driver_data_t plat_dsu_data;
+
+static inline unsigned int read_cluster_eventctr_num(void)
+{
+	return ((read_clusterpmcr() >> CLUSTERPMCR_N_SHIFT) &
+			CLUSTERPMCR_N_MASK);
+}
+
+void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
+
+void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
+
+void cluster_on_dsu_pmu_context_restore(void);
+
+void cluster_off_dsu_pmu_context_save(void);
+
+void dsu_driver_init(const dsu_driver_data_t *data);
+#endif
+#endif /* DSU_H */

diff --git a/include/drivers/arm/gic.h b/include/drivers/arm/gic.h
new file mode 100644
index 0000000..e98737a
--- /dev/null
+++ b/include/drivers/arm/gic.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef GIC_H
+#define GIC_H
+/* the function names conflict with some platform implementations. */
+#if USE_GIC_DRIVER
+void gic_init(unsigned int cpu_idx);
+void gic_cpuif_enable(unsigned int cpu_idx);
+void gic_cpuif_disable(unsigned int cpu_idx);
+void gic_pcpu_off(unsigned int cpu_idx);
+void gic_pcpu_init(unsigned int cpu_idx);
+void gic_save(void);
+void gic_resume(void);
+#endif
+#endif /* GIC_H */

diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
new file mode 100644
index 0000000..d01d24b
--- /dev/null
+++ b/include/drivers/arm/gicv5.h

@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GICV5_H
+#define GICV5_H
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/mmio.h>
+#endif
+
+#include <lib/utils_def.h>
+
+/* Interrupt Domain definitions */
+#define INTDMN_S				0
+#define INTDMN_NS				1
+#define INTDMN_EL3				2
+#define INTDMN_RL				3
+
+/* Trigger modes */
+#define TM_EDGE					0
+#define TM_LEVEL				1
+
+/* Architected PPI numbers */
+#define PPI_TRBIRQ				31
+#define PPI_CNTP				30
+#define PPI_CNTPS				29
+#define PPI_CNTHV				28
+#define PPI_CNTV				27
+#define PPI_CNTHP				26
+#define PPI_GICMNT				25
+#define PPI_CTIIRQ				24
+#define PPI_PMUIRQ				23
+#define PPI_COMMIRQ				22
+#define PPI_PMBIRQ				21
+#define PPI_CNTHPS				20
+#define PPI_CNTHVS				19
+#define PPI_DB_NS				2
+#define PPI_DB_RL				1
+#define PPI_DB_S				0
+
+/* Register fields common to all IRI components.
+ * They have the same name and offset in every config frame */
+#define IRI_AIDR_COMPONENT_SHIFT		8
+#define IRI_AIDR_COMPONENT_WIDTH		4
+#define IRI_AIDR_COMPONENT_IRS			0
+#define IRI_AIDR_COMPONENT_ITS			1
+#define IRI_AIDR_COMPONENT_IWB			2
+#define IRI_AIDR_ARCH_MAJOR_SHIFT		4
+#define IRI_AIDR_ARCH_MAJOR_WIDTH		4
+#define IRI_AIDR_ARCH_MAJOR_V5			0
+#define IRI_AIDR_ARCH_MINOR_SHIFT		0
+#define IRI_AIDR_ARCH_MINOR_WIDTH		4
+#define IRI_AIDR_ARCH_MINOR_P0			0
+
+/* IRS register fields */
+#define IRS_IDR6_SPI_IRS_RANGE_SHIFT		0
+#define IRS_IDR6_SPI_IRS_RANGE_WIDTH		24
+#define IRS_IDR7_SPI_BASE_SHIFT			0
+#define IRS_IDR7_SPI_BASE_WIDTH			24
+
+#define IRS_SPI_STATUSR_IDLE_BIT		BIT(0)
+#define IRS_SPI_STATUSR_V_BIT			BIT(1)
+
+/* IWB register fields */
+#define IWB_IDR0_DOMAINS_SHIFT			11
+#define IWB_IDR0_DOMAINS_WIDTH			4
+#define IWB_IDR0_IWRANGE_SHIFT			0
+#define IWB_IDR0_IWRANGE_WIDTH			10
+
+#define IWB_CR0_IWBEN_BIT			BIT(0)
+#define IWB_CR0_IDLE_BIT			BIT(1)
+
+#define IWB_WENABLE_STATUSR_IDLE_BIT		BIT(0)
+#define IWB_WDOMAIN_STATUSR_IDLE_BIT		BIT(0)
+
+#define IWB_WDOMAINR_DOMAINX_MASK		0x3
+
+#ifndef __ASSEMBLER__
+
+#define _PPI_FIELD_SHIFT(_REG, _ppi_id)						\
+	((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT))
+
+#define write_icc_ppi_domainr(_var, _ppi_id, _value)				\
+	do {									\
+		_var |=  (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\
+	} while (false)
+
+
+#define DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset)				\
+static inline void write_##_name(uintptr_t base, uint32_t val)			\
+{										\
+	mmio_write_32(base + _offset, val);					\
+}
+
+#define DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset)				\
+static inline uint32_t read_##_name(uintptr_t base)				\
+{										\
+	return mmio_read_32(base + _offset);					\
+}
+
+#define DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)			\
+static inline void write_##_name(uintptr_t base, uint16_t index, uint32_t val)	\
+{										\
+	mmio_write_32(base + _offset + (index * sizeof(uint32_t)), val);	\
+}
+
+#define DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset)			\
+static inline uint32_t read_##_name(uintptr_t base, uint16_t index)		\
+{										\
+	return mmio_read_32(base + _offset + (index * sizeof(uint32_t)));	\
+}
+
+#define DEFINE_GICV5_MMIO_RW_FUNCS(_name, _offset)				\
+	DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset)				\
+	DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset)
+
+#define DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(_name, _offset)			\
+	DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset)			\
+	DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iri_aidr,			0x44)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_idr0,			0x00)
+DEFINE_GICV5_MMIO_RW_FUNCS( iwb_cr0,			0x80)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wenable_statusr,	0xc0)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wdomain_statusr,	0xc4)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wenabler,	0x2000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wtmr,		0x4000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wdomainr,	0x6000)
+
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr6,			0x0018)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr7,			0x001c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_selr,		0x0108)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_domainr,		0x010c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_cfgr,		0x0114)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_spi_statusr,		0x0118)
+
+#define WAIT_FOR_IDLE(base, reg, reg_up)					\
+	do {									\
+		while ((read_##reg(base) & reg_up##_IDLE_BIT) == 0U) {}		\
+	} while (0)
+
+/* wait for IDLE but also check the V bit was set */
+#define WAIT_FOR_VIDLE(base, reg, reg_up)					\
+	do {									\
+		uint32_t val;							\
+		while (((val = read_##reg(base)) & reg_up##_IDLE_BIT) == 0U) {}	\
+		assert((val & reg##_V_BIT) != 0U);				\
+	} while (0)
+
+#define WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base)					\
+	WAIT_FOR_IDLE(base, irs_spi_statusr, IRS_SPI_STATUSR)
+
+#define WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base)					\
+	WAIT_FOR_IDLE(base, iwb_wenable_statusr, IWB_WENABLE_STATUSR)
+#define WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base)					\
+	WAIT_FOR_IDLE(base, iwb_wdomain_statusr, IWB_WDOMAIN_STATUSR)
+#define WAIT_FOR_IDLE_IWB_CR0(base)						\
+	WAIT_FOR_IDLE(base, iwb_cr0, IWB_CR0)
+
+#define WIRE_PROP_DESC(_id, _domain, _tm) \
+	{ \
+		.id = (_id), \
+		.domain = (_domain), \
+		.tm = (_tm), \
+	}
+
+struct gicv5_wire_props {
+	/* continuous wire ID as seen by the attached component */
+	uint32_t id;
+	/* use the INTDMN_XYZ macros */
+	uint8_t domain:2;
+	/* use the TM_XYZ (eg. TM_EDGE) macros */
+	uint8_t tm:1;
+};
+
+/* to describe every IRS in the system */
+struct gicv5_irs {
+	/* mapped device nGnRnE by the platform*/
+	uintptr_t el3_config_frame;
+	struct gicv5_wire_props *spis;
+	uint32_t num_spis;
+};
+
+/*
+ * to describe every IWB in the system where EL3 is the MPPAS. IWBs that have
+ * another world as an MPPAS need not be included
+ */
+struct gicv5_iwb {
+	/* mapped device nGnRnE by the platform*/
+	uintptr_t config_frame;
+	struct gicv5_wire_props *wires;
+	uint32_t num_wires;
+};
+
+struct gicv5_driver_data {
+	struct gicv5_irs *irss;
+	struct gicv5_iwb *iwbs;
+	uint32_t num_irss;
+	uint32_t num_iwbs;
+};
+
+extern const struct gicv5_driver_data plat_gicv5_driver_data;
+
+void gicv5_driver_init();
+uint8_t gicv5_get_pending_interrupt_type(void);
+bool gicv5_has_interrupt_type(unsigned int type);
+void gicv5_enable_ppis();
+#endif /* __ASSEMBLER__ */
+#endif /* GICV5_H */

diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h
index 37da56f..5a36e26 100644
--- a/include/drivers/arm/smmu_v3.h
+++ b/include/drivers/arm/smmu_v3.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -58,6 +58,8 @@
 
 /* SMMU_ROOT_IDR0 register fields */
 #define SMMU_ROOT_IDR0_ROOT_IMPL	(1UL << 0)
+#define SMMU_ROOT_IDR0_BA_REALM_SHIFT	22U
+#define SMMU_ROOT_IDR0_BA_REALM_MASK	GENMASK_32(31U, SMMU_ROOT_IDR0_BA_REALM_SHIFT)
 
 /* SMMU_ROOT_CR0 register fields */
 #define SMMU_ROOT_CR0_GPCEN		(1UL << 1)

diff --git a/include/drivers/auth/auth_util.h b/include/drivers/auth/auth_util.h
new file mode 100644
index 0000000..546669f
--- /dev/null
+++ b/include/drivers/auth/auth_util.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AUTH_UTIL_H
+#define AUTH_UTIL_H
+
+const char *get_current_pk_oid(void);
+void set_current_pk_oid(const char *pk_oid);
+
+#endif /* AUTH_UTIL_H */

diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
index bec19da..fd49b2d 100644
--- a/include/drivers/auth/crypto_mod.h
+++ b/include/drivers/auth/crypto_mod.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -79,6 +79,12 @@
 			    unsigned int key_flags, const void *iv,
 			    unsigned int iv_len, const void *tag,
 			    unsigned int tag_len);
+
+	/*
+	 * Finish using the crypto library,
+	 * anything to be done to wrap up crypto usage done here.
+	 */
+	void (*finish)(void);
 } crypto_lib_desc_t;
 
 /* Public functions */
@@ -118,9 +124,17 @@
 int crypto_mod_convert_pk(void *full_pk_ptr, unsigned int full_pk_len,
 			  void **hashed_pk_ptr, unsigned int *hashed_pk_len);
 
+#if CRYPTO_SUPPORT
+void crypto_mod_finish(void);
+#else
+static inline void crypto_mod_finish(void)
+{
+}
+#endif /* CRYPTO_SUPPORT */
+
 /* Macro to register a cryptographic library */
 #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
-			    _calc_hash, _auth_decrypt, _convert_pk) \
+			    _calc_hash, _auth_decrypt, _convert_pk, _finish) \
 	const crypto_lib_desc_t crypto_lib_desc = { \
 		.name = _name, \
 		.init = _init, \
@@ -128,7 +142,8 @@
 		.verify_hash = _verify_hash, \
 		.calc_hash = _calc_hash, \
 		.auth_decrypt = _auth_decrypt, \
-		.convert_pk = _convert_pk \
+		.convert_pk = _convert_pk, \
+		.finish = _finish \
 	}
 
 extern const crypto_lib_desc_t crypto_lib_desc;

diff --git a/include/drivers/auth/mbedtls/default_mbedtls_config.h b/include/drivers/auth/mbedtls/default_mbedtls_config.h
index 23daf24..e097eb9 100644
--- a/include/drivers/auth/mbedtls/default_mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/default_mbedtls_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,9 +11,9 @@
  */
 
 /*
- * This file is compatible with versions >= 3.6.2
+ * This file is compatible with versions >= 3.6.3
  */
-#define MBEDTLS_CONFIG_VERSION         0x03060200
+#define MBEDTLS_CONFIG_VERSION         0x03060300
 
 /*
  * Key algorithms currently supported on mbed TLS libraries

diff --git a/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
index 00b1f34..c88f21c 100644
--- a/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Ltd. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Ltd. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,11 +27,15 @@
 #define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
 
 /*
- * Override heap size for PSA Crypto when RSA key size > 2048.
+ * Override heap size for PSA Crypto for RSA keys.
  */
-#if TF_MBEDTLS_USE_RSA && TF_MBEDTLS_KEY_SIZE > 2048
-#undef TF_MBEDTLS_HEAP_SIZE
-#define TF_MBEDTLS_HEAP_SIZE        U(12 * 1024)
+#if TF_MBEDTLS_USE_RSA
+  #undef TF_MBEDTLS_HEAP_SIZE
+  #if TF_MBEDTLS_KEY_SIZE > 2048
+    #define TF_MBEDTLS_HEAP_SIZE    U(12 * 1024)
+  #elif TF_MBEDTLS_KEY_SIZE <= 2048
+    #define TF_MBEDTLS_HEAP_SIZE    U(9 * 1024)
+  #endif
 #endif
 
 #endif /* PSA_MBEDTLS_CONFIG_H */

diff --git a/include/drivers/auth/mbedtls/mbedtls_psa_crypto.h b/include/drivers/auth/mbedtls/mbedtls_psa_crypto.h
new file mode 100644
index 0000000..85c854d
--- /dev/null
+++ b/include/drivers/auth/mbedtls/mbedtls_psa_crypto.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MBEDTLS_PSA_CRYPTO_H
+#define MBEDTLS_PSA_CRYPTO_H
+
+#define MAX_CACHED_KEYS				10
+
+typedef struct key_cache_s {
+	const char *pk_oid;			/* Store OID of the public key */
+	psa_key_id_t key_id;			/* PSA key ID */
+	psa_algorithm_t psa_alg;		/* PSA Algorithm associated with the key */
+	psa_key_attributes_t psa_key_attr;	/* PSA key attributes associated with the key */
+	bool valid;				/* Whether this cache entry is valid */
+} key_cache_t;
+
+#endif /* MBEDTLS_PSA_CRYPTO_H */

diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index f8d616f..895a705 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h

@@ -342,7 +342,6 @@
 /* MMC Peripheral Definition */
 #define SOCFPGA_MMC_BLOCK_MASK			(SOCFPGA_MMC_BLOCK_SIZE - U(1))
 #define SOCFPGA_MMC_BOOT_CLK_RATE		(400 * 1000)
-#define MMC_RESPONSE_NONE			0
 #define SDHC_CDNS_SRS03_VALUE			0x01020013
 
 /* Value randomly chosen for eMMC RCA, it should be > 1 */

diff --git a/include/drivers/console.h b/include/drivers/console.h
index fa4eb94..0de2c99 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h

@@ -27,7 +27,7 @@
 #define CONSOLE_FLAG_RUNTIME		(U(1) << 1)
 #define CONSOLE_FLAG_CRASH		(U(1) << 2)
 /* Bits 3 to 7 reserved for additional scopes in future expansion. */
-#define CONSOLE_FLAG_SCOPE_MASK		((U(1) << 8) - 1)
+#define CONSOLE_FLAG_SCOPE_MASK		GENMASK(7, 0)
 /* Bits 8 to 31 for non-scope use. */
 #define CONSOLE_FLAG_TRANSLATE_CRLF	(U(1) << 8)
 

diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h
index e9fdfb7..0ef6831 100644
--- a/include/drivers/delay_timer.h
+++ b/include/drivers/delay_timer.h

@@ -21,7 +21,7 @@
  * the clock period in microseconds.
  ********************************************************************/
 
-typedef struct timer_ops {
+typedef struct timer_operation {
 	uint32_t (*get_timer_value)(void);
 	uint32_t clk_mult;
 	uint32_t clk_div;

diff --git a/include/drivers/marvell/trng.h b/include/drivers/marvell/trng.h
new file mode 100644
index 0000000..e4f39f4
--- /dev/null
+++ b/include/drivers/marvell/trng.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TRNG_H__
+#define __TRNG_H__
+
+#include <stdint.h>
+
+int mv_trng_get_random32(uint32_t *rand, uint8_t num);
+
+#endif /* __TRNG_H__ */

diff --git a/include/drivers/measured_boot/event_log/event_handoff.h b/include/drivers/measured_boot/event_log/event_handoff.h
new file mode 100644
index 0000000..e969d1f
--- /dev/null
+++ b/include/drivers/measured_boot/event_log/event_handoff.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef HANDOFF_H
+#define HANDOFF_H
+
+#include <stdint.h>
+
+#include <lib/transfer_list.h>
+
+/**
+ * Initializes or extends the TPM event log in the transfer list.
+ *
+ * If an event log entry exists, attempts to resize it. Otherwise, adds a new entry.
+ * Copies old data if needed. Updates free to reflect available space.
+ *
+ * @param tl         Pointer to the transfer list header.
+ * @param req_size   Requested size (bytes)
+ * @param free       Available size (bytes)
+ * @return           Pointer to writable space in the log, or NULL on failure.
+ */
+uint8_t *transfer_list_event_log_extend(struct transfer_list_header *tl,
+					size_t req_size, size_t *free);
+
+/**
+ * Finalizes the event log after writing is complete.
+ *
+ * Resizes the event log to match actual data written, updates checksum,
+ * and flushes cache for the next stage.
+ *
+ * @param tl         Pointer to the transfer list header.
+ * @param cursor     End offset of written log data.
+ * @return           Pointer to finalized log data (past reserved bytes), or NULL.
+ */
+uint8_t *transfer_list_event_log_finish(struct transfer_list_header *tl,
+					uintptr_t cursor);
+
+#define EVENT_LOG_RESERVED_BYTES U(4)
+
+#endif /* HANDOFF_H */

diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index b44526a..b5adfdc 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,12 +7,12 @@
 #ifndef EVENT_LOG_H
 #define EVENT_LOG_H
 
+#include <stddef.h>
 #include <stdint.h>
 
-#include <common/debug.h>
-#include <common/tbbr/tbbr_img_def.h>
 #include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/event_log/tcg.h>
+#include "event_handoff.h"
+#include "tcg.h"
 
 /*
  * Set Event Log debug level to one of:
@@ -33,7 +33,7 @@
 #elif EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
 #define	LOG_EVENT	VERBOSE
 #else
-#error "Not supported EVENT_LOG_LEVEL"
+#define LOG_EVENT printf
 #endif
 
 /* Number of hashing algorithms supported */
@@ -65,18 +65,130 @@
 			sizeof(event2_data_t))
 
 /* Functions' declarations */
-void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish);
-void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish);
-void event_log_write_specid_event(void);
-void event_log_write_header(void);
-void dump_event_log(uint8_t *log_addr, size_t log_size);
-int event_log_measure(uintptr_t data_base, uint32_t data_size,
-		      unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
-void event_log_record(const uint8_t *hash, uint32_t event_type,
-		      const event_log_metadata_t *metadata_ptr);
+
+/**
+ * Initialize the Event Log buffer.
+ *
+ * Sets global pointers to manage the Event Log memory region,
+ * allowing subsequent log operations to write into the buffer.
+ *
+ * @param[in] event_log_start  Pointer to the start of the Event Log buffer.
+ * @param[in] event_log_finish Pointer to the end of the buffer
+ *                             (i.e., one byte past the last valid address).
+ *
+ * @return 0 on success, or -EINVAL if the input range is invalid.
+ */
+int event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish);
+
+/**
+ * Dump the contents of the Event Log.
+ *
+ * Outputs the raw contents of the Event Log buffer, typically
+ * for debugging or audit purposes.
+ *
+ * @param[in] log_addr Pointer to the start of the Event Log buffer.
+ * @param[in] log_size Size of the Event Log buffer in bytes.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_dump(uint8_t *log_addr, size_t log_size);
+
+/**
+ * Initialize the Event Log subsystem.
+ *
+ * Wrapper around `event_log_buf_init()` to configure the memory range
+ * for the Event Log buffer.
+ *
+ * @param[in] event_log_start  Pointer to the start of the Event Log buffer.
+ * @param[in] event_log_finish Pointer to the end of the buffer
+ *                             (i.e., one byte past the last valid address).
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish);
+
+/**
+ * Measure input data and log its hash to the Event Log.
+ *
+ * Computes the cryptographic hash of the specified data and records it
+ * in the Event Log as a TCG_PCR_EVENT2 structure using event type EV_POST_CODE.
+ * Useful for firmware or image attestation.
+ *
+ * @param[in] data_base     Pointer to the base of the data to be measured.
+ * @param[in] data_size     Size of the data in bytes.
+ * @param[in] data_id       Identifier used to match against metadata.
+ * @param[in] metadata_ptr  Pointer to an array of event_log_metadata_t.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
 int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
 				 uint32_t data_id,
 				 const event_log_metadata_t *metadata_ptr);
+
+/**
+ * Measure the input data and return its hash.
+ *
+ * Computes the cryptographic hash of the specified memory region using
+ * the default hashing algorithm configured in the Event Log subsystem.
+ *
+ * @param[in]  data_base  Pointer to the base of the data to be measured.
+ * @param[in]  data_size  Size of the data in bytes.
+ * @param[out] hash_data  Buffer to hold the resulting hash output
+ *                        (must be at least CRYPTO_MD_MAX_SIZE bytes).
+ *
+ * @return 0 on success, or an error code on failure.
+ */
+int event_log_measure(uintptr_t data_base, uint32_t data_size,
+		      unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
+
+/**
+ * Record a measurement event in the Event Log.
+ *
+ * Writes a TCG_PCR_EVENT2 structure to the Event Log using the
+ * provided hash and metadata. This function assumes the buffer
+ * has enough space and that `event_log_buf_init()` has been called.
+ *
+ * @param[in] hash         Pointer to the digest (TCG_DIGEST_SIZE bytes).
+ * @param[in] event_type   Type of the event, as defined in tcg.h.
+ * @param[in] metadata_ptr Pointer to an event_log_metadata_t structure
+ *                         providing event-specific context (e.g., PCR index, name).
+ *
+ * @return 0 on success, or -ENOMEM if the buffer has insufficient space.
+ */
+int event_log_record(const uint8_t *hash, uint32_t event_type,
+		     const event_log_metadata_t *metadata_ptr);
+
+/**
+ * Initialize the Event Log with mandatory header events.
+ *
+ * Writes the Specification ID (SpecID) and Startup Locality events
+ * as required by the TCG PC Client Platform Firmware Profile.
+ * These must be the first entries in the Event Log.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_write_header(void);
+
+/**
+ * Write the SpecID event to the Event Log.
+ *
+ * Records the TCG_EfiSpecIDEventStruct to declare the structure
+ * and supported algorithms of the Event Log format.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_write_specid_event(void);
+
+/**
+ * Get the current size of the Event Log.
+ *
+ * Calculates how many bytes of the Event Log buffer have been used,
+ * based on the current log pointer and the start of the buffer.
+ *
+ * @param[in] event_log_start Pointer to the start of the Event Log buffer.
+ *
+ * @return The number of bytes currently used in the Event Log.
+ */
 size_t event_log_get_cur_size(uint8_t *event_log_start);
 
 #endif /* EVENT_LOG_H */

diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index e94693d..55ed35c 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h

@@ -19,29 +19,29 @@
 
 #define MMC_ACMD(_x)			U(_x)
 
-#define OCR_POWERUP			BIT(31)
-#define OCR_HCS				BIT(30)
-#define OCR_BYTE_MODE			(U(0) << 29)
-#define OCR_SECTOR_MODE			(U(2) << 29)
-#define OCR_ACCESS_MODE_MASK		(U(3) << 29)
-#define OCR_3_5_3_6			BIT(23)
-#define OCR_3_4_3_5			BIT(22)
-#define OCR_3_3_3_4			BIT(21)
-#define OCR_3_2_3_3			BIT(20)
-#define OCR_3_1_3_2			BIT(19)
-#define OCR_3_0_3_1			BIT(18)
-#define OCR_2_9_3_0			BIT(17)
-#define OCR_2_8_2_9			BIT(16)
-#define OCR_2_7_2_8			BIT(15)
-#define OCR_VDD_MIN_2V7			GENMASK(23, 15)
-#define OCR_VDD_MIN_2V0			GENMASK(14, 8)
-#define OCR_VDD_MIN_1V7			BIT(7)
+#define OCR_POWERUP			BIT_32(31U)
+#define OCR_HCS				BIT_32(30U)
+#define OCR_BYTE_MODE			(U(0) << 29U)
+#define OCR_SECTOR_MODE			(U(2) << 29U)
+#define OCR_ACCESS_MODE_MASK		(U(3) << 29U)
+#define OCR_3_5_3_6			BIT_32(23U)
+#define OCR_3_4_3_5			BIT_32(22U)
+#define OCR_3_3_3_4			BIT_32(21U)
+#define OCR_3_2_3_3			BIT_32(20U)
+#define OCR_3_1_3_2			BIT_32(19U)
+#define OCR_3_0_3_1			BIT_32(18U)
+#define OCR_2_9_3_0			BIT_32(17U)
+#define OCR_2_8_2_9			BIT_32(16U)
+#define OCR_2_7_2_8			BIT_32(15U)
+#define OCR_VDD_MIN_2V7			GENMASK_32(23U, 15U)
+#define OCR_VDD_MIN_2V0			GENMASK_32(14U, 8U)
+#define OCR_VDD_MIN_1V7			BIT_32(7U)
 
-#define MMC_RSP_48			BIT(0)
-#define MMC_RSP_136			BIT(1)		/* 136 bit response */
-#define MMC_RSP_CRC			BIT(2)		/* expect valid crc */
-#define MMC_RSP_CMD_IDX			BIT(3)		/* response contains cmd idx */
-#define MMC_RSP_BUSY			BIT(4)		/* device may be busy */
+#define MMC_RSP_48			BIT_32(0U)
+#define MMC_RSP_136			BIT_32(1U)		/* 136 bit response */
+#define MMC_RSP_CRC			BIT_32(2U)		/* expect valid crc */
+#define MMC_RSP_CMD_IDX			BIT_32(3U)		/* response contains cmd idx */
+#define MMC_RSP_BUSY			BIT_32(4U)		/* device may be busy */
 
 /* JEDEC 4.51 chapter 6.12 */
 #define MMC_RESPONSE_R1			(MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
@@ -52,6 +52,7 @@
 #define MMC_RESPONSE_R5			(MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
 #define MMC_RESPONSE_R6			(MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
 #define MMC_RESPONSE_R7			(MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_NONE		0U
 
 /* Value randomly chosen for eMMC RCA, it should be > 1 */
 #define MMC_FIX_RCA			6

diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
index bc11aca..02bd4d0 100644
--- a/include/drivers/nxp/crypto/caam/sec_hw_specific.h
+++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h

@@ -123,6 +123,7 @@
 
  /* RNG RDSTA bitmask */
 #define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
+#define RNG_STATE1_HANDLE_INSTANTIATED	0x00000002
 #define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
  /* use von Neumann data in both entropy shifter and statistical checker */
 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC	 0

diff --git a/include/drivers/nxp/trdc/imx_trdc.h b/include/drivers/nxp/trdc/imx_trdc.h
index 0b41fcf..3ee60f9 100644
--- a/include/drivers/nxp/trdc/imx_trdc.h
+++ b/include/drivers/nxp/trdc/imx_trdc.h

@@ -5,7 +5,7 @@
  */
 
 #ifndef IMX_TRDC_H
-#define IMX_XRDC_H
+#define IMX_TRDC_H
 
 #define MBC_BLK_ALL	U(255)
 #define MRC_REG_ALL	U(16)

diff --git a/include/drivers/rambus/trng_ip_76.h b/include/drivers/rambus/trng_ip_76.h
deleted file mode 100644
index 6de8fc7..0000000
--- a/include/drivers/rambus/trng_ip_76.h
+++ /dev/null

@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-#ifndef __TRNG_IP_76_H__
-#define __TRNG_IP_76_H__
-
-#include <stdbool.h>
-#include <stdint.h>
-
-int32_t eip76_rng_read_rand_buf(void *data, bool wait);
-int32_t eip76_rng_probe(uintptr_t base_addr);
-int32_t eip76_rng_get_random(uint8_t *data, uint32_t len);
-
-#endif /* __TRNG_IP_76_H__ */

diff --git a/include/drivers/st/bsec3_reg.h b/include/drivers/st/bsec3_reg.h
index 177e30b..4263f76 100644
--- a/include/drivers/st/bsec3_reg.h
+++ b/include/drivers/st/bsec3_reg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -84,7 +84,7 @@
 
 /* BSEC_OTPSR register fields */
 #define BSEC_OTPSR_BUSY			BIT_32(0)
-#define BSEC_OTPSR_FUSEOK		BIT_32(1)
+#define BSEC_OTPSR_INIT_DONE		BIT_32(1)
 #define BSEC_OTPSR_HIDEUP		BIT_32(2)
 #define BSEC_OTPSR_OTPNVIR		BIT_32(4)
 #define BSEC_OTPSR_OTPERR		BIT_32(5)

diff --git a/include/drivers/st/stm32mp21_pwr.h b/include/drivers/st/stm32mp21_pwr.h
new file mode 100644
index 0000000..570f079
--- /dev/null
+++ b/include/drivers/st/stm32mp21_pwr.h

@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_PWR_H
+#define STM32MP21_PWR_H
+
+#include <lib/utils_def.h>
+
+#define PWR_CR1					U(0x00)
+#define PWR_CR2					U(0x04)
+#define PWR_CR3					U(0x08)
+#define PWR_CR7					U(0x18)
+#define PWR_CR8					U(0x1C)
+#define PWR_CR9					U(0x20)
+#define PWR_CR10				U(0x24)
+#define PWR_CR11				U(0x28)
+#define PWR_BDCR				U(0x38)
+#define PWR_CPU1CR				U(0x40)
+#define PWR_CPU2CR				U(0x44)
+#define PWR_D1CR				U(0x4C)
+#define PWR_D2CR				U(0x50)
+#define PWR_WKUPCR1				U(0x60)
+#define PWR_WKUPCR2				U(0x64)
+#define PWR_WKUPCR3				U(0x68)
+#define PWR_WKUPCR4				U(0x6C)
+#define PWR_WKUPCR5				U(0x70)
+#define PWR_WKUPCR6				U(0x74)
+#define PWR_RSECCFGR				U(0x100)
+#define PWR_RPRIVCFGR				U(0x104)
+#define PWR_R0CIDCFGR				U(0x108)
+#define PWR_R1CIDCFGR				U(0x10C)
+#define PWR_R2CIDCFGR				U(0x110)
+#define PWR_R3CIDCFGR				U(0x114)
+#define PWR_R4CIDCFGR				U(0x118)
+#define PWR_R5CIDCFGR				U(0x11C)
+#define PWR_R6CIDCFGR				U(0x120)
+#define PWR_WIOSECCFGR				U(0x180)
+#define PWR_WIOPRIVCFGR				U(0x184)
+#define PWR_WIO1CIDCFGR				U(0x188)
+#define PWR_WIO1SEMCR				U(0x18C)
+#define PWR_WIO2CIDCFGR				U(0x190)
+#define PWR_WIO2SEMCR				U(0x194)
+#define PWR_WIO3CIDCFGR				U(0x198)
+#define PWR_WIO3SEMCR				U(0x19C)
+#define PWR_WIO4CIDCFGR				U(0x1A0)
+#define PWR_WIO4SEMCR				U(0x1A4)
+#define PWR_WIO5CIDCFGR				U(0x1A8)
+#define PWR_WIO5SEMCR				U(0x1AC)
+#define PWR_WIO6CIDCFGR				U(0x1B0)
+#define PWR_WIO6SEMCR				U(0x1B4)
+#define PWR_CPU1D1SR				U(0x200)
+#define PWR_CPU2D2SR				U(0x204)
+#define PWR_DBGR				U(0x308)
+#define PWR_VERR				U(0x3F4)
+#define PWR_IPIDR				U(0x3F8)
+#define PWR_SIDR				U(0x3FC)
+
+/* PWR_CR1 register fields */
+#define PWR_CR1_VDDIO3VMEN			BIT(0)
+#define PWR_CR1_USB33VMEN			BIT(2)
+#define PWR_CR1_AVMEN				BIT(4)
+#define PWR_CR1_VDDIO3SV			BIT(8)
+#define PWR_CR1_USB33SV				BIT(10)
+#define PWR_CR1_ASV				BIT(12)
+#define PWR_CR1_VDDIO3RDY			BIT(16)
+#define PWR_CR1_USB33RDY			BIT(18)
+#define PWR_CR1_ARDY				BIT(20)
+#define PWR_CR1_VDDIOVRSEL			BIT(24)
+#define PWR_CR1_VDDIO3VRSEL			BIT(25)
+#define PWR_CR1_GPVMO				BIT(31)
+
+/* PWR_CR2 register fields */
+#define PWR_CR2_MONEN				BIT(0)
+#define PWR_CR2_VBATL				BIT(8)
+#define PWR_CR2_VBATH				BIT(9)
+#define PWR_CR2_TEMPL				BIT(10)
+#define PWR_CR2_TEMPH				BIT(11)
+
+/* PWR_CR3 register fields */
+#define PWR_CR3_PVDEN				BIT(0)
+#define PWR_CR3_PVDO				BIT(8)
+
+/* PWR_CR7 register fields */
+#define PWR_CR7_VDDIO2VMEN			BIT(0)
+#define PWR_CR7_VDDIO2SV			BIT(8)
+#define PWR_CR7_VDDIO2RDY			BIT(16)
+#define PWR_CR7_VDDIO2VRSEL			BIT(24)
+#define PWR_CR7_VDDIO2VRSTBY			BIT(25)
+
+/* PWR_CR8 register fields */
+#define PWR_CR8_VDDIO1VMEN			BIT(0)
+#define PWR_CR8_VDDIO1SV			BIT(8)
+#define PWR_CR8_VDDIO1RDY			BIT(16)
+#define PWR_CR8_VDDIO1VRSEL			BIT(24)
+#define PWR_CR8_VDDIO1VRSTBY			BIT(25)
+
+/* PWR_CR9 register fields */
+#define PWR_CR9_BKPRBSEN			BIT(0)
+
+/* PWR_CR10 register fields */
+#define PWR_CR10_RETRBSEN_MASK			GENMASK_32(1, 0)
+#define PWR_CR10_RETRBSEN_SHIFT			0
+#define PWR_CR10_RETRBSEN_DISABLE		0U
+#define PWR_CR10_RETRBSEN_STANDBY_VBAT		1U
+#define PWR_CR10_RETRBSEN_STANDBY		2U
+
+/* PWR_CR11 register fields */
+#define PWR_CR11_DDRRETDIS			BIT(0)
+
+/* PWR_BDCR register fields */
+#define PWR_BDCR_DBP				BIT(0)
+
+/* PWR_CPU1CR register fields */
+#define PWR_CPU1CR_PDDS_D2			BIT(0)
+#define PWR_CPU1CR_PDDS_D1			BIT(1)
+#define PWR_CPU1CR_VBF				BIT(4)
+#define PWR_CPU1CR_STOPF			BIT(5)
+#define PWR_CPU1CR_SBF				BIT(6)
+#define PWR_CPU1CR_SBF_D1			BIT(7)
+#define PWR_CPU1CR_CSSF				BIT(9)
+#define PWR_CPU1CR_STANDBYWFIL2			BIT(15)
+#define PWR_CPU1CR_LPDS_D1			BIT(16)
+#define PWR_CPU1CR_LVDS_D1			BIT(17)
+
+/* PWR_CPU2CR register fields */
+#define PWR_CPU2CR_PDDS_D2			BIT(0)
+#define PWR_CPU2CR_VBF				BIT(4)
+#define PWR_CPU2CR_STOPF			BIT(5)
+#define PWR_CPU2CR_SBF				BIT(6)
+#define PWR_CPU2CR_SBF_D2			BIT(7)
+#define PWR_CPU2CR_CSSF				BIT(9)
+#define PWR_CPU2CR_DEEPSLEEP			BIT(15)
+#define PWR_CPU2CR_LPDS_D2			BIT(16)
+#define PWR_CPU2CR_LVDS_D2			BIT(17)
+
+/* PWR_D1CR register fields */
+#define PWR_D1CR_LPCFG_D1			BIT(0)
+#define PWR_D1CR_POPL_D1_MASK			GENMASK_32(12, 8)
+#define PWR_D1CR_POPL_D1_SHIFT			8
+
+/* PWR_D2CR register fields */
+#define PWR_D2CR_LPCFG_D2			BIT(0)
+#define PWR_D2CR_POPL_D2_MASK			GENMASK_32(12, 8)
+#define PWR_D2CR_POPL_D2_SHIFT			8
+#define PWR_D2CR_LPLVDLY_D2_MASK		GENMASK_32(18, 16)
+#define PWR_D2CR_LPLVDLY_D2_SHIFT		16
+#define PWR_D2CR_PODH_D2_MASK			GENMASK_32(27, 24)
+#define PWR_D2CR_PODH_D2_SHIFT			24
+
+/* PWR_WKUPCR1 register fields */
+#define PWR_WKUPCR1_WKUPC			BIT(0)
+#define PWR_WKUPCR1_WKUPP			BIT(8)
+#define PWR_WKUPCR1_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR1_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR1_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR1_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR1_WKUPF			BIT(31)
+
+/* PWR_WKUPCR2 register fields */
+#define PWR_WKUPCR2_WKUPC			BIT(0)
+#define PWR_WKUPCR2_WKUPP			BIT(8)
+#define PWR_WKUPCR2_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR2_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR2_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR2_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR2_WKUPF			BIT(31)
+
+/* PWR_WKUPCR3 register fields */
+#define PWR_WKUPCR3_WKUPC			BIT(0)
+#define PWR_WKUPCR3_WKUPP			BIT(8)
+#define PWR_WKUPCR3_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR3_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR3_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR3_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR3_WKUPF			BIT(31)
+
+/* PWR_WKUPCR4 register fields */
+#define PWR_WKUPCR4_WKUPC			BIT(0)
+#define PWR_WKUPCR4_WKUPP			BIT(8)
+#define PWR_WKUPCR4_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR4_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR4_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR4_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR4_WKUPF			BIT(31)
+
+/* PWR_WKUPCR5 register fields */
+#define PWR_WKUPCR5_WKUPC			BIT(0)
+#define PWR_WKUPCR5_WKUPP			BIT(8)
+#define PWR_WKUPCR5_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR5_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR5_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR5_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR5_WKUPF			BIT(31)
+
+/* PWR_WKUPCR6 register fields */
+#define PWR_WKUPCR6_WKUPC			BIT(0)
+#define PWR_WKUPCR6_WKUPP			BIT(8)
+#define PWR_WKUPCR6_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR6_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR6_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR6_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR6_WKUPF			BIT(31)
+
+/* PWR_RSECCFGR register fields */
+#define PWR_RSECCFGR_RSEC0			BIT(0)
+#define PWR_RSECCFGR_RSEC1			BIT(1)
+#define PWR_RSECCFGR_RSEC2			BIT(2)
+#define PWR_RSECCFGR_RSEC3			BIT(3)
+#define PWR_RSECCFGR_RSEC4			BIT(4)
+#define PWR_RSECCFGR_RSEC5			BIT(5)
+#define PWR_RSECCFGR_RSEC6			BIT(6)
+
+/* PWR_RPRIVCFGR register fields */
+#define PWR_RPRIVCFGR_RPRIV0			BIT(0)
+#define PWR_RPRIVCFGR_RPRIV1			BIT(1)
+#define PWR_RPRIVCFGR_RPRIV2			BIT(2)
+#define PWR_RPRIVCFGR_RPRIV3			BIT(3)
+#define PWR_RPRIVCFGR_RPRIV4			BIT(4)
+#define PWR_RPRIVCFGR_RPRIV5			BIT(5)
+#define PWR_RPRIVCFGR_RPRIV6			BIT(6)
+
+/* PWR_R0CIDCFGR register fields */
+#define PWR_R0CIDCFGR_CFEN			BIT(0)
+#define PWR_R0CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R0CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R1CIDCFGR register fields */
+#define PWR_R1CIDCFGR_CFEN			BIT(0)
+#define PWR_R1CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R1CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R2CIDCFGR register fields */
+#define PWR_R2CIDCFGR_CFEN			BIT(0)
+#define PWR_R2CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R2CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R3CIDCFGR register fields */
+#define PWR_R3CIDCFGR_CFEN			BIT(0)
+#define PWR_R3CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R3CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R4CIDCFGR register fields */
+#define PWR_R4CIDCFGR_CFEN			BIT(0)
+#define PWR_R4CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R4CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R5CIDCFGR register fields */
+#define PWR_R5CIDCFGR_CFEN			BIT(0)
+#define PWR_R5CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R5CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R6CIDCFGR register fields */
+#define PWR_R6CIDCFGR_CFEN			BIT(0)
+#define PWR_R6CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R6CIDCFGR_SCID_SHIFT		4
+
+/* PWR_WIOSECCFGR register fields */
+#define PWR_WIOSECCFGR_WIOSEC1			BIT(0)
+#define PWR_WIOSECCFGR_WIOSEC2			BIT(1)
+#define PWR_WIOSECCFGR_WIOSEC3			BIT(2)
+#define PWR_WIOSECCFGR_WIOSEC4			BIT(3)
+#define PWR_WIOSECCFGR_WIOSEC5			BIT(4)
+#define PWR_WIOSECCFGR_WIOSEC6			BIT(5)
+
+/* PWR_WIOPRIVCFGR register fields */
+#define PWR_WIOPRIVCFGR_WIOPRIV1		BIT(0)
+#define PWR_WIOPRIVCFGR_WIOPRIV2		BIT(1)
+#define PWR_WIOPRIVCFGR_WIOPRIV3		BIT(2)
+#define PWR_WIOPRIVCFGR_WIOPRIV4		BIT(3)
+#define PWR_WIOPRIVCFGR_WIOPRIV5		BIT(4)
+#define PWR_WIOPRIVCFGR_WIOPRIV6		BIT(5)
+
+/* PWR_WIO1CIDCFGR register fields */
+#define PWR_WIO1CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO1CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO1CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO1CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO1CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO1CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO1CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO1CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO1CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO1CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO1CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO1CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO1SEMCR register fields */
+#define PWR_WIO1SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO1SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO1SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO2CIDCFGR register fields */
+#define PWR_WIO2CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO2CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO2CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO2CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO2CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO2CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO2CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO2CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO2CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO2CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO2CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO2CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO2SEMCR register fields */
+#define PWR_WIO2SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO2SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO2SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO3CIDCFGR register fields */
+#define PWR_WIO3CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO3CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO3CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO3CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO3CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO3CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO3CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO3CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO3CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO3CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO3CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO3CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO3SEMCR register fields */
+#define PWR_WIO3SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO3SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO3SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO4CIDCFGR register fields */
+#define PWR_WIO4CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO4CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO4CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO4CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO4CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO4CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO4CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO4CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO4CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO4CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO4CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO4CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO4SEMCR register fields */
+#define PWR_WIO4SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO4SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO4SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO5CIDCFGR register fields */
+#define PWR_WIO5CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO5CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO5CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO5CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO5CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO5CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO5CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO5CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO5CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO5CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO5CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO5CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO5SEMCR register fields */
+#define PWR_WIO5SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO5SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO5SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO6CIDCFGR register fields */
+#define PWR_WIO6CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO6CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO6CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO6CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO6CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO6CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO6CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO6CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO6CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO6CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO6CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO6CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO6SEMCR register fields */
+#define PWR_WIO6SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO6SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO6SEMCR_SEMCID_SHIFT		4
+
+/* PWR_CPU1D1SR register fields */
+#define PWR_CPU1D1SR_HOLD_BOOT			BIT(0)
+#define PWR_CPU1D1SR_CSTATE_MASK		GENMASK_32(3, 2)
+#define PWR_CPU1D1SR_CSTATE_SHIFT		2
+#define PWR_CPU1D1SR_DSTATE_MASK		GENMASK_32(10, 8)
+#define PWR_CPU1D1SR_DSTATE_SHIFT		8
+
+/* PWR_CPU2D2SR register fields */
+#define PWR_CPU2D2SR_HOLD_BOOT			BIT(0)
+#define PWR_CPU2D2SR_WFBEN			BIT(1)
+#define PWR_CPU2D2SR_CSTATE_MASK		GENMASK_32(3, 2)
+#define PWR_CPU2D2SR_CSTATE_SHIFT		2
+#define PWR_CPU2D2SR_DSTATE_MASK		GENMASK_32(10, 8)
+#define PWR_CPU2D2SR_DSTATE_SHIFT		8
+
+/* PWR_DBGR register fields */
+#define PWR_DBGR_VDDIOKRETRAM			BIT(16)
+#define PWR_DBGR_VDDIOKBKPRAM			BIT(17)
+
+/* PWR_VERR register fields */
+#define PWR_VERR_MINREV_MASK			GENMASK_32(3, 0)
+#define PWR_VERR_MINREV_SHIFT			0
+#define PWR_VERR_MAJREV_MASK			GENMASK_32(7, 4)
+#define PWR_VERR_MAJREV_SHIFT			4
+
+#endif /* STM32MP21_PWR_H */
+

diff --git a/include/drivers/st/stm32mp21_rcc.h b/include/drivers/st/stm32mp21_rcc.h
new file mode 100644
index 0000000..a3787d0
--- /dev/null
+++ b/include/drivers/st/stm32mp21_rcc.h

@@ -0,0 +1,4668 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_RCC_H
+#define STM32MP21_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR0				U(0x0)
+#define RCC_SECCFGR1				U(0x4)
+#define RCC_SECCFGR2				U(0x8)
+#define RCC_SECCFGR3				U(0xC)
+#define RCC_PRIVCFGR0				U(0x10)
+#define RCC_PRIVCFGR1				U(0x14)
+#define RCC_PRIVCFGR2				U(0x18)
+#define RCC_PRIVCFGR3				U(0x1C)
+#define RCC_RCFGLOCKR0				U(0x20)
+#define RCC_RCFGLOCKR1				U(0x24)
+#define RCC_RCFGLOCKR2				U(0x28)
+#define RCC_RCFGLOCKR3				U(0x2C)
+#define RCC_R0CIDCFGR				U(0x30)
+#define RCC_R0SEMCR				U(0x34)
+#define RCC_R1CIDCFGR				U(0x38)
+#define RCC_R1SEMCR				U(0x3C)
+#define RCC_R2CIDCFGR				U(0x40)
+#define RCC_R2SEMCR				U(0x44)
+#define RCC_R3CIDCFGR				U(0x48)
+#define RCC_R3SEMCR				U(0x4C)
+#define RCC_R4CIDCFGR				U(0x50)
+#define RCC_R4SEMCR				U(0x54)
+#define RCC_R5CIDCFGR				U(0x58)
+#define RCC_R5SEMCR				U(0x5C)
+#define RCC_R6CIDCFGR				U(0x60)
+#define RCC_R6SEMCR				U(0x64)
+#define RCC_R7CIDCFGR				U(0x68)
+#define RCC_R7SEMCR				U(0x6C)
+#define RCC_R8CIDCFGR				U(0x70)
+#define RCC_R8SEMCR				U(0x74)
+#define RCC_R9CIDCFGR				U(0x78)
+#define RCC_R9SEMCR				U(0x7C)
+#define RCC_R10CIDCFGR				U(0x80)
+#define RCC_R10SEMCR				U(0x84)
+#define RCC_R11CIDCFGR				U(0x88)
+#define RCC_R11SEMCR				U(0x8C)
+#define RCC_R12CIDCFGR				U(0x90)
+#define RCC_R12SEMCR				U(0x94)
+#define RCC_R13CIDCFGR				U(0x98)
+#define RCC_R13SEMCR				U(0x9C)
+#define RCC_R14CIDCFGR				U(0xA0)
+#define RCC_R14SEMCR				U(0xA4)
+#define RCC_R15CIDCFGR				U(0xA8)
+#define RCC_R15SEMCR				U(0xAC)
+#define RCC_R16CIDCFGR				U(0xB0)
+#define RCC_R16SEMCR				U(0xB4)
+#define RCC_R17CIDCFGR				U(0xB8)
+#define RCC_R17SEMCR				U(0xBC)
+#define RCC_R18CIDCFGR				U(0xC0)
+#define RCC_R18SEMCR				U(0xC4)
+#define RCC_R19CIDCFGR				U(0xC8)
+#define RCC_R19SEMCR				U(0xCC)
+#define RCC_R20CIDCFGR				U(0xD0)
+#define RCC_R20SEMCR				U(0xD4)
+#define RCC_R21CIDCFGR				U(0xD8)
+#define RCC_R21SEMCR				U(0xDC)
+#define RCC_R22CIDCFGR				U(0xE0)
+#define RCC_R22SEMCR				U(0xE4)
+#define RCC_R23CIDCFGR				U(0xE8)
+#define RCC_R23SEMCR				U(0xEC)
+#define RCC_R24CIDCFGR				U(0xF0)
+#define RCC_R24SEMCR				U(0xF4)
+#define RCC_R25CIDCFGR				U(0xF8)
+#define RCC_R25SEMCR				U(0xFC)
+#define RCC_R26CIDCFGR				U(0x100)
+#define RCC_R26SEMCR				U(0x104)
+#define RCC_R27CIDCFGR				U(0x108)
+#define RCC_R27SEMCR				U(0x10C)
+#define RCC_R28CIDCFGR				U(0x110)
+#define RCC_R28SEMCR				U(0x114)
+#define RCC_R29CIDCFGR				U(0x118)
+#define RCC_R29SEMCR				U(0x11C)
+#define RCC_R30CIDCFGR				U(0x120)
+#define RCC_R30SEMCR				U(0x124)
+#define RCC_R31CIDCFGR				U(0x128)
+#define RCC_R31SEMCR				U(0x12C)
+#define RCC_R32CIDCFGR				U(0x130)
+#define RCC_R32SEMCR				U(0x134)
+#define RCC_R33CIDCFGR				U(0x138)
+#define RCC_R33SEMCR				U(0x13C)
+#define RCC_R34CIDCFGR				U(0x140)
+#define RCC_R34SEMCR				U(0x144)
+#define RCC_R35CIDCFGR				U(0x148)
+#define RCC_R35SEMCR				U(0x14C)
+#define RCC_R36CIDCFGR				U(0x150)
+#define RCC_R36SEMCR				U(0x154)
+#define RCC_R37CIDCFGR				U(0x158)
+#define RCC_R37SEMCR				U(0x15C)
+#define RCC_R38CIDCFGR				U(0x160)
+#define RCC_R38SEMCR				U(0x164)
+#define RCC_R39CIDCFGR				U(0x168)
+#define RCC_R39SEMCR				U(0x16C)
+#define RCC_R40CIDCFGR				U(0x170)
+#define RCC_R40SEMCR				U(0x174)
+#define RCC_R41CIDCFGR				U(0x178)
+#define RCC_R41SEMCR				U(0x17C)
+#define RCC_R42CIDCFGR				U(0x180)
+#define RCC_R42SEMCR				U(0x184)
+#define RCC_R43CIDCFGR				U(0x188)
+#define RCC_R43SEMCR				U(0x18C)
+#define RCC_R44CIDCFGR				U(0x190)
+#define RCC_R44SEMCR				U(0x194)
+#define RCC_R45CIDCFGR				U(0x198)
+#define RCC_R45SEMCR				U(0x19C)
+#define RCC_R46CIDCFGR				U(0x1A0)
+#define RCC_R46SEMCR				U(0x1A4)
+#define RCC_R47CIDCFGR				U(0x1A8)
+#define RCC_R47SEMCR				U(0x1AC)
+#define RCC_R48CIDCFGR				U(0x1B0)
+#define RCC_R48SEMCR				U(0x1B4)
+#define RCC_R49CIDCFGR				U(0x1B8)
+#define RCC_R49SEMCR				U(0x1BC)
+#define RCC_R50CIDCFGR				U(0x1C0)
+#define RCC_R50SEMCR				U(0x1C4)
+#define RCC_R51CIDCFGR				U(0x1C8)
+#define RCC_R51SEMCR				U(0x1CC)
+#define RCC_R52CIDCFGR				U(0x1D0)
+#define RCC_R52SEMCR				U(0x1D4)
+#define RCC_R53CIDCFGR				U(0x1D8)
+#define RCC_R53SEMCR				U(0x1DC)
+#define RCC_R54CIDCFGR				U(0x1E0)
+#define RCC_R54SEMCR				U(0x1E4)
+#define RCC_R55CIDCFGR				U(0x1E8)
+#define RCC_R55SEMCR				U(0x1EC)
+#define RCC_R56CIDCFGR				U(0x1F0)
+#define RCC_R56SEMCR				U(0x1F4)
+#define RCC_R57CIDCFGR				U(0x1F8)
+#define RCC_R57SEMCR				U(0x1FC)
+#define RCC_R58CIDCFGR				U(0x200)
+#define RCC_R58SEMCR				U(0x204)
+#define RCC_R59CIDCFGR				U(0x208)
+#define RCC_R59SEMCR				U(0x20C)
+#define RCC_R60CIDCFGR				U(0x210)
+#define RCC_R60SEMCR				U(0x214)
+#define RCC_R61CIDCFGR				U(0x218)
+#define RCC_R61SEMCR				U(0x21C)
+#define RCC_R62CIDCFGR				U(0x220)
+#define RCC_R62SEMCR				U(0x224)
+#define RCC_R63CIDCFGR				U(0x228)
+#define RCC_R63SEMCR				U(0x22C)
+#define RCC_R64CIDCFGR				U(0x230)
+#define RCC_R64SEMCR				U(0x234)
+#define RCC_R65CIDCFGR				U(0x238)
+#define RCC_R65SEMCR				U(0x23C)
+#define RCC_R66CIDCFGR				U(0x240)
+#define RCC_R66SEMCR				U(0x244)
+#define RCC_R67CIDCFGR				U(0x248)
+#define RCC_R67SEMCR				U(0x24C)
+#define RCC_R68CIDCFGR				U(0x250)
+#define RCC_R68SEMCR				U(0x254)
+#define RCC_R69CIDCFGR				U(0x258)
+#define RCC_R69SEMCR				U(0x25C)
+#define RCC_R70CIDCFGR				U(0x260)
+#define RCC_R70SEMCR				U(0x264)
+#define RCC_R71CIDCFGR				U(0x268)
+#define RCC_R71SEMCR				U(0x26C)
+#define RCC_R72CIDCFGR				U(0x270)
+#define RCC_R72SEMCR				U(0x274)
+#define RCC_R73CIDCFGR				U(0x278)
+#define RCC_R73SEMCR				U(0x27C)
+#define RCC_R74CIDCFGR				U(0x280)
+#define RCC_R74SEMCR				U(0x284)
+#define RCC_R75CIDCFGR				U(0x288)
+#define RCC_R75SEMCR				U(0x28C)
+#define RCC_R76CIDCFGR				U(0x290)
+#define RCC_R76SEMCR				U(0x294)
+#define RCC_R77CIDCFGR				U(0x298)
+#define RCC_R77SEMCR				U(0x29C)
+#define RCC_R78CIDCFGR				U(0x2A0)
+#define RCC_R78SEMCR				U(0x2A4)
+#define RCC_R79CIDCFGR				U(0x2A8)
+#define RCC_R79SEMCR				U(0x2AC)
+#define RCC_R80CIDCFGR				U(0x2B0)
+#define RCC_R80SEMCR				U(0x2B4)
+#define RCC_R81CIDCFGR				U(0x2B8)
+#define RCC_R81SEMCR				U(0x2BC)
+#define RCC_R82CIDCFGR				U(0x2C0)
+#define RCC_R82SEMCR				U(0x2C4)
+#define RCC_R83CIDCFGR				U(0x2C8)
+#define RCC_R83SEMCR				U(0x2CC)
+#define RCC_R84CIDCFGR				U(0x2D0)
+#define RCC_R84SEMCR				U(0x2D4)
+#define RCC_R85CIDCFGR				U(0x2D8)
+#define RCC_R85SEMCR				U(0x2DC)
+#define RCC_R86CIDCFGR				U(0x2E0)
+#define RCC_R86SEMCR				U(0x2E4)
+#define RCC_R87CIDCFGR				U(0x2E8)
+#define RCC_R87SEMCR				U(0x2EC)
+#define RCC_R88CIDCFGR				U(0x2F0)
+#define RCC_R88SEMCR				U(0x2F4)
+#define RCC_R89CIDCFGR				U(0x2F8)
+#define RCC_R89SEMCR				U(0x2FC)
+#define RCC_R90CIDCFGR				U(0x300)
+#define RCC_R90SEMCR				U(0x304)
+#define RCC_R91CIDCFGR				U(0x308)
+#define RCC_R91SEMCR				U(0x30C)
+#define RCC_R92CIDCFGR				U(0x310)
+#define RCC_R92SEMCR				U(0x314)
+#define RCC_R93CIDCFGR				U(0x318)
+#define RCC_R93SEMCR				U(0x31C)
+#define RCC_R94CIDCFGR				U(0x320)
+#define RCC_R94SEMCR				U(0x324)
+#define RCC_R95CIDCFGR				U(0x328)
+#define RCC_R95SEMCR				U(0x32C)
+#define RCC_R96CIDCFGR				U(0x330)
+#define RCC_R96SEMCR				U(0x334)
+#define RCC_R97CIDCFGR				U(0x338)
+#define RCC_R97SEMCR				U(0x33C)
+#define RCC_R98CIDCFGR				U(0x340)
+#define RCC_R98SEMCR				U(0x344)
+#define RCC_R99CIDCFGR				U(0x348)
+#define RCC_R99SEMCR				U(0x34C)
+#define RCC_R100CIDCFGR				U(0x350)
+#define RCC_R100SEMCR				U(0x354)
+#define RCC_R101CIDCFGR				U(0x358)
+#define RCC_R101SEMCR				U(0x35C)
+#define RCC_R102CIDCFGR				U(0x360)
+#define RCC_R102SEMCR				U(0x364)
+#define RCC_R103CIDCFGR				U(0x368)
+#define RCC_R103SEMCR				U(0x36C)
+#define RCC_R104CIDCFGR				U(0x370)
+#define RCC_R104SEMCR				U(0x374)
+#define RCC_R105CIDCFGR				U(0x378)
+#define RCC_R105SEMCR				U(0x37C)
+#define RCC_R106CIDCFGR				U(0x380)
+#define RCC_R106SEMCR				U(0x384)
+#define RCC_R107CIDCFGR				U(0x388)
+#define RCC_R107SEMCR				U(0x38C)
+#define RCC_R108CIDCFGR				U(0x390)
+#define RCC_R108SEMCR				U(0x394)
+#define RCC_R109CIDCFGR				U(0x398)
+#define RCC_R109SEMCR				U(0x39C)
+#define RCC_R110CIDCFGR				U(0x3A0)
+#define RCC_R110SEMCR				U(0x3A4)
+#define RCC_R111CIDCFGR				U(0x3A8)
+#define RCC_R111SEMCR				U(0x3AC)
+#define RCC_R112CIDCFGR				U(0x3B0)
+#define RCC_R112SEMCR				U(0x3B4)
+#define RCC_R113CIDCFGR				U(0x3B8)
+#define RCC_R113SEMCR				U(0x3BC)
+#define RCC_GRSTCSETR				U(0x400)
+#define RCC_C1RSTCSETR				U(0x404)
+#define RCC_C2RSTCSETR				U(0x40C)
+#define RCC_HWRSTSCLRR				U(0x410)
+#define RCC_C1HWRSTSCLRR			U(0x414)
+#define RCC_C2HWRSTSCLRR			U(0x418)
+#define RCC_C1BOOTRSTSSETR			U(0x41C)
+#define RCC_C1BOOTRSTSCLRR			U(0x420)
+#define RCC_C2BOOTRSTSSETR			U(0x424)
+#define RCC_C2BOOTRSTSCLRR			U(0x428)
+#define RCC_C1SREQSETR				U(0x42C)
+#define RCC_C1SREQCLRR				U(0x430)
+#define RCC_CPUBOOTCR				U(0x434)
+#define RCC_STBYBOOTCR				U(0x438)
+#define RCC_LEGBOOTCR				U(0x43C)
+#define RCC_BDCR				U(0x440)
+#define RCC_RDCR				U(0x44C)
+#define RCC_C1MSRDCR				U(0x450)
+#define RCC_PWRLPDLYCR				U(0x454)
+#define RCC_C1CIESETR				U(0x458)
+#define RCC_C1CIFCLRR				U(0x45C)
+#define RCC_C2CIESETR				U(0x460)
+#define RCC_C2CIFCLRR				U(0x464)
+#define RCC_IWDGC1FZSETR			U(0x468)
+#define RCC_IWDGC1FZCLRR			U(0x46C)
+#define RCC_IWDGC1CFGSETR			U(0x470)
+#define RCC_IWDGC1CFGCLRR			U(0x474)
+#define RCC_IWDGC2FZSETR			U(0x478)
+#define RCC_IWDGC2FZCLRR			U(0x47C)
+#define RCC_IWDGC2CFGSETR			U(0x480)
+#define RCC_IWDGC2CFGCLRR			U(0x484)
+#define RCC_MCO1CFGR				U(0x488)
+#define RCC_MCO2CFGR				U(0x48C)
+#define RCC_OCENSETR				U(0x490)
+#define RCC_OCENCLRR				U(0x494)
+#define RCC_OCRDYR				U(0x498)
+#define RCC_HSICFGR				U(0x49C)
+#define RCC_MSICFGR				U(0x4A0)
+#define RCC_LSICR				U(0x4A4)
+#define RCC_RTCDIVR				U(0x4A8)
+#define RCC_APB1DIVR				U(0x4AC)
+#define RCC_APB2DIVR				U(0x4B0)
+#define RCC_APB3DIVR				U(0x4B4)
+#define RCC_APB4DIVR				U(0x4B8)
+#define RCC_APB5DIVR				U(0x4BC)
+#define RCC_APBDBGDIVR				U(0x4C0)
+#define RCC_TIMG1PRER				U(0x4C8)
+#define RCC_TIMG2PRER				U(0x4CC)
+#define RCC_LSMCUDIVR				U(0x4D0)
+#define RCC_DDRCPCFGR				U(0x4D4)
+#define RCC_DDRCAPBCFGR				U(0x4D8)
+#define RCC_DDRPHYCAPBCFGR			U(0x4DC)
+#define RCC_DDRPHYCCFGR				U(0x4E0)
+#define RCC_DDRCFGR				U(0x4E4)
+#define RCC_DDRITFCFGR				U(0x4E8)
+#define RCC_SYSRAMCFGR				U(0x4F0)
+#define RCC_SRAM1CFGR				U(0x4F8)
+#define RCC_RETRAMCFGR				U(0x500)
+#define RCC_BKPSRAMCFGR				U(0x504)
+#define RCC_OSPI1CFGR				U(0x514)
+#define RCC_FMCCFGR				U(0x51C)
+#define RCC_DBGCFGR				U(0x520)
+#define RCC_STMCFGR				U(0x524)
+#define RCC_ETRCFGR				U(0x528)
+#define RCC_GPIOACFGR				U(0x52C)
+#define RCC_GPIOBCFGR				U(0x530)
+#define RCC_GPIOCCFGR				U(0x534)
+#define RCC_GPIODCFGR				U(0x538)
+#define RCC_GPIOECFGR				U(0x53C)
+#define RCC_GPIOFCFGR				U(0x540)
+#define RCC_GPIOGCFGR				U(0x544)
+#define RCC_GPIOHCFGR				U(0x548)
+#define RCC_GPIOICFGR				U(0x54C)
+#define RCC_GPIOZCFGR				U(0x558)
+#define RCC_HPDMA1CFGR				U(0x55C)
+#define RCC_HPDMA2CFGR				U(0x560)
+#define RCC_HPDMA3CFGR				U(0x564)
+#define RCC_IPCC1CFGR				U(0x570)
+#define RCC_RTCCFGR				U(0x578)
+#define RCC_SYSCPU1CFGR				U(0x580)
+#define RCC_BSECCFGR				U(0x584)
+#define RCC_PLL2CFGR1				U(0x590)
+#define RCC_PLL2CFGR2				U(0x594)
+#define RCC_PLL2CFGR3				U(0x598)
+#define RCC_PLL2CFGR4				U(0x59C)
+#define RCC_PLL2CFGR5				U(0x5A0)
+#define RCC_PLL2CFGR6				U(0x5A8)
+#define RCC_PLL2CFGR7				U(0x5AC)
+#define RCC_HSIFMONCR				U(0x5E0)
+#define RCC_HSIFVALR				U(0x5E4)
+#define RCC_MSIFMONCR				U(0x5E8)
+#define RCC_MSIFVALR				U(0x5EC)
+#define RCC_TIM1CFGR				U(0x700)
+#define RCC_TIM2CFGR				U(0x704)
+#define RCC_TIM3CFGR				U(0x708)
+#define RCC_TIM4CFGR				U(0x70C)
+#define RCC_TIM5CFGR				U(0x710)
+#define RCC_TIM6CFGR				U(0x714)
+#define RCC_TIM7CFGR				U(0x718)
+#define RCC_TIM8CFGR				U(0x71C)
+#define RCC_TIM10CFGR				U(0x720)
+#define RCC_TIM11CFGR				U(0x724)
+#define RCC_TIM12CFGR				U(0x728)
+#define RCC_TIM13CFGR				U(0x72C)
+#define RCC_TIM14CFGR				U(0x730)
+#define RCC_TIM15CFGR				U(0x734)
+#define RCC_TIM16CFGR				U(0x738)
+#define RCC_TIM17CFGR				U(0x73C)
+#define RCC_LPTIM1CFGR				U(0x744)
+#define RCC_LPTIM2CFGR				U(0x748)
+#define RCC_LPTIM3CFGR				U(0x74C)
+#define RCC_LPTIM4CFGR				U(0x750)
+#define RCC_LPTIM5CFGR				U(0x754)
+#define RCC_SPI1CFGR				U(0x758)
+#define RCC_SPI2CFGR				U(0x75C)
+#define RCC_SPI3CFGR				U(0x760)
+#define RCC_SPI4CFGR				U(0x764)
+#define RCC_SPI5CFGR				U(0x768)
+#define RCC_SPI6CFGR				U(0x76C)
+#define RCC_SPDIFRXCFGR				U(0x778)
+#define RCC_USART1CFGR				U(0x77C)
+#define RCC_USART2CFGR				U(0x780)
+#define RCC_USART3CFGR				U(0x784)
+#define RCC_UART4CFGR				U(0x788)
+#define RCC_UART5CFGR				U(0x78C)
+#define RCC_USART6CFGR				U(0x790)
+#define RCC_UART7CFGR				U(0x794)
+#define RCC_LPUART1CFGR				U(0x7A0)
+#define RCC_I2C1CFGR				U(0x7A4)
+#define RCC_I2C2CFGR				U(0x7A8)
+#define RCC_I2C3CFGR				U(0x7AC)
+#define RCC_SAI1CFGR				U(0x7C4)
+#define RCC_SAI2CFGR				U(0x7C8)
+#define RCC_SAI3CFGR				U(0x7CC)
+#define RCC_SAI4CFGR				U(0x7D0)
+#define RCC_MDF1CFGR				U(0x7D8)
+#define RCC_FDCANCFGR				U(0x7E0)
+#define RCC_HDPCFGR				U(0x7E4)
+#define RCC_ADC1CFGR				U(0x7E8)
+#define RCC_ADC2CFGR				U(0x7EC)
+#define RCC_ETH1CFGR				U(0x7F0)
+#define RCC_ETH2CFGR				U(0x7F4)
+#define RCC_USBHCFGR				U(0x7FC)
+#define RCC_USB2PHY1CFGR			U(0x800)
+#define RCC_OTGCFGR				U(0x808)
+#define RCC_USB2PHY2CFGR			U(0x80C)
+#define RCC_STGENCFGR				U(0x824)
+#define RCC_SDMMC1CFGR				U(0x830)
+#define RCC_SDMMC2CFGR				U(0x834)
+#define RCC_SDMMC3CFGR				U(0x838)
+#define RCC_LTDCCFGR				U(0x840)
+#define RCC_CSICFGR				U(0x858)
+#define RCC_DCMIPPCFGR				U(0x85C)
+#define RCC_DCMIPSSICFGR			U(0x860)
+#define RCC_RNG1CFGR				U(0x870)
+#define RCC_RNG2CFGR				U(0x874)
+#define RCC_PKACFGR				U(0x878)
+#define RCC_SAESCFGR				U(0x87C)
+#define RCC_HASH1CFGR				U(0x880)
+#define RCC_HASH2CFGR				U(0x884)
+#define RCC_CRYP1CFGR				U(0x888)
+#define RCC_CRYP2CFGR				U(0x88C)
+#define RCC_IWDG1CFGR				U(0x894)
+#define RCC_IWDG2CFGR				U(0x898)
+#define RCC_IWDG3CFGR				U(0x89C)
+#define RCC_IWDG4CFGR				U(0x8A0)
+#define RCC_WWDG1CFGR				U(0x8A4)
+#define RCC_VREFCFGR				U(0x8AC)
+#define RCC_DTSCFGR				U(0x8B0)
+#define RCC_CRCCFGR				U(0x8B4)
+#define RCC_SERCCFGR				U(0x8B8)
+#define RCC_DDRPERFMCFGR			U(0x8C0)
+#define RCC_I3C1CFGR				U(0x8C8)
+#define RCC_I3C2CFGR				U(0x8CC)
+#define RCC_I3C3CFGR				U(0x8D0)
+#define RCC_MUXSELCFGR				U(0x1000)
+#define RCC_XBAR0CFGR				U(0x1018)
+#define RCC_XBAR1CFGR				U(0x101C)
+#define RCC_XBAR2CFGR				U(0x1020)
+#define RCC_XBAR3CFGR				U(0x1024)
+#define RCC_XBAR4CFGR				U(0x1028)
+#define RCC_XBAR5CFGR				U(0x102C)
+#define RCC_XBAR6CFGR				U(0x1030)
+#define RCC_XBAR7CFGR				U(0x1034)
+#define RCC_XBAR8CFGR				U(0x1038)
+#define RCC_XBAR9CFGR				U(0x103C)
+#define RCC_XBAR10CFGR				U(0x1040)
+#define RCC_XBAR11CFGR				U(0x1044)
+#define RCC_XBAR12CFGR				U(0x1048)
+#define RCC_XBAR13CFGR				U(0x104C)
+#define RCC_XBAR14CFGR				U(0x1050)
+#define RCC_XBAR15CFGR				U(0x1054)
+#define RCC_XBAR16CFGR				U(0x1058)
+#define RCC_XBAR17CFGR				U(0x105C)
+#define RCC_XBAR18CFGR				U(0x1060)
+#define RCC_XBAR19CFGR				U(0x1064)
+#define RCC_XBAR20CFGR				U(0x1068)
+#define RCC_XBAR21CFGR				U(0x106C)
+#define RCC_XBAR22CFGR				U(0x1070)
+#define RCC_XBAR23CFGR				U(0x1074)
+#define RCC_XBAR24CFGR				U(0x1078)
+#define RCC_XBAR25CFGR				U(0x107C)
+#define RCC_XBAR26CFGR				U(0x1080)
+#define RCC_XBAR27CFGR				U(0x1084)
+#define RCC_XBAR28CFGR				U(0x1088)
+#define RCC_XBAR29CFGR				U(0x108C)
+#define RCC_XBAR30CFGR				U(0x1090)
+#define RCC_XBAR31CFGR				U(0x1094)
+#define RCC_XBAR32CFGR				U(0x1098)
+#define RCC_XBAR33CFGR				U(0x109C)
+#define RCC_XBAR34CFGR				U(0x10A0)
+#define RCC_XBAR35CFGR				U(0x10A4)
+#define RCC_XBAR36CFGR				U(0x10A8)
+#define RCC_XBAR37CFGR				U(0x10AC)
+#define RCC_XBAR38CFGR				U(0x10B0)
+#define RCC_XBAR39CFGR				U(0x10B4)
+#define RCC_XBAR40CFGR				U(0x10B8)
+#define RCC_XBAR41CFGR				U(0x10BC)
+#define RCC_XBAR42CFGR				U(0x10C0)
+#define RCC_XBAR43CFGR				U(0x10C4)
+#define RCC_XBAR44CFGR				U(0x10C8)
+#define RCC_XBAR45CFGR				U(0x10CC)
+#define RCC_XBAR46CFGR				U(0x10D0)
+#define RCC_XBAR47CFGR				U(0x10D4)
+#define RCC_XBAR48CFGR				U(0x10D8)
+#define RCC_XBAR49CFGR				U(0x10DC)
+#define RCC_XBAR50CFGR				U(0x10E0)
+#define RCC_XBAR51CFGR				U(0x10E4)
+#define RCC_XBAR52CFGR				U(0x10E8)
+#define RCC_XBAR53CFGR				U(0x10EC)
+#define RCC_XBAR54CFGR				U(0x10F0)
+#define RCC_XBAR55CFGR				U(0x10F4)
+#define RCC_XBAR56CFGR				U(0x10F8)
+#define RCC_XBAR57CFGR				U(0x10FC)
+#define RCC_XBAR58CFGR				U(0x1100)
+#define RCC_XBAR59CFGR				U(0x1104)
+#define RCC_XBAR60CFGR				U(0x1108)
+#define RCC_XBAR61CFGR				U(0x110C)
+#define RCC_XBAR62CFGR				U(0x1110)
+#define RCC_XBAR63CFGR				U(0x1114)
+#define RCC_PREDIV0CFGR				U(0x1118)
+#define RCC_PREDIV1CFGR				U(0x111C)
+#define RCC_PREDIV2CFGR				U(0x1120)
+#define RCC_PREDIV3CFGR				U(0x1124)
+#define RCC_PREDIV4CFGR				U(0x1128)
+#define RCC_PREDIV5CFGR				U(0x112C)
+#define RCC_PREDIV6CFGR				U(0x1130)
+#define RCC_PREDIV7CFGR				U(0x1134)
+#define RCC_PREDIV8CFGR				U(0x1138)
+#define RCC_PREDIV9CFGR				U(0x113C)
+#define RCC_PREDIV10CFGR			U(0x1140)
+#define RCC_PREDIV11CFGR			U(0x1144)
+#define RCC_PREDIV12CFGR			U(0x1148)
+#define RCC_PREDIV13CFGR			U(0x114C)
+#define RCC_PREDIV14CFGR			U(0x1150)
+#define RCC_PREDIV15CFGR			U(0x1154)
+#define RCC_PREDIV16CFGR			U(0x1158)
+#define RCC_PREDIV17CFGR			U(0x115C)
+#define RCC_PREDIV18CFGR			U(0x1160)
+#define RCC_PREDIV19CFGR			U(0x1164)
+#define RCC_PREDIV20CFGR			U(0x1168)
+#define RCC_PREDIV21CFGR			U(0x116C)
+#define RCC_PREDIV22CFGR			U(0x1170)
+#define RCC_PREDIV23CFGR			U(0x1174)
+#define RCC_PREDIV24CFGR			U(0x1178)
+#define RCC_PREDIV25CFGR			U(0x117C)
+#define RCC_PREDIV26CFGR			U(0x1180)
+#define RCC_PREDIV27CFGR			U(0x1184)
+#define RCC_PREDIV28CFGR			U(0x1188)
+#define RCC_PREDIV29CFGR			U(0x118C)
+#define RCC_PREDIV30CFGR			U(0x1190)
+#define RCC_PREDIV31CFGR			U(0x1194)
+#define RCC_PREDIV32CFGR			U(0x1198)
+#define RCC_PREDIV33CFGR			U(0x119C)
+#define RCC_PREDIV34CFGR			U(0x11A0)
+#define RCC_PREDIV35CFGR			U(0x11A4)
+#define RCC_PREDIV36CFGR			U(0x11A8)
+#define RCC_PREDIV37CFGR			U(0x11AC)
+#define RCC_PREDIV38CFGR			U(0x11B0)
+#define RCC_PREDIV39CFGR			U(0x11B4)
+#define RCC_PREDIV40CFGR			U(0x11B8)
+#define RCC_PREDIV41CFGR			U(0x11BC)
+#define RCC_PREDIV42CFGR			U(0x11C0)
+#define RCC_PREDIV43CFGR			U(0x11C4)
+#define RCC_PREDIV44CFGR			U(0x11C8)
+#define RCC_PREDIV45CFGR			U(0x11CC)
+#define RCC_PREDIV46CFGR			U(0x11D0)
+#define RCC_PREDIV47CFGR			U(0x11D4)
+#define RCC_PREDIV48CFGR			U(0x11D8)
+#define RCC_PREDIV49CFGR			U(0x11DC)
+#define RCC_PREDIV50CFGR			U(0x11E0)
+#define RCC_PREDIV51CFGR			U(0x11E4)
+#define RCC_PREDIV52CFGR			U(0x11E8)
+#define RCC_PREDIV53CFGR			U(0x11EC)
+#define RCC_PREDIV54CFGR			U(0x11F0)
+#define RCC_PREDIV55CFGR			U(0x11F4)
+#define RCC_PREDIV56CFGR			U(0x11F8)
+#define RCC_PREDIV57CFGR			U(0x11FC)
+#define RCC_PREDIV58CFGR			U(0x1200)
+#define RCC_PREDIV59CFGR			U(0x1204)
+#define RCC_PREDIV60CFGR			U(0x1208)
+#define RCC_PREDIV61CFGR			U(0x120C)
+#define RCC_PREDIV62CFGR			U(0x1210)
+#define RCC_PREDIV63CFGR			U(0x1214)
+#define RCC_PREDIVSR1				U(0x1218)
+#define RCC_PREDIVSR2				U(0x121C)
+#define RCC_FINDIV0CFGR				U(0x1224)
+#define RCC_FINDIV1CFGR				U(0x1228)
+#define RCC_FINDIV2CFGR				U(0x122C)
+#define RCC_FINDIV3CFGR				U(0x1230)
+#define RCC_FINDIV4CFGR				U(0x1234)
+#define RCC_FINDIV5CFGR				U(0x1238)
+#define RCC_FINDIV6CFGR				U(0x123C)
+#define RCC_FINDIV7CFGR				U(0x1240)
+#define RCC_FINDIV8CFGR				U(0x1244)
+#define RCC_FINDIV9CFGR				U(0x1248)
+#define RCC_FINDIV10CFGR			U(0x124C)
+#define RCC_FINDIV11CFGR			U(0x1250)
+#define RCC_FINDIV12CFGR			U(0x1254)
+#define RCC_FINDIV13CFGR			U(0x1258)
+#define RCC_FINDIV14CFGR			U(0x125C)
+#define RCC_FINDIV15CFGR			U(0x1260)
+#define RCC_FINDIV16CFGR			U(0x1264)
+#define RCC_FINDIV17CFGR			U(0x1268)
+#define RCC_FINDIV18CFGR			U(0x126C)
+#define RCC_FINDIV19CFGR			U(0x1270)
+#define RCC_FINDIV20CFGR			U(0x1274)
+#define RCC_FINDIV21CFGR			U(0x1278)
+#define RCC_FINDIV22CFGR			U(0x127C)
+#define RCC_FINDIV23CFGR			U(0x1280)
+#define RCC_FINDIV24CFGR			U(0x1284)
+#define RCC_FINDIV25CFGR			U(0x1288)
+#define RCC_FINDIV26CFGR			U(0x128C)
+#define RCC_FINDIV27CFGR			U(0x1290)
+#define RCC_FINDIV28CFGR			U(0x1294)
+#define RCC_FINDIV29CFGR			U(0x1298)
+#define RCC_FINDIV30CFGR			U(0x129C)
+#define RCC_FINDIV31CFGR			U(0x12A0)
+#define RCC_FINDIV32CFGR			U(0x12A4)
+#define RCC_FINDIV33CFGR			U(0x12A8)
+#define RCC_FINDIV34CFGR			U(0x12AC)
+#define RCC_FINDIV35CFGR			U(0x12B0)
+#define RCC_FINDIV36CFGR			U(0x12B4)
+#define RCC_FINDIV37CFGR			U(0x12B8)
+#define RCC_FINDIV38CFGR			U(0x12BC)
+#define RCC_FINDIV39CFGR			U(0x12C0)
+#define RCC_FINDIV40CFGR			U(0x12C4)
+#define RCC_FINDIV41CFGR			U(0x12C8)
+#define RCC_FINDIV42CFGR			U(0x12CC)
+#define RCC_FINDIV43CFGR			U(0x12D0)
+#define RCC_FINDIV44CFGR			U(0x12D4)
+#define RCC_FINDIV45CFGR			U(0x12D8)
+#define RCC_FINDIV46CFGR			U(0x12DC)
+#define RCC_FINDIV47CFGR			U(0x12E0)
+#define RCC_FINDIV48CFGR			U(0x12E4)
+#define RCC_FINDIV49CFGR			U(0x12E8)
+#define RCC_FINDIV50CFGR			U(0x12EC)
+#define RCC_FINDIV51CFGR			U(0x12F0)
+#define RCC_FINDIV52CFGR			U(0x12F4)
+#define RCC_FINDIV53CFGR			U(0x12F8)
+#define RCC_FINDIV54CFGR			U(0x12FC)
+#define RCC_FINDIV55CFGR			U(0x1300)
+#define RCC_FINDIV56CFGR			U(0x1304)
+#define RCC_FINDIV57CFGR			U(0x1308)
+#define RCC_FINDIV58CFGR			U(0x130C)
+#define RCC_FINDIV59CFGR			U(0x1310)
+#define RCC_FINDIV60CFGR			U(0x1314)
+#define RCC_FINDIV61CFGR			U(0x1318)
+#define RCC_FINDIV62CFGR			U(0x131C)
+#define RCC_FINDIV63CFGR			U(0x1320)
+#define RCC_FINDIVSR1				U(0x1324)
+#define RCC_FINDIVSR2				U(0x1328)
+#define RCC_FCALCOBS0CFGR			U(0x1340)
+#define RCC_FCALCOBS1CFGR			U(0x1344)
+#define RCC_FCALCREFCFGR			U(0x1348)
+#define RCC_FCALCCR1				U(0x134C)
+#define RCC_FCALCCR2				U(0x1354)
+#define RCC_FCALCSR				U(0x1358)
+#define RCC_PLL4CFGR1				U(0x1360)
+#define RCC_PLL4CFGR2				U(0x1364)
+#define RCC_PLL4CFGR3				U(0x1368)
+#define RCC_PLL4CFGR4				U(0x136C)
+#define RCC_PLL4CFGR5				U(0x1370)
+#define RCC_PLL4CFGR6				U(0x1378)
+#define RCC_PLL4CFGR7				U(0x137C)
+#define RCC_PLL5CFGR1				U(0x1388)
+#define RCC_PLL5CFGR2				U(0x138C)
+#define RCC_PLL5CFGR3				U(0x1390)
+#define RCC_PLL5CFGR4				U(0x1394)
+#define RCC_PLL5CFGR5				U(0x1398)
+#define RCC_PLL5CFGR6				U(0x13A0)
+#define RCC_PLL5CFGR7				U(0x13A4)
+#define RCC_PLL6CFGR1				U(0x13B0)
+#define RCC_PLL6CFGR2				U(0x13B4)
+#define RCC_PLL6CFGR3				U(0x13B8)
+#define RCC_PLL6CFGR4				U(0x13BC)
+#define RCC_PLL6CFGR5				U(0x13C0)
+#define RCC_PLL6CFGR6				U(0x13C8)
+#define RCC_PLL6CFGR7				U(0x13CC)
+#define RCC_PLL7CFGR1				U(0x13D8)
+#define RCC_PLL7CFGR2				U(0x13DC)
+#define RCC_PLL7CFGR3				U(0x13E0)
+#define RCC_PLL7CFGR4				U(0x13E4)
+#define RCC_PLL7CFGR5				U(0x13E8)
+#define RCC_PLL7CFGR6				U(0x13F0)
+#define RCC_PLL7CFGR7				U(0x13F4)
+#define RCC_PLL8CFGR1				U(0x1400)
+#define RCC_PLL8CFGR2				U(0x1404)
+#define RCC_PLL8CFGR3				U(0x1408)
+#define RCC_PLL8CFGR4				U(0x140C)
+#define RCC_PLL8CFGR5				U(0x1410)
+#define RCC_PLL8CFGR6				U(0x1418)
+#define RCC_PLL8CFGR7				U(0x141C)
+#define RCC_VERR				U(0xFFF4)
+#define RCC_IDR					U(0xFFF8)
+#define RCC_SIDR				U(0xFFFC)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET			U(4)
+
+/* RCC_SECCFGR3 register fields */
+#define RCC_SECCFGR3_SEC_MASK			GENMASK_32(17, 0)
+#define RCC_SECCFGR3_SEC_SHIFT			0
+
+/* RCC_PRIVCFGR3 register fields */
+#define RCC_PRIVCFGR3_PRIV_MASK			GENMASK_32(17, 0)
+#define RCC_PRIVCFGR3_PRIV_SHIFT		0
+
+/* RCC_RCFGLOCKR3 register fields */
+#define RCC_RCFGLOCKR3_RLOCK_MASK		GENMASK_32(17, 0)
+#define RCC_RCFGLOCKR3_RLOCK_SHIFT		0
+
+/* RCC_R0CIDCFGR register fields */
+#define RCC_R0CIDCFGR_CFEN			BIT(0)
+#define RCC_R0CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R0CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R0CIDCFGR_SCID_SHIFT		4
+#define RCC_R0CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R0CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R0SEMCR register fields */
+#define RCC_R0SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R0SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R0SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R1CIDCFGR register fields */
+#define RCC_R1CIDCFGR_CFEN			BIT(0)
+#define RCC_R1CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R1CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R1CIDCFGR_SCID_SHIFT		4
+#define RCC_R1CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R1CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R1SEMCR register fields */
+#define RCC_R1SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R1SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R1SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R2CIDCFGR register fields */
+#define RCC_R2CIDCFGR_CFEN			BIT(0)
+#define RCC_R2CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R2CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R2CIDCFGR_SCID_SHIFT		4
+#define RCC_R2CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R2CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R2SEMCR register fields */
+#define RCC_R2SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R2SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R2SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R3CIDCFGR register fields */
+#define RCC_R3CIDCFGR_CFEN			BIT(0)
+#define RCC_R3CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R3CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R3CIDCFGR_SCID_SHIFT		4
+#define RCC_R3CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R3CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R3SEMCR register fields */
+#define RCC_R3SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R3SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R3SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R4CIDCFGR register fields */
+#define RCC_R4CIDCFGR_CFEN			BIT(0)
+#define RCC_R4CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R4CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R4CIDCFGR_SCID_SHIFT		4
+#define RCC_R4CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R4CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R4SEMCR register fields */
+#define RCC_R4SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R4SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R4SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R5CIDCFGR register fields */
+#define RCC_R5CIDCFGR_CFEN			BIT(0)
+#define RCC_R5CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R5CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R5CIDCFGR_SCID_SHIFT		4
+#define RCC_R5CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R5CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R5SEMCR register fields */
+#define RCC_R5SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R5SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R5SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R6CIDCFGR register fields */
+#define RCC_R6CIDCFGR_CFEN			BIT(0)
+#define RCC_R6CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R6CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R6CIDCFGR_SCID_SHIFT		4
+#define RCC_R6CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R6CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R6SEMCR register fields */
+#define RCC_R6SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R6SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R6SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R7CIDCFGR register fields */
+#define RCC_R7CIDCFGR_CFEN			BIT(0)
+#define RCC_R7CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R7CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R7CIDCFGR_SCID_SHIFT		4
+#define RCC_R7CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R7CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R7SEMCR register fields */
+#define RCC_R7SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R7SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R7SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R8CIDCFGR register fields */
+#define RCC_R8CIDCFGR_CFEN			BIT(0)
+#define RCC_R8CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R8CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R8CIDCFGR_SCID_SHIFT		4
+#define RCC_R8CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R8CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R8SEMCR register fields */
+#define RCC_R8SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R8SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R8SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R9CIDCFGR register fields */
+#define RCC_R9CIDCFGR_CFEN			BIT(0)
+#define RCC_R9CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R9CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R9CIDCFGR_SCID_SHIFT		4
+#define RCC_R9CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R9CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R9SEMCR register fields */
+#define RCC_R9SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R9SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R9SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R10CIDCFGR register fields */
+#define RCC_R10CIDCFGR_CFEN			BIT(0)
+#define RCC_R10CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R10CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R10CIDCFGR_SCID_SHIFT		4
+#define RCC_R10CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R10CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R10SEMCR register fields */
+#define RCC_R10SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R10SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R10SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R11CIDCFGR register fields */
+#define RCC_R11CIDCFGR_CFEN			BIT(0)
+#define RCC_R11CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R11CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R11CIDCFGR_SCID_SHIFT		4
+#define RCC_R11CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R11CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R11SEMCR register fields */
+#define RCC_R11SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R11SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R11SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R12CIDCFGR register fields */
+#define RCC_R12CIDCFGR_CFEN			BIT(0)
+#define RCC_R12CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R12CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R12CIDCFGR_SCID_SHIFT		4
+#define RCC_R12CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R12CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R12SEMCR register fields */
+#define RCC_R12SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R12SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R12SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R13CIDCFGR register fields */
+#define RCC_R13CIDCFGR_CFEN			BIT(0)
+#define RCC_R13CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R13CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R13CIDCFGR_SCID_SHIFT		4
+#define RCC_R13CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R13CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R13SEMCR register fields */
+#define RCC_R13SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R13SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R13SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R14CIDCFGR register fields */
+#define RCC_R14CIDCFGR_CFEN			BIT(0)
+#define RCC_R14CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R14CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R14CIDCFGR_SCID_SHIFT		4
+#define RCC_R14CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R14CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R14SEMCR register fields */
+#define RCC_R14SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R14SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R14SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R15CIDCFGR register fields */
+#define RCC_R15CIDCFGR_CFEN			BIT(0)
+#define RCC_R15CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R15CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R15CIDCFGR_SCID_SHIFT		4
+#define RCC_R15CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R15CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R15SEMCR register fields */
+#define RCC_R15SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R15SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R15SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R16CIDCFGR register fields */
+#define RCC_R16CIDCFGR_CFEN			BIT(0)
+#define RCC_R16CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R16CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R16CIDCFGR_SCID_SHIFT		4
+#define RCC_R16CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R16CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R16SEMCR register fields */
+#define RCC_R16SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R16SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R16SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R17CIDCFGR register fields */
+#define RCC_R17CIDCFGR_CFEN			BIT(0)
+#define RCC_R17CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R17CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R17CIDCFGR_SCID_SHIFT		4
+#define RCC_R17CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R17CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R17SEMCR register fields */
+#define RCC_R17SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R17SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R17SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R18CIDCFGR register fields */
+#define RCC_R18CIDCFGR_CFEN			BIT(0)
+#define RCC_R18CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R18CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R18CIDCFGR_SCID_SHIFT		4
+#define RCC_R18CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R18CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R18SEMCR register fields */
+#define RCC_R18SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R18SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R18SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R19CIDCFGR register fields */
+#define RCC_R19CIDCFGR_CFEN			BIT(0)
+#define RCC_R19CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R19CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R19CIDCFGR_SCID_SHIFT		4
+#define RCC_R19CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R19CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R19SEMCR register fields */
+#define RCC_R19SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R19SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R19SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R20CIDCFGR register fields */
+#define RCC_R20CIDCFGR_CFEN			BIT(0)
+#define RCC_R20CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R20CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R20CIDCFGR_SCID_SHIFT		4
+#define RCC_R20CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R20CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R20SEMCR register fields */
+#define RCC_R20SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R20SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R20SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R21CIDCFGR register fields */
+#define RCC_R21CIDCFGR_CFEN			BIT(0)
+#define RCC_R21CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R21CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R21CIDCFGR_SCID_SHIFT		4
+#define RCC_R21CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R21CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R21SEMCR register fields */
+#define RCC_R21SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R21SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R21SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R22CIDCFGR register fields */
+#define RCC_R22CIDCFGR_CFEN			BIT(0)
+#define RCC_R22CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R22CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R22CIDCFGR_SCID_SHIFT		4
+#define RCC_R22CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R22CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R22SEMCR register fields */
+#define RCC_R22SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R22SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R22SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R23CIDCFGR register fields */
+#define RCC_R23CIDCFGR_CFEN			BIT(0)
+#define RCC_R23CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R23CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R23CIDCFGR_SCID_SHIFT		4
+#define RCC_R23CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R23CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R23SEMCR register fields */
+#define RCC_R23SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R23SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R23SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R24CIDCFGR register fields */
+#define RCC_R24CIDCFGR_CFEN			BIT(0)
+#define RCC_R24CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R24CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R24CIDCFGR_SCID_SHIFT		4
+#define RCC_R24CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R24CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R24SEMCR register fields */
+#define RCC_R24SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R24SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R24SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R25CIDCFGR register fields */
+#define RCC_R25CIDCFGR_CFEN			BIT(0)
+#define RCC_R25CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R25CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R25CIDCFGR_SCID_SHIFT		4
+#define RCC_R25CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R25CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R25SEMCR register fields */
+#define RCC_R25SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R25SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R25SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R26CIDCFGR register fields */
+#define RCC_R26CIDCFGR_CFEN			BIT(0)
+#define RCC_R26CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R26CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R26CIDCFGR_SCID_SHIFT		4
+#define RCC_R26CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R26CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R26SEMCR register fields */
+#define RCC_R26SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R26SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R26SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R27CIDCFGR register fields */
+#define RCC_R27CIDCFGR_CFEN			BIT(0)
+#define RCC_R27CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R27CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R27CIDCFGR_SCID_SHIFT		4
+#define RCC_R27CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R27CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R27SEMCR register fields */
+#define RCC_R27SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R27SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R27SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R28CIDCFGR register fields */
+#define RCC_R28CIDCFGR_CFEN			BIT(0)
+#define RCC_R28CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R28CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R28CIDCFGR_SCID_SHIFT		4
+#define RCC_R28CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R28CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R28SEMCR register fields */
+#define RCC_R28SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R28SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R28SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R29CIDCFGR register fields */
+#define RCC_R29CIDCFGR_CFEN			BIT(0)
+#define RCC_R29CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R29CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R29CIDCFGR_SCID_SHIFT		4
+#define RCC_R29CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R29CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R29SEMCR register fields */
+#define RCC_R29SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R29SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R29SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R30CIDCFGR register fields */
+#define RCC_R30CIDCFGR_CFEN			BIT(0)
+#define RCC_R30CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R30CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R30CIDCFGR_SCID_SHIFT		4
+#define RCC_R30CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R30CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R30SEMCR register fields */
+#define RCC_R30SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R30SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R30SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R31CIDCFGR register fields */
+#define RCC_R31CIDCFGR_CFEN			BIT(0)
+#define RCC_R31CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R31CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R31CIDCFGR_SCID_SHIFT		4
+#define RCC_R31CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R31CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R31SEMCR register fields */
+#define RCC_R31SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R31SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R31SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R32CIDCFGR register fields */
+#define RCC_R32CIDCFGR_CFEN			BIT(0)
+#define RCC_R32CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R32CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R32CIDCFGR_SCID_SHIFT		4
+#define RCC_R32CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R32CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R32SEMCR register fields */
+#define RCC_R32SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R32SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R32SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R33CIDCFGR register fields */
+#define RCC_R33CIDCFGR_CFEN			BIT(0)
+#define RCC_R33CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R33CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R33CIDCFGR_SCID_SHIFT		4
+#define RCC_R33CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R33CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R33SEMCR register fields */
+#define RCC_R33SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R33SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R33SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R34CIDCFGR register fields */
+#define RCC_R34CIDCFGR_CFEN			BIT(0)
+#define RCC_R34CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R34CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R34CIDCFGR_SCID_SHIFT		4
+#define RCC_R34CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R34CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R34SEMCR register fields */
+#define RCC_R34SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R34SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R34SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R35CIDCFGR register fields */
+#define RCC_R35CIDCFGR_CFEN			BIT(0)
+#define RCC_R35CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R35CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R35CIDCFGR_SCID_SHIFT		4
+#define RCC_R35CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R35CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R35SEMCR register fields */
+#define RCC_R35SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R35SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R35SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R36CIDCFGR register fields */
+#define RCC_R36CIDCFGR_CFEN			BIT(0)
+#define RCC_R36CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R36CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R36CIDCFGR_SCID_SHIFT		4
+#define RCC_R36CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R36CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R36SEMCR register fields */
+#define RCC_R36SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R36SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R36SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R37CIDCFGR register fields */
+#define RCC_R37CIDCFGR_CFEN			BIT(0)
+#define RCC_R37CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R37CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R37CIDCFGR_SCID_SHIFT		4
+#define RCC_R37CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R37CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R37SEMCR register fields */
+#define RCC_R37SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R37SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R37SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R38CIDCFGR register fields */
+#define RCC_R38CIDCFGR_CFEN			BIT(0)
+#define RCC_R38CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R38CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R38CIDCFGR_SCID_SHIFT		4
+#define RCC_R38CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R38CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R38SEMCR register fields */
+#define RCC_R38SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R38SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R38SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R39CIDCFGR register fields */
+#define RCC_R39CIDCFGR_CFEN			BIT(0)
+#define RCC_R39CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R39CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R39CIDCFGR_SCID_SHIFT		4
+#define RCC_R39CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R39CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R39SEMCR register fields */
+#define RCC_R39SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R39SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R39SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R40CIDCFGR register fields */
+#define RCC_R40CIDCFGR_CFEN			BIT(0)
+#define RCC_R40CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R40CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R40CIDCFGR_SCID_SHIFT		4
+#define RCC_R40CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R40CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R40SEMCR register fields */
+#define RCC_R40SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R40SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R40SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R41CIDCFGR register fields */
+#define RCC_R41CIDCFGR_CFEN			BIT(0)
+#define RCC_R41CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R41CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R41CIDCFGR_SCID_SHIFT		4
+#define RCC_R41CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R41CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R41SEMCR register fields */
+#define RCC_R41SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R41SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R41SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R42CIDCFGR register fields */
+#define RCC_R42CIDCFGR_CFEN			BIT(0)
+#define RCC_R42CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R42CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R42CIDCFGR_SCID_SHIFT		4
+#define RCC_R42CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R42CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R42SEMCR register fields */
+#define RCC_R42SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R42SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R42SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R43CIDCFGR register fields */
+#define RCC_R43CIDCFGR_CFEN			BIT(0)
+#define RCC_R43CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R43CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R43CIDCFGR_SCID_SHIFT		4
+#define RCC_R43CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R43CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R43SEMCR register fields */
+#define RCC_R43SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R43SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R43SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R44CIDCFGR register fields */
+#define RCC_R44CIDCFGR_CFEN			BIT(0)
+#define RCC_R44CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R44CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R44CIDCFGR_SCID_SHIFT		4
+#define RCC_R44CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R44CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R44SEMCR register fields */
+#define RCC_R44SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R44SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R44SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R45CIDCFGR register fields */
+#define RCC_R45CIDCFGR_CFEN			BIT(0)
+#define RCC_R45CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R45CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R45CIDCFGR_SCID_SHIFT		4
+#define RCC_R45CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R45CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R45SEMCR register fields */
+#define RCC_R45SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R45SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R45SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R46CIDCFGR register fields */
+#define RCC_R46CIDCFGR_CFEN			BIT(0)
+#define RCC_R46CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R46CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R46CIDCFGR_SCID_SHIFT		4
+#define RCC_R46CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R46CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R46SEMCR register fields */
+#define RCC_R46SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R46SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R46SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R47CIDCFGR register fields */
+#define RCC_R47CIDCFGR_CFEN			BIT(0)
+#define RCC_R47CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R47CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R47CIDCFGR_SCID_SHIFT		4
+#define RCC_R47CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R47CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R47SEMCR register fields */
+#define RCC_R47SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R47SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R47SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R48CIDCFGR register fields */
+#define RCC_R48CIDCFGR_CFEN			BIT(0)
+#define RCC_R48CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R48CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R48CIDCFGR_SCID_SHIFT		4
+#define RCC_R48CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R48CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R48SEMCR register fields */
+#define RCC_R48SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R48SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R48SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R49CIDCFGR register fields */
+#define RCC_R49CIDCFGR_CFEN			BIT(0)
+#define RCC_R49CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R49CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R49CIDCFGR_SCID_SHIFT		4
+#define RCC_R49CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R49CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R49SEMCR register fields */
+#define RCC_R49SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R49SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R49SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R50CIDCFGR register fields */
+#define RCC_R50CIDCFGR_CFEN			BIT(0)
+#define RCC_R50CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R50CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R50CIDCFGR_SCID_SHIFT		4
+#define RCC_R50CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R50CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R50SEMCR register fields */
+#define RCC_R50SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R50SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R50SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R51CIDCFGR register fields */
+#define RCC_R51CIDCFGR_CFEN			BIT(0)
+#define RCC_R51CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R51CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R51CIDCFGR_SCID_SHIFT		4
+#define RCC_R51CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R51CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R51SEMCR register fields */
+#define RCC_R51SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R51SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R51SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R52CIDCFGR register fields */
+#define RCC_R52CIDCFGR_CFEN			BIT(0)
+#define RCC_R52CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R52CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R52CIDCFGR_SCID_SHIFT		4
+#define RCC_R52CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R52CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R52SEMCR register fields */
+#define RCC_R52SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R52SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R52SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R53CIDCFGR register fields */
+#define RCC_R53CIDCFGR_CFEN			BIT(0)
+#define RCC_R53CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R53CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R53CIDCFGR_SCID_SHIFT		4
+#define RCC_R53CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R53CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R53SEMCR register fields */
+#define RCC_R53SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R53SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R53SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R54CIDCFGR register fields */
+#define RCC_R54CIDCFGR_CFEN			BIT(0)
+#define RCC_R54CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R54CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R54CIDCFGR_SCID_SHIFT		4
+#define RCC_R54CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R54CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R54SEMCR register fields */
+#define RCC_R54SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R54SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R54SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R55CIDCFGR register fields */
+#define RCC_R55CIDCFGR_CFEN			BIT(0)
+#define RCC_R55CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R55CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R55CIDCFGR_SCID_SHIFT		4
+#define RCC_R55CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R55CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R55SEMCR register fields */
+#define RCC_R55SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R55SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R55SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R56CIDCFGR register fields */
+#define RCC_R56CIDCFGR_CFEN			BIT(0)
+#define RCC_R56CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R56CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R56CIDCFGR_SCID_SHIFT		4
+#define RCC_R56CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R56CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R56SEMCR register fields */
+#define RCC_R56SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R56SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R56SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R57CIDCFGR register fields */
+#define RCC_R57CIDCFGR_CFEN			BIT(0)
+#define RCC_R57CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R57CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R57CIDCFGR_SCID_SHIFT		4
+#define RCC_R57CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R57CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R57SEMCR register fields */
+#define RCC_R57SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R57SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R57SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R58CIDCFGR register fields */
+#define RCC_R58CIDCFGR_CFEN			BIT(0)
+#define RCC_R58CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R58CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R58CIDCFGR_SCID_SHIFT		4
+#define RCC_R58CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R58CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R58SEMCR register fields */
+#define RCC_R58SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R58SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R58SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R59CIDCFGR register fields */
+#define RCC_R59CIDCFGR_CFEN			BIT(0)
+#define RCC_R59CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R59CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R59CIDCFGR_SCID_SHIFT		4
+#define RCC_R59CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R59CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R59SEMCR register fields */
+#define RCC_R59SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R59SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R59SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R60CIDCFGR register fields */
+#define RCC_R60CIDCFGR_CFEN			BIT(0)
+#define RCC_R60CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R60CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R60CIDCFGR_SCID_SHIFT		4
+#define RCC_R60CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R60CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R60SEMCR register fields */
+#define RCC_R60SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R60SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R60SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R61CIDCFGR register fields */
+#define RCC_R61CIDCFGR_CFEN			BIT(0)
+#define RCC_R61CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R61CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R61CIDCFGR_SCID_SHIFT		4
+#define RCC_R61CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R61CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R61SEMCR register fields */
+#define RCC_R61SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R61SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R61SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R62CIDCFGR register fields */
+#define RCC_R62CIDCFGR_CFEN			BIT(0)
+#define RCC_R62CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R62CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R62CIDCFGR_SCID_SHIFT		4
+#define RCC_R62CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R62CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R62SEMCR register fields */
+#define RCC_R62SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R62SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R62SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R63CIDCFGR register fields */
+#define RCC_R63CIDCFGR_CFEN			BIT(0)
+#define RCC_R63CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R63CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R63CIDCFGR_SCID_SHIFT		4
+#define RCC_R63CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R63CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R63SEMCR register fields */
+#define RCC_R63SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R63SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R63SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R64CIDCFGR register fields */
+#define RCC_R64CIDCFGR_CFEN			BIT(0)
+#define RCC_R64CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R64CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R64CIDCFGR_SCID_SHIFT		4
+#define RCC_R64CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R64CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R64SEMCR register fields */
+#define RCC_R64SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R64SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R64SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R65CIDCFGR register fields */
+#define RCC_R65CIDCFGR_CFEN			BIT(0)
+#define RCC_R65CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R65CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R65CIDCFGR_SCID_SHIFT		4
+#define RCC_R65CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R65CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R65SEMCR register fields */
+#define RCC_R65SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R65SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R65SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R66CIDCFGR register fields */
+#define RCC_R66CIDCFGR_CFEN			BIT(0)
+#define RCC_R66CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R66CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R66CIDCFGR_SCID_SHIFT		4
+#define RCC_R66CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R66CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R66SEMCR register fields */
+#define RCC_R66SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R66SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R66SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R67CIDCFGR register fields */
+#define RCC_R67CIDCFGR_CFEN			BIT(0)
+#define RCC_R67CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R67CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R67CIDCFGR_SCID_SHIFT		4
+#define RCC_R67CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R67CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R67SEMCR register fields */
+#define RCC_R67SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R67SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R67SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R68CIDCFGR register fields */
+#define RCC_R68CIDCFGR_CFEN			BIT(0)
+#define RCC_R68CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R68CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R68CIDCFGR_SCID_SHIFT		4
+#define RCC_R68CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R68CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R68SEMCR register fields */
+#define RCC_R68SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R68SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R68SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R69CIDCFGR register fields */
+#define RCC_R69CIDCFGR_CFEN			BIT(0)
+#define RCC_R69CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R69CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R69CIDCFGR_SCID_SHIFT		4
+#define RCC_R69CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R69CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R69SEMCR register fields */
+#define RCC_R69SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R69SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R69SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R70CIDCFGR register fields */
+#define RCC_R70CIDCFGR_CFEN			BIT(0)
+#define RCC_R70CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R70CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R70CIDCFGR_SCID_SHIFT		4
+#define RCC_R70CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R70CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R70SEMCR register fields */
+#define RCC_R70SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R70SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R70SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R71CIDCFGR register fields */
+#define RCC_R71CIDCFGR_CFEN			BIT(0)
+#define RCC_R71CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R71CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R71CIDCFGR_SCID_SHIFT		4
+#define RCC_R71CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R71CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R71SEMCR register fields */
+#define RCC_R71SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R71SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R71SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R72CIDCFGR register fields */
+#define RCC_R72CIDCFGR_CFEN			BIT(0)
+#define RCC_R72CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R72CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R72CIDCFGR_SCID_SHIFT		4
+#define RCC_R72CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R72CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R72SEMCR register fields */
+#define RCC_R72SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R72SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R72SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R73CIDCFGR register fields */
+#define RCC_R73CIDCFGR_CFEN			BIT(0)
+#define RCC_R73CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R73CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R73CIDCFGR_SCID_SHIFT		4
+#define RCC_R73CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R73CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R73SEMCR register fields */
+#define RCC_R73SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R73SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R73SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R74CIDCFGR register fields */
+#define RCC_R74CIDCFGR_CFEN			BIT(0)
+#define RCC_R74CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R74CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R74CIDCFGR_SCID_SHIFT		4
+#define RCC_R74CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R74CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R74SEMCR register fields */
+#define RCC_R74SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R74SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R74SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R75CIDCFGR register fields */
+#define RCC_R75CIDCFGR_CFEN			BIT(0)
+#define RCC_R75CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R75CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R75CIDCFGR_SCID_SHIFT		4
+#define RCC_R75CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R75CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R75SEMCR register fields */
+#define RCC_R75SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R75SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R75SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R76CIDCFGR register fields */
+#define RCC_R76CIDCFGR_CFEN			BIT(0)
+#define RCC_R76CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R76CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R76CIDCFGR_SCID_SHIFT		4
+#define RCC_R76CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R76CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R76SEMCR register fields */
+#define RCC_R76SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R76SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R76SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R77CIDCFGR register fields */
+#define RCC_R77CIDCFGR_CFEN			BIT(0)
+#define RCC_R77CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R77CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R77CIDCFGR_SCID_SHIFT		4
+#define RCC_R77CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R77CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R77SEMCR register fields */
+#define RCC_R77SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R77SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R77SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R78CIDCFGR register fields */
+#define RCC_R78CIDCFGR_CFEN			BIT(0)
+#define RCC_R78CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R78CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R78CIDCFGR_SCID_SHIFT		4
+#define RCC_R78CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R78CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R78SEMCR register fields */
+#define RCC_R78SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R78SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R78SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R79CIDCFGR register fields */
+#define RCC_R79CIDCFGR_CFEN			BIT(0)
+#define RCC_R79CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R79CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R79CIDCFGR_SCID_SHIFT		4
+#define RCC_R79CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R79CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R79SEMCR register fields */
+#define RCC_R79SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R79SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R79SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R80CIDCFGR register fields */
+#define RCC_R80CIDCFGR_CFEN			BIT(0)
+#define RCC_R80CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R80CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R80CIDCFGR_SCID_SHIFT		4
+#define RCC_R80CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R80CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R80SEMCR register fields */
+#define RCC_R80SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R80SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R80SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R81CIDCFGR register fields */
+#define RCC_R81CIDCFGR_CFEN			BIT(0)
+#define RCC_R81CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R81CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R81CIDCFGR_SCID_SHIFT		4
+#define RCC_R81CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R81CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R81SEMCR register fields */
+#define RCC_R81SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R81SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R81SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R82CIDCFGR register fields */
+#define RCC_R82CIDCFGR_CFEN			BIT(0)
+#define RCC_R82CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R82CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R82CIDCFGR_SCID_SHIFT		4
+#define RCC_R82CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R82CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R82SEMCR register fields */
+#define RCC_R82SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R82SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R82SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R83CIDCFGR register fields */
+#define RCC_R83CIDCFGR_CFEN			BIT(0)
+#define RCC_R83CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R83CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R83CIDCFGR_SCID_SHIFT		4
+#define RCC_R83CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R83CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R83SEMCR register fields */
+#define RCC_R83SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R83SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R83SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R84CIDCFGR register fields */
+#define RCC_R84CIDCFGR_CFEN			BIT(0)
+#define RCC_R84CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R84CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R84CIDCFGR_SCID_SHIFT		4
+#define RCC_R84CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R84CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R84SEMCR register fields */
+#define RCC_R84SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R84SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R84SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R85CIDCFGR register fields */
+#define RCC_R85CIDCFGR_CFEN			BIT(0)
+#define RCC_R85CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R85CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R85CIDCFGR_SCID_SHIFT		4
+#define RCC_R85CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R85CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R85SEMCR register fields */
+#define RCC_R85SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R85SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R85SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R86CIDCFGR register fields */
+#define RCC_R86CIDCFGR_CFEN			BIT(0)
+#define RCC_R86CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R86CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R86CIDCFGR_SCID_SHIFT		4
+#define RCC_R86CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R86CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R86SEMCR register fields */
+#define RCC_R86SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R86SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R86SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R87CIDCFGR register fields */
+#define RCC_R87CIDCFGR_CFEN			BIT(0)
+#define RCC_R87CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R87CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R87CIDCFGR_SCID_SHIFT		4
+#define RCC_R87CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R87CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R87SEMCR register fields */
+#define RCC_R87SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R87SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R87SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R88CIDCFGR register fields */
+#define RCC_R88CIDCFGR_CFEN			BIT(0)
+#define RCC_R88CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R88CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R88CIDCFGR_SCID_SHIFT		4
+#define RCC_R88CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R88CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R88SEMCR register fields */
+#define RCC_R88SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R88SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R88SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R89CIDCFGR register fields */
+#define RCC_R89CIDCFGR_CFEN			BIT(0)
+#define RCC_R89CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R89CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R89CIDCFGR_SCID_SHIFT		4
+#define RCC_R89CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R89CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R89SEMCR register fields */
+#define RCC_R89SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R89SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R89SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R90CIDCFGR register fields */
+#define RCC_R90CIDCFGR_CFEN			BIT(0)
+#define RCC_R90CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R90CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R90CIDCFGR_SCID_SHIFT		4
+#define RCC_R90CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R90CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R90SEMCR register fields */
+#define RCC_R90SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R90SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R90SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R91CIDCFGR register fields */
+#define RCC_R91CIDCFGR_CFEN			BIT(0)
+#define RCC_R91CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R91CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R91CIDCFGR_SCID_SHIFT		4
+#define RCC_R91CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R91CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R91SEMCR register fields */
+#define RCC_R91SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R91SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R91SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R92CIDCFGR register fields */
+#define RCC_R92CIDCFGR_CFEN			BIT(0)
+#define RCC_R92CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R92CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R92CIDCFGR_SCID_SHIFT		4
+#define RCC_R92CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R92CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R92SEMCR register fields */
+#define RCC_R92SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R92SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R92SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R93CIDCFGR register fields */
+#define RCC_R93CIDCFGR_CFEN			BIT(0)
+#define RCC_R93CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R93CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R93CIDCFGR_SCID_SHIFT		4
+#define RCC_R93CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R93CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R93SEMCR register fields */
+#define RCC_R93SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R93SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R93SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R94CIDCFGR register fields */
+#define RCC_R94CIDCFGR_CFEN			BIT(0)
+#define RCC_R94CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R94CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R94CIDCFGR_SCID_SHIFT		4
+#define RCC_R94CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R94CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R94SEMCR register fields */
+#define RCC_R94SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R94SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R94SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R95CIDCFGR register fields */
+#define RCC_R95CIDCFGR_CFEN			BIT(0)
+#define RCC_R95CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R95CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R95CIDCFGR_SCID_SHIFT		4
+#define RCC_R95CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R95CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R95SEMCR register fields */
+#define RCC_R95SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R95SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R95SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R96CIDCFGR register fields */
+#define RCC_R96CIDCFGR_CFEN			BIT(0)
+#define RCC_R96CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R96CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R96CIDCFGR_SCID_SHIFT		4
+#define RCC_R96CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R96CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R96SEMCR register fields */
+#define RCC_R96SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R96SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R96SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R97CIDCFGR register fields */
+#define RCC_R97CIDCFGR_CFEN			BIT(0)
+#define RCC_R97CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R97CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R97CIDCFGR_SCID_SHIFT		4
+#define RCC_R97CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R97CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R97SEMCR register fields */
+#define RCC_R97SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R97SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R97SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R98CIDCFGR register fields */
+#define RCC_R98CIDCFGR_CFEN			BIT(0)
+#define RCC_R98CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R98CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R98CIDCFGR_SCID_SHIFT		4
+#define RCC_R98CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R98CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R98SEMCR register fields */
+#define RCC_R98SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R98SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R98SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R99CIDCFGR register fields */
+#define RCC_R99CIDCFGR_CFEN			BIT(0)
+#define RCC_R99CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R99CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R99CIDCFGR_SCID_SHIFT		4
+#define RCC_R99CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R99CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R99SEMCR register fields */
+#define RCC_R99SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R99SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R99SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R100CIDCFGR register fields */
+#define RCC_R100CIDCFGR_CFEN			BIT(0)
+#define RCC_R100CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R100CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R100CIDCFGR_SCID_SHIFT		4
+#define RCC_R100CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R100CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R100SEMCR register fields */
+#define RCC_R100SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R100SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R100SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R101CIDCFGR register fields */
+#define RCC_R101CIDCFGR_CFEN			BIT(0)
+#define RCC_R101CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R101CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R101CIDCFGR_SCID_SHIFT		4
+#define RCC_R101CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R101CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R101SEMCR register fields */
+#define RCC_R101SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R101SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R101SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R102CIDCFGR register fields */
+#define RCC_R102CIDCFGR_CFEN			BIT(0)
+#define RCC_R102CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R102CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R102CIDCFGR_SCID_SHIFT		4
+#define RCC_R102CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R102CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R102SEMCR register fields */
+#define RCC_R102SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R102SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R102SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R103CIDCFGR register fields */
+#define RCC_R103CIDCFGR_CFEN			BIT(0)
+#define RCC_R103CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R103CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R103CIDCFGR_SCID_SHIFT		4
+#define RCC_R103CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R103CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R103SEMCR register fields */
+#define RCC_R103SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R103SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R103SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R104CIDCFGR register fields */
+#define RCC_R104CIDCFGR_CFEN			BIT(0)
+#define RCC_R104CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R104CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R104CIDCFGR_SCID_SHIFT		4
+#define RCC_R104CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R104CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R104SEMCR register fields */
+#define RCC_R104SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R104SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R104SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R105CIDCFGR register fields */
+#define RCC_R105CIDCFGR_CFEN			BIT(0)
+#define RCC_R105CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R105CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R105CIDCFGR_SCID_SHIFT		4
+#define RCC_R105CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R105CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R105SEMCR register fields */
+#define RCC_R105SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R105SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R105SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R106CIDCFGR register fields */
+#define RCC_R106CIDCFGR_CFEN			BIT(0)
+#define RCC_R106CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R106CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R106CIDCFGR_SCID_SHIFT		4
+#define RCC_R106CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R106CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R106SEMCR register fields */
+#define RCC_R106SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R106SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R106SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R107CIDCFGR register fields */
+#define RCC_R107CIDCFGR_CFEN			BIT(0)
+#define RCC_R107CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R107CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R107CIDCFGR_SCID_SHIFT		4
+#define RCC_R107CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R107CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R107SEMCR register fields */
+#define RCC_R107SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R107SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R107SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R108CIDCFGR register fields */
+#define RCC_R108CIDCFGR_CFEN			BIT(0)
+#define RCC_R108CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R108CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R108CIDCFGR_SCID_SHIFT		4
+#define RCC_R108CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R108CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R108SEMCR register fields */
+#define RCC_R108SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R108SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R108SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R109CIDCFGR register fields */
+#define RCC_R109CIDCFGR_CFEN			BIT(0)
+#define RCC_R109CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R109CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R109CIDCFGR_SCID_SHIFT		4
+#define RCC_R109CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R109CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R109SEMCR register fields */
+#define RCC_R109SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R109SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R109SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R110CIDCFGR register fields */
+#define RCC_R110CIDCFGR_CFEN			BIT(0)
+#define RCC_R110CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R110CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R110CIDCFGR_SCID_SHIFT		4
+#define RCC_R110CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R110CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R110SEMCR register fields */
+#define RCC_R110SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R110SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R110SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R111CIDCFGR register fields */
+#define RCC_R111CIDCFGR_CFEN			BIT(0)
+#define RCC_R111CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R111CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R111CIDCFGR_SCID_SHIFT		4
+#define RCC_R111CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R111CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R111SEMCR register fields */
+#define RCC_R111SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R111SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R111SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R112CIDCFGR register fields */
+#define RCC_R112CIDCFGR_CFEN			BIT(0)
+#define RCC_R112CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R112CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R112CIDCFGR_SCID_SHIFT		4
+#define RCC_R112CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R112CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R112SEMCR register fields */
+#define RCC_R112SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R112SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R112SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R113CIDCFGR register fields */
+#define RCC_R113CIDCFGR_CFEN			BIT(0)
+#define RCC_R113CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R113CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R113CIDCFGR_SCID_SHIFT		4
+#define RCC_R113CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R113CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R113SEMCR register fields */
+#define RCC_R113SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R113SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R113SEMCR_SEMCID_SHIFT		4
+
+/* RCC_RxCIDCFGR register fields */
+#define RCC_RxCIDCFGR_CFEN			BIT(0)
+#define RCC_RxCIDCFGR_SEM_EN			BIT(1)
+#define RCC_RxCIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_RxCIDCFGR_SCID_SHIFT		4
+#define RCC_RxCIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_RxCIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_RxSEMCR register fields */
+#define RCC_RxSEMCR_SEM_MUTEX			BIT(0)
+#define RCC_RxSEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_RxSEMCR_SEMCID_SHIFT		4
+
+/* RCC_GRSTCSETR register fields */
+#define RCC_GRSTCSETR_SYSRST			BIT(0)
+
+/* RCC_C1RSTCSETR register fields */
+#define RCC_C1RSTCSETR_C1RST			BIT(0)
+
+/* RCC_C2RSTCSETR register fields */
+#define RCC_C2RSTCSETR_C2RST			BIT(0)
+
+/* RCC_CxRSTCSETR register fields */
+#define RCC_CxRSTCSETR_CxRST			BIT(0)
+
+/* RCC_HWRSTSCLRR register fields */
+#define RCC_HWRSTSCLRR_PORRSTF			BIT(0)
+#define RCC_HWRSTSCLRR_BORRSTF			BIT(1)
+#define RCC_HWRSTSCLRR_PADRSTF			BIT(2)
+#define RCC_HWRSTSCLRR_HCSSRSTF			BIT(3)
+#define RCC_HWRSTSCLRR_VCORERSTF		BIT(4)
+#define RCC_HWRSTSCLRR_SYSC1RSTF		BIT(5)
+#define RCC_HWRSTSCLRR_SYSC2RSTF		BIT(6)
+#define RCC_HWRSTSCLRR_IWDG1SYSRSTF		BIT(7)
+#define RCC_HWRSTSCLRR_IWDG2SYSRSTF		BIT(8)
+#define RCC_HWRSTSCLRR_IWDG3SYSRSTF		BIT(9)
+#define RCC_HWRSTSCLRR_IWDG4SYSRSTF		BIT(10)
+#define RCC_HWRSTSCLRR_RETCRCERRRSTF		BIT(12)
+#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF	BIT(13)
+#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF	BIT(14)
+
+/* RCC_C1HWRSTSCLRR register fields */
+#define RCC_C1HWRSTSCLRR_VCPURSTF		BIT(0)
+#define RCC_C1HWRSTSCLRR_C1RSTF			BIT(1)
+
+/* RCC_C2HWRSTSCLRR register fields */
+#define RCC_C2HWRSTSCLRR_C2RSTF			BIT(0)
+
+/* RCC_C1BOOTRSTSSETR register fields */
+#define RCC_C1BOOTRSTSSETR_PORRSTF		BIT(0)
+#define RCC_C1BOOTRSTSSETR_BORRSTF		BIT(1)
+#define RCC_C1BOOTRSTSSETR_PADRSTF		BIT(2)
+#define RCC_C1BOOTRSTSSETR_HCSSRSTF		BIT(3)
+#define RCC_C1BOOTRSTSSETR_VCORERSTF		BIT(4)
+#define RCC_C1BOOTRSTSSETR_VCPURSTF		BIT(5)
+#define RCC_C1BOOTRSTSSETR_SYSC1RSTF		BIT(6)
+#define RCC_C1BOOTRSTSSETR_SYSC2RSTF		BIT(7)
+#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C1BOOTRSTSSETR_C1RSTF		BIT(13)
+#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF	BIT(17)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C1BOOTRSTSSETR_STBYC1RSTF		BIT(20)
+#define RCC_C1BOOTRSTSSETR_D1STBYRSTF		BIT(22)
+#define RCC_C1BOOTRSTSSETR_D2STBYRSTF		BIT(23)
+
+/* RCC_C1BOOTRSTSCLRR register fields */
+#define RCC_C1BOOTRSTSCLRR_PORRSTF		BIT(0)
+#define RCC_C1BOOTRSTSCLRR_BORRSTF		BIT(1)
+#define RCC_C1BOOTRSTSCLRR_PADRSTF		BIT(2)
+#define RCC_C1BOOTRSTSCLRR_HCSSRSTF		BIT(3)
+#define RCC_C1BOOTRSTSCLRR_VCORERSTF		BIT(4)
+#define RCC_C1BOOTRSTSCLRR_VCPURSTF		BIT(5)
+#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF		BIT(6)
+#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF		BIT(7)
+#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C1BOOTRSTSCLRR_C1RSTF		BIT(13)
+#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF	BIT(17)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF		BIT(20)
+#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF		BIT(22)
+#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF		BIT(23)
+
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF)
+
+/* RCC_C2BOOTRSTSSETR register fields */
+#define RCC_C2BOOTRSTSSETR_PORRSTF		BIT(0)
+#define RCC_C2BOOTRSTSSETR_BORRSTF		BIT(1)
+#define RCC_C2BOOTRSTSSETR_PADRSTF		BIT(2)
+#define RCC_C2BOOTRSTSSETR_HCSSRSTF		BIT(3)
+#define RCC_C2BOOTRSTSSETR_VCORERSTF		BIT(4)
+#define RCC_C2BOOTRSTSSETR_SYSC1RSTF		BIT(6)
+#define RCC_C2BOOTRSTSSETR_SYSC2RSTF		BIT(7)
+#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C2BOOTRSTSSETR_C2RSTF		BIT(14)
+#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF	BIT(17)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C2BOOTRSTSSETR_STBYC2RSTF		BIT(21)
+#define RCC_C2BOOTRSTSSETR_D2STBYRSTF		BIT(23)
+
+/* RCC_C2BOOTRSTSCLRR register fields */
+#define RCC_C2BOOTRSTSCLRR_PORRSTF		BIT(0)
+#define RCC_C2BOOTRSTSCLRR_BORRSTF		BIT(1)
+#define RCC_C2BOOTRSTSCLRR_PADRSTF		BIT(2)
+#define RCC_C2BOOTRSTSCLRR_HCSSRSTF		BIT(3)
+#define RCC_C2BOOTRSTSCLRR_VCORERSTF		BIT(4)
+#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF		BIT(6)
+#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF		BIT(7)
+#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C2BOOTRSTSCLRR_C2RSTF		BIT(14)
+#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF	BIT(17)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF		BIT(21)
+#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF		BIT(23)
+
+/* RCC_C1SREQSETR register fields */
+#define RCC_C1SREQSETR_STPREQ_P0		BIT(0)
+#define RCC_C1SREQSETR_STPREQ_P1		BIT(1)
+#define RCC_C1SREQSETR_STPREQ_MASK		GENMASK_32(1, 0)
+#define RCC_C1SREQSETR_ESLPREQ			BIT(16)
+
+/* RCC_C1SREQCLRR register fields */
+#define RCC_C1SREQCLRR_STPREQ_P0		BIT(0)
+#define RCC_C1SREQCLRR_STPREQ_P1		BIT(1)
+#define RCC_C1SREQCLRR_STPREQ_MASK		GENMASK_32(1, 0)
+#define RCC_C1SREQCLRR_ESLPREQ			BIT(16)
+
+/* RCC_CPUBOOTCR register fields */
+#define RCC_CPUBOOTCR_BOOT_CPU2			BIT(0)
+#define RCC_CPUBOOTCR_BOOT_CPU1			BIT(1)
+
+/* RCC_STBYBOOTCR register fields */
+#define RCC_STBYBOOTCR_CPU_BEN_SEL		BIT(1)
+#define RCC_STBYBOOTCR_COLD_CPU2		BIT(2)
+#define RCC_STBYBOOTCR_CPU2_HW_BEN		BIT(4)
+#define RCC_STBYBOOTCR_CPU1_HW_BEN		BIT(5)
+#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN		BIT(8)
+
+/* RCC_LEGBOOTCR register fields */
+#define RCC_LEGBOOTCR_LEGACY_BEN		BIT(0)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON				BIT(0)
+#define RCC_BDCR_LSEBYP				BIT(1)
+#define RCC_BDCR_LSERDY				BIT(2)
+#define RCC_BDCR_LSEDIGBYP			BIT(3)
+#define RCC_BDCR_LSEDRV_MASK			GENMASK_32(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT			4
+#define RCC_BDCR_LSECSSON			BIT(6)
+#define RCC_BDCR_LSEGFON			BIT(7)
+#define RCC_BDCR_LSECSSD			BIT(8)
+#define RCC_BDCR_RTCSRC_MASK			GENMASK_32(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT			16
+#define RCC_BDCR_RTCCKEN			BIT(20)
+#define RCC_BDCR_VSWRST				BIT(31)
+
+/* RCC_RDCR register fields */
+#define RCC_RDCR_MRD_MASK			GENMASK_32(20, 16)
+#define RCC_RDCR_MRD_SHIFT			16
+#define RCC_RDCR_EADLY_MASK			GENMASK_32(27, 24)
+#define RCC_RDCR_EADLY_SHIFT			24
+
+/* RCC_C1MSRDCR register fields */
+#define RCC_C1MSRDCR_C1MSRD_MASK		GENMASK_32(4, 0)
+#define RCC_C1MSRDCR_C1MSRD_SHIFT		0
+#define RCC_C1MSRDCR_C1MSRST			BIT(8)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK		GENMASK_32(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT		0
+#define RCC_PWRLPDLYCR_CPU2TMPSKP		BIT(24)
+
+/* RCC_C1CIESETR register fields */
+#define RCC_C1CIESETR_LSIRDYIE			BIT(0)
+#define RCC_C1CIESETR_LSERDYIE			BIT(1)
+#define RCC_C1CIESETR_HSIRDYIE			BIT(2)
+#define RCC_C1CIESETR_HSERDYIE			BIT(3)
+#define RCC_C1CIESETR_MSIRDYIE			BIT(4)
+#define RCC_C1CIESETR_PLL1RDYIE			BIT(5)
+#define RCC_C1CIESETR_PLL2RDYIE			BIT(6)
+#define RCC_C1CIESETR_PLL3RDYIE			BIT(7)
+#define RCC_C1CIESETR_PLL4RDYIE			BIT(8)
+#define RCC_C1CIESETR_PLL5RDYIE			BIT(9)
+#define RCC_C1CIESETR_PLL6RDYIE			BIT(10)
+#define RCC_C1CIESETR_PLL7RDYIE			BIT(11)
+#define RCC_C1CIESETR_PLL8RDYIE			BIT(12)
+#define RCC_C1CIESETR_LSECSSIE			BIT(16)
+#define RCC_C1CIESETR_WKUPIE			BIT(20)
+
+/* RCC_C1CIFCLRR register fields */
+#define RCC_C1CIFCLRR_LSIRDYF			BIT(0)
+#define RCC_C1CIFCLRR_LSERDYF			BIT(1)
+#define RCC_C1CIFCLRR_HSIRDYF			BIT(2)
+#define RCC_C1CIFCLRR_HSERDYF			BIT(3)
+#define RCC_C1CIFCLRR_MSIRDYF			BIT(4)
+#define RCC_C1CIFCLRR_PLL1RDYF			BIT(5)
+#define RCC_C1CIFCLRR_PLL2RDYF			BIT(6)
+#define RCC_C1CIFCLRR_PLL3RDYF			BIT(7)
+#define RCC_C1CIFCLRR_PLL4RDYF			BIT(8)
+#define RCC_C1CIFCLRR_PLL5RDYF			BIT(9)
+#define RCC_C1CIFCLRR_PLL6RDYF			BIT(10)
+#define RCC_C1CIFCLRR_PLL7RDYF			BIT(11)
+#define RCC_C1CIFCLRR_PLL8RDYF			BIT(12)
+#define RCC_C1CIFCLRR_LSECSSF			BIT(16)
+#define RCC_C1CIFCLRR_WKUPF			BIT(20)
+
+/* RCC_C2CIESETR register fields */
+#define RCC_C2CIESETR_LSIRDYIE			BIT(0)
+#define RCC_C2CIESETR_LSERDYIE			BIT(1)
+#define RCC_C2CIESETR_HSIRDYIE			BIT(2)
+#define RCC_C2CIESETR_HSERDYIE			BIT(3)
+#define RCC_C2CIESETR_MSIRDYIE			BIT(4)
+#define RCC_C2CIESETR_PLL1RDYIE			BIT(5)
+#define RCC_C2CIESETR_PLL2RDYIE			BIT(6)
+#define RCC_C2CIESETR_PLL3RDYIE			BIT(7)
+#define RCC_C2CIESETR_PLL4RDYIE			BIT(8)
+#define RCC_C2CIESETR_PLL5RDYIE			BIT(9)
+#define RCC_C2CIESETR_PLL6RDYIE			BIT(10)
+#define RCC_C2CIESETR_PLL7RDYIE			BIT(11)
+#define RCC_C2CIESETR_PLL8RDYIE			BIT(12)
+#define RCC_C2CIESETR_LSECSSIE			BIT(16)
+#define RCC_C2CIESETR_WKUPIE			BIT(20)
+
+/* RCC_C2CIFCLRR register fields */
+#define RCC_C2CIFCLRR_LSIRDYF			BIT(0)
+#define RCC_C2CIFCLRR_LSERDYF			BIT(1)
+#define RCC_C2CIFCLRR_HSIRDYF			BIT(2)
+#define RCC_C2CIFCLRR_HSERDYF			BIT(3)
+#define RCC_C2CIFCLRR_MSIRDYF			BIT(4)
+#define RCC_C2CIFCLRR_PLL1RDYF			BIT(5)
+#define RCC_C2CIFCLRR_PLL2RDYF			BIT(6)
+#define RCC_C2CIFCLRR_PLL3RDYF			BIT(7)
+#define RCC_C2CIFCLRR_PLL4RDYF			BIT(8)
+#define RCC_C2CIFCLRR_PLL5RDYF			BIT(9)
+#define RCC_C2CIFCLRR_PLL6RDYF			BIT(10)
+#define RCC_C2CIFCLRR_PLL7RDYF			BIT(11)
+#define RCC_C2CIFCLRR_PLL8RDYF			BIT(12)
+#define RCC_C2CIFCLRR_LSECSSF			BIT(16)
+#define RCC_C2CIFCLRR_WKUPF			BIT(20)
+
+/* RCC_CxCIESETR register fields */
+#define RCC_CxCIESETR_LSIRDYIE			BIT(0)
+#define RCC_CxCIESETR_LSERDYIE			BIT(1)
+#define RCC_CxCIESETR_HSIRDYIE			BIT(2)
+#define RCC_CxCIESETR_HSERDYIE			BIT(3)
+#define RCC_CxCIESETR_CSIRDYIE			BIT(4)
+#define RCC_CxCIESETR_SHSIRDYIE			BIT(5)
+#define RCC_CxCIESETR_PLL1RDYIE			BIT(6)
+#define RCC_CxCIESETR_PLL2RDYIE			BIT(7)
+#define RCC_CxCIESETR_PLL3RDYIE			BIT(8)
+#define RCC_CxCIESETR_PLL4RDYIE			BIT(9)
+#define RCC_CxCIESETR_PLL5RDYIE			BIT(10)
+#define RCC_CxCIESETR_PLL6RDYIE			BIT(11)
+#define RCC_CxCIESETR_PLL7RDYIE			BIT(12)
+#define RCC_CxCIESETR_PLL8RDYIE			BIT(13)
+#define RCC_CxCIESETR_LSECSSIE			BIT(16)
+#define RCC_CxCIESETR_WKUPIE			BIT(20)
+
+/* RCC_CxCIFCLRR register fields */
+#define RCC_CxCIFCLRR_LSIRDYF			BIT(0)
+#define RCC_CxCIFCLRR_LSERDYF			BIT(1)
+#define RCC_CxCIFCLRR_HSIRDYF			BIT(2)
+#define RCC_CxCIFCLRR_HSERDYF			BIT(3)
+#define RCC_CxCIFCLRR_CSIRDYF			BIT(4)
+#define RCC_CxCIFCLRR_SHSIRDYF			BIT(5)
+#define RCC_CxCIFCLRR_PLL1RDYF			BIT(6)
+#define RCC_CxCIFCLRR_PLL2RDYF			BIT(7)
+#define RCC_CxCIFCLRR_PLL3RDYF			BIT(8)
+#define RCC_CxCIFCLRR_PLL4RDYF			BIT(9)
+#define RCC_CxCIFCLRR_PLL5RDYF			BIT(10)
+#define RCC_CxCIFCLRR_PLL6RDYF			BIT(11)
+#define RCC_CxCIFCLRR_PLL7RDYF			BIT(12)
+#define RCC_CxCIFCLRR_PLL8RDYF			BIT(13)
+#define RCC_CxCIFCLRR_LSECSSF			BIT(16)
+#define RCC_CxCIFCLRR_WKUPF			BIT(20)
+
+/* RCC_IWDGC1FZSETR register fields */
+#define RCC_IWDGC1FZSETR_FZ_IWDG1		BIT(0)
+#define RCC_IWDGC1FZSETR_FZ_IWDG2		BIT(1)
+
+/* RCC_IWDGC1FZCLRR register fields */
+#define RCC_IWDGC1FZCLRR_FZ_IWDG1		BIT(0)
+#define RCC_IWDGC1FZCLRR_FZ_IWDG2		BIT(1)
+
+/* RCC_IWDGC1CFGSETR register fields */
+#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN	BIT(0)
+#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN	BIT(2)
+#define RCC_IWDGC1CFGSETR_IWDG2_KERRST		BIT(18)
+
+/* RCC_IWDGC1CFGCLRR register fields */
+#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN	BIT(0)
+#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN	BIT(2)
+#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST		BIT(18)
+
+/* RCC_IWDGC2FZSETR register fields */
+#define RCC_IWDGC2FZSETR_FZ_IWDG3		BIT(0)
+#define RCC_IWDGC2FZSETR_FZ_IWDG4		BIT(1)
+
+/* RCC_IWDGC2FZCLRR register fields */
+#define RCC_IWDGC2FZCLRR_FZ_IWDG3		BIT(0)
+#define RCC_IWDGC2FZCLRR_FZ_IWDG4		BIT(1)
+
+/* RCC_IWDGC2CFGSETR register fields */
+#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN	BIT(0)
+#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN	BIT(2)
+#define RCC_IWDGC2CFGSETR_IWDG4_KERRST		BIT(18)
+
+/* RCC_IWDGC2CFGCLRR register fields */
+#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN	BIT(0)
+#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN	BIT(2)
+#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST		BIT(18)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL			BIT(0)
+#define RCC_MCO1CFGR_MCO1ON			BIT(8)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL			BIT(0)
+#define RCC_MCO2CFGR_MCO2ON			BIT(8)
+
+/* RCC_MCOxCFGR register fields */
+#define RCC_MCOxCFGR_MCOxSEL			BIT(0)
+#define RCC_MCOxCFGR_MCOxON			BIT(8)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION			BIT(0)
+#define RCC_OCENSETR_HSIKERON			BIT(1)
+#define RCC_OCENSETR_MSION			BIT(2)
+#define RCC_OCENSETR_MSIKERON			BIT(3)
+#define RCC_OCENSETR_HSEDIV2ON			BIT(5)
+#define RCC_OCENSETR_HSEDIV2BYP			BIT(6)
+#define RCC_OCENSETR_HSEDIGBYP			BIT(7)
+#define RCC_OCENSETR_HSEON			BIT(8)
+#define RCC_OCENSETR_HSEKERON			BIT(9)
+#define RCC_OCENSETR_HSEBYP			BIT(10)
+#define RCC_OCENSETR_HSECSSON			BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION			BIT(0)
+#define RCC_OCENCLRR_HSIKERON			BIT(1)
+#define RCC_OCENCLRR_MSION			BIT(2)
+#define RCC_OCENCLRR_MSIKERON			BIT(3)
+#define RCC_OCENCLRR_HSEDIV2ON			BIT(5)
+#define RCC_OCENCLRR_HSEDIV2BYP			BIT(6)
+#define RCC_OCENCLRR_HSEDIGBYP			BIT(7)
+#define RCC_OCENCLRR_HSEON			BIT(8)
+#define RCC_OCENCLRR_HSEKERON			BIT(9)
+#define RCC_OCENCLRR_HSEBYP			BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY			BIT(0)
+#define RCC_OCRDYR_MSIRDY			BIT(2)
+#define RCC_OCRDYR_HSERDY			BIT(8)
+#define RCC_OCRDYR_CKREST			BIT(25)
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSITRIM_MASK		GENMASK_32(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT		8
+#define RCC_HSICFGR_HSICAL_MASK			GENMASK_32(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT		16
+
+/* RCC_MSICFGR register fields */
+#define RCC_MSICFGR_MSITRIM_MASK		GENMASK_32(12, 8)
+#define RCC_MSICFGR_MSITRIM_SHIFT		8
+#define RCC_MSICFGR_MSICAL_MASK			GENMASK_32(23, 16)
+#define RCC_MSICFGR_MSICAL_SHIFT		16
+
+/* RCC_LSICR register fields */
+#define RCC_LSICR_LSION				BIT(0)
+#define RCC_LSICR_LSIRDY			BIT(1)
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK			GENMASK_32(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT		0
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT		0
+#define RCC_APB1DIVR_APB1DIVRDY			BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT		0
+#define RCC_APB2DIVR_APB2DIVRDY			BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT		0
+#define RCC_APB3DIVR_APB3DIVRDY			BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT		0
+#define RCC_APB4DIVR_APB4DIVRDY			BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT		0
+#define RCC_APB5DIVR_APB5DIVRDY			BIT(31)
+
+/* RCC_APBDBGDIVR register fields */
+#define RCC_APBDBGDIVR_APBDBGDIV_MASK		GENMASK_32(2, 0)
+#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT		0
+#define RCC_APBDBGDIVR_APBDBGDIVRDY		BIT(31)
+
+/* RCC_APBxDIVR register fields */
+#define RCC_APBxDIVR_APBxDIV_MASK		GENMASK_32(2, 0)
+#define RCC_APBxDIVR_APBxDIV_SHIFT		0
+#define RCC_APBxDIVR_APBxDIVRDY			BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE			BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY		BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE			BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY		BIT(31)
+
+/* RCC_TIMGxPRER register fields */
+#define RCC_TIMGxPRER_TIMGxPRE			BIT(0)
+#define RCC_TIMGxPRER_TIMGxPRERDY		BIT(31)
+
+/* RCC_LSMCUDIVR register fields */
+#define RCC_LSMCUDIVR_LSMCUDIV			BIT(0)
+#define RCC_LSMCUDIVR_LSMCUDIVRDY		BIT(31)
+
+/* RCC_DDRCPCFGR register fields */
+#define RCC_DDRCPCFGR_DDRCPRST			BIT(0)
+#define RCC_DDRCPCFGR_DDRCPEN			BIT(1)
+#define RCC_DDRCPCFGR_DDRCPLPEN			BIT(2)
+
+/* RCC_DDRCAPBCFGR register fields */
+#define RCC_DDRCAPBCFGR_DDRCAPBRST		BIT(0)
+#define RCC_DDRCAPBCFGR_DDRCAPBEN		BIT(1)
+#define RCC_DDRCAPBCFGR_DDRCAPBLPEN		BIT(2)
+
+/* RCC_DDRPHYCAPBCFGR register fields */
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST	BIT(0)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN		BIT(1)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN	BIT(2)
+
+/* RCC_DDRPHYCCFGR register fields */
+#define RCC_DDRPHYCCFGR_DDRPHYCEN		BIT(1)
+
+/* RCC_DDRCFGR register fields */
+#define RCC_DDRCFGR_DDRCFGRST			BIT(0)
+#define RCC_DDRCFGR_DDRCFGEN			BIT(1)
+#define RCC_DDRCFGR_DDRCFGLPEN			BIT(2)
+
+/* RCC_DDRITFCFGR register fields */
+#define RCC_DDRITFCFGR_DDRRST			BIT(0)
+#define RCC_DDRITFCFGR_DDRCKMOD_MASK		GENMASK_32(5, 4)
+#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT		4
+#define RCC_DDRITFCFGR_DDRCKMOD_HSR		BIT(5)
+#define RCC_DDRITFCFGR_DDRSHR			BIT(8)
+#define RCC_DDRITFCFGR_DDRPHYDLP		BIT(16)
+
+/* RCC_SYSRAMCFGR register fields */
+#define RCC_SYSRAMCFGR_SYSRAMEN			BIT(1)
+#define RCC_SYSRAMCFGR_SYSRAMLPEN		BIT(2)
+
+/* RCC_SRAM1CFGR register fields */
+#define RCC_SRAM1CFGR_SRAM1EN			BIT(1)
+#define RCC_SRAM1CFGR_SRAM1LPEN			BIT(2)
+
+/* RCC_RETRAMCFGR register fields */
+#define RCC_RETRAMCFGR_RETRAMEN			BIT(1)
+#define RCC_RETRAMCFGR_RETRAMLPEN		BIT(2)
+
+/* RCC_BKPSRAMCFGR register fields */
+#define RCC_BKPSRAMCFGR_BKPSRAMEN		BIT(1)
+#define RCC_BKPSRAMCFGR_BKPSRAMLPEN		BIT(2)
+
+/* RCC_OSPI1CFGR register fields */
+#define RCC_OSPI1CFGR_OSPI1RST			BIT(0)
+#define RCC_OSPI1CFGR_OSPI1EN			BIT(1)
+#define RCC_OSPI1CFGR_OSPI1LPEN			BIT(2)
+#define RCC_OSPI1CFGR_OTFDEC1RST		BIT(8)
+#define RCC_OSPI1CFGR_OSPI1DLLRST		BIT(16)
+
+/* RCC_OSPIxCFGR register fields */
+#define RCC_OSPIxCFGR_OSPIxRST			BIT(0)
+#define RCC_OSPIxCFGR_OSPIxEN			BIT(1)
+#define RCC_OSPIxCFGR_OSPIxLPEN			BIT(2)
+#define RCC_OSPIxCFGR_OTFDECxRST		BIT(8)
+#define RCC_OSPIxCFGR_OSPIxDLLRST		BIT(16)
+
+/* RCC_FMCCFGR register fields */
+#define RCC_FMCCFGR_FMCRST			BIT(0)
+#define RCC_FMCCFGR_FMCEN			BIT(1)
+#define RCC_FMCCFGR_FMCLPEN			BIT(2)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_DBGEN			BIT(8)
+#define RCC_DBGCFGR_TRACEEN			BIT(9)
+#define RCC_DBGCFGR_DBGMCUEN			BIT(10)
+#define RCC_DBGCFGR_DBGRST			BIT(12)
+
+/* RCC_STMCFGR register fields */
+#define RCC_STMCFGR_STMEN			BIT(1)
+#define RCC_STMCFGR_STMLPEN			BIT(2)
+
+/* RCC_ETRCFGR register fields */
+#define RCC_ETRCFGR_ETREN			BIT(1)
+#define RCC_ETRCFGR_ETRLPEN			BIT(2)
+
+/* RCC_GPIOACFGR register fields */
+#define RCC_GPIOACFGR_GPIOARST			BIT(0)
+#define RCC_GPIOACFGR_GPIOAEN			BIT(1)
+#define RCC_GPIOACFGR_GPIOALPEN			BIT(2)
+
+/* RCC_GPIOBCFGR register fields */
+#define RCC_GPIOBCFGR_GPIOBRST			BIT(0)
+#define RCC_GPIOBCFGR_GPIOBEN			BIT(1)
+#define RCC_GPIOBCFGR_GPIOBLPEN			BIT(2)
+
+/* RCC_GPIOCCFGR register fields */
+#define RCC_GPIOCCFGR_GPIOCRST			BIT(0)
+#define RCC_GPIOCCFGR_GPIOCEN			BIT(1)
+#define RCC_GPIOCCFGR_GPIOCLPEN			BIT(2)
+
+/* RCC_GPIODCFGR register fields */
+#define RCC_GPIODCFGR_GPIODRST			BIT(0)
+#define RCC_GPIODCFGR_GPIODEN			BIT(1)
+#define RCC_GPIODCFGR_GPIODLPEN			BIT(2)
+
+/* RCC_GPIOECFGR register fields */
+#define RCC_GPIOECFGR_GPIOERST			BIT(0)
+#define RCC_GPIOECFGR_GPIOEEN			BIT(1)
+#define RCC_GPIOECFGR_GPIOELPEN			BIT(2)
+
+/* RCC_GPIOFCFGR register fields */
+#define RCC_GPIOFCFGR_GPIOFRST			BIT(0)
+#define RCC_GPIOFCFGR_GPIOFEN			BIT(1)
+#define RCC_GPIOFCFGR_GPIOFLPEN			BIT(2)
+
+/* RCC_GPIOGCFGR register fields */
+#define RCC_GPIOGCFGR_GPIOGRST			BIT(0)
+#define RCC_GPIOGCFGR_GPIOGEN			BIT(1)
+#define RCC_GPIOGCFGR_GPIOGLPEN			BIT(2)
+
+/* RCC_GPIOHCFGR register fields */
+#define RCC_GPIOHCFGR_GPIOHRST			BIT(0)
+#define RCC_GPIOHCFGR_GPIOHEN			BIT(1)
+#define RCC_GPIOHCFGR_GPIOHLPEN			BIT(2)
+
+/* RCC_GPIOICFGR register fields */
+#define RCC_GPIOICFGR_GPIOIRST			BIT(0)
+#define RCC_GPIOICFGR_GPIOIEN			BIT(1)
+#define RCC_GPIOICFGR_GPIOILPEN			BIT(2)
+
+/* RCC_GPIOZCFGR register fields */
+#define RCC_GPIOZCFGR_GPIOZRST			BIT(0)
+#define RCC_GPIOZCFGR_GPIOZEN			BIT(1)
+#define RCC_GPIOZCFGR_GPIOZLPEN			BIT(2)
+
+/* RCC_GPIOxCFGR register fields */
+#define RCC_GPIOxCFGR_GPIOxRST			BIT(0)
+#define RCC_GPIOxCFGR_GPIOxEN			BIT(1)
+#define RCC_GPIOxCFGR_GPIOxLPEN			BIT(2)
+#define RCC_GPIOxCFGR_GPIOxAMEN			BIT(3)
+
+/* RCC_HPDMA1CFGR register fields */
+#define RCC_HPDMA1CFGR_HPDMA1RST		BIT(0)
+#define RCC_HPDMA1CFGR_HPDMA1EN			BIT(1)
+#define RCC_HPDMA1CFGR_HPDMA1LPEN		BIT(2)
+
+/* RCC_HPDMA2CFGR register fields */
+#define RCC_HPDMA2CFGR_HPDMA2RST		BIT(0)
+#define RCC_HPDMA2CFGR_HPDMA2EN			BIT(1)
+#define RCC_HPDMA2CFGR_HPDMA2LPEN		BIT(2)
+
+/* RCC_HPDMA3CFGR register fields */
+#define RCC_HPDMA3CFGR_HPDMA3RST		BIT(0)
+#define RCC_HPDMA3CFGR_HPDMA3EN			BIT(1)
+#define RCC_HPDMA3CFGR_HPDMA3LPEN		BIT(2)
+
+/* RCC_HPDMAxCFGR register fields */
+#define RCC_HPDMAxCFGR_HPDMAxRST		BIT(0)
+#define RCC_HPDMAxCFGR_HPDMAxEN			BIT(1)
+#define RCC_HPDMAxCFGR_HPDMAxLPEN		BIT(2)
+
+/* RCC_IPCC1CFGR register fields */
+#define RCC_IPCC1CFGR_IPCC1RST			BIT(0)
+#define RCC_IPCC1CFGR_IPCC1EN			BIT(1)
+#define RCC_IPCC1CFGR_IPCC1LPEN			BIT(2)
+
+/* RCC_RTCCFGR register fields */
+#define RCC_RTCCFGR_RTCEN			BIT(1)
+#define RCC_RTCCFGR_RTCLPEN			BIT(2)
+
+/* RCC_SYSCPU1CFGR register fields */
+#define RCC_SYSCPU1CFGR_SYSCPU1EN		BIT(1)
+#define RCC_SYSCPU1CFGR_SYSCPU1LPEN		BIT(2)
+
+/* RCC_BSECCFGR register fields */
+#define RCC_BSECCFGR_BSECEN			BIT(1)
+#define RCC_BSECCFGR_BSECLPEN			BIT(2)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL2CFGR1_PLLEN			BIT(8)
+#define RCC_PLL2CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL2CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL2CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL2CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL2CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL2CFGR3 register fields */
+#define RCC_PLL2CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL2CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL2CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL2CFGR3_DACEN			BIT(25)
+#define RCC_PLL2CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL2CFGR4 register fields */
+#define RCC_PLL2CFGR4_DSMEN			BIT(8)
+#define RCC_PLL2CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL2CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL2CFGR5 register fields */
+#define RCC_PLL2CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL2CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL2CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL2CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL2CFGR6 register fields */
+#define RCC_PLL2CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL2CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL2CFGR7 register fields */
+#define RCC_PLL2CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL2CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST			BIT(0)
+#define RCC_PLLxCFGR1_PLLEN			BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY			BIT(24)
+#define RCC_PLLxCFGR1_CKREFST			BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT		0
+#define RCC_PLLxCFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT		0
+#define RCC_PLLxCFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLLxCFGR3_DACEN			BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN			BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLLxCFGR4_BYPASS			BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT		0
+#define RCC_PLLxCFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_HSIFMONCR register fields */
+#define RCC_HSIFMONCR_HSIREF_MASK		GENMASK_32(10, 0)
+#define RCC_HSIFMONCR_HSIREF_SHIFT		0
+#define RCC_HSIFMONCR_HSIMONEN			BIT(15)
+#define RCC_HSIFMONCR_HSIDEV_MASK		GENMASK_32(21, 16)
+#define RCC_HSIFMONCR_HSIDEV_SHIFT		16
+#define RCC_HSIFMONCR_HSIMONIE			BIT(30)
+#define RCC_HSIFMONCR_HSIMONF			BIT(31)
+
+/* RCC_HSIFVALR register fields */
+#define RCC_HSIFVALR_HSIVAL_MASK		GENMASK_32(10, 0)
+#define RCC_HSIFVALR_HSIVAL_SHIFT		0
+
+/* RCC_MSIFMONCR register fields */
+#define RCC_MSIFMONCR_MSIREF_MASK		GENMASK_32(8, 0)
+#define RCC_MSIFMONCR_MSIREF_SHIFT		0
+#define RCC_MSIFMONCR_MSIMONEN			BIT(15)
+#define RCC_MSIFMONCR_MSIDEV_MASK		GENMASK_32(20, 16)
+#define RCC_MSIFMONCR_MSIDEV_SHIFT		16
+#define RCC_MSIFMONCR_MSIMONIE			BIT(30)
+#define RCC_MSIFMONCR_MSIMONF			BIT(31)
+
+/* RCC_MSIFVALR register fields */
+#define RCC_MSIFVALR_MSIVAL_MASK		GENMASK_32(8, 0)
+#define RCC_MSIFVALR_MSIVAL_SHIFT		0
+
+/* RCC_TIM1CFGR register fields */
+#define RCC_TIM1CFGR_TIM1RST			BIT(0)
+#define RCC_TIM1CFGR_TIM1EN			BIT(1)
+#define RCC_TIM1CFGR_TIM1LPEN			BIT(2)
+
+/* RCC_TIM2CFGR register fields */
+#define RCC_TIM2CFGR_TIM2RST			BIT(0)
+#define RCC_TIM2CFGR_TIM2EN			BIT(1)
+#define RCC_TIM2CFGR_TIM2LPEN			BIT(2)
+
+/* RCC_TIM3CFGR register fields */
+#define RCC_TIM3CFGR_TIM3RST			BIT(0)
+#define RCC_TIM3CFGR_TIM3EN			BIT(1)
+#define RCC_TIM3CFGR_TIM3LPEN			BIT(2)
+
+/* RCC_TIM4CFGR register fields */
+#define RCC_TIM4CFGR_TIM4RST			BIT(0)
+#define RCC_TIM4CFGR_TIM4EN			BIT(1)
+#define RCC_TIM4CFGR_TIM4LPEN			BIT(2)
+
+/* RCC_TIM5CFGR register fields */
+#define RCC_TIM5CFGR_TIM5RST			BIT(0)
+#define RCC_TIM5CFGR_TIM5EN			BIT(1)
+#define RCC_TIM5CFGR_TIM5LPEN			BIT(2)
+
+/* RCC_TIM6CFGR register fields */
+#define RCC_TIM6CFGR_TIM6RST			BIT(0)
+#define RCC_TIM6CFGR_TIM6EN			BIT(1)
+#define RCC_TIM6CFGR_TIM6LPEN			BIT(2)
+
+/* RCC_TIM7CFGR register fields */
+#define RCC_TIM7CFGR_TIM7RST			BIT(0)
+#define RCC_TIM7CFGR_TIM7EN			BIT(1)
+#define RCC_TIM7CFGR_TIM7LPEN			BIT(2)
+
+/* RCC_TIM8CFGR register fields */
+#define RCC_TIM8CFGR_TIM8RST			BIT(0)
+#define RCC_TIM8CFGR_TIM8EN			BIT(1)
+#define RCC_TIM8CFGR_TIM8LPEN			BIT(2)
+
+/* RCC_TIM10CFGR register fields */
+#define RCC_TIM10CFGR_TIM10RST			BIT(0)
+#define RCC_TIM10CFGR_TIM10EN			BIT(1)
+#define RCC_TIM10CFGR_TIM10LPEN			BIT(2)
+
+/* RCC_TIM11CFGR register fields */
+#define RCC_TIM11CFGR_TIM11RST			BIT(0)
+#define RCC_TIM11CFGR_TIM11EN			BIT(1)
+#define RCC_TIM11CFGR_TIM11LPEN			BIT(2)
+
+/* RCC_TIM12CFGR register fields */
+#define RCC_TIM12CFGR_TIM12RST			BIT(0)
+#define RCC_TIM12CFGR_TIM12EN			BIT(1)
+#define RCC_TIM12CFGR_TIM12LPEN			BIT(2)
+
+/* RCC_TIM13CFGR register fields */
+#define RCC_TIM13CFGR_TIM13RST			BIT(0)
+#define RCC_TIM13CFGR_TIM13EN			BIT(1)
+#define RCC_TIM13CFGR_TIM13LPEN			BIT(2)
+
+/* RCC_TIM14CFGR register fields */
+#define RCC_TIM14CFGR_TIM14RST			BIT(0)
+#define RCC_TIM14CFGR_TIM14EN			BIT(1)
+#define RCC_TIM14CFGR_TIM14LPEN			BIT(2)
+
+/* RCC_TIM15CFGR register fields */
+#define RCC_TIM15CFGR_TIM15RST			BIT(0)
+#define RCC_TIM15CFGR_TIM15EN			BIT(1)
+#define RCC_TIM15CFGR_TIM15LPEN			BIT(2)
+
+/* RCC_TIM16CFGR register fields */
+#define RCC_TIM16CFGR_TIM16RST			BIT(0)
+#define RCC_TIM16CFGR_TIM16EN			BIT(1)
+#define RCC_TIM16CFGR_TIM16LPEN			BIT(2)
+
+/* RCC_TIM17CFGR register fields */
+#define RCC_TIM17CFGR_TIM17RST			BIT(0)
+#define RCC_TIM17CFGR_TIM17EN			BIT(1)
+#define RCC_TIM17CFGR_TIM17LPEN			BIT(2)
+
+/* RCC_LPTIM1CFGR register fields */
+#define RCC_LPTIM1CFGR_LPTIM1RST		BIT(0)
+#define RCC_LPTIM1CFGR_LPTIM1EN			BIT(1)
+#define RCC_LPTIM1CFGR_LPTIM1LPEN		BIT(2)
+
+/* RCC_LPTIM2CFGR register fields */
+#define RCC_LPTIM2CFGR_LPTIM2RST		BIT(0)
+#define RCC_LPTIM2CFGR_LPTIM2EN			BIT(1)
+#define RCC_LPTIM2CFGR_LPTIM2LPEN		BIT(2)
+
+/* RCC_LPTIM3CFGR register fields */
+#define RCC_LPTIM3CFGR_LPTIM3RST		BIT(0)
+#define RCC_LPTIM3CFGR_LPTIM3EN			BIT(1)
+#define RCC_LPTIM3CFGR_LPTIM3LPEN		BIT(2)
+
+/* RCC_LPTIM4CFGR register fields */
+#define RCC_LPTIM4CFGR_LPTIM4RST		BIT(0)
+#define RCC_LPTIM4CFGR_LPTIM4EN			BIT(1)
+#define RCC_LPTIM4CFGR_LPTIM4LPEN		BIT(2)
+
+/* RCC_LPTIM5CFGR register fields */
+#define RCC_LPTIM5CFGR_LPTIM5RST		BIT(0)
+#define RCC_LPTIM5CFGR_LPTIM5EN			BIT(1)
+#define RCC_LPTIM5CFGR_LPTIM5LPEN		BIT(2)
+
+/* RCC_LPTIMxCFGR register fields */
+#define RCC_LPTIMxCFGR_LPTIMxRST		BIT(0)
+#define RCC_LPTIMxCFGR_LPTIMxEN			BIT(1)
+#define RCC_LPTIMxCFGR_LPTIMxLPEN		BIT(2)
+#define RCC_LPTIMxCFGR_LPTIMxAMEN		BIT(3)
+
+/* RCC_SPI1CFGR register fields */
+#define RCC_SPI1CFGR_SPI1RST			BIT(0)
+#define RCC_SPI1CFGR_SPI1EN			BIT(1)
+#define RCC_SPI1CFGR_SPI1LPEN			BIT(2)
+
+/* RCC_SPI2CFGR register fields */
+#define RCC_SPI2CFGR_SPI2RST			BIT(0)
+#define RCC_SPI2CFGR_SPI2EN			BIT(1)
+#define RCC_SPI2CFGR_SPI2LPEN			BIT(2)
+
+/* RCC_SPI3CFGR register fields */
+#define RCC_SPI3CFGR_SPI3RST			BIT(0)
+#define RCC_SPI3CFGR_SPI3EN			BIT(1)
+#define RCC_SPI3CFGR_SPI3LPEN			BIT(2)
+
+/* RCC_SPI4CFGR register fields */
+#define RCC_SPI4CFGR_SPI4RST			BIT(0)
+#define RCC_SPI4CFGR_SPI4EN			BIT(1)
+#define RCC_SPI4CFGR_SPI4LPEN			BIT(2)
+
+/* RCC_SPI5CFGR register fields */
+#define RCC_SPI5CFGR_SPI5RST			BIT(0)
+#define RCC_SPI5CFGR_SPI5EN			BIT(1)
+#define RCC_SPI5CFGR_SPI5LPEN			BIT(2)
+
+/* RCC_SPI6CFGR register fields */
+#define RCC_SPI6CFGR_SPI6RST			BIT(0)
+#define RCC_SPI6CFGR_SPI6EN			BIT(1)
+#define RCC_SPI6CFGR_SPI6LPEN			BIT(2)
+
+/* RCC_SPIxCFGR register fields */
+#define RCC_SPIxCFGR_SPIxRST			BIT(0)
+#define RCC_SPIxCFGR_SPIxEN			BIT(1)
+#define RCC_SPIxCFGR_SPIxLPEN			BIT(2)
+#define RCC_SPIxCFGR_SPIxAMEN			BIT(3)
+
+/* RCC_SPDIFRXCFGR register fields */
+#define RCC_SPDIFRXCFGR_SPDIFRXRST		BIT(0)
+#define RCC_SPDIFRXCFGR_SPDIFRXEN		BIT(1)
+#define RCC_SPDIFRXCFGR_SPDIFRXLPEN		BIT(2)
+
+/* RCC_USART1CFGR register fields */
+#define RCC_USART1CFGR_USART1RST		BIT(0)
+#define RCC_USART1CFGR_USART1EN			BIT(1)
+#define RCC_USART1CFGR_USART1LPEN		BIT(2)
+
+/* RCC_USART2CFGR register fields */
+#define RCC_USART2CFGR_USART2RST		BIT(0)
+#define RCC_USART2CFGR_USART2EN			BIT(1)
+#define RCC_USART2CFGR_USART2LPEN		BIT(2)
+
+/* RCC_USART3CFGR register fields */
+#define RCC_USART3CFGR_USART3RST		BIT(0)
+#define RCC_USART3CFGR_USART3EN			BIT(1)
+#define RCC_USART3CFGR_USART3LPEN		BIT(2)
+
+/* RCC_UART4CFGR register fields */
+#define RCC_UART4CFGR_UART4RST			BIT(0)
+#define RCC_UART4CFGR_UART4EN			BIT(1)
+#define RCC_UART4CFGR_UART4LPEN			BIT(2)
+
+/* RCC_UART5CFGR register fields */
+#define RCC_UART5CFGR_UART5RST			BIT(0)
+#define RCC_UART5CFGR_UART5EN			BIT(1)
+#define RCC_UART5CFGR_UART5LPEN			BIT(2)
+
+/* RCC_USART6CFGR register fields */
+#define RCC_USART6CFGR_USART6RST		BIT(0)
+#define RCC_USART6CFGR_USART6EN			BIT(1)
+#define RCC_USART6CFGR_USART6LPEN		BIT(2)
+
+/* RCC_UART7CFGR register fields */
+#define RCC_UART7CFGR_UART7RST			BIT(0)
+#define RCC_UART7CFGR_UART7EN			BIT(1)
+#define RCC_UART7CFGR_UART7LPEN			BIT(2)
+
+/* RCC_USARTxCFGR register fields */
+#define RCC_USARTxCFGR_USARTxRST		BIT(0)
+#define RCC_USARTxCFGR_USARTxEN			BIT(1)
+#define RCC_USARTxCFGR_USARTxLPEN		BIT(2)
+
+/* RCC_UARTxCFGR register fields */
+#define RCC_UARTxCFGR_UARTxRST			BIT(0)
+#define RCC_UARTxCFGR_UARTxEN			BIT(1)
+#define RCC_UARTxCFGR_UARTxLPEN			BIT(2)
+
+/* RCC_LPUART1CFGR register fields */
+#define RCC_LPUART1CFGR_LPUART1RST		BIT(0)
+#define RCC_LPUART1CFGR_LPUART1EN		BIT(1)
+#define RCC_LPUART1CFGR_LPUART1LPEN		BIT(2)
+
+/* RCC_I2C1CFGR register fields */
+#define RCC_I2C1CFGR_I2C1RST			BIT(0)
+#define RCC_I2C1CFGR_I2C1EN			BIT(1)
+#define RCC_I2C1CFGR_I2C1LPEN			BIT(2)
+
+/* RCC_I2C2CFGR register fields */
+#define RCC_I2C2CFGR_I2C2RST			BIT(0)
+#define RCC_I2C2CFGR_I2C2EN			BIT(1)
+#define RCC_I2C2CFGR_I2C2LPEN			BIT(2)
+
+/* RCC_I2C3CFGR register fields */
+#define RCC_I2C3CFGR_I2C3RST			BIT(0)
+#define RCC_I2C3CFGR_I2C3EN			BIT(1)
+#define RCC_I2C3CFGR_I2C3LPEN			BIT(2)
+
+/* RCC_I2CxCFGR register fields */
+#define RCC_I2CxCFGR_I2CxRST			BIT(0)
+#define RCC_I2CxCFGR_I2CxEN			BIT(1)
+#define RCC_I2CxCFGR_I2CxLPEN			BIT(2)
+#define RCC_I2CxCFGR_I2CxAMEN			BIT(3)
+
+/* RCC_SAI1CFGR register fields */
+#define RCC_SAI1CFGR_SAI1RST			BIT(0)
+#define RCC_SAI1CFGR_SAI1EN			BIT(1)
+#define RCC_SAI1CFGR_SAI1LPEN			BIT(2)
+
+/* RCC_SAI2CFGR register fields */
+#define RCC_SAI2CFGR_SAI2RST			BIT(0)
+#define RCC_SAI2CFGR_SAI2EN			BIT(1)
+#define RCC_SAI2CFGR_SAI2LPEN			BIT(2)
+
+/* RCC_SAI3CFGR register fields */
+#define RCC_SAI3CFGR_SAI3RST			BIT(0)
+#define RCC_SAI3CFGR_SAI3EN			BIT(1)
+#define RCC_SAI3CFGR_SAI3LPEN			BIT(2)
+
+/* RCC_SAI4CFGR register fields */
+#define RCC_SAI4CFGR_SAI4RST			BIT(0)
+#define RCC_SAI4CFGR_SAI4EN			BIT(1)
+#define RCC_SAI4CFGR_SAI4LPEN			BIT(2)
+
+/* RCC_SAIxCFGR register fields */
+#define RCC_SAIxCFGR_SAIxRST			BIT(0)
+#define RCC_SAIxCFGR_SAIxEN			BIT(1)
+#define RCC_SAIxCFGR_SAIxLPEN			BIT(2)
+
+/* RCC_MDF1CFGR register fields */
+#define RCC_MDF1CFGR_MDF1RST			BIT(0)
+#define RCC_MDF1CFGR_MDF1EN			BIT(1)
+#define RCC_MDF1CFGR_MDF1LPEN			BIT(2)
+
+/* RCC_FDCANCFGR register fields */
+#define RCC_FDCANCFGR_FDCANRST			BIT(0)
+#define RCC_FDCANCFGR_FDCANEN			BIT(1)
+#define RCC_FDCANCFGR_FDCANLPEN			BIT(2)
+
+/* RCC_HDPCFGR register fields */
+#define RCC_HDPCFGR_HDPRST			BIT(0)
+#define RCC_HDPCFGR_HDPEN			BIT(1)
+
+/* RCC_ADC1CFGR register fields */
+#define RCC_ADC1CFGR_ADC1RST			BIT(0)
+#define RCC_ADC1CFGR_ADC1EN			BIT(1)
+#define RCC_ADC1CFGR_ADC1LPEN			BIT(2)
+#define RCC_ADC1CFGR_ADC1KERSEL			BIT(12)
+
+/* RCC_ADC2CFGR register fields */
+#define RCC_ADC2CFGR_ADC2RST			BIT(0)
+#define RCC_ADC2CFGR_ADC2EN			BIT(1)
+#define RCC_ADC2CFGR_ADC2LPEN			BIT(2)
+#define RCC_ADC2CFGR_ADC2KERSEL_MASK		GENMASK_32(13, 12)
+#define RCC_ADC2CFGR_ADC2KERSEL_SHIFT		12
+
+/* RCC_ETH1CFGR register fields */
+#define RCC_ETH1CFGR_ETH1RST			BIT(0)
+#define RCC_ETH1CFGR_ETH1MACEN			BIT(1)
+#define RCC_ETH1CFGR_ETH1MACLPEN		BIT(2)
+#define RCC_ETH1CFGR_ETH1STPEN			BIT(4)
+#define RCC_ETH1CFGR_ETH1EN			BIT(5)
+#define RCC_ETH1CFGR_ETH1LPEN			BIT(6)
+#define RCC_ETH1CFGR_ETH1TXEN			BIT(8)
+#define RCC_ETH1CFGR_ETH1TXLPEN			BIT(9)
+#define RCC_ETH1CFGR_ETH1RXEN			BIT(10)
+#define RCC_ETH1CFGR_ETH1RXLPEN			BIT(11)
+
+/* RCC_ETH2CFGR register fields */
+#define RCC_ETH2CFGR_ETH2RST			BIT(0)
+#define RCC_ETH2CFGR_ETH2MACEN			BIT(1)
+#define RCC_ETH2CFGR_ETH2MACLPEN		BIT(2)
+#define RCC_ETH2CFGR_ETH2STPEN			BIT(4)
+#define RCC_ETH2CFGR_ETH2EN			BIT(5)
+#define RCC_ETH2CFGR_ETH2LPEN			BIT(6)
+#define RCC_ETH2CFGR_ETH2TXEN			BIT(8)
+#define RCC_ETH2CFGR_ETH2TXLPEN			BIT(9)
+#define RCC_ETH2CFGR_ETH2RXEN			BIT(10)
+#define RCC_ETH2CFGR_ETH2RXLPEN			BIT(11)
+
+/* RCC_ETHxCFGR register fields */
+#define RCC_ETHxCFGR_ETHxRST			BIT(0)
+#define RCC_ETHxCFGR_ETHxMACEN			BIT(1)
+#define RCC_ETHxCFGR_ETHxMACLPEN		BIT(2)
+#define RCC_ETHxCFGR_ETHxSTPEN			BIT(4)
+#define RCC_ETHxCFGR_ETHxEN			BIT(5)
+#define RCC_ETHxCFGR_ETHxLPEN			BIT(6)
+#define RCC_ETHxCFGR_ETHxTXEN			BIT(8)
+#define RCC_ETHxCFGR_ETHxTXLPEN			BIT(9)
+#define RCC_ETHxCFGR_ETHxRXEN			BIT(10)
+#define RCC_ETHxCFGR_ETHxRXLPEN			BIT(11)
+
+/* RCC_USBHCFGR register fields */
+#define RCC_USBHCFGR_USBHRST			BIT(0)
+#define RCC_USBHCFGR_USBHEN			BIT(1)
+#define RCC_USBHCFGR_USBHLPEN			BIT(2)
+#define RCC_USBHCFGR_USBHSTPEN			BIT(4)
+
+/* RCC_USB2PHY1CFGR register fields */
+#define RCC_USB2PHY1CFGR_USB2PHY1RST		BIT(0)
+#define RCC_USB2PHY1CFGR_USB2PHY1EN		BIT(1)
+#define RCC_USB2PHY1CFGR_USB2PHY1LPEN		BIT(2)
+#define RCC_USB2PHY1CFGR_USB2PHY1STPEN		BIT(4)
+#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL	BIT(15)
+
+/* RCC_OTGCFGR register fields */
+#define RCC_OTGCFGR_OTGRST			BIT(0)
+#define RCC_OTGCFGR_OTGEN			BIT(1)
+#define RCC_OTGCFGR_OTGLPEN			BIT(2)
+
+/* RCC_USB2PHY2CFGR register fields */
+#define RCC_USB2PHY2CFGR_USB2PHY2RST		BIT(0)
+#define RCC_USB2PHY2CFGR_USB2PHY2EN		BIT(1)
+#define RCC_USB2PHY2CFGR_USB2PHY2LPEN		BIT(2)
+#define RCC_USB2PHY2CFGR_USB2PHY2STPEN		BIT(4)
+#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL	BIT(15)
+
+/* RCC_USB2PHYxCFGR register fields */
+#define RCC_USB2PHYxCFGR_USB2PHY1RST		BIT(0)
+#define RCC_USB2PHYxCFGR_USB2PHY1EN		BIT(1)
+#define RCC_USB2PHYxCFGR_USB2PHY1LPEN		BIT(2)
+#define RCC_USB2PHYxCFGR_USB2PHY1STPEN		BIT(4)
+#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL	BIT(15)
+
+/* RCC_STGENCFGR register fields */
+#define RCC_STGENCFGR_STGENEN			BIT(1)
+#define RCC_STGENCFGR_STGENLPEN			BIT(2)
+#define RCC_STGENCFGR_STGENSTPEN		BIT(4)
+
+/* RCC_SDMMC1CFGR register fields */
+#define RCC_SDMMC1CFGR_SDMMC1RST		BIT(0)
+#define RCC_SDMMC1CFGR_SDMMC1EN			BIT(1)
+#define RCC_SDMMC1CFGR_SDMMC1LPEN		BIT(2)
+#define RCC_SDMMC1CFGR_SDMMC1DLLRST		BIT(16)
+
+/* RCC_SDMMC2CFGR register fields */
+#define RCC_SDMMC2CFGR_SDMMC2RST		BIT(0)
+#define RCC_SDMMC2CFGR_SDMMC2EN			BIT(1)
+#define RCC_SDMMC2CFGR_SDMMC2LPEN		BIT(2)
+#define RCC_SDMMC2CFGR_SDMMC2DLLRST		BIT(16)
+
+/* RCC_SDMMC3CFGR register fields */
+#define RCC_SDMMC3CFGR_SDMMC3RST		BIT(0)
+#define RCC_SDMMC3CFGR_SDMMC3EN			BIT(1)
+#define RCC_SDMMC3CFGR_SDMMC3LPEN		BIT(2)
+#define RCC_SDMMC3CFGR_SDMMC3DLLRST		BIT(16)
+
+/* RCC_SDMMCxCFGR register fields */
+#define RCC_SDMMCxCFGR_SDMMC1RST		BIT(0)
+#define RCC_SDMMCxCFGR_SDMMC1EN			BIT(1)
+#define RCC_SDMMCxCFGR_SDMMC1LPEN		BIT(2)
+#define RCC_SDMMCxCFGR_SDMMC1DLLRST		BIT(16)
+
+/* RCC_LTDCCFGR register fields */
+#define RCC_LTDCCFGR_LTDCRST			BIT(0)
+#define RCC_LTDCCFGR_LTDCEN			BIT(1)
+#define RCC_LTDCCFGR_LTDCLPEN			BIT(2)
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSIRST			BIT(0)
+#define RCC_CSICFGR_CSIEN			BIT(1)
+#define RCC_CSICFGR_CSILPEN			BIT(2)
+
+/* RCC_DCMIPPCFGR register fields */
+#define RCC_DCMIPPCFGR_DCMIPPRST		BIT(0)
+#define RCC_DCMIPPCFGR_DCMIPPEN			BIT(1)
+#define RCC_DCMIPPCFGR_DCMIPPLPEN		BIT(2)
+
+/* RCC_DCMIPSSICFGR register fields */
+#define RCC_DCMIPSSICFGR_DCMIPSSIRST		BIT(0)
+#define RCC_DCMIPSSICFGR_DCMIPSSIEN		BIT(1)
+#define RCC_DCMIPSSICFGR_DCMIPSSILPEN		BIT(2)
+
+/* RCC_RNG1CFGR register fields */
+#define RCC_RNG1CFGR_RNG1RST			BIT(0)
+#define RCC_RNG1CFGR_RNG1EN			BIT(1)
+#define RCC_RNG1CFGR_RNG1LPEN			BIT(2)
+
+/* RCC_RNG2CFGR register fields */
+#define RCC_RNG2CFGR_RNG2RST			BIT(0)
+#define RCC_RNG2CFGR_RNG2EN			BIT(1)
+#define RCC_RNG2CFGR_RNG2LPEN			BIT(2)
+
+/* RCC_PKACFGR register fields */
+#define RCC_PKACFGR_PKARST			BIT(0)
+#define RCC_PKACFGR_PKAEN			BIT(1)
+#define RCC_PKACFGR_PKALPEN			BIT(2)
+
+/* RCC_SAESCFGR register fields */
+#define RCC_SAESCFGR_SAESRST			BIT(0)
+#define RCC_SAESCFGR_SAESEN			BIT(1)
+#define RCC_SAESCFGR_SAESLPEN			BIT(2)
+
+/* RCC_HASH1CFGR register fields */
+#define RCC_HASH1CFGR_HASH1RST			BIT(0)
+#define RCC_HASH1CFGR_HASH1EN			BIT(1)
+#define RCC_HASH1CFGR_HASH1LPEN			BIT(2)
+
+/* RCC_HASH2CFGR register fields */
+#define RCC_HASH2CFGR_HASH2RST			BIT(0)
+#define RCC_HASH2CFGR_HASH2EN			BIT(1)
+#define RCC_HASH2CFGR_HASH2LPEN			BIT(2)
+
+/* RCC_CRYP1CFGR register fields */
+#define RCC_CRYP1CFGR_CRYP1RST			BIT(0)
+#define RCC_CRYP1CFGR_CRYP1EN			BIT(1)
+#define RCC_CRYP1CFGR_CRYP1LPEN			BIT(2)
+
+/* RCC_CRYP2CFGR register fields */
+#define RCC_CRYP2CFGR_CRYP2RST			BIT(0)
+#define RCC_CRYP2CFGR_CRYP2EN			BIT(1)
+#define RCC_CRYP2CFGR_CRYP2LPEN			BIT(2)
+
+/* RCC_CRYPxCFGR register fields */
+#define RCC_CRYPxCFGR_CRYPxRST			BIT(0)
+#define RCC_CRYPxCFGR_CRYPxEN			BIT(1)
+#define RCC_CRYPxCFGR_CRYPxLPEN			BIT(2)
+
+/* RCC_IWDG1CFGR register fields */
+#define RCC_IWDG1CFGR_IWDG1EN			BIT(1)
+#define RCC_IWDG1CFGR_IWDG1LPEN			BIT(2)
+
+/* RCC_IWDG2CFGR register fields */
+#define RCC_IWDG2CFGR_IWDG2EN			BIT(1)
+#define RCC_IWDG2CFGR_IWDG2LPEN			BIT(2)
+
+/* RCC_IWDG3CFGR register fields */
+#define RCC_IWDG3CFGR_IWDG3EN			BIT(1)
+#define RCC_IWDG3CFGR_IWDG3LPEN			BIT(2)
+
+/* RCC_IWDG4CFGR register fields */
+#define RCC_IWDG4CFGR_IWDG4EN			BIT(1)
+#define RCC_IWDG4CFGR_IWDG4LPEN			BIT(2)
+
+/* RCC_IWDGxCFGR register fields */
+#define RCC_IWDGxCFGR_IWDGxEN			BIT(1)
+#define RCC_IWDGxCFGR_IWDGxLPEN			BIT(2)
+
+/* RCC_WWDG1CFGR register fields */
+#define RCC_WWDG1CFGR_WWDG1RST			BIT(0)
+#define RCC_WWDG1CFGR_WWDG1EN			BIT(1)
+#define RCC_WWDG1CFGR_WWDG1LPEN			BIT(2)
+
+/* RCC_VREFCFGR register fields */
+#define RCC_VREFCFGR_VREFRST			BIT(0)
+#define RCC_VREFCFGR_VREFEN			BIT(1)
+#define RCC_VREFCFGR_VREFLPEN			BIT(2)
+
+/* RCC_DTSCFGR register fields */
+#define RCC_DTSCFGR_DTSRST			BIT(0)
+#define RCC_DTSCFGR_DTSEN			BIT(1)
+#define RCC_DTSCFGR_DTSLPEN			BIT(2)
+#define RCC_DTSCFGR_DTSKERSEL_MASK		GENMASK_32(13, 12)
+#define RCC_DTSCFGR_DTSKERSEL_SHIFT		12
+
+/* RCC_CRCCFGR register fields */
+#define RCC_CRCCFGR_CRCRST			BIT(0)
+#define RCC_CRCCFGR_CRCEN			BIT(1)
+#define RCC_CRCCFGR_CRCLPEN			BIT(2)
+
+/* RCC_SERCCFGR register fields */
+#define RCC_SERCCFGR_SERCRST			BIT(0)
+#define RCC_SERCCFGR_SERCEN			BIT(1)
+#define RCC_SERCCFGR_SERCLPEN			BIT(2)
+
+/* RCC_DDRPERFMCFGR register fields */
+#define RCC_DDRPERFMCFGR_DDRPERFMRST		BIT(0)
+#define RCC_DDRPERFMCFGR_DDRPERFMEN		BIT(1)
+#define RCC_DDRPERFMCFGR_DDRPERFMLPEN		BIT(2)
+
+/* RCC_I3C1CFGR register fields */
+#define RCC_I3C1CFGR_I3C1RST			BIT(0)
+#define RCC_I3C1CFGR_I3C1EN			BIT(1)
+#define RCC_I3C1CFGR_I3C1LPEN			BIT(2)
+
+/* RCC_I3C2CFGR register fields */
+#define RCC_I3C2CFGR_I3C2RST			BIT(0)
+#define RCC_I3C2CFGR_I3C2EN			BIT(1)
+#define RCC_I3C2CFGR_I3C2LPEN			BIT(2)
+
+/* RCC_I3C3CFGR register fields */
+#define RCC_I3C3CFGR_I3C3RST			BIT(0)
+#define RCC_I3C3CFGR_I3C3EN			BIT(1)
+#define RCC_I3C3CFGR_I3C3LPEN			BIT(2)
+
+/* RCC_I3CxCFGR register fields */
+#define RCC_I3CxCFGR_I3CxRST			BIT(0)
+#define RCC_I3CxCFGR_I3CxEN			BIT(1)
+#define RCC_I3CxCFGR_I3CxLPEN			BIT(2)
+#define RCC_I3CxCFGR_I3CxAMEN			BIT(3)
+
+/* RCC_MUXSELCFGR register fields */
+#define RCC_MUXSELCFGR_MUXSEL0_MASK		GENMASK_32(2, 0)
+#define RCC_MUXSELCFGR_MUXSEL0_SHIFT		0
+#define RCC_MUXSELCFGR_MUXSEL1_MASK		GENMASK_32(6, 4)
+#define RCC_MUXSELCFGR_MUXSEL1_SHIFT		4
+#define RCC_MUXSELCFGR_MUXSEL2_MASK		GENMASK_32(10, 8)
+#define RCC_MUXSELCFGR_MUXSEL2_SHIFT		8
+#define RCC_MUXSELCFGR_MUXSEL3_MASK		GENMASK_32(14, 12)
+#define RCC_MUXSELCFGR_MUXSEL3_SHIFT		12
+#define RCC_MUXSELCFGR_MUXSEL4_MASK		GENMASK_32(18, 16)
+#define RCC_MUXSELCFGR_MUXSEL4_SHIFT		16
+#define RCC_MUXSELCFGR_MUXSEL5_MASK		GENMASK_32(21, 20)
+#define RCC_MUXSELCFGR_MUXSEL5_SHIFT		20
+#define RCC_MUXSELCFGR_MUXSEL6_MASK		GENMASK_32(25, 24)
+#define RCC_MUXSELCFGR_MUXSEL6_SHIFT		24
+#define RCC_MUXSELCFGR_MUXSEL7_MASK		GENMASK_32(29, 28)
+#define RCC_MUXSELCFGR_MUXSEL7_SHIFT		28
+
+/* RCC_XBAR0CFGR register fields */
+#define RCC_XBAR0CFGR_XBAR0SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT		0
+#define RCC_XBAR0CFGR_XBAR0EN			BIT(6)
+#define RCC_XBAR0CFGR_XBAR0STS			BIT(7)
+
+/* RCC_XBAR1CFGR register fields */
+#define RCC_XBAR1CFGR_XBAR1SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT		0
+#define RCC_XBAR1CFGR_XBAR1EN			BIT(6)
+#define RCC_XBAR1CFGR_XBAR1STS			BIT(7)
+
+/* RCC_XBAR2CFGR register fields */
+#define RCC_XBAR2CFGR_XBAR2SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT		0
+#define RCC_XBAR2CFGR_XBAR2EN			BIT(6)
+#define RCC_XBAR2CFGR_XBAR2STS			BIT(7)
+
+/* RCC_XBAR3CFGR register fields */
+#define RCC_XBAR3CFGR_XBAR3SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT		0
+#define RCC_XBAR3CFGR_XBAR3EN			BIT(6)
+#define RCC_XBAR3CFGR_XBAR3STS			BIT(7)
+
+/* RCC_XBAR4CFGR register fields */
+#define RCC_XBAR4CFGR_XBAR4SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT		0
+#define RCC_XBAR4CFGR_XBAR4EN			BIT(6)
+#define RCC_XBAR4CFGR_XBAR4STS			BIT(7)
+
+/* RCC_XBAR5CFGR register fields */
+#define RCC_XBAR5CFGR_XBAR5SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT		0
+#define RCC_XBAR5CFGR_XBAR5EN			BIT(6)
+#define RCC_XBAR5CFGR_XBAR5STS			BIT(7)
+
+/* RCC_XBAR6CFGR register fields */
+#define RCC_XBAR6CFGR_XBAR6SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT		0
+#define RCC_XBAR6CFGR_XBAR6EN			BIT(6)
+#define RCC_XBAR6CFGR_XBAR6STS			BIT(7)
+
+/* RCC_XBAR7CFGR register fields */
+#define RCC_XBAR7CFGR_XBAR7SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT		0
+#define RCC_XBAR7CFGR_XBAR7EN			BIT(6)
+#define RCC_XBAR7CFGR_XBAR7STS			BIT(7)
+
+/* RCC_XBAR8CFGR register fields */
+#define RCC_XBAR8CFGR_XBAR8SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT		0
+#define RCC_XBAR8CFGR_XBAR8EN			BIT(6)
+#define RCC_XBAR8CFGR_XBAR8STS			BIT(7)
+
+/* RCC_XBAR9CFGR register fields */
+#define RCC_XBAR9CFGR_XBAR9SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT		0
+#define RCC_XBAR9CFGR_XBAR9EN			BIT(6)
+#define RCC_XBAR9CFGR_XBAR9STS			BIT(7)
+
+/* RCC_XBAR10CFGR register fields */
+#define RCC_XBAR10CFGR_XBAR10SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT		0
+#define RCC_XBAR10CFGR_XBAR10EN			BIT(6)
+#define RCC_XBAR10CFGR_XBAR10STS		BIT(7)
+
+/* RCC_XBAR11CFGR register fields */
+#define RCC_XBAR11CFGR_XBAR11SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT		0
+#define RCC_XBAR11CFGR_XBAR11EN			BIT(6)
+#define RCC_XBAR11CFGR_XBAR11STS		BIT(7)
+
+/* RCC_XBAR12CFGR register fields */
+#define RCC_XBAR12CFGR_XBAR12SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT		0
+#define RCC_XBAR12CFGR_XBAR12EN			BIT(6)
+#define RCC_XBAR12CFGR_XBAR12STS		BIT(7)
+
+/* RCC_XBAR13CFGR register fields */
+#define RCC_XBAR13CFGR_XBAR13SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT		0
+#define RCC_XBAR13CFGR_XBAR13EN			BIT(6)
+#define RCC_XBAR13CFGR_XBAR13STS		BIT(7)
+
+/* RCC_XBAR14CFGR register fields */
+#define RCC_XBAR14CFGR_XBAR14SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT		0
+#define RCC_XBAR14CFGR_XBAR14EN			BIT(6)
+#define RCC_XBAR14CFGR_XBAR14STS		BIT(7)
+
+/* RCC_XBAR15CFGR register fields */
+#define RCC_XBAR15CFGR_XBAR15SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT		0
+#define RCC_XBAR15CFGR_XBAR15EN			BIT(6)
+#define RCC_XBAR15CFGR_XBAR15STS		BIT(7)
+
+/* RCC_XBAR16CFGR register fields */
+#define RCC_XBAR16CFGR_XBAR16SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT		0
+#define RCC_XBAR16CFGR_XBAR16EN			BIT(6)
+#define RCC_XBAR16CFGR_XBAR16STS		BIT(7)
+
+/* RCC_XBAR17CFGR register fields */
+#define RCC_XBAR17CFGR_XBAR17SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT		0
+#define RCC_XBAR17CFGR_XBAR17EN			BIT(6)
+#define RCC_XBAR17CFGR_XBAR17STS		BIT(7)
+
+/* RCC_XBAR18CFGR register fields */
+#define RCC_XBAR18CFGR_XBAR18SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT		0
+#define RCC_XBAR18CFGR_XBAR18EN			BIT(6)
+#define RCC_XBAR18CFGR_XBAR18STS		BIT(7)
+
+/* RCC_XBAR19CFGR register fields */
+#define RCC_XBAR19CFGR_XBAR19SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT		0
+#define RCC_XBAR19CFGR_XBAR19EN			BIT(6)
+#define RCC_XBAR19CFGR_XBAR19STS		BIT(7)
+
+/* RCC_XBAR20CFGR register fields */
+#define RCC_XBAR20CFGR_XBAR20SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT		0
+#define RCC_XBAR20CFGR_XBAR20EN			BIT(6)
+#define RCC_XBAR20CFGR_XBAR20STS		BIT(7)
+
+/* RCC_XBAR21CFGR register fields */
+#define RCC_XBAR21CFGR_XBAR21SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT		0
+#define RCC_XBAR21CFGR_XBAR21EN			BIT(6)
+#define RCC_XBAR21CFGR_XBAR21STS		BIT(7)
+
+/* RCC_XBAR22CFGR register fields */
+#define RCC_XBAR22CFGR_XBAR22SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT		0
+#define RCC_XBAR22CFGR_XBAR22EN			BIT(6)
+#define RCC_XBAR22CFGR_XBAR22STS		BIT(7)
+
+/* RCC_XBAR23CFGR register fields */
+#define RCC_XBAR23CFGR_XBAR23SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT		0
+#define RCC_XBAR23CFGR_XBAR23EN			BIT(6)
+#define RCC_XBAR23CFGR_XBAR23STS		BIT(7)
+
+/* RCC_XBAR24CFGR register fields */
+#define RCC_XBAR24CFGR_XBAR24SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT		0
+#define RCC_XBAR24CFGR_XBAR24EN			BIT(6)
+#define RCC_XBAR24CFGR_XBAR24STS		BIT(7)
+
+/* RCC_XBAR25CFGR register fields */
+#define RCC_XBAR25CFGR_XBAR25SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT		0
+#define RCC_XBAR25CFGR_XBAR25EN			BIT(6)
+#define RCC_XBAR25CFGR_XBAR25STS		BIT(7)
+
+/* RCC_XBAR26CFGR register fields */
+#define RCC_XBAR26CFGR_XBAR26SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT		0
+#define RCC_XBAR26CFGR_XBAR26EN			BIT(6)
+#define RCC_XBAR26CFGR_XBAR26STS		BIT(7)
+
+/* RCC_XBAR27CFGR register fields */
+#define RCC_XBAR27CFGR_XBAR27SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT		0
+#define RCC_XBAR27CFGR_XBAR27EN			BIT(6)
+#define RCC_XBAR27CFGR_XBAR27STS		BIT(7)
+
+/* RCC_XBAR28CFGR register fields */
+#define RCC_XBAR28CFGR_XBAR28SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT		0
+#define RCC_XBAR28CFGR_XBAR28EN			BIT(6)
+#define RCC_XBAR28CFGR_XBAR28STS		BIT(7)
+
+/* RCC_XBAR29CFGR register fields */
+#define RCC_XBAR29CFGR_XBAR29SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT		0
+#define RCC_XBAR29CFGR_XBAR29EN			BIT(6)
+#define RCC_XBAR29CFGR_XBAR29STS		BIT(7)
+
+/* RCC_XBAR30CFGR register fields */
+#define RCC_XBAR30CFGR_XBAR30SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT		0
+#define RCC_XBAR30CFGR_XBAR30EN			BIT(6)
+#define RCC_XBAR30CFGR_XBAR30STS		BIT(7)
+
+/* RCC_XBAR31CFGR register fields */
+#define RCC_XBAR31CFGR_XBAR31SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT		0
+#define RCC_XBAR31CFGR_XBAR31EN			BIT(6)
+#define RCC_XBAR31CFGR_XBAR31STS		BIT(7)
+
+/* RCC_XBAR32CFGR register fields */
+#define RCC_XBAR32CFGR_XBAR32SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT		0
+#define RCC_XBAR32CFGR_XBAR32EN			BIT(6)
+#define RCC_XBAR32CFGR_XBAR32STS		BIT(7)
+
+/* RCC_XBAR33CFGR register fields */
+#define RCC_XBAR33CFGR_XBAR33SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT		0
+#define RCC_XBAR33CFGR_XBAR33EN			BIT(6)
+#define RCC_XBAR33CFGR_XBAR33STS		BIT(7)
+
+/* RCC_XBAR34CFGR register fields */
+#define RCC_XBAR34CFGR_XBAR34SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT		0
+#define RCC_XBAR34CFGR_XBAR34EN			BIT(6)
+#define RCC_XBAR34CFGR_XBAR34STS		BIT(7)
+
+/* RCC_XBAR35CFGR register fields */
+#define RCC_XBAR35CFGR_XBAR35SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT		0
+#define RCC_XBAR35CFGR_XBAR35EN			BIT(6)
+#define RCC_XBAR35CFGR_XBAR35STS		BIT(7)
+
+/* RCC_XBAR36CFGR register fields */
+#define RCC_XBAR36CFGR_XBAR36SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT		0
+#define RCC_XBAR36CFGR_XBAR36EN			BIT(6)
+#define RCC_XBAR36CFGR_XBAR36STS		BIT(7)
+
+/* RCC_XBAR37CFGR register fields */
+#define RCC_XBAR37CFGR_XBAR37SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT		0
+#define RCC_XBAR37CFGR_XBAR37EN			BIT(6)
+#define RCC_XBAR37CFGR_XBAR37STS		BIT(7)
+
+/* RCC_XBAR38CFGR register fields */
+#define RCC_XBAR38CFGR_XBAR38SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT		0
+#define RCC_XBAR38CFGR_XBAR38EN			BIT(6)
+#define RCC_XBAR38CFGR_XBAR38STS		BIT(7)
+
+/* RCC_XBAR39CFGR register fields */
+#define RCC_XBAR39CFGR_XBAR39SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT		0
+#define RCC_XBAR39CFGR_XBAR39EN			BIT(6)
+#define RCC_XBAR39CFGR_XBAR39STS		BIT(7)
+
+/* RCC_XBAR40CFGR register fields */
+#define RCC_XBAR40CFGR_XBAR40SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT		0
+#define RCC_XBAR40CFGR_XBAR40EN			BIT(6)
+#define RCC_XBAR40CFGR_XBAR40STS		BIT(7)
+
+/* RCC_XBAR41CFGR register fields */
+#define RCC_XBAR41CFGR_XBAR41SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT		0
+#define RCC_XBAR41CFGR_XBAR41EN			BIT(6)
+#define RCC_XBAR41CFGR_XBAR41STS		BIT(7)
+
+/* RCC_XBAR42CFGR register fields */
+#define RCC_XBAR42CFGR_XBAR42SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT		0
+#define RCC_XBAR42CFGR_XBAR42EN			BIT(6)
+#define RCC_XBAR42CFGR_XBAR42STS		BIT(7)
+
+/* RCC_XBAR43CFGR register fields */
+#define RCC_XBAR43CFGR_XBAR43SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT		0
+#define RCC_XBAR43CFGR_XBAR43EN			BIT(6)
+#define RCC_XBAR43CFGR_XBAR43STS		BIT(7)
+
+/* RCC_XBAR44CFGR register fields */
+#define RCC_XBAR44CFGR_XBAR44SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT		0
+#define RCC_XBAR44CFGR_XBAR44EN			BIT(6)
+#define RCC_XBAR44CFGR_XBAR44STS		BIT(7)
+
+/* RCC_XBAR45CFGR register fields */
+#define RCC_XBAR45CFGR_XBAR45SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT		0
+#define RCC_XBAR45CFGR_XBAR45EN			BIT(6)
+#define RCC_XBAR45CFGR_XBAR45STS		BIT(7)
+
+/* RCC_XBAR46CFGR register fields */
+#define RCC_XBAR46CFGR_XBAR46SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT		0
+#define RCC_XBAR46CFGR_XBAR46EN			BIT(6)
+#define RCC_XBAR46CFGR_XBAR46STS		BIT(7)
+
+/* RCC_XBAR47CFGR register fields */
+#define RCC_XBAR47CFGR_XBAR47SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT		0
+#define RCC_XBAR47CFGR_XBAR47EN			BIT(6)
+#define RCC_XBAR47CFGR_XBAR47STS		BIT(7)
+
+/* RCC_XBAR48CFGR register fields */
+#define RCC_XBAR48CFGR_XBAR48SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT		0
+#define RCC_XBAR48CFGR_XBAR48EN			BIT(6)
+#define RCC_XBAR48CFGR_XBAR48STS		BIT(7)
+
+/* RCC_XBAR49CFGR register fields */
+#define RCC_XBAR49CFGR_XBAR49SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT		0
+#define RCC_XBAR49CFGR_XBAR49EN			BIT(6)
+#define RCC_XBAR49CFGR_XBAR49STS		BIT(7)
+
+/* RCC_XBAR50CFGR register fields */
+#define RCC_XBAR50CFGR_XBAR50SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT		0
+#define RCC_XBAR50CFGR_XBAR50EN			BIT(6)
+#define RCC_XBAR50CFGR_XBAR50STS		BIT(7)
+
+/* RCC_XBAR51CFGR register fields */
+#define RCC_XBAR51CFGR_XBAR51SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT		0
+#define RCC_XBAR51CFGR_XBAR51EN			BIT(6)
+#define RCC_XBAR51CFGR_XBAR51STS		BIT(7)
+
+/* RCC_XBAR52CFGR register fields */
+#define RCC_XBAR52CFGR_XBAR52SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT		0
+#define RCC_XBAR52CFGR_XBAR52EN			BIT(6)
+#define RCC_XBAR52CFGR_XBAR52STS		BIT(7)
+
+/* RCC_XBAR53CFGR register fields */
+#define RCC_XBAR53CFGR_XBAR53SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT		0
+#define RCC_XBAR53CFGR_XBAR53EN			BIT(6)
+#define RCC_XBAR53CFGR_XBAR53STS		BIT(7)
+
+/* RCC_XBAR54CFGR register fields */
+#define RCC_XBAR54CFGR_XBAR54SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT		0
+#define RCC_XBAR54CFGR_XBAR54EN			BIT(6)
+#define RCC_XBAR54CFGR_XBAR54STS		BIT(7)
+
+/* RCC_XBAR55CFGR register fields */
+#define RCC_XBAR55CFGR_XBAR55SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT		0
+#define RCC_XBAR55CFGR_XBAR55EN			BIT(6)
+#define RCC_XBAR55CFGR_XBAR55STS		BIT(7)
+
+/* RCC_XBAR56CFGR register fields */
+#define RCC_XBAR56CFGR_XBAR56SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT		0
+#define RCC_XBAR56CFGR_XBAR56EN			BIT(6)
+#define RCC_XBAR56CFGR_XBAR56STS		BIT(7)
+
+/* RCC_XBAR57CFGR register fields */
+#define RCC_XBAR57CFGR_XBAR57SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT		0
+#define RCC_XBAR57CFGR_XBAR57EN			BIT(6)
+#define RCC_XBAR57CFGR_XBAR57STS		BIT(7)
+
+/* RCC_XBAR58CFGR register fields */
+#define RCC_XBAR58CFGR_XBAR58SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT		0
+#define RCC_XBAR58CFGR_XBAR58EN			BIT(6)
+#define RCC_XBAR58CFGR_XBAR58STS		BIT(7)
+
+/* RCC_XBAR59CFGR register fields */
+#define RCC_XBAR59CFGR_XBAR59SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT		0
+#define RCC_XBAR59CFGR_XBAR59EN			BIT(6)
+#define RCC_XBAR59CFGR_XBAR59STS		BIT(7)
+
+/* RCC_XBAR60CFGR register fields */
+#define RCC_XBAR60CFGR_XBAR60SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT		0
+#define RCC_XBAR60CFGR_XBAR60EN			BIT(6)
+#define RCC_XBAR60CFGR_XBAR60STS		BIT(7)
+
+/* RCC_XBAR61CFGR register fields */
+#define RCC_XBAR61CFGR_XBAR61SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT		0
+#define RCC_XBAR61CFGR_XBAR61EN			BIT(6)
+#define RCC_XBAR61CFGR_XBAR61STS		BIT(7)
+
+/* RCC_XBAR62CFGR register fields */
+#define RCC_XBAR62CFGR_XBAR62SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT		0
+#define RCC_XBAR62CFGR_XBAR62EN			BIT(6)
+#define RCC_XBAR62CFGR_XBAR62STS		BIT(7)
+
+/* RCC_XBAR63CFGR register fields */
+#define RCC_XBAR63CFGR_XBAR63SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT		0
+#define RCC_XBAR63CFGR_XBAR63EN			BIT(6)
+#define RCC_XBAR63CFGR_XBAR63STS		BIT(7)
+
+/* RCC_XBARxCFGR register fields */
+#define RCC_XBARxCFGR_XBARxSEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBARxCFGR_XBARxSEL_SHIFT		0
+#define RCC_XBARxCFGR_XBARxEN			BIT(6)
+#define RCC_XBARxCFGR_XBARxSTS			BIT(7)
+
+/* RCC_PREDIV0CFGR register fields */
+#define RCC_PREDIV0CFGR_PREDIV0_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV0CFGR_PREDIV0_SHIFT		0
+
+/* RCC_PREDIV1CFGR register fields */
+#define RCC_PREDIV1CFGR_PREDIV1_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV1CFGR_PREDIV1_SHIFT		0
+
+/* RCC_PREDIV2CFGR register fields */
+#define RCC_PREDIV2CFGR_PREDIV2_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV2CFGR_PREDIV2_SHIFT		0
+
+/* RCC_PREDIV3CFGR register fields */
+#define RCC_PREDIV3CFGR_PREDIV3_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV3CFGR_PREDIV3_SHIFT		0
+
+/* RCC_PREDIV4CFGR register fields */
+#define RCC_PREDIV4CFGR_PREDIV4_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV4CFGR_PREDIV4_SHIFT		0
+
+/* RCC_PREDIV5CFGR register fields */
+#define RCC_PREDIV5CFGR_PREDIV5_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV5CFGR_PREDIV5_SHIFT		0
+
+/* RCC_PREDIV6CFGR register fields */
+#define RCC_PREDIV6CFGR_PREDIV6_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV6CFGR_PREDIV6_SHIFT		0
+
+/* RCC_PREDIV7CFGR register fields */
+#define RCC_PREDIV7CFGR_PREDIV7_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV7CFGR_PREDIV7_SHIFT		0
+
+/* RCC_PREDIV8CFGR register fields */
+#define RCC_PREDIV8CFGR_PREDIV8_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV8CFGR_PREDIV8_SHIFT		0
+
+/* RCC_PREDIV9CFGR register fields */
+#define RCC_PREDIV9CFGR_PREDIV9_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV9CFGR_PREDIV9_SHIFT		0
+
+/* RCC_PREDIV10CFGR register fields */
+#define RCC_PREDIV10CFGR_PREDIV10_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV10CFGR_PREDIV10_SHIFT		0
+
+/* RCC_PREDIV11CFGR register fields */
+#define RCC_PREDIV11CFGR_PREDIV11_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV11CFGR_PREDIV11_SHIFT		0
+
+/* RCC_PREDIV12CFGR register fields */
+#define RCC_PREDIV12CFGR_PREDIV12_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV12CFGR_PREDIV12_SHIFT		0
+
+/* RCC_PREDIV13CFGR register fields */
+#define RCC_PREDIV13CFGR_PREDIV13_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV13CFGR_PREDIV13_SHIFT		0
+
+/* RCC_PREDIV14CFGR register fields */
+#define RCC_PREDIV14CFGR_PREDIV14_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV14CFGR_PREDIV14_SHIFT		0
+
+/* RCC_PREDIV15CFGR register fields */
+#define RCC_PREDIV15CFGR_PREDIV15_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV15CFGR_PREDIV15_SHIFT		0
+
+/* RCC_PREDIV16CFGR register fields */
+#define RCC_PREDIV16CFGR_PREDIV16_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV16CFGR_PREDIV16_SHIFT		0
+
+/* RCC_PREDIV17CFGR register fields */
+#define RCC_PREDIV17CFGR_PREDIV17_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV17CFGR_PREDIV17_SHIFT		0
+
+/* RCC_PREDIV18CFGR register fields */
+#define RCC_PREDIV18CFGR_PREDIV18_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV18CFGR_PREDIV18_SHIFT		0
+
+/* RCC_PREDIV19CFGR register fields */
+#define RCC_PREDIV19CFGR_PREDIV19_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV19CFGR_PREDIV19_SHIFT		0
+
+/* RCC_PREDIV20CFGR register fields */
+#define RCC_PREDIV20CFGR_PREDIV20_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV20CFGR_PREDIV20_SHIFT		0
+
+/* RCC_PREDIV21CFGR register fields */
+#define RCC_PREDIV21CFGR_PREDIV21_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV21CFGR_PREDIV21_SHIFT		0
+
+/* RCC_PREDIV22CFGR register fields */
+#define RCC_PREDIV22CFGR_PREDIV22_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV22CFGR_PREDIV22_SHIFT		0
+
+/* RCC_PREDIV23CFGR register fields */
+#define RCC_PREDIV23CFGR_PREDIV23_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV23CFGR_PREDIV23_SHIFT		0
+
+/* RCC_PREDIV24CFGR register fields */
+#define RCC_PREDIV24CFGR_PREDIV24_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV24CFGR_PREDIV24_SHIFT		0
+
+/* RCC_PREDIV25CFGR register fields */
+#define RCC_PREDIV25CFGR_PREDIV25_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV25CFGR_PREDIV25_SHIFT		0
+
+/* RCC_PREDIV26CFGR register fields */
+#define RCC_PREDIV26CFGR_PREDIV26_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV26CFGR_PREDIV26_SHIFT		0
+
+/* RCC_PREDIV27CFGR register fields */
+#define RCC_PREDIV27CFGR_PREDIV27_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV27CFGR_PREDIV27_SHIFT		0
+
+/* RCC_PREDIV28CFGR register fields */
+#define RCC_PREDIV28CFGR_PREDIV28_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV28CFGR_PREDIV28_SHIFT		0
+
+/* RCC_PREDIV29CFGR register fields */
+#define RCC_PREDIV29CFGR_PREDIV29_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV29CFGR_PREDIV29_SHIFT		0
+
+/* RCC_PREDIV30CFGR register fields */
+#define RCC_PREDIV30CFGR_PREDIV30_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV30CFGR_PREDIV30_SHIFT		0
+
+/* RCC_PREDIV31CFGR register fields */
+#define RCC_PREDIV31CFGR_PREDIV31_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV31CFGR_PREDIV31_SHIFT		0
+
+/* RCC_PREDIV32CFGR register fields */
+#define RCC_PREDIV32CFGR_PREDIV32_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV32CFGR_PREDIV32_SHIFT		0
+
+/* RCC_PREDIV33CFGR register fields */
+#define RCC_PREDIV33CFGR_PREDIV33_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV33CFGR_PREDIV33_SHIFT		0
+
+/* RCC_PREDIV34CFGR register fields */
+#define RCC_PREDIV34CFGR_PREDIV34_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV34CFGR_PREDIV34_SHIFT		0
+
+/* RCC_PREDIV35CFGR register fields */
+#define RCC_PREDIV35CFGR_PREDIV35_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV35CFGR_PREDIV35_SHIFT		0
+
+/* RCC_PREDIV36CFGR register fields */
+#define RCC_PREDIV36CFGR_PREDIV36_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV36CFGR_PREDIV36_SHIFT		0
+
+/* RCC_PREDIV37CFGR register fields */
+#define RCC_PREDIV37CFGR_PREDIV37_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV37CFGR_PREDIV37_SHIFT		0
+
+/* RCC_PREDIV38CFGR register fields */
+#define RCC_PREDIV38CFGR_PREDIV38_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV38CFGR_PREDIV38_SHIFT		0
+
+/* RCC_PREDIV39CFGR register fields */
+#define RCC_PREDIV39CFGR_PREDIV39_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV39CFGR_PREDIV39_SHIFT		0
+
+/* RCC_PREDIV40CFGR register fields */
+#define RCC_PREDIV40CFGR_PREDIV40_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV40CFGR_PREDIV40_SHIFT		0
+
+/* RCC_PREDIV41CFGR register fields */
+#define RCC_PREDIV41CFGR_PREDIV41_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV41CFGR_PREDIV41_SHIFT		0
+
+/* RCC_PREDIV42CFGR register fields */
+#define RCC_PREDIV42CFGR_PREDIV42_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV42CFGR_PREDIV42_SHIFT		0
+
+/* RCC_PREDIV43CFGR register fields */
+#define RCC_PREDIV43CFGR_PREDIV43_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV43CFGR_PREDIV43_SHIFT		0
+
+/* RCC_PREDIV44CFGR register fields */
+#define RCC_PREDIV44CFGR_PREDIV44_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV44CFGR_PREDIV44_SHIFT		0
+
+/* RCC_PREDIV45CFGR register fields */
+#define RCC_PREDIV45CFGR_PREDIV45_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV45CFGR_PREDIV45_SHIFT		0
+
+/* RCC_PREDIV46CFGR register fields */
+#define RCC_PREDIV46CFGR_PREDIV46_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV46CFGR_PREDIV46_SHIFT		0
+
+/* RCC_PREDIV47CFGR register fields */
+#define RCC_PREDIV47CFGR_PREDIV47_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV47CFGR_PREDIV47_SHIFT		0
+
+/* RCC_PREDIV48CFGR register fields */
+#define RCC_PREDIV48CFGR_PREDIV48_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV48CFGR_PREDIV48_SHIFT		0
+
+/* RCC_PREDIV49CFGR register fields */
+#define RCC_PREDIV49CFGR_PREDIV49_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV49CFGR_PREDIV49_SHIFT		0
+
+/* RCC_PREDIV50CFGR register fields */
+#define RCC_PREDIV50CFGR_PREDIV50_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV50CFGR_PREDIV50_SHIFT		0
+
+/* RCC_PREDIV51CFGR register fields */
+#define RCC_PREDIV51CFGR_PREDIV51_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV51CFGR_PREDIV51_SHIFT		0
+
+/* RCC_PREDIV52CFGR register fields */
+#define RCC_PREDIV52CFGR_PREDIV52_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV52CFGR_PREDIV52_SHIFT		0
+
+/* RCC_PREDIV53CFGR register fields */
+#define RCC_PREDIV53CFGR_PREDIV53_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV53CFGR_PREDIV53_SHIFT		0
+
+/* RCC_PREDIV54CFGR register fields */
+#define RCC_PREDIV54CFGR_PREDIV54_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV54CFGR_PREDIV54_SHIFT		0
+
+/* RCC_PREDIV55CFGR register fields */
+#define RCC_PREDIV55CFGR_PREDIV55_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV55CFGR_PREDIV55_SHIFT		0
+
+/* RCC_PREDIV56CFGR register fields */
+#define RCC_PREDIV56CFGR_PREDIV56_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV56CFGR_PREDIV56_SHIFT		0
+
+/* RCC_PREDIV57CFGR register fields */
+#define RCC_PREDIV57CFGR_PREDIV57_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV57CFGR_PREDIV57_SHIFT		0
+
+/* RCC_PREDIV58CFGR register fields */
+#define RCC_PREDIV58CFGR_PREDIV58_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV58CFGR_PREDIV58_SHIFT		0
+
+/* RCC_PREDIV59CFGR register fields */
+#define RCC_PREDIV59CFGR_PREDIV59_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV59CFGR_PREDIV59_SHIFT		0
+
+/* RCC_PREDIV60CFGR register fields */
+#define RCC_PREDIV60CFGR_PREDIV60_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV60CFGR_PREDIV60_SHIFT		0
+
+/* RCC_PREDIV61CFGR register fields */
+#define RCC_PREDIV61CFGR_PREDIV61_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV61CFGR_PREDIV61_SHIFT		0
+
+/* RCC_PREDIV62CFGR register fields */
+#define RCC_PREDIV62CFGR_PREDIV62_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV62CFGR_PREDIV62_SHIFT		0
+
+/* RCC_PREDIV63CFGR register fields */
+#define RCC_PREDIV63CFGR_PREDIV63_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV63CFGR_PREDIV63_SHIFT		0
+
+/* RCC_PREDIVxCFGR register fields */
+#define RCC_PREDIVxCFGR_PREDIVx_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIVxCFGR_PREDIVx_SHIFT		0
+
+/* RCC_FINDIV0CFGR register fields */
+#define RCC_FINDIV0CFGR_FINDIV0_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV0CFGR_FINDIV0_SHIFT		0
+#define RCC_FINDIV0CFGR_FINDIV0EN		BIT(6)
+
+/* RCC_FINDIV1CFGR register fields */
+#define RCC_FINDIV1CFGR_FINDIV1_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV1CFGR_FINDIV1_SHIFT		0
+#define RCC_FINDIV1CFGR_FINDIV1EN		BIT(6)
+
+/* RCC_FINDIV2CFGR register fields */
+#define RCC_FINDIV2CFGR_FINDIV2_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV2CFGR_FINDIV2_SHIFT		0
+#define RCC_FINDIV2CFGR_FINDIV2EN		BIT(6)
+
+/* RCC_FINDIV3CFGR register fields */
+#define RCC_FINDIV3CFGR_FINDIV3_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV3CFGR_FINDIV3_SHIFT		0
+#define RCC_FINDIV3CFGR_FINDIV3EN		BIT(6)
+
+/* RCC_FINDIV4CFGR register fields */
+#define RCC_FINDIV4CFGR_FINDIV4_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV4CFGR_FINDIV4_SHIFT		0
+#define RCC_FINDIV4CFGR_FINDIV4EN		BIT(6)
+
+/* RCC_FINDIV5CFGR register fields */
+#define RCC_FINDIV5CFGR_FINDIV5_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV5CFGR_FINDIV5_SHIFT		0
+#define RCC_FINDIV5CFGR_FINDIV5EN		BIT(6)
+
+/* RCC_FINDIV6CFGR register fields */
+#define RCC_FINDIV6CFGR_FINDIV6_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV6CFGR_FINDIV6_SHIFT		0
+#define RCC_FINDIV6CFGR_FINDIV6EN		BIT(6)
+
+/* RCC_FINDIV7CFGR register fields */
+#define RCC_FINDIV7CFGR_FINDIV7_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV7CFGR_FINDIV7_SHIFT		0
+#define RCC_FINDIV7CFGR_FINDIV7EN		BIT(6)
+
+/* RCC_FINDIV8CFGR register fields */
+#define RCC_FINDIV8CFGR_FINDIV8_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV8CFGR_FINDIV8_SHIFT		0
+#define RCC_FINDIV8CFGR_FINDIV8EN		BIT(6)
+
+/* RCC_FINDIV9CFGR register fields */
+#define RCC_FINDIV9CFGR_FINDIV9_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV9CFGR_FINDIV9_SHIFT		0
+#define RCC_FINDIV9CFGR_FINDIV9EN		BIT(6)
+
+/* RCC_FINDIV10CFGR register fields */
+#define RCC_FINDIV10CFGR_FINDIV10_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV10CFGR_FINDIV10_SHIFT		0
+#define RCC_FINDIV10CFGR_FINDIV10EN		BIT(6)
+
+/* RCC_FINDIV11CFGR register fields */
+#define RCC_FINDIV11CFGR_FINDIV11_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV11CFGR_FINDIV11_SHIFT		0
+#define RCC_FINDIV11CFGR_FINDIV11EN		BIT(6)
+
+/* RCC_FINDIV12CFGR register fields */
+#define RCC_FINDIV12CFGR_FINDIV12_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV12CFGR_FINDIV12_SHIFT		0
+#define RCC_FINDIV12CFGR_FINDIV12EN		BIT(6)
+
+/* RCC_FINDIV13CFGR register fields */
+#define RCC_FINDIV13CFGR_FINDIV13_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV13CFGR_FINDIV13_SHIFT		0
+#define RCC_FINDIV13CFGR_FINDIV13EN		BIT(6)
+
+/* RCC_FINDIV14CFGR register fields */
+#define RCC_FINDIV14CFGR_FINDIV14_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV14CFGR_FINDIV14_SHIFT		0
+#define RCC_FINDIV14CFGR_FINDIV14EN		BIT(6)
+
+/* RCC_FINDIV15CFGR register fields */
+#define RCC_FINDIV15CFGR_FINDIV15_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV15CFGR_FINDIV15_SHIFT		0
+#define RCC_FINDIV15CFGR_FINDIV15EN		BIT(6)
+
+/* RCC_FINDIV16CFGR register fields */
+#define RCC_FINDIV16CFGR_FINDIV16_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV16CFGR_FINDIV16_SHIFT		0
+#define RCC_FINDIV16CFGR_FINDIV16EN		BIT(6)
+
+/* RCC_FINDIV17CFGR register fields */
+#define RCC_FINDIV17CFGR_FINDIV17_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV17CFGR_FINDIV17_SHIFT		0
+#define RCC_FINDIV17CFGR_FINDIV17EN		BIT(6)
+
+/* RCC_FINDIV18CFGR register fields */
+#define RCC_FINDIV18CFGR_FINDIV18_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV18CFGR_FINDIV18_SHIFT		0
+#define RCC_FINDIV18CFGR_FINDIV18EN		BIT(6)
+
+/* RCC_FINDIV19CFGR register fields */
+#define RCC_FINDIV19CFGR_FINDIV19_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV19CFGR_FINDIV19_SHIFT		0
+#define RCC_FINDIV19CFGR_FINDIV19EN		BIT(6)
+
+/* RCC_FINDIV20CFGR register fields */
+#define RCC_FINDIV20CFGR_FINDIV20_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV20CFGR_FINDIV20_SHIFT		0
+#define RCC_FINDIV20CFGR_FINDIV20EN		BIT(6)
+
+/* RCC_FINDIV21CFGR register fields */
+#define RCC_FINDIV21CFGR_FINDIV21_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV21CFGR_FINDIV21_SHIFT		0
+#define RCC_FINDIV21CFGR_FINDIV21EN		BIT(6)
+
+/* RCC_FINDIV22CFGR register fields */
+#define RCC_FINDIV22CFGR_FINDIV22_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV22CFGR_FINDIV22_SHIFT		0
+#define RCC_FINDIV22CFGR_FINDIV22EN		BIT(6)
+
+/* RCC_FINDIV23CFGR register fields */
+#define RCC_FINDIV23CFGR_FINDIV23_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV23CFGR_FINDIV23_SHIFT		0
+#define RCC_FINDIV23CFGR_FINDIV23EN		BIT(6)
+
+/* RCC_FINDIV24CFGR register fields */
+#define RCC_FINDIV24CFGR_FINDIV24_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV24CFGR_FINDIV24_SHIFT		0
+#define RCC_FINDIV24CFGR_FINDIV24EN		BIT(6)
+
+/* RCC_FINDIV25CFGR register fields */
+#define RCC_FINDIV25CFGR_FINDIV25_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV25CFGR_FINDIV25_SHIFT		0
+#define RCC_FINDIV25CFGR_FINDIV25EN		BIT(6)
+
+/* RCC_FINDIV26CFGR register fields */
+#define RCC_FINDIV26CFGR_FINDIV26_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV26CFGR_FINDIV26_SHIFT		0
+#define RCC_FINDIV26CFGR_FINDIV26EN		BIT(6)
+
+/* RCC_FINDIV27CFGR register fields */
+#define RCC_FINDIV27CFGR_FINDIV27_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV27CFGR_FINDIV27_SHIFT		0
+#define RCC_FINDIV27CFGR_FINDIV27EN		BIT(6)
+
+/* RCC_FINDIV28CFGR register fields */
+#define RCC_FINDIV28CFGR_FINDIV28_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV28CFGR_FINDIV28_SHIFT		0
+#define RCC_FINDIV28CFGR_FINDIV28EN		BIT(6)
+
+/* RCC_FINDIV29CFGR register fields */
+#define RCC_FINDIV29CFGR_FINDIV29_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV29CFGR_FINDIV29_SHIFT		0
+#define RCC_FINDIV29CFGR_FINDIV29EN		BIT(6)
+
+/* RCC_FINDIV30CFGR register fields */
+#define RCC_FINDIV30CFGR_FINDIV30_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV30CFGR_FINDIV30_SHIFT		0
+#define RCC_FINDIV30CFGR_FINDIV30EN		BIT(6)
+
+/* RCC_FINDIV31CFGR register fields */
+#define RCC_FINDIV31CFGR_FINDIV31_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV31CFGR_FINDIV31_SHIFT		0
+#define RCC_FINDIV31CFGR_FINDIV31EN		BIT(6)
+
+/* RCC_FINDIV32CFGR register fields */
+#define RCC_FINDIV32CFGR_FINDIV32_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV32CFGR_FINDIV32_SHIFT		0
+#define RCC_FINDIV32CFGR_FINDIV32EN		BIT(6)
+
+/* RCC_FINDIV33CFGR register fields */
+#define RCC_FINDIV33CFGR_FINDIV33_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV33CFGR_FINDIV33_SHIFT		0
+#define RCC_FINDIV33CFGR_FINDIV33EN		BIT(6)
+
+/* RCC_FINDIV34CFGR register fields */
+#define RCC_FINDIV34CFGR_FINDIV34_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV34CFGR_FINDIV34_SHIFT		0
+#define RCC_FINDIV34CFGR_FINDIV34EN		BIT(6)
+
+/* RCC_FINDIV35CFGR register fields */
+#define RCC_FINDIV35CFGR_FINDIV35_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV35CFGR_FINDIV35_SHIFT		0
+#define RCC_FINDIV35CFGR_FINDIV35EN		BIT(6)
+
+/* RCC_FINDIV36CFGR register fields */
+#define RCC_FINDIV36CFGR_FINDIV36_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV36CFGR_FINDIV36_SHIFT		0
+#define RCC_FINDIV36CFGR_FINDIV36EN		BIT(6)
+
+/* RCC_FINDIV37CFGR register fields */
+#define RCC_FINDIV37CFGR_FINDIV37_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV37CFGR_FINDIV37_SHIFT		0
+#define RCC_FINDIV37CFGR_FINDIV37EN		BIT(6)
+
+/* RCC_FINDIV38CFGR register fields */
+#define RCC_FINDIV38CFGR_FINDIV38_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV38CFGR_FINDIV38_SHIFT		0
+#define RCC_FINDIV38CFGR_FINDIV38EN		BIT(6)
+
+/* RCC_FINDIV39CFGR register fields */
+#define RCC_FINDIV39CFGR_FINDIV39_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV39CFGR_FINDIV39_SHIFT		0
+#define RCC_FINDIV39CFGR_FINDIV39EN		BIT(6)
+
+/* RCC_FINDIV40CFGR register fields */
+#define RCC_FINDIV40CFGR_FINDIV40_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV40CFGR_FINDIV40_SHIFT		0
+#define RCC_FINDIV40CFGR_FINDIV40EN		BIT(6)
+
+/* RCC_FINDIV41CFGR register fields */
+#define RCC_FINDIV41CFGR_FINDIV41_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV41CFGR_FINDIV41_SHIFT		0
+#define RCC_FINDIV41CFGR_FINDIV41EN		BIT(6)
+
+/* RCC_FINDIV42CFGR register fields */
+#define RCC_FINDIV42CFGR_FINDIV42_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV42CFGR_FINDIV42_SHIFT		0
+#define RCC_FINDIV42CFGR_FINDIV42EN		BIT(6)
+
+/* RCC_FINDIV43CFGR register fields */
+#define RCC_FINDIV43CFGR_FINDIV43_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV43CFGR_FINDIV43_SHIFT		0
+#define RCC_FINDIV43CFGR_FINDIV43EN		BIT(6)
+
+/* RCC_FINDIV44CFGR register fields */
+#define RCC_FINDIV44CFGR_FINDIV44_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV44CFGR_FINDIV44_SHIFT		0
+#define RCC_FINDIV44CFGR_FINDIV44EN		BIT(6)
+
+/* RCC_FINDIV45CFGR register fields */
+#define RCC_FINDIV45CFGR_FINDIV45_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV45CFGR_FINDIV45_SHIFT		0
+#define RCC_FINDIV45CFGR_FINDIV45EN		BIT(6)
+
+/* RCC_FINDIV46CFGR register fields */
+#define RCC_FINDIV46CFGR_FINDIV46_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV46CFGR_FINDIV46_SHIFT		0
+#define RCC_FINDIV46CFGR_FINDIV46EN		BIT(6)
+
+/* RCC_FINDIV47CFGR register fields */
+#define RCC_FINDIV47CFGR_FINDIV47_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV47CFGR_FINDIV47_SHIFT		0
+#define RCC_FINDIV47CFGR_FINDIV47EN		BIT(6)
+
+/* RCC_FINDIV48CFGR register fields */
+#define RCC_FINDIV48CFGR_FINDIV48_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV48CFGR_FINDIV48_SHIFT		0
+#define RCC_FINDIV48CFGR_FINDIV48EN		BIT(6)
+
+/* RCC_FINDIV49CFGR register fields */
+#define RCC_FINDIV49CFGR_FINDIV49_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV49CFGR_FINDIV49_SHIFT		0
+#define RCC_FINDIV49CFGR_FINDIV49EN		BIT(6)
+
+/* RCC_FINDIV50CFGR register fields */
+#define RCC_FINDIV50CFGR_FINDIV50_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV50CFGR_FINDIV50_SHIFT		0
+#define RCC_FINDIV50CFGR_FINDIV50EN		BIT(6)
+
+/* RCC_FINDIV51CFGR register fields */
+#define RCC_FINDIV51CFGR_FINDIV51_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV51CFGR_FINDIV51_SHIFT		0
+#define RCC_FINDIV51CFGR_FINDIV51EN		BIT(6)
+
+/* RCC_FINDIV52CFGR register fields */
+#define RCC_FINDIV52CFGR_FINDIV52_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV52CFGR_FINDIV52_SHIFT		0
+#define RCC_FINDIV52CFGR_FINDIV52EN		BIT(6)
+
+/* RCC_FINDIV53CFGR register fields */
+#define RCC_FINDIV53CFGR_FINDIV53_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV53CFGR_FINDIV53_SHIFT		0
+#define RCC_FINDIV53CFGR_FINDIV53EN		BIT(6)
+
+/* RCC_FINDIV54CFGR register fields */
+#define RCC_FINDIV54CFGR_FINDIV54_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV54CFGR_FINDIV54_SHIFT		0
+#define RCC_FINDIV54CFGR_FINDIV54EN		BIT(6)
+
+/* RCC_FINDIV55CFGR register fields */
+#define RCC_FINDIV55CFGR_FINDIV55_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV55CFGR_FINDIV55_SHIFT		0
+#define RCC_FINDIV55CFGR_FINDIV55EN		BIT(6)
+
+/* RCC_FINDIV56CFGR register fields */
+#define RCC_FINDIV56CFGR_FINDIV56_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV56CFGR_FINDIV56_SHIFT		0
+#define RCC_FINDIV56CFGR_FINDIV56EN		BIT(6)
+
+/* RCC_FINDIV57CFGR register fields */
+#define RCC_FINDIV57CFGR_FINDIV57_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV57CFGR_FINDIV57_SHIFT		0
+#define RCC_FINDIV57CFGR_FINDIV57EN		BIT(6)
+
+/* RCC_FINDIV58CFGR register fields */
+#define RCC_FINDIV58CFGR_FINDIV58_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV58CFGR_FINDIV58_SHIFT		0
+#define RCC_FINDIV58CFGR_FINDIV58EN		BIT(6)
+
+/* RCC_FINDIV59CFGR register fields */
+#define RCC_FINDIV59CFGR_FINDIV59_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV59CFGR_FINDIV59_SHIFT		0
+#define RCC_FINDIV59CFGR_FINDIV59EN		BIT(6)
+
+/* RCC_FINDIV60CFGR register fields */
+#define RCC_FINDIV60CFGR_FINDIV60_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV60CFGR_FINDIV60_SHIFT		0
+#define RCC_FINDIV60CFGR_FINDIV60EN		BIT(6)
+
+/* RCC_FINDIV61CFGR register fields */
+#define RCC_FINDIV61CFGR_FINDIV61_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV61CFGR_FINDIV61_SHIFT		0
+#define RCC_FINDIV61CFGR_FINDIV61EN		BIT(6)
+
+/* RCC_FINDIV62CFGR register fields */
+#define RCC_FINDIV62CFGR_FINDIV62_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV62CFGR_FINDIV62_SHIFT		0
+#define RCC_FINDIV62CFGR_FINDIV62EN		BIT(6)
+
+/* RCC_FINDIV63CFGR register fields */
+#define RCC_FINDIV63CFGR_FINDIV63_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV63CFGR_FINDIV63_SHIFT		0
+#define RCC_FINDIV63CFGR_FINDIV63EN		BIT(6)
+
+/* RCC_FINDIVxCFGR register fields */
+#define RCC_FINDIVxCFGR_FINDIVx_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIVxCFGR_FINDIVx_SHIFT		0
+#define RCC_FINDIVxCFGR_FINDIVxEN		BIT(6)
+
+/* RCC_FCALCOBS0CFGR register fields */
+#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK		GENMASK_32(7, 0)
+#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT	0
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK		GENMASK_32(10, 8)
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT	8
+#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL		BIT(15)
+#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL		BIT(16)
+#define RCC_FCALCOBS0CFGR_FCALCCKINV		BIT(17)
+#define RCC_FCALCOBS0CFGR_CKOBSINV		BIT(18)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK		GENMASK_32(24, 22)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT	22
+#define RCC_FCALCOBS0CFGR_FCALCCKEN		BIT(25)
+#define RCC_FCALCOBS0CFGR_CKOBSEN		BIT(26)
+
+/* RCC_FCALCOBS1CFGR register fields */
+#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK		GENMASK_32(7, 0)
+#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT	0
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK		GENMASK_32(10, 8)
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT	8
+#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL		BIT(16)
+#define RCC_FCALCOBS1CFGR_CKOBSINV		BIT(18)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK		GENMASK_32(24, 22)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT	22
+#define RCC_FCALCOBS1CFGR_CKOBSEN		BIT(26)
+#define RCC_FCALCOBS1CFGR_FCALCRSTN		BIT(27)
+
+/* RCC_FCALCREFCFGR register fields */
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK	GENMASK_32(2, 0)
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT	0
+
+/* RCC_FCALCCR1 register fields */
+#define RCC_FCALCCR1_FCALCRUN			BIT(0)
+
+/* RCC_FCALCCR2 register fields */
+#define RCC_FCALCCR2_FCALCMD_MASK		GENMASK_32(4, 3)
+#define RCC_FCALCCR2_FCALCMD_SHIFT		3
+#define RCC_FCALCCR2_FCALCTWC_MASK		GENMASK_32(14, 11)
+#define RCC_FCALCCR2_FCALCTWC_SHIFT		11
+#define RCC_FCALCCR2_FCALCTYP_MASK		GENMASK_32(21, 17)
+#define RCC_FCALCCR2_FCALCTYP_SHIFT		17
+
+/* RCC_FCALCSR register fields */
+#define RCC_FCALCSR_FVAL_MASK			GENMASK_32(16, 0)
+#define RCC_FCALCSR_FVAL_SHIFT			0
+#define RCC_FCALCSR_FCALCSTS			BIT(19)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL4CFGR1_PLLEN			BIT(8)
+#define RCC_PLL4CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL4CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL4CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL4CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL4CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL4CFGR3 register fields */
+#define RCC_PLL4CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL4CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL4CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL4CFGR3_DACEN			BIT(25)
+#define RCC_PLL4CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL4CFGR4 register fields */
+#define RCC_PLL4CFGR4_DSMEN			BIT(8)
+#define RCC_PLL4CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL4CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL4CFGR5 register fields */
+#define RCC_PLL4CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL4CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL4CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL4CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL4CFGR6 register fields */
+#define RCC_PLL4CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL4CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL4CFGR7 register fields */
+#define RCC_PLL4CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL4CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL5CFGR1 register fields */
+#define RCC_PLL5CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL5CFGR1_PLLEN			BIT(8)
+#define RCC_PLL5CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL5CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL5CFGR2 register fields */
+#define RCC_PLL5CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL5CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL5CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL5CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL5CFGR3 register fields */
+#define RCC_PLL5CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL5CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL5CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL5CFGR3_DACEN			BIT(25)
+#define RCC_PLL5CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL5CFGR4 register fields */
+#define RCC_PLL5CFGR4_DSMEN			BIT(8)
+#define RCC_PLL5CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL5CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL5CFGR5 register fields */
+#define RCC_PLL5CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL5CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL5CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL5CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL5CFGR6 register fields */
+#define RCC_PLL5CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL5CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL5CFGR7 register fields */
+#define RCC_PLL5CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL5CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL6CFGR1 register fields */
+#define RCC_PLL6CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL6CFGR1_PLLEN			BIT(8)
+#define RCC_PLL6CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL6CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL6CFGR2 register fields */
+#define RCC_PLL6CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL6CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL6CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL6CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL6CFGR3 register fields */
+#define RCC_PLL6CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL6CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL6CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL6CFGR3_DACEN			BIT(25)
+#define RCC_PLL6CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL6CFGR4 register fields */
+#define RCC_PLL6CFGR4_DSMEN			BIT(8)
+#define RCC_PLL6CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL6CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL6CFGR5 register fields */
+#define RCC_PLL6CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL6CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL6CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL6CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL6CFGR6 register fields */
+#define RCC_PLL6CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL6CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL6CFGR7 register fields */
+#define RCC_PLL6CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL6CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL7CFGR1 register fields */
+#define RCC_PLL7CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL7CFGR1_PLLEN			BIT(8)
+#define RCC_PLL7CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL7CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL7CFGR2 register fields */
+#define RCC_PLL7CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL7CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL7CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL7CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL7CFGR3 register fields */
+#define RCC_PLL7CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL7CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL7CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL7CFGR3_DACEN			BIT(25)
+#define RCC_PLL7CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL7CFGR4 register fields */
+#define RCC_PLL7CFGR4_DSMEN			BIT(8)
+#define RCC_PLL7CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL7CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL7CFGR5 register fields */
+#define RCC_PLL7CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL7CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL7CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL7CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL7CFGR6 register fields */
+#define RCC_PLL7CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL7CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL7CFGR7 register fields */
+#define RCC_PLL7CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL7CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL8CFGR1 register fields */
+#define RCC_PLL8CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL8CFGR1_PLLEN			BIT(8)
+#define RCC_PLL8CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL8CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL8CFGR2 register fields */
+#define RCC_PLL8CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL8CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL8CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL8CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL8CFGR3 register fields */
+#define RCC_PLL8CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL8CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL8CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL8CFGR3_DACEN			BIT(25)
+#define RCC_PLL8CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL8CFGR4 register fields */
+#define RCC_PLL8CFGR4_DSMEN			BIT(8)
+#define RCC_PLL8CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL8CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL8CFGR5 register fields */
+#define RCC_PLL8CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL8CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL8CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL8CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL8CFGR6 register fields */
+#define RCC_PLL8CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL8CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL8CFGR7 register fields */
+#define RCC_PLL8CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL8CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST			BIT(0)
+#define RCC_PLLxCFGR1_PLLEN			BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY			BIT(24)
+#define RCC_PLLxCFGR1_CKREFST			BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT		0
+#define RCC_PLLxCFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT		0
+#define RCC_PLLxCFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLLxCFGR3_DACEN			BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN			BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLLxCFGR4_BYPASS			BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT		0
+#define RCC_PLLxCFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK			GENMASK_32(3, 0)
+#define RCC_VERR_MINREV_SHIFT			0
+#define RCC_VERR_MAJREV_MASK			GENMASK_32(7, 4)
+#define RCC_VERR_MAJREV_SHIFT			4
+
+#endif /* STM32MP21_RCC_H */

diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
index d5d228c..752d3c3 100644
--- a/include/drivers/st/stm32mp25_rcc.h
+++ b/include/drivers/st/stm32mp25_rcc.h

@@ -2308,6 +2308,12 @@
 #define RCC_C1BOOTRSTSCLRR_D1STBYRSTF		BIT(22)
 #define RCC_C1BOOTRSTSCLRR_D2STBYRSTF		BIT(23)
 
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF)
+
 /* RCC_C2BOOTRSTSSETR register fields */
 #define RCC_C2BOOTRSTSSETR_PORRSTF		BIT(0)
 #define RCC_C2BOOTRSTSSETR_BORRSTF		BIT(1)

diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
index 9329fff..d9bf7ae 100644
--- a/include/drivers/st/stm32mp2_ddr_helpers.h
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,7 +22,6 @@
 void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
 void ddr_wait_lp3_mode(bool state);
 int ddr_sr_exit_loop(void);
-uint32_t ddr_get_io_calibration_val(void);
 int ddr_sr_entry(bool standby);
 int ddr_sr_exit(void);
 enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);

diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 57b0668..970ff19 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h

@@ -28,7 +28,7 @@
 struct stm32mp_ddr_reg_desc {
 	uint16_t offset;	/* Offset for base address */
 	uint8_t par_offset;	/* Offset for parameter array */
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
 	bool qd; /* quasi-dynamic register if true */
 #endif
 };

diff --git a/include/drivers/st/stpmic2.h b/include/drivers/st/stpmic2.h
index 58ba64a..b2aadfb 100644
--- a/include/drivers/st/stpmic2.h
+++ b/include/drivers/st/stpmic2.h

@@ -146,6 +146,51 @@
 #define INT_DBG_LATCH_R3	0x82
 #define INT_DBG_LATCH_R4	0x83
 
+/* NVM user control registers */
+#define NVM_SR			0x8E
+#define NVM_CR			0x8F
+
+/* NVM user shadow registers */
+#define NVM_MAIN_CTRL_SHR1	0x90
+#define NVM_MAIN_CTRL_SHR2	0x91
+#define NVM_RANK_SHR1		0x92
+#define NVM_RANK_SHR2		0x93
+#define NVM_RANK_SHR3		0x94
+#define NVM_RANK_SHR4		0x95
+#define NVM_RANK_SHR5		0x96
+#define NVM_RANK_SHR6		0x97
+#define NVM_RANK_SHR7		0x98
+#define NVM_RANK_SHR8		0x99
+#define NVM_BUCK_MODE_SHR1	0x9A
+#define NVM_BUCK_MODE_SHR2	0x9B
+#define NVM_BUCK1_VOUT_SHR	0x9C
+#define NVM_BUCK2_VOUT_SHR	0x9D
+#define NVM_BUCK3_VOUT_SHR	0x9E
+#define NVM_BUCK4_VOUT_SHR	0x9F
+#define NVM_BUCK5_VOUT_SHR	0xA0
+#define NVM_BUCK6_VOUT_SHR	0xA1
+#define NVM_BUCK7_VOUT_SHR	0xA2
+#define NVM_LDO2_SHR		0xA3
+#define NVM_LDO3_SHR		0xA4
+#define NVM_LDO5_SHR		0xA5
+#define NVM_LDO6_SHR		0xA6
+#define NVM_LDO7_SHR		0xA7
+#define NVM_LDO8_SHR		0xA8
+#define NVM_PD_SHR1		0xA9
+#define NVM_PD_SHR2		0xAA
+#define NVM_PD_SHR3		0xAB
+#define NVM_BUCKS_IOUT_SHR1	0xAC
+#define NVM_BUCKS_IOUT_SHR2	0xAD
+#define NVM_LDOS_IOUT_SHR	0xAE
+#define NVM_FS_OCP_SHR1	0xAF
+#define NVM_FS_OCP_SHR2	0xB0
+#define NVM_FS_SHR1		0xB1
+#define NVM_FS_SHR2		0xB2
+#define NVM_FS_SHR3		0xB3
+#define NVM_I2C_ADDR_SHR	0xB5
+#define NVM_USER_SHR1		0xB6
+#define NVM_USER_SHR2		0xB7
+
 /* BUCKS_MRST_CR bits definition */
 #define BUCK1_MRST		BIT(0)
 #define BUCK2_MRST		BIT(1)
@@ -237,6 +282,16 @@
 #define FS_OCP_LDO7		BIT(6)
 #define FS_OCP_LDO8		BIT(7)
 
+/* NVM_CR */
+#define NVM_CMD_MASK		GENMASK_32(1, 0)
+
+#define NVM_CMD_PROGRAM		1
+#define NVM_CMD_READ		2
+
+/* NVM_SR */
+#define NVM_BUSY		BIT(0)
+#define NVM_WRITE_FAIL		BIT(1)
+
 /* IRQ definitions */
 #define IT_PONKEY_F	0
 #define IT_PONKEY_R	1
@@ -291,9 +346,7 @@
 int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
 				  uint8_t id, uint16_t millivolts);
 
-#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
 void stpmic2_dump_regulators(struct pmic_handle_s *pmic);
-#endif
 
 int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val);
 int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val);

diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..f23c536
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h

@@ -0,0 +1,429 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
+#define _DT_BINDINGS_STM32MP21_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK			0
+#define HSE_CK			1
+#define MSI_CK			2
+#define LSI_CK			3
+#define LSE_CK			4
+#define I2S_CK			5
+#define RTC_CK			6
+#define SPDIF_CK_SYMB		7
+
+/* PLL CLOCKS */
+#define PLL1_CK			8
+#define PLL2_CK			9
+#define PLL4_CK			10
+#define PLL5_CK			11
+#define PLL6_CK			12
+#define PLL7_CK			13
+#define PLL8_CK			14
+
+#define CK_CPU1			15
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1		16
+#define CK_ICN_APB2		17
+#define CK_ICN_APB3		18
+#define CK_ICN_APB4		19
+#define CK_ICN_APB5		20
+#define CK_ICN_APBDBG		21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK		22
+#define TIMG2_CK		23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU		24
+#define CK_ICN_SDMMC		25
+#define CK_ICN_DDR		26
+#define CK_ICN_DISPLAY		27
+#define CK_ICN_HSL		28
+#define CK_ICN_NIC		29
+#define CK_ICN_VID		30
+#define CK_FLEXGEN_07		31
+#define CK_FLEXGEN_08		32
+#define CK_FLEXGEN_09		33
+#define CK_FLEXGEN_10		34
+#define CK_FLEXGEN_11		35
+#define CK_FLEXGEN_12		36
+#define CK_FLEXGEN_13		37
+#define CK_FLEXGEN_14		38
+#define CK_FLEXGEN_15		39
+#define CK_FLEXGEN_16		40
+#define CK_FLEXGEN_17		41
+#define CK_FLEXGEN_18		42
+#define CK_FLEXGEN_19		43
+#define CK_FLEXGEN_20		44
+#define CK_FLEXGEN_21		45
+#define CK_FLEXGEN_22		46
+#define CK_FLEXGEN_23		47
+#define CK_FLEXGEN_24		48
+#define CK_FLEXGEN_25		49
+#define CK_FLEXGEN_26		50
+#define CK_FLEXGEN_27		51
+#define CK_FLEXGEN_28		52
+#define CK_FLEXGEN_29		53
+#define CK_FLEXGEN_30		54
+#define CK_FLEXGEN_31		55
+#define CK_FLEXGEN_32		56
+#define CK_FLEXGEN_33		57
+#define CK_FLEXGEN_34		58
+#define CK_FLEXGEN_35		59
+#define CK_FLEXGEN_36		60
+#define CK_FLEXGEN_37		61
+#define CK_FLEXGEN_38		62
+#define CK_FLEXGEN_39		63
+#define CK_FLEXGEN_40		64
+#define CK_FLEXGEN_41		65
+#define CK_FLEXGEN_42		66
+#define CK_FLEXGEN_43		67
+#define CK_FLEXGEN_44		68
+#define CK_FLEXGEN_45		69
+#define CK_FLEXGEN_46		70
+#define CK_FLEXGEN_47		71
+#define CK_FLEXGEN_48		72
+#define CK_FLEXGEN_49		73
+#define CK_FLEXGEN_50		74
+#define CK_FLEXGEN_51		75
+#define CK_FLEXGEN_52		76
+#define CK_FLEXGEN_53		77
+#define CK_FLEXGEN_54		78
+#define CK_FLEXGEN_55		79
+#define CK_FLEXGEN_56		80
+#define CK_FLEXGEN_57		81
+#define CK_FLEXGEN_58		82
+#define CK_FLEXGEN_59		83
+#define CK_FLEXGEN_60		84
+#define CK_FLEXGEN_61		85
+#define CK_FLEXGEN_62		86
+#define CK_FLEXGEN_63		87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU		88
+
+#define CK_BUS_STM		89
+#define CK_BUS_FMC		90
+#define CK_BUS_ETH1		91
+#define CK_BUS_ETH2		92
+#define CK_BUS_DDRPHYC		93
+#define CK_BUS_SYSCPU1		94
+#define CK_BUS_HPDMA1		95
+#define CK_BUS_HPDMA2		96
+#define CK_BUS_HPDMA3		97
+#define CK_BUS_ADC1		98
+#define CK_BUS_ADC2		99
+#define CK_BUS_IPCC1		100
+#define CK_BUS_DCMIPSSI		101
+#define CK_BUS_CRC		102
+#define CK_BUS_MDF1		103
+#define CK_BUS_BKPSRAM		104
+#define CK_BUS_HASH1		105
+#define CK_BUS_HASH2		106
+#define CK_BUS_RNG1		107
+#define CK_BUS_RNG2		108
+#define CK_BUS_CRYP1		109
+#define CK_BUS_CRYP2		110
+#define CK_BUS_SAES		111
+#define CK_BUS_PKA		112
+#define CK_BUS_GPIOA		113
+#define CK_BUS_GPIOB		114
+#define CK_BUS_GPIOC		115
+#define CK_BUS_GPIOD		116
+#define CK_BUS_GPIOE		117
+#define CK_BUS_GPIOF		118
+#define CK_BUS_GPIOG		119
+#define CK_BUS_GPIOH		120
+#define CK_BUS_GPIOI		121
+#define CK_BUS_GPIOZ		122
+#define CK_BUS_RTC		124
+#define CK_BUS_LPUART1		125
+#define CK_BUS_LPTIM3		126
+#define CK_BUS_LPTIM4		127
+#define CK_BUS_LPTIM5		128
+#define CK_BUS_TIM2		129
+#define CK_BUS_TIM3		130
+#define CK_BUS_TIM4		131
+#define CK_BUS_TIM5		132
+#define CK_BUS_TIM6		133
+#define CK_BUS_TIM7		134
+#define CK_BUS_TIM10		135
+#define CK_BUS_TIM11		136
+#define CK_BUS_TIM12		137
+#define CK_BUS_TIM13		138
+#define CK_BUS_TIM14		139
+#define CK_BUS_LPTIM1		140
+#define CK_BUS_LPTIM2		141
+#define CK_BUS_SPI2		142
+#define CK_BUS_SPI3		143
+#define CK_BUS_SPDIFRX		144
+#define CK_BUS_USART2		145
+#define CK_BUS_USART3		146
+#define CK_BUS_UART4		147
+#define CK_BUS_UART5		148
+#define CK_BUS_I2C1		149
+#define CK_BUS_I2C2		150
+#define CK_BUS_I2C3		151
+#define CK_BUS_I3C1		152
+#define CK_BUS_I3C2		153
+#define CK_BUS_I3C3		154
+#define CK_BUS_TIM1		155
+#define CK_BUS_TIM8		156
+#define CK_BUS_TIM15		157
+#define CK_BUS_TIM16		158
+#define CK_BUS_TIM17		159
+#define CK_BUS_SAI1		160
+#define CK_BUS_SAI2		161
+#define CK_BUS_SAI3		162
+#define CK_BUS_SAI4		163
+#define CK_BUS_USART1		164
+#define CK_BUS_USART6		165
+#define CK_BUS_UART7		166
+#define CK_BUS_FDCAN		167
+#define CK_BUS_SPI1		168
+#define CK_BUS_SPI4		169
+#define CK_BUS_SPI5		170
+#define CK_BUS_SPI6		171
+#define CK_BUS_BSEC		172
+#define CK_BUS_IWDG1		173
+#define CK_BUS_IWDG2		174
+#define CK_BUS_IWDG3		175
+#define CK_BUS_IWDG4		176
+#define CK_BUS_WWDG1		177
+#define CK_BUS_VREF		178
+#define CK_BUS_DTS		179
+#define CK_BUS_SERC		180
+#define CK_BUS_HDP		181
+#define CK_BUS_DDRPERFM		182
+#define CK_BUS_OTG		183
+#define CK_BUS_LTDC		184
+#define CK_BUS_CSI		185
+#define CK_BUS_DCMIPP		186
+#define CK_BUS_DDRC		187
+#define CK_BUS_DDRCFG		188
+#define CK_BUS_STGEN		189
+#define CK_SYSDBG		190
+#define CK_KER_TIM2		191
+#define CK_KER_TIM3		192
+#define CK_KER_TIM4		193
+#define CK_KER_TIM5		194
+#define CK_KER_TIM6		195
+#define CK_KER_TIM7		196
+#define CK_KER_TIM10		197
+#define CK_KER_TIM11		198
+#define CK_KER_TIM12		199
+#define CK_KER_TIM13		200
+#define CK_KER_TIM14		201
+#define CK_KER_TIM1		202
+#define CK_KER_TIM8		203
+#define CK_KER_TIM15		204
+#define CK_KER_TIM16		205
+#define CK_KER_TIM17		206
+#define CK_BUS_SYSRAM		207
+#define CK_BUS_RETRAM		208
+#define CK_BUS_OSPI1		209
+#define CK_BUS_OTFD1		210
+#define CK_BUS_SRAM1		211
+#define CK_BUS_SDMMC1		212
+#define CK_BUS_SDMMC2		213
+#define CK_BUS_SDMMC3		214
+#define CK_BUS_DDR		215
+#define CK_BUS_RISAF4		216
+#define CK_BUS_USBHOHCI		217
+#define CK_BUS_USBHEHCI		218
+#define CK_KER_LPTIM1		219
+#define CK_KER_LPTIM2		220
+#define CK_KER_USART2		221
+#define CK_KER_UART4		222
+#define CK_KER_USART3		223
+#define CK_KER_UART5		224
+#define CK_KER_SPI2		225
+#define CK_KER_SPI3		226
+#define CK_KER_SPDIFRX		227
+#define CK_KER_I2C1		228
+#define CK_KER_I2C2		229
+#define CK_KER_I3C1		230
+#define CK_KER_I3C2		231
+#define CK_KER_I2C3		232
+#define CK_KER_I3C3		233
+#define CK_KER_SPI1		234
+#define CK_KER_SPI4		235
+#define CK_KER_SPI5		236
+#define CK_KER_SPI6		237
+#define CK_KER_USART1		238
+#define CK_KER_USART6		239
+#define CK_KER_UART7		240
+#define CK_KER_MDF1		241
+#define CK_KER_SAI1		242
+#define CK_KER_SAI2		243
+#define CK_KER_SAI3		244
+#define CK_KER_SAI4		245
+#define CK_KER_FDCAN		246
+#define CK_KER_CSI		247
+#define CK_KER_CSITXESC		248
+#define CK_KER_CSIPHY		249
+#define CK_KER_STGEN		250
+#define CK_KER_USB2PHY2EN	251
+#define CK_KER_LPUART1		252
+#define CK_KER_LPTIM3		253
+#define CK_KER_LPTIM4		254
+#define CK_KER_LPTIM5		255
+#define CK_KER_TSDBG		256
+#define CK_KER_TPIU		257
+#define CK_BUS_ETR		258
+#define CK_BUS_SYSATB		259
+#define CK_KER_ADC1		260
+#define CK_KER_ADC2		261
+#define CK_KER_OSPI1		262
+#define CK_KER_FMC		263
+#define CK_KER_SDMMC1		264
+#define CK_KER_SDMMC2		265
+#define CK_KER_SDMMC3		266
+#define CK_KER_ETH1		267
+#define CK_KER_ETH2		268
+#define CK_KER_ETH1PTP		269
+#define CK_KER_ETH2PTP		270
+#define CK_KER_USB2PHY1		271
+#define CK_KER_USB2PHY2		272
+#define CK_MCO1			273
+#define CK_MCO2			274
+#define CK_KER_DTS		275
+#define CK_ETH1_RX		276
+#define CK_ETH1_TX		277
+#define CK_ETH1_MAC		278
+#define CK_ETH2_RX		279
+#define CK_ETH2_TX		280
+#define CK_ETH2_MAC		281
+#define CK_ETH1_STP		282
+#define CK_ETH2_STP		283
+#define CK_KER_LTDC		284
+#define HSE_DIV2_CK		285
+#define CK_DBGMCU		286
+#define CK_DAP			287
+#define CK_KER_ETR		288
+#define CK_KER_STM		289
+
+#define STM32MP21_LAST_CLK	290
+
+#define CK_SCMI_ICN_HS_MCU	0
+#define CK_SCMI_ICN_SDMMC	1
+#define CK_SCMI_ICN_DDR		2
+#define CK_SCMI_ICN_DISPLAY	3
+#define CK_SCMI_ICN_HSL		4
+#define CK_SCMI_ICN_NIC		5
+#define CK_SCMI_ICN_VID		6
+#define CK_SCMI_FLEXGEN_07	7
+#define CK_SCMI_FLEXGEN_08	8
+#define CK_SCMI_FLEXGEN_09	9
+#define CK_SCMI_FLEXGEN_10	10
+#define CK_SCMI_FLEXGEN_11	11
+#define CK_SCMI_FLEXGEN_12	12
+#define CK_SCMI_FLEXGEN_13	13
+#define CK_SCMI_FLEXGEN_14	14
+#define CK_SCMI_FLEXGEN_15	15
+#define CK_SCMI_FLEXGEN_16	16
+#define CK_SCMI_FLEXGEN_17	17
+#define CK_SCMI_FLEXGEN_18	18
+#define CK_SCMI_FLEXGEN_19	19
+#define CK_SCMI_FLEXGEN_20	20
+#define CK_SCMI_FLEXGEN_21	21
+#define CK_SCMI_FLEXGEN_22	22
+#define CK_SCMI_FLEXGEN_23	23
+#define CK_SCMI_FLEXGEN_24	24
+#define CK_SCMI_FLEXGEN_25	25
+#define CK_SCMI_FLEXGEN_26	26
+#define CK_SCMI_FLEXGEN_27	27
+#define CK_SCMI_FLEXGEN_28	28
+#define CK_SCMI_FLEXGEN_29	29
+#define CK_SCMI_FLEXGEN_30	30
+#define CK_SCMI_FLEXGEN_31	31
+#define CK_SCMI_FLEXGEN_32	32
+#define CK_SCMI_FLEXGEN_33	33
+#define CK_SCMI_FLEXGEN_34	34
+#define CK_SCMI_FLEXGEN_35	35
+#define CK_SCMI_FLEXGEN_36	36
+#define CK_SCMI_FLEXGEN_37	37
+#define CK_SCMI_FLEXGEN_38	38
+#define CK_SCMI_FLEXGEN_39	39
+#define CK_SCMI_FLEXGEN_40	40
+#define CK_SCMI_FLEXGEN_41	41
+#define CK_SCMI_FLEXGEN_42	42
+#define CK_SCMI_FLEXGEN_43	43
+#define CK_SCMI_FLEXGEN_44	44
+#define CK_SCMI_FLEXGEN_45	45
+#define CK_SCMI_FLEXGEN_46	46
+#define CK_SCMI_FLEXGEN_47	47
+#define CK_SCMI_FLEXGEN_48	48
+#define CK_SCMI_FLEXGEN_49	49
+#define CK_SCMI_FLEXGEN_50	50
+#define CK_SCMI_FLEXGEN_51	51
+#define CK_SCMI_FLEXGEN_52	52
+#define CK_SCMI_FLEXGEN_53	53
+#define CK_SCMI_FLEXGEN_54	54
+#define CK_SCMI_FLEXGEN_55	55
+#define CK_SCMI_FLEXGEN_56	56
+#define CK_SCMI_FLEXGEN_57	57
+#define CK_SCMI_FLEXGEN_58	58
+#define CK_SCMI_FLEXGEN_59	59
+#define CK_SCMI_FLEXGEN_60	60
+#define CK_SCMI_FLEXGEN_61	61
+#define CK_SCMI_FLEXGEN_62	62
+#define CK_SCMI_FLEXGEN_63	63
+#define CK_SCMI_ICN_LS_MCU	64
+#define CK_SCMI_HSE		65
+#define CK_SCMI_LSE		66
+#define CK_SCMI_HSI		67
+#define CK_SCMI_LSI		68
+#define CK_SCMI_MSI		69
+#define CK_SCMI_HSE_DIV2	70
+#define CK_SCMI_CPU1		71
+#define CK_SCMI_SYSCPU1		72
+#define CK_SCMI_PLL2		73
+#define CK_SCMI_RTC		74
+#define CK_SCMI_RTCCK		75
+#define CK_SCMI_ICN_APB1	76
+#define CK_SCMI_ICN_APB2	77
+#define CK_SCMI_ICN_APB3	78
+#define CK_SCMI_ICN_APB4	79
+#define CK_SCMI_ICN_APB5	80
+#define CK_SCMI_ICN_APBDBG	81
+#define CK_SCMI_TIMG1		82
+#define CK_SCMI_TIMG2		83
+#define CK_SCMI_BKPSRAM		84
+#define CK_SCMI_BSEC		85
+#define CK_SCMI_BUS_ETR		86
+#define CK_SCMI_FMC		87
+#define CK_SCMI_GPIOA		88
+#define CK_SCMI_GPIOB		89
+#define CK_SCMI_GPIOC		90
+#define CK_SCMI_GPIOD		91
+#define CK_SCMI_GPIOE		92
+#define CK_SCMI_GPIOF		93
+#define CK_SCMI_GPIOG		94
+#define CK_SCMI_GPIOH		95
+#define CK_SCMI_GPIOI		96
+#define CK_SCMI_GPIOZ		97
+#define CK_SCMI_HPDMA1		98
+#define CK_SCMI_HPDMA2		99
+#define CK_SCMI_HPDMA3		100
+#define CK_SCMI_IPCC1		101
+#define CK_SCMI_RETRAM		102
+#define CK_SCMI_SRAM1		103
+#define CK_SCMI_SYSRAM		104
+#define CK_SCMI_OSPI1		105
+#define CK_SCMI_TPIU		106
+#define CK_SCMI_SYSDBG		107
+#define CK_SCMI_SYSATB		108
+#define CK_SCMI_TSDBG		109
+#define CK_SCMI_BUS_STM		110
+#define CK_SCMI_KER_STM		111
+#define CK_SCMI_KER_ETR		112
+
+#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */

diff --git a/include/dt-bindings/clock/stm32mp21-clksrc.h b/include/dt-bindings/clock/stm32mp21-clksrc.h
new file mode 100644
index 0000000..560ca0a
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp21-clksrc.h

@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+
+#define CMD_DIV		0
+#define CMD_MUX		1
+#define CMD_CLK		2
+#define CMD_FLEXGEN	3
+
+#define CMD_ADDR_BIT	0x80000000
+
+#define CMD_SHIFT	26
+#define CMD_MASK	0xFC000000
+#define CMD_DATA_MASK	0x03FFFFFF
+
+#define DIV_ID_SHIFT	8
+#define DIV_ID_MASK	0x0000FF00
+
+#define DIV_DIVN_SHIFT	0
+#define DIV_DIVN_MASK	0x000000FF
+
+#define MUX_ID_SHIFT	4
+#define MUX_ID_MASK	0x00000FF0
+
+#define MUX_SEL_SHIFT	0
+#define MUX_SEL_MASK	0x0000000F
+
+/* CLK define */
+#define CLK_ON_MASK	BIT(21)
+#define CLK_ON_SHIFT	21
+
+#define CLK_ID_MASK	GENMASK_32(20, 12)
+#define CLK_ID_SHIFT	12
+
+#define CLK_NO_DIV_MASK	0x0000080
+#define CLK_DIV_MASK	GENMASK_32(10, 5)
+#define CLK_DIV_SHIFT	5
+
+#define CLK_NO_SEL_MASK	0x00000010
+#define CLK_SEL_MASK	GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT	0
+
+#define CLK_CFG(clk_id, sel, div, state)	((CMD_CLK << CMD_SHIFT) |\
+						 ((state) << CLK_ON_SHIFT) |\
+						 ((clk_id) << CLK_ID_SHIFT) |\
+						 ((div) << CLK_DIV_SHIFT) |\
+						 ((sel) << CLK_SEL_SHIFT))
+
+#define CLK_OFF		0
+#define CLK_ON		1
+#define CLK_NODIV	0x00000040
+#define CLK_NOMUX	0x00000010
+
+/* Flexgen define */
+#define FLEX_ID_SHIFT	20
+#define FLEX_SEL_SHIFT	16
+#define FLEX_PDIV_SHIFT	6
+#define FLEX_FDIV_SHIFT	0
+
+#define FLEX_ID_MASK	GENMASK_32(25, 20)
+#define FLEX_SEL_MASK	GENMASK_32(19, 16)
+#define FLEX_PDIV_MASK	GENMASK_32(15, 6)
+#define FLEX_FDIV_MASK	GENMASK_32(5, 0)
+
+#define DIV_CFG(div_id, div)	((CMD_DIV << CMD_SHIFT) |\
+				 ((div_id) << DIV_ID_SHIFT |\
+				 (div)))
+
+#define MUX_CFG(mux_id, sel)	((CMD_MUX << CMD_SHIFT) |\
+				 ((mux_id) << MUX_ID_SHIFT |\
+				 (sel)))
+
+#define CLK_ADDR_SHIFT		16
+#define CLK_ADDR_MASK		0x7FFF0000
+#define CLK_ADDR_VAL_MASK	0xFFFF
+
+#define DIV_LSMCU	0
+#define DIV_APB1	1
+#define DIV_APB2	2
+#define DIV_APB3	3
+#define DIV_APB4	4
+#define DIV_APB5	5
+#define DIV_APBDBG	6
+#define DIV_RTC		7
+#define DIV_NB		8
+
+#define MUX_MUXSEL0	0
+#define MUX_MUXSEL1	1
+#define MUX_MUXSEL2	2
+#define MUX_MUXSEL3	3
+#define MUX_MUXSEL4	4
+#define MUX_MUXSEL5	5
+#define MUX_MUXSEL6	6
+#define MUX_MUXSEL7	7
+#define MUX_XBARSEL	8
+#define MUX_RTC		9
+#define MUX_MCO1	10
+#define MUX_MCO2	11
+#define MUX_ADC1	12
+#define MUX_ADC2	13
+#define MUX_USB2PHY1	14
+#define MUX_USB2PHY2	15
+#define MUX_DTS		16
+#define MUX_CPU1	17
+#define MUX_NB		18
+
+#define MUXSEL_HSI		0
+#define MUXSEL_HSE		1
+#define MUXSEL_MSI		2
+
+/* KERNEL source clocks */
+#define MUX_RTC_DISABLED	0x0
+#define MUX_RTC_LSE		0x1
+#define MUX_RTC_LSI		0x2
+#define MUX_RTC_HSE		0x3
+
+#define MUX_MCO1_FLEX61		0x0
+#define MUX_MCO1_OBSER0		0x1
+
+#define MUX_MCO2_FLEX62		0x0
+#define MUX_MCO2_OBSER1		0x1
+
+#define MUX_ADC1_FLEX46		0x0
+#define MUX_ADC1_LSMCU		0x1
+
+#define MUX_ADC2_FLEX47		0x0
+#define MUX_ADC2_LSMCU		0x1
+#define MUX_ADC2_FLEX46		0x2
+
+#define MUX_USB2PHY1_FLEX57	0x0
+#define MUX_USB2PHY1_HSE	0x1
+
+#define MUX_USB2PHY2_FLEX58	0x0
+#define MUX_USB2PHY2_HSE	0x1
+
+#define MUX_DTS_HSI		0x0
+#define MUX_DTS_HSE		0x1
+#define MUX_DTS_MSI		0x2
+
+/* PLLs source clocks */
+#define PLL_SRC_HSI		0x0
+#define PLL_SRC_HSE		0x1
+#define PLL_SRC_MSI		0x2
+#define PLL_SRC_DISABLED	0x3
+
+/* XBAR source clocks */
+#define XBAR_SRC_PLL4		0x0
+#define XBAR_SRC_PLL5		0x1
+#define XBAR_SRC_PLL6		0x2
+#define XBAR_SRC_PLL7		0x3
+#define XBAR_SRC_PLL8		0x4
+#define XBAR_SRC_HSI		0x5
+#define XBAR_SRC_HSE		0x6
+#define XBAR_SRC_MSI		0x7
+#define XBAR_SRC_HSI_KER	0x8
+#define XBAR_SRC_HSE_KER	0x9
+#define XBAR_SRC_MSI_KER	0xA
+#define XBAR_SRC_SPDIF_SYMB	0xB
+#define XBAR_SRC_I2S		0xC
+#define XBAR_SRC_LSI		0xD
+#define XBAR_SRC_LSE		0xE
+
+/*
+ * Configure a XBAR channel with its clock source
+ * channel_nb: XBAR channel number from 0 to 63
+ * channel_src: one of the 15 previous XBAR source clocks defines
+ * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
+ *		   can be either 1, 2, 4 or 1024
+ * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
+ *		   from 1 to 64
+ */
+
+#define FLEXGEN_CFG(ch, sel, pdiv, fdiv)	((CMD_FLEXGEN << CMD_SHIFT) |\
+						((ch) << FLEX_ID_SHIFT) |\
+						((sel) << FLEX_SEL_SHIFT) |\
+						((pdiv) << FLEX_PDIV_SHIFT) |\
+						((fdiv) << FLEX_FDIV_SHIFT))
+
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1			0x488
+#define MCO2			0x48C
+
+#define MCO_OFF			0
+#define MCO_ON			1
+#define MCO_STATUS_SHIFT	8
+
+#define MCO_CFG(addr, sel, status)	(CMD_ADDR_BIT |\
+					((addr) << CLK_ADDR_SHIFT) |\
+					((status) << MCO_STATUS_SHIFT) |\
+					(sel))
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD	0
+#define SSCG_MODE_DOWN_SPREAD	1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST		0
+#define LSEDRV_MEDIUM_LOW	2
+#define LSEDRV_MEDIUM_HIGH	1
+#define LSEDRV_HIGHEST		3
+
+#endif /* _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ */

diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..377a170
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h

@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
+#define _DT_BINDINGS_STM32MP21_RESET_H_
+
+/* TF-A use a binding required by driver, not aligned with Linux*/
+
+#define SYS_R		8192
+#define C1_R		8224
+#define C2_R		8288
+#define C2_HOLDBOOT_R	8608
+#define C1_HOLDBOOT_R	8609
+#define VSW_R		8672
+#define C1MS_R		8840
+#define IWDG2_KER_R	9106
+#define IWDG4_KER_R	9234
+#define DDRCP_R		9888
+#define DDRCAPB_R	9920
+#define DDRPHYCAPB_R	9952
+#define DDRCFG_R	10016
+#define DDR_R		10048
+#define OSPI1_R		10400
+#define OSPI1DLL_R	10416
+#define FMC_R		10464
+#define DBG_R		10508
+#define GPIOA_R		10592
+#define GPIOB_R		10624
+#define GPIOC_R		10656
+#define GPIOD_R		10688
+#define GPIOE_R		10720
+#define GPIOF_R		10752
+#define GPIOG_R		10784
+#define GPIOH_R		10816
+#define GPIOI_R		10848
+#define GPIOZ_R		10944
+#define HPDMA1_R	10976
+#define HPDMA2_R	11008
+#define HPDMA3_R	11040
+#define IPCC1_R		11136
+#define SSMOD_R		11392
+#define TIM1_R		14336
+#define TIM2_R		14368
+#define TIM3_R		14400
+#define TIM4_R		14432
+#define TIM5_R		14464
+#define TIM6_R		14496
+#define TIM7_R		14528
+#define TIM8_R		14560
+#define TIM10_R		14592
+#define TIM11_R		14624
+#define TIM12_R		14656
+#define TIM13_R		14688
+#define TIM14_R		14720
+#define TIM15_R		14752
+#define TIM16_R		14784
+#define TIM17_R		14816
+#define LPTIM1_R	14880
+#define LPTIM2_R	14912
+#define LPTIM3_R	14944
+#define LPTIM4_R	14976
+#define LPTIM5_R	15008
+#define SPI1_R		15040
+#define SPI2_R		15072
+#define SPI3_R		15104
+#define SPI4_R		15136
+#define SPI5_R		15168
+#define SPI6_R		15200
+#define SPDIFRX_R	15296
+#define USART1_R	15328
+#define USART2_R	15360
+#define USART3_R	15392
+#define UART4_R		15424
+#define UART5_R		15456
+#define USART6_R	15488
+#define UART7_R		15520
+#define LPUART1_R	15616
+#define I2C1_R		15648
+#define I2C2_R		15680
+#define I2C3_R		15712
+#define SAI1_R		15904
+#define SAI2_R		15936
+#define SAI3_R		15968
+#define SAI4_R		16000
+#define MDF1_R		16064
+#define ADF1_R		16096
+#define FDCAN_R		16128
+#define HDP_R		16160
+#define ADC1_R		16192
+#define ADC2_R		16224
+#define ETH1_R		16256
+#define ETH2_R		16288
+#define USBH_R		16352
+#define USB2PHY1_R	16384
+#define OTG_R		16448
+#define USB2PHY2_R	16480
+#define SDMMC1_R	16768
+#define SDMMC1DLL_R	16784
+#define SDMMC2_R	16800
+#define SDMMC2DLL_R	16816
+#define SDMMC3_R	16832
+#define SDMMC3DLL_R	16848
+#define LTDC_R		16896
+#define CSI_R		17088
+#define DCMIPP_R	17120
+#define DCMIPSSI_R	17152
+#define RNG1_R		17280
+#define RNG2_R		17312
+#define PKA_R		17344
+#define SAES_R		17376
+#define HASH1_R		17408
+#define HASH2_R		17440
+#define CRYP1_R		17472
+#define CRYP2_R		17504
+#define WWDG1_R		17696
+#define VREF_R		17760
+#define DTS_R		17792
+#define CRC_R		17824
+#define SERC_R		17856
+#define I3C1_R		17984
+#define I3C2_R		18016
+#define I3C3_R		18048
+
+#define RST_SCMI_C1_R		0
+#define RST_SCMI_C2_R		1
+#define RST_SCMI_C1_HOLDBOOT_R	2
+#define RST_SCMI_C2_HOLDBOOT_R	3
+#define RST_SCMI_FMC		4
+#define RST_SCMI_OSPI1		5
+#define RST_SCMI_OSPI1DLL	6
+
+#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */

diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index 650193c..ccd35f9 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h

@@ -44,6 +44,11 @@
 #define CORTEX_A710_CPUACTLR3_EL1				S3_0_C15_C1_2
 
 /*******************************************************************************
+ * CPU Auxiliary Control register 4 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A710_CPUACTLR4_EL1                               S3_0_C15_C1_3
+
+/*******************************************************************************
  * CPU Auxiliary Control register 5 specific definitions.
  ******************************************************************************/
 #define CORTEX_A710_CPUACTLR5_EL1				S3_0_C15_C8_0
@@ -52,14 +57,6 @@
 #define CORTEX_A710_CPUACTLR5_EL1_BIT_44			(ULL(1) << 44)
 
 /*******************************************************************************
- * CPU Auxiliary Control register specific definitions.
- ******************************************************************************/
-#define CORTEX_A710_CPUECTLR2_EL1				S3_0_C15_C1_5
-#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV			ULL(9)
-#define CPUECTLR2_EL1_PF_MODE_LSB				U(11)
-#define CPUECTLR2_EL1_PF_MODE_WIDTH				U(4)
-
-/*******************************************************************************
  * CPU Selected Instruction Private register specific definitions.
  ******************************************************************************/
 #define CORTEX_A710_CPUPSELR_EL3				S3_6_C15_C8_0

diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 2984f82..203bdfd 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,9 +19,6 @@
  ******************************************************************************/
 #define CORTEX_A78_CPUECTLR_EL1				S3_0_C15_C1_4
 #define CORTEX_A78_CPUECTLR_EL1_BIT_8			(ULL(1) << 8)
-#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV		ULL(3)
-#define CPUECTLR_EL1_PF_MODE_LSB			U(6)
-#define CPUECTLR_EL1_PF_MODE_WIDTH			U(2)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h
index d600eca..2033120 100644
--- a/include/lib/cpus/aarch64/cortex_a78c.h
+++ b/include/lib/cpus/aarch64/cortex_a78c.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,8 +24,6 @@
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
 #define CORTEX_A78C_CPUECTLR_EL1		        S3_0_C15_C1_4
-#define CORTEX_A78C_CPUECTLR_EL1_BIT_6		        (ULL(1) << 6)
-#define CORTEX_A78C_CPUECTLR_EL1_BIT_7		        (ULL(1) << 7)
 #define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN		(ULL(1) << 53)
 
 /*******************************************************************************

diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
index 9ec5177..4516339 100644
--- a/include/lib/cpus/aarch64/cortex_x2.h
+++ b/include/lib/cpus/aarch64/cortex_x2.h

@@ -19,15 +19,6 @@
 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT			(ULL(1) << 8)
 
 /*******************************************************************************
- * CPU Extended Control register 2 specific definitions
- ******************************************************************************/
-#define CORTEX_X2_CPUECTLR2_EL1					S3_0_C15_C1_5
-
-#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT			U(11)
-#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH			U(4)
-#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV			ULL(0x9)
-
-/*******************************************************************************
  * CPU Auxiliary Control register 3 specific definitions.
  ******************************************************************************/
 #define CORTEX_X2_CPUACTLR3_EL1				S3_0_C15_C1_2

diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index 8834db1..2869ec8 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h

@@ -49,15 +49,6 @@
 #define CORTEX_X3_CPUACTLR6_EL1			S3_0_C15_C8_1
 
 /*******************************************************************************
- * CPU Extended Control register 2 specific definitions.
- ******************************************************************************/
-#define CORTEX_X3_CPUECTLR2_EL1			S3_0_C15_C1_5
-
-#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB	U(11)
-#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH	U(4)
-#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV	ULL(0x9)
-
-/*******************************************************************************
  * CPU Auxiliary Control register 3 specific definitions.
  ******************************************************************************/
 #define CORTEX_X3_CPUACTLR3_EL1			S3_0_C15_C1_2

diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index c35503a..84107a4 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S

@@ -50,22 +50,6 @@
 	 *	Numeric value expected to read from CPU's MIDR
 	 * _resetfunc:
 	 *	Reset function for the CPU.
-	 * _extra1:
-	 *	This is a placeholder for future per CPU operations.  Currently,
-	 *	some CPUs use this entry to set a test function to determine if
-	 *	the workaround for CVE-2017-5715 needs to be applied or not.
-	 * _extra2:
-	 *	This is a placeholder for future per CPU operations. Currently
-	 *	some CPUs use this entry to set a function to disable the
-	 *	workaround for CVE-2018-3639.
-	 * _extra3:
-	 *	This is a placeholder for future per CPU operations. Currently,
-	 *	some CPUs use this entry to set a test function to determine if
-	 *	the workaround for CVE-2022-23960 needs to be applied or not.
-	 * _extra4:
-	 *	This is a placeholder for future per CPU operations. Currently,
-	 *	some CPUs use this entry to set a test function to determine if
-	 *	the workaround for CVE-2024-7881 needs to be applied or not.
 	 * _e_handler:
 	 *	This is a placeholder for future per CPU exception handlers.
 	 * _power_down_ops:
@@ -78,7 +62,6 @@
 	 *	used to handle power down at subsequent levels
 	 */
 	.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
-		_extra1:req, _extra2:req, _extra3:req, _extra4:req, \
 		_e_handler:req, _power_down_ops:vararg
 	.section .cpu_ops, "a"
 	.align 3
@@ -87,10 +70,6 @@
 #if defined(IMAGE_AT_EL3)
 	.quad \_resetfunc
 #endif
-	.quad \_extra1
-	.quad \_extra2
-	.quad \_extra3
-	.quad \_extra4
 	.quad \_e_handler
 #ifdef IMAGE_BL31
 	/* Insert list of functions */
@@ -153,28 +132,13 @@
 
 	.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
 		_power_down_ops:vararg
-		declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, 0, \
-			\_power_down_ops
+		declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, \_power_down_ops
 	.endm
 
 	.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
 		_e_handler:req, _power_down_ops:vararg
 		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
-			0, 0, 0, 0, \_e_handler, \_power_down_ops
-	.endm
-
-	.macro declare_cpu_ops_wa _name:req, _midr:req, \
-		_resetfunc:req, _extra1:req, _extra2:req, \
-		_extra3:req, _power_down_ops:vararg
-		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
-			\_extra1, \_extra2, \_extra3, 0, 0, \_power_down_ops
-	.endm
-
-	.macro declare_cpu_ops_wa_4 _name:req, _midr:req, \
-		_resetfunc:req, _extra1:req, _extra2:req, \
-		_extra3:req, _extra4:req, _power_down_ops:vararg
-		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
-			\_extra1, \_extra2, \_extra3, \_extra4, 0, \_power_down_ops
+			\_e_handler, \_power_down_ops
 	.endm
 
 	/*
@@ -188,14 +152,14 @@
 	 * If the field equals 1, branch targets trained in one context cannot
 	 * affect speculative execution in a different context.
 	 *
-	 * If the field equals 2, it means that the system is also aware of
+	 * If the field equals 2 or 3, it means that the system is also aware of
 	 * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
 	 * expect users of the registers to do the right thing.
 	 *
 	 * Only apply mitigations if the value of this field is 0.
 	 */
 #if ENABLE_ASSERTIONS
-	cmp	\_reg, #3 /* Only values 0 to 2 are expected */
+	cmp	\_reg, #4 /* Only values 0 to 3 are expected */
 	ASM_ASSERT(lo)
 #endif
 
@@ -240,7 +204,7 @@
  *	Default value is 0.
  */
 .macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _split_wa=0
-#if REPORT_ERRATA || ERRATA_ABI_SUPPORT
+#if INCLUDE_ERRATA_LIST
 	.pushsection .rodata.errata_entries
 		.align	3
 		.ifndef \_cpu\()_errata_list_start
@@ -534,6 +498,40 @@
 	cset	x0, ls
 .endm
 
+
+#if __clang_major__ < 17
+/*
+ * A problem with clang version < 17 can cause resolving nested
+ * 'cfi_startproc' to fail compilation.
+ * So add a compatibility variant for start and endfunc expansions
+ * to ignore `cfi_startproc` and `cfi_endproc`, this to be used only with
+ * check_errata/reset macros if we build TF-A with clang version < 17
+ */
+
+.macro func_compat _name, _align=2
+	.section .text.asm.\_name, "ax"
+	.type \_name, %function
+	.align \_align
+	\_name:
+#if ENABLE_BTI
+	BTI	jc
+#endif
+.endm
+
+/*
+ * This macro is used to mark the end of a function.
+ */
+.macro endfunc_compat _name
+	.size \_name, . - \_name
+.endm
+
+#else
+
+#define func_compat func
+#define endfunc_compat endfunc
+
+#endif /* __clang_version__ < 17 */
+
 /*
  * Helpers to select which revisions errata apply to.
  *
@@ -555,35 +553,35 @@
  *	argument: x0 - cpu_rev_var
  */
 .macro check_erratum_ls _cpu:req, _cve:req, _id:req, _rev_num:req
-	func check_erratum_\_cpu\()_\_id
+	func_compat check_erratum_\_cpu\()_\_id
 		cpu_rev_var_ls \_rev_num
 		ret
-	endfunc check_erratum_\_cpu\()_\_id
+	endfunc_compat check_erratum_\_cpu\()_\_id
 .endm
 
 .macro check_erratum_hs _cpu:req, _cve:req, _id:req, _rev_num:req
-	func check_erratum_\_cpu\()_\_id
+	func_compat check_erratum_\_cpu\()_\_id
 		cpu_rev_var_hs \_rev_num
 		ret
-	endfunc check_erratum_\_cpu\()_\_id
+	endfunc_compat check_erratum_\_cpu\()_\_id
 .endm
 
 .macro check_erratum_range _cpu:req, _cve:req, _id:req, _rev_num_lo:req, _rev_num_hi:req
-	func check_erratum_\_cpu\()_\_id
+	func_compat check_erratum_\_cpu\()_\_id
 		cpu_rev_var_range \_rev_num_lo, \_rev_num_hi
 		ret
-	endfunc check_erratum_\_cpu\()_\_id
+	endfunc_compat check_erratum_\_cpu\()_\_id
 .endm
 
 .macro check_erratum_chosen _cpu:req, _cve:req, _id:req, _chosen:req
-	func check_erratum_\_cpu\()_\_id
+	func_compat check_erratum_\_cpu\()_\_id
 		.if \_chosen
 			mov	x0, #ERRATA_APPLIES
 		.else
 			mov	x0, #ERRATA_MISSING
 		.endif
 		ret
-	endfunc check_erratum_\_cpu\()_\_id
+	endfunc_compat check_erratum_\_cpu\()_\_id
 .endm
 
 /*
@@ -591,14 +589,13 @@
  * body: clobber x0 to x4
  */
 .macro check_erratum_custom_start _cpu:req, _cve:req, _id:req
-	func check_erratum_\_cpu\()_\_id
+	func_compat check_erratum_\_cpu\()_\_id
 .endm
 
 .macro check_erratum_custom_end _cpu:req, _cve:req, _id:req
-	endfunc check_erratum_\_cpu\()_\_id
+	endfunc_compat check_erratum_\_cpu\()_\_id
 .endm
 
-
 /*******************************************************************************
  * CPU reset function wrapper
  ******************************************************************************/
@@ -611,7 +608,7 @@
  *	Name of cpu as given to declare_cpu_ops
  */
 .macro cpu_reset_prologue _cpu:req
-	func \_cpu\()_reset_func
+	func_compat \_cpu\()_reset_func
 		mov	x15, x30
 		get_rev_var x14, x0
 .endm
@@ -636,7 +633,7 @@
 .macro cpu_reset_func_end _cpu:req
 		isb
 		ret	x15
-	endfunc \_cpu\()_reset_func
+	endfunc_compat \_cpu\()_reset_func
 .endm
 
 /*

diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index 78b3e7f..089ea52 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h

@@ -26,14 +26,32 @@
 #define CLUSTERIDR_VAR_SHIFT	U(4)
 #define CLUSTERIDR_VAR_BITS	U(4)
 
+#define CLUSTERREVIDR_EL1	S3_0_C15_C3_2
+
 /********************************************************************
  * DSU Cluster Auxiliary Control registers definitions
  ********************************************************************/
 #define CLUSTERACTLR_EL1	S3_0_C15_C3_3
-#define CLUSTERPWRCTLR_EL1	S3_0_C15_C3_5
 
-#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING	(ULL(1) << 15)
-#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING	(ULL(3) << 15)
+/* CLUSTERPWRCTLR_EL1 register definitions */
+#define CLUSTERPWRCTLR_EL1		S3_0_C15_C3_5
+#define CLUSTERPWRCTLR_FUNCRET_WIDTH	U(3)
+#define CLUSTERPWRCTLR_FUNCRET_SHIFT	U(0)
+#define CLUSTERPWRCTLR_FUNCRET_RESET	U(0)
+#define CLUSTERPWRCTLR_CACHEPWR_WIDTH	U(4)
+#define CLUSTERPWRCTLR_CACHEPWR_SHIFT	U(4)
+#define CLUSTERPWRCTLR_CACHEPWR_RESET	U(7)
+
+#define CLUSTERACTLR_EL1_ASSERT_CBUSY			(ULL(1) << 8)
+#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING		(ULL(1) << 15)
+#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING		(ULL(3) << 15)
+#define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY	(ULL(3) << 20)
+
+/* CLUSTERPWRDN_EL1 register definitions */
+#define CLUSTERPWRDN_PWRDN_WIDTH	U(1)
+#define CLUSTERPWRDN_PWRDN_SHIFT	U(0)
+#define CLUSTERPWRDN_MEMRET_WIDTH	U(1)
+#define CLUSTERPWRDN_MEMRET_SHIFT	U(1)
 
 /********************************************************************
  * Masks applied for DSU errata workarounds

diff --git a/include/lib/cpus/aarch64/dsu_macros.S b/include/lib/cpus/aarch64/dsu_macros.S
index 6c8cb69..fd23f66 100644
--- a/include/lib/cpus/aarch64/dsu_macros.S
+++ b/include/lib/cpus/aarch64/dsu_macros.S

@@ -94,4 +94,44 @@
 	orr	x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING
 	msr	CLUSTERACTLR_EL1, x0
 .endm
+
+/*
+ * Check if erratum is fixed via CLUSTERREVIDR_EL1 bit (\bitpos).
+ * If not fixed (bit is clear), set x0 = ERRATA_APPLIES (from x3).
+ * If fixed (bit is set), keep x0 = ERRATA_NOT_APPLIES.
+ */
+.macro check_revidr_bit bitpos:req
+	mrs	x4, CLUSTERREVIDR_EL1
+	mov	x1, #1
+	lsl	x1, x1, #\bitpos
+	tst	x1, x4
+	csel	x0, x0, x3, NE
+.endm
+
+.macro check_errata_dsu_2900952_applies
+	mov	x0, #ERRATA_NOT_APPLIES
+	mov	x3, #ERRATA_APPLIES
+
+	/* Check if DSU revision is equal to r2p0 */
+	mrs	x1, CLUSTERIDR_EL1
+
+	/* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+	ubfx	x2, x1, #CLUSTERIDR_REV_SHIFT,\
+			#(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+	cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT)
+	b.ne	1f
+	check_revidr_bit 1
+1:
+.endm
+
+.macro errata_dsu_2900952_wa_apply
+
+	ldr	x1, =((CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY | \
+				CLUSTERACTLR_EL1_ASSERT_CBUSY))
+
+	mrs	x0, CLUSTERACTLR_EL1
+	orr	x0, x0, x1
+	msr	CLUSTERACTLR_EL1, x0
+.endm
+
 #endif /* DSU_MACROS_S */

diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index f5837d4..e4487c4 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h

@@ -62,9 +62,6 @@
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
 #define NEOVERSE_N2_CPUECTLR2_EL1			S3_0_C15_C1_5
-#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV		ULL(9)
-#define CPUECTLR2_EL1_PF_MODE_LSB			U(11)
-#define CPUECTLR2_EL1_PF_MODE_WIDTH			U(4)
 #define CPUECTLR2_EL1_TXREQ_STATIC_FULL 		ULL(0)
 #define CPUECTLR2_EL1_TXREQ_LSB				U(0)
 #define CPUECTLR2_EL1_TXREQ_WIDTH			U(3)

diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 1e2d7ea..bbba2a7 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,9 +22,6 @@
 #define NEOVERSE_V1_CPUPCR_EL3					S3_6_C15_C8_1
 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8				(ULL(1) << 8)
 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53				(ULL(1) << 53)
-#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV			ULL(3)
-#define CPUECTLR_EL1_PF_MODE_LSB				U(6)
-#define CPUECTLR_EL1_PF_MODE_WIDTH				U(2)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions

diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h
index 427cafa..cdbe2bb 100644
--- a/include/lib/cpus/aarch64/neoverse_v2.h
+++ b/include/lib/cpus/aarch64/neoverse_v2.h

@@ -32,9 +32,6 @@
  * CPU Extended Control register 2 specific definitions.
  ******************************************************************************/
 #define NEOVERSE_V2_CPUECTLR2_EL1			S3_0_C15_C1_5
-#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV		ULL(9)
-#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB		U(11)
-#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH		U(4)
 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL	ULL(0)
 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB		U(0)
 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH		U(3)

diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h
index 0b08919..5ba78cf 100644
--- a/include/lib/cpus/cpu_ops.h
+++ b/include/lib/cpus/cpu_ops.h

@@ -22,14 +22,6 @@
 /* The number of CPU operations allowed */
 #define CPU_MAX_PWR_DWN_OPS		2
 
-#if __aarch64__
-#define CPU_NO_EXTRA1_FUNC		0
-#define CPU_NO_EXTRA2_FUNC		0
-#define CPU_NO_EXTRA3_FUNC		0
-#define CPU_NO_EXTRA4_FUNC		0
-#endif /* __aarch64__ */
-
-
 /*
  * Define the sizes of the fields in the cpu_ops structure. Word size is set per
  * Aarch so keep these definitions the same and each can include whatever it
@@ -41,10 +33,6 @@
 #else
 #define CPU_RESET_FUNC_SIZE	0
 #endif /* IMAGE_AT_EL3 */
-#define CPU_EXTRA1_FUNC_SIZE	CPU_WORD_SIZE
-#define CPU_EXTRA2_FUNC_SIZE	CPU_WORD_SIZE
-#define CPU_EXTRA3_FUNC_SIZE	CPU_WORD_SIZE
-#define CPU_EXTRA4_FUNC_SIZE	CPU_WORD_SIZE
 #define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
 /* The power down core and cluster is needed only in BL31 and BL32 */
 #if defined(IMAGE_BL31) || defined(IMAGE_BL32)
@@ -86,11 +74,7 @@
 #define CPU_MIDR		0
 #define CPU_RESET_FUNC		CPU_MIDR + CPU_MIDR_SIZE
 #if __aarch64__
-#define CPU_EXTRA1_FUNC		CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
-#define CPU_EXTRA2_FUNC		CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
-#define CPU_EXTRA3_FUNC		CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
-#define CPU_EXTRA4_FUNC		CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
-#define CPU_E_HANDLER_FUNC	CPU_EXTRA4_FUNC + CPU_EXTRA4_FUNC_SIZE
+#define CPU_E_HANDLER_FUNC	CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
 #define CPU_PWR_DWN_OPS		CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
 #else
 #define CPU_PWR_DWN_OPS		CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
@@ -117,10 +101,6 @@
 	void (*reset_func)(void);
 #endif /* IMAGE_AT_EL3 */
 #if __aarch64__
-	void (*extra1_func)(void);
-	void (*extra2_func)(void);
-	void (*extra3_func)(void);
-	void (*extra4_func)(void);
 	void (*e_handler_func)(long es);
 #endif /* __aarch64__ */
 #if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS

diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 8e28d46..bb755e0 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h

@@ -27,6 +27,18 @@
 #define ERRATA_APPLIES		1
 #define ERRATA_MISSING		2
 
+/* Errata ID for smc workarounds */
+#define ARCH_WORKAROUND_2		2
+#define ARCH_WORKAROUND_3		3
+
+#define INCLUDE_ERRATA_LIST	(		\
+	REPORT_ERRATA			|	\
+	ERRATA_ABI_SUPPORT		|	\
+	WORKAROUND_CVE_2017_5715	|	\
+	WORKAROUND_CVE_2018_3639	|	\
+	WORKAROUND_CVE_2022_23960	|	\
+	WORKAROUND_CVE_2024_7881)
+
 #ifndef __ASSEMBLER__
 #include <lib/cassert.h>
 
@@ -67,10 +79,11 @@
 }
 #endif
 
-
 bool check_if_trbe_disable_affected_core(void);
 int check_wa_cve_2024_7881(void);
 bool errata_ich_vmcr_el2_applies(void);
+struct erratum_entry *find_erratum_entry(uint32_t errata_id);
+int check_erratum_applies(uint32_t cve, int errata_id);
 
 #else
 
@@ -80,11 +93,10 @@
  * NOTE an erratum and CVE id could clash. However, both numbers are very large
  * and the probablity is minuscule. Working around this makes code very
  * complicated and extremely difficult to read so it is not considered. In the
- * unlikely event that this does happen, prepending the CVE id with a 0 should
- * resolve the conflict
+ * unlikely event that this does happen, the build will fail, and unless the
+ * framework is updated to account for this one of the IDs will need to be
+ * altered to prevent the conflict.
  */
-#define ERRATUM(id)		0, id
-#define CVE(year, id)		year, id
 #define NO_ISB			1
 #define NO_ASSERT		0
 #define NO_APPLY_AT_RESET	0
@@ -97,6 +109,9 @@
 
 #endif /* __ASSEMBLER__ */
 
+#define ERRATUM(id)		0, id
+#define CVE(year, id)		year, id
+
 /* Macro to get CPU revision code for checking errata version compatibility. */
 #define CPU_REV(r, p)		((r << 4) | p)
 

diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
deleted file mode 100644
index 2ad56e1..0000000
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ /dev/null

@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2017_5715_H
-#define WA_CVE_2017_5715_H
-
-int check_wa_cve_2017_5715(void);
-
-#endif /* WA_CVE_2017_5715_H */

diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
deleted file mode 100644
index 5a7c9bf..0000000
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ /dev/null

@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2018_3639_H
-#define WA_CVE_2018_3639_H
-
-void *wa_cve_2018_3639_get_disable_ptr(void);
-
-#endif /* WA_CVE_2018_3639_H */

diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
deleted file mode 100644
index 50c0f76..0000000
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ /dev/null

@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2022_23960_H
-#define WA_CVE_2022_23960_H
-
-int check_smccc_arch_wa3_applies(void);
-
-#endif /* WA_CVE_2022_23960_H */

diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index a48ed96..72a8ea2 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h

@@ -34,17 +34,11 @@
 void cm_prepare_el3_exit(uint32_t security_state);
 void cm_prepare_el3_exit_ns(void);
 
-#if !IMAGE_BL1
-void cm_init_context_by_index(unsigned int cpu_idx,
-			      const struct entry_point_info *ep);
-#endif /* !IMAGE_BL1 */
-
 #ifdef __aarch64__
 #if IMAGE_BL31
 void cm_manage_extensions_el3(unsigned int my_idx);
 void manage_extensions_nonsecure_per_world(void);
 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx);
-void cm_handle_asymmetric_features(void);
 #endif
 
 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
@@ -97,7 +91,6 @@
 void cm_set_next_context(void *context);
 static inline void cm_manage_extensions_el3(unsigned int cpu_idx) {}
 static inline void manage_extensions_nonsecure_per_world(void) {}
-static inline void cm_handle_asymmetric_features(void) {}
 #endif /* __aarch64__ */
 
 #endif /* CONTEXT_MGMT_H */

diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index e417f45..20a6c39 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h

@@ -23,10 +23,10 @@
 /* Size of cpu_context array */
 #define CPU_DATA_CONTEXT_NUM		3
 /* Offset of cpu_ops_ptr, size 8 bytes */
-#define CPU_DATA_CPU_OPS_PTR		0x18
+#define CPU_DATA_CPU_OPS_PTR		0x20
 #else /* ENABLE_RME */
 #define CPU_DATA_CONTEXT_NUM		2
-#define CPU_DATA_CPU_OPS_PTR		0x10
+#define CPU_DATA_CPU_OPS_PTR		0x18
 #endif /* ENABLE_RME */
 
 #if ENABLE_PAUTH
@@ -47,8 +47,9 @@
 #if CRASH_REPORTING
 #error "Crash reporting is not supported in AArch32"
 #endif
-#define CPU_DATA_CPU_OPS_PTR		0x0
-#define CPU_DATA_CRASH_BUF_OFFSET	(0x4 + PSCI_CPU_DATA_SIZE)
+#define WARMBOOT_EP_INFO		0x0
+#define CPU_DATA_CPU_OPS_PTR		0x4
+#define CPU_DATA_CRASH_BUF_OFFSET	(CPU_DATA_CPU_OPS_PTR + PSCI_CPU_DATA_SIZE)
 
 #endif	/* __aarch64__ */
 
@@ -79,7 +80,12 @@
 #if ENABLE_RUNTIME_INSTRUMENTATION
 /* Temporary space to store PMF timestamps from assembly code */
 #define CPU_DATA_PMF_TS_COUNT		1
+#if __aarch64__
 #define CPU_DATA_PMF_TS0_OFFSET		CPU_DATA_EHF_DATA_BUF_END
+#else
+/* alignment */
+#define CPU_DATA_PMF_TS0_OFFSET		(CPU_DATA_EHF_DATA_BUF_END + 8)
+#endif
 #define CPU_DATA_PMF_TS0_IDX		0
 #endif
 
@@ -131,7 +137,8 @@
 #ifdef __aarch64__
 	void *cpu_context[CPU_DATA_CONTEXT_NUM];
 #endif /* __aarch64__ */
-	uintptr_t cpu_ops_ptr;
+	entry_point_info_t *warmboot_ep_info;
+	struct cpu_ops *cpu_ops_ptr;
 	struct psci_cpu_data psci_svc_cpu_data;
 #if ENABLE_PAUTH
 	uint64_t apiakey[2];
@@ -189,16 +196,19 @@
 		assert_cpu_data_pmf_ts0_offset_mismatch);
 #endif
 
-struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
+static inline cpu_data_t *_cpu_data_by_index(unsigned int cpu_index)
+{
+	return &percpu_data[cpu_index];
+}
 
 #ifdef __aarch64__
 /* Return the cpu_data structure for the current CPU. */
-static inline struct cpu_data *_cpu_data(void)
+static inline cpu_data_t *_cpu_data(void)
 {
 	return (cpu_data_t *)read_tpidr_el3();
 }
 #else
-struct cpu_data *_cpu_data(void);
+cpu_data_t *_cpu_data(void);
 #endif
 
 /*

diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h
index dbc2226..db47b80 100644
--- a/include/lib/extensions/pauth.h
+++ b/include/lib/extensions/pauth.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,12 +7,34 @@
 #ifndef PAUTH_H
 #define PAUTH_H
 
-/*******************************************************************************
- * ARMv8.3-PAuth support functions
- ******************************************************************************/
+#if ENABLE_PAUTH
+/* Platform hook to generate the APIAKey */
+uint128_t plat_init_apkey(void);
 
-/* Disable ARMv8.3 pointer authentication in EL1/EL3 */
+void pauth_init(void);
+void pauth_enable_el1(void);
+void pauth_enable_el3(void);
+void pauth_enable_el2(void);
 void pauth_disable_el1(void);
 void pauth_disable_el3(void);
-
+#else
+static inline void pauth_init(void)
+{
+}
+static inline void pauth_enable_el1(void)
+{
+}
+static inline void pauth_enable_el3(void)
+{
+}
+static inline void pauth_enable_el2(void)
+{
+}
+static inline void pauth_disable_el1(void)
+{
+}
+static inline void pauth_disable_el3(void)
+{
+}
+#endif
 #endif /* PAUTH_H */

diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h
index 97b7824..3bd4a70 100644
--- a/include/lib/libc/cdefs.h
+++ b/include/lib/libc/cdefs.h

@@ -16,12 +16,20 @@
 #define __aligned(x)	__attribute__((__aligned__(x)))
 #define __section(x)	__attribute__((__section__(x)))
 #define __fallthrough	__attribute__((__fallthrough__))
+#define __noinline	__attribute__((__noinline__))
+#define __no_pauth	__attribute__((target("branch-protection=none")))
 #if RECLAIM_INIT_CODE
 /*
  * Add each function to a section that is unique so the functions can still
- * be garbage collected
+ * be garbage collected.
+ *
+ * NOTICE: for this to work, these functions will NOT be inlined.
+ * TODO: the noinline attribute can be removed if RECLAIM_INIT_CODE is made
+ * platform agnostic and called after bl31_main(). Then, top-level functions
+ * (those that can't be inlined like bl31_main()) can be annotated with __init
+ * and noinline can be removed.
  */
-#define __init		__section(".text.init." __FILE__ "." __XSTRING(__LINE__))
+#define __init		__section(".text.init." __FILE__ "." __XSTRING(__LINE__)) __noinline
 #else
 #define __init
 #endif

diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h
index c2c9b22..30ced2a 100644
--- a/include/lib/libc/stdbool.h
+++ b/include/lib/libc/stdbool.h

@@ -9,8 +9,8 @@
 
 #define bool	_Bool
 
-#define true	(0 < 1)
-#define false	(0 > 1)
+#define true	(0 == 0)
+#define false	(0 == 1)
 
 #define __bool_true_false_are_defined	1
 

diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h
index bba9816..098fded 100644
--- a/include/lib/libc/string.h
+++ b/include/lib/libc/string.h

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 /*
- * Portions copyright (c) 2018-2020, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
  * Portions copyright (c) 2023, Intel Corporation. All rights reserved.
  * All rights reserved.
  */
@@ -14,19 +14,26 @@
 
 #include <stddef.h>
 
-void *memcpy(void *dst, const void *src, size_t len);
+/*
+ * When conditions are right, the compiler may have a baked-in call that can be
+ * inlined and that will be much more optimal than our generic implementation.
+ * When it doesn't, it will emit a call to the original function for which we
+ * provide an implementation.
+ */
+#define memcpy  __builtin_memcpy
+#define memset  __builtin_memset
+#define memcmp  __builtin_memcmp
+#define memchr  __builtin_memchr
+#define strcmp  __builtin_strcmp
+#define strncmp __builtin_strncmp
+#define strchr  __builtin_strchr
+#define strlen  __builtin_strlen
+#define strrchr __builtin_strrchr
+
 int memcpy_s(void *dst, size_t dsize, void *src, size_t ssize);
 void *memmove(void *dst, const void *src, size_t len);
-int memcmp(const void *s1, const void *s2, size_t len);
-int strcmp(const char *s1, const char *s2);
-int strncmp(const char *s1, const char *s2, size_t n);
-void *memchr(const void *src, int c, size_t len);
 void *memrchr(const void *src, int c, size_t len);
-char *strchr(const char *s, int c);
-void *memset(void *dst, int val, size_t count);
-size_t strlen(const char *s);
 size_t strnlen(const char *s, size_t maxlen);
-char *strrchr(const char *p, int ch);
 size_t strlcpy(char * dst, const char * src, size_t dsize);
 size_t strlcat(char * dst, const char * src, size_t dsize);
 char *strtok_r(char *s, const char *delim, char **last);

diff --git a/include/lib/libc/string_private.h b/include/lib/libc/string_private.h
new file mode 100644
index 0000000..ab7647a
--- /dev/null
+++ b/include/lib/libc/string_private.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STRING_PRIVATE_H
+#define STRING_PRIVATE_H
+
+/* Do not include outside of the libc. Use string.h instead. */
+
+#include <stddef.h>
+
+void *memcpy(void *dst, const void *src, size_t len);
+int memcmp(const void *s1, const void *s2, size_t len);
+int strcmp(const char *s1, const char *s2);
+int strncmp(const char *s1, const char *s2, size_t n);
+void *memchr(const void *src, int c, size_t len);
+char *strchr(const char *s, int c);
+void *memset(void *dst, int val, size_t count);
+size_t strlen(const char *s);
+char *strrchr(const char *p, int ch);
+
+#endif /* STRING_PRIVATE_H */

diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h
index 8c9296b..1e1d5fc 100644
--- a/include/lib/psci/psci_lib.h
+++ b/include/lib/psci/psci_lib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -98,6 +98,7 @@
 void __dead2 psci_pwrdown_cpu_end_terminal(void);
 void psci_pwrdown_cpu_end_wakeup(unsigned int power_level);
 void psci_do_manage_extensions(void);
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core);
 
 #endif /* __ASSEMBLER__ */
 

diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
index c403031..bdc6349 100644
--- a/include/lib/transfer_list.h
+++ b/include/lib/transfer_list.h

@@ -62,6 +62,8 @@
 	TL_TAG_EXEC_EP_INFO64 = 0x102,
 	TL_TAG_SRAM_LAYOUT64 = 0x104,
 	TL_TAG_MBEDTLS_HEAP_INFO = 0x105,
+	TL_TAG_EXEC_EP_INFO32 = 0x106,
+	TL_TAG_SRAM_LAYOUT32 = 0x107,
 };
 
 enum transfer_list_ops {

diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 6d8a06a..7dcc5ce 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h

@@ -58,9 +58,40 @@
 #define GENMASK				GENMASK_32
 #endif
 
+/*
+ * Similar to GENMASK_64 but uses a named register field to compute the mask.
+ * For a register field REG_FIELD, the macros REG_FIELD_WIDTH and
+ * REG_FIELD_SHIFT must be defined.
+ */
+#define MASK(regfield)							\
+	((~0ULL >> (64ULL - (regfield##_WIDTH))) << (regfield##_SHIFT))
+
 #define HI(addr)			(addr >> 32)
 #define LO(addr)			(addr & 0xffffffff)
 
+#define HI_64(addr)			(addr >> 64)
+#define LO_64(addr)			(addr & 0xffffffffffffffff)
+
+/**
+ * EXTRACT_FIELD - Extracts a specific bit field from a value.
+ *
+ * @reg:      The input value containing the field.
+
+ * @regfield: A bitmask representing the field. For a register field REG_FIELD,
+ *            the macros REG_FIELD_WIDTH and REG_FIELD_SHIFT must be defined.
+
+ * The result of this macro is the contents of the field right shifted to the
+ * least significant bit positions, with the rest being zero.
+ */
+#define EXTRACT(regfield, reg) \
+	(((reg) & MASK(regfield)) >> (regfield##_SHIFT))
+
+#define UPDATE_REG_FIELD(regfield, reg, val) \
+	do { \
+		(reg) &= ~(MASK(regfield)); \
+		(reg) |= ((uint64_t)(val) << (regfield##_SHIFT)); \
+	} while (0)
+
 /*
  * This variant of div_round_up can be used in macro definition but should not
  * be used in C code as the `div` parameter is evaluated twice.
@@ -218,17 +249,4 @@
  */
 #define KHZ_TICKS_PER_SEC U(1000)
 
-/**
- * EXTRACT_FIELD - Extracts a specific bit field from a value.
- *
- * @val:   The input value containing the field.
- * @mask:  A bitmask representing the maximum value of the field
- * @shift: The starting bit position of the field.
- *
- * This macro shifts the input value (@val) to the right by @shift bits,
- * aligning the target field to the least significant bits (LSB).
- * It then applies @mask to extract only the relevant bits.
- */
-#define EXTRACT_FIELD(val, mask, shift)   (((val) >> (shift)) & (mask))
-
 #endif /* UTILS_DEF_H */

diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h
deleted file mode 100644
index 3a470ad..0000000
--- a/include/lib/xlat_mpu/xlat_mpu.h
+++ /dev/null

@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef XLAT_MPU_H
-#define XLAT_MPU_H
-
-#ifndef __ASSEMBLER__
-
-#include <lib/cassert.h>
-
-#define XLAT_TABLES_LIB_V2	1
-
-void enable_mpu_el2(unsigned int flags);
-void enable_mpu_direct_el2(unsigned int flags);
-
-/*
- * Function to wipe clean and disable all MPU regions.  This function expects
- * that the MPU has already been turned off, and caching concerns addressed,
- * but it nevertheless also explicitly turns off the MPU.
- */
-void clear_all_mpu_regions(void);
-
-#endif /* __ASSEMBLER__ */
-#endif /* XLAT_MPU_H */

diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index 5434a9a..a0bc1f3 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -62,10 +62,8 @@
 #define OSH			(U(0x2) << 6)
 #define ISH			(U(0x3) << 6)
 
-#ifdef __aarch64__
 /* Guarded Page bit */
 #define GP			(ULL(1) << 50)
-#endif
 
 #define TABLE_ADDR_MASK		ULL(0x0000FFFFFFFFF000)
 
@@ -150,8 +148,8 @@
 
 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
 #define ATTR_NON_CACHEABLE		MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
-/* Device-nGnRE */
-#define ATTR_DEVICE			MAIR_DEV_nGnRE
+/* Device-nGnRnE */
+#define ATTR_DEVICE			MAIR_DEV_nGnRnE
 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
 #define ATTR_IWBWA_OWBWA_NTR		MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
 #define MAIR_ATTR_SET(attr, index)	((attr) << ((index) << 3))

diff --git a/include/plat/arm/board/fvp_r/fvp_r_bl1.h b/include/plat/arm/board/fvp_r/fvp_r_bl1.h
deleted file mode 100644
index 0b41e67..0000000
--- a/include/plat/arm/board/fvp_r/fvp_r_bl1.h
+++ /dev/null

@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FVP_R_BL1_H
-#define FVP_R_BL1_H
-
-void bl1_load_bl33(void);
-void bl1_transfer_bl33(void);
-
-#endif /* FVP_R_BL1_H */

diff --git a/include/plat/arm/common/plat_acs_smc_handler.h b/include/plat/arm/common/plat_acs_smc_handler.h
new file mode 100644
index 0000000..4d337cb
--- /dev/null
+++ b/include/plat/arm/common/plat_acs_smc_handler.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef ACS_SMC_HANDLER_H
+#define ACS_SMC_HANDLER_H
+
+#include <common/runtime_svc.h>
+#include <lib/utils_def.h>
+
+/* ARM ACS SMC service call */
+#define ARM_VEN_EL3_ACS_SMC_HANDLER     U(0xC7000030)
+#define is_acs_fid(smc_fid)             (smc_fid == ARM_VEN_EL3_ACS_SMC_HANDLER)
+
+uintptr_t plat_arm_acs_smc_handler(unsigned int smc_fid,
+				   uint64_t services,
+				   uint64_t arg0,
+				   uint64_t arg1,
+				   uint64_t arg2,
+				   void *handle);
+#endif /* ACS_SMC_HANDLER_H */

diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 1d7a59d..aed85f5 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 #include <stdint.h>
 
 #include <common/desc_image_load.h>
+#include <drivers/arm/gic.h>
 #include <drivers/arm/tzc_common.h>
 #include <lib/bakery_lock.h>
 #include <lib/cassert.h>
@@ -147,6 +148,14 @@
 
 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
 
+#ifdef __aarch64__
+#define TL_TAG_EXEC_EP_INFO	TL_TAG_EXEC_EP_INFO64
+#define TL_TAG_SRAM_LAYOUT	TL_TAG_SRAM_LAYOUT64
+#else
+#define TL_TAG_EXEC_EP_INFO	TL_TAG_EXEC_EP_INFO32
+#define TL_TAG_SRAM_LAYOUT	TL_TAG_SRAM_LAYOUT32
+#endif
+
 #if ARM_RECOM_STATE_ID_ENC
 /*
  * Macros used to parse state information from State-ID if it is using the
@@ -249,7 +258,8 @@
 void arm_bl1_plat_arch_setup(void);
 
 /* BL2 utility functions */
-void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout);
+void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1,
+				   u_register_t arg2, u_register_t arg3);
 void arm_bl2_platform_setup(void);
 void arm_bl2_plat_arch_setup(void);
 uint32_t arm_get_spsr_for_bl32_entry(void);
@@ -273,13 +283,8 @@
 void arm_bl2u_plat_arch_setup(void);
 
 /* BL31 utility functions */
-#if TRANSFER_LIST
 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
 				   u_register_t arg2, u_register_t arg3);
-#else
-void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
-				uintptr_t hw_config, void *plat_params_from_bl2);
-#endif
 void arm_bl31_platform_setup(void);
 void arm_bl31_plat_runtime_setup(void);
 void arm_bl31_plat_arch_setup(void);
@@ -295,11 +300,12 @@
 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size);
 
 /* TSP utility functions */
-void arm_tsp_early_platform_setup(void);
+void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+				  u_register_t arg2, u_register_t arg3);
 
 /* SP_MIN utility functions */
-void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
-				uintptr_t hw_config, void *plat_params_from_bl2);
+void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			u_register_t arg2, u_register_t arg3);
 void arm_sp_min_plat_runtime_setup(void);
 void arm_sp_min_plat_arch_setup(void);
 
@@ -354,6 +360,9 @@
  * Mandatory functions required in ARM standard platforms
  */
 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
+
+/* should not be used, but keep for compatibility */
+#if USE_GIC_DRIVER == 0
 void plat_arm_gic_driver_init(void);
 void plat_arm_gic_init(void);
 void plat_arm_gic_cpuif_enable(void);
@@ -363,6 +372,7 @@
 void plat_arm_gic_pcpu_init(void);
 void plat_arm_gic_save(void);
 void plat_arm_gic_resume(void);
+#endif
 void plat_arm_security_setup(void);
 void plat_arm_pwrc_setup(void);
 void plat_arm_interconnect_init(void);

diff --git a/include/plat/common/plat_lfa.h b/include/plat/common/plat_lfa.h
new file mode 100644
index 0000000..fa7c2f9
--- /dev/null
+++ b/include/plat/common/plat_lfa.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_LFA_H
+#define PLAT_LFA_H
+
+#include <services/lfa_component_desc.h>
+#include <tools_share/uuid.h>
+
+typedef struct plat_lfa_component_info {
+	const uint32_t lfa_component_id;
+	const uuid_t uuid;
+	struct lfa_component_ops *activator;
+	bool activation_pending;
+} plat_lfa_component_info_t;
+
+uint32_t plat_lfa_get_components(plat_lfa_component_info_t **components);
+bool is_plat_lfa_activation_pending(uint32_t lfa_component_id);
+int plat_lfa_cancel(uint32_t lfa_component_id);
+int plat_lfa_load_auth_image(uint32_t lfa_component_id);
+
+#endif /* PLAT_LFA_H */

diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 708cbcd..8c6ee98 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h

@@ -24,6 +24,9 @@
 #if DRTM_SUPPORT
 #include "plat_drtm.h"
 #endif /* DRTM_SUPPORT */
+#if LFA_SUPPORT
+#include "plat_lfa.h"
+#endif /* LFA_SUPPORT */
 
 /*******************************************************************************
  * Forward declarations
@@ -399,7 +402,25 @@
 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared);
 int plat_rmmd_load_manifest(struct rmm_manifest *manifest);
 int plat_rmmd_mecid_key_update(uint16_t mecid);
-#endif
+
+/* The following 4 functions are to be implemented if
+ * RMMD_ENABLE_IDE_KEY_PROG=1.
+ * The following functions are expected to return E_RMM_* error codes.
+ */
+int plat_rmmd_el3_ide_key_program(uint64_t ecam_address, uint64_t root_port_id,
+				  uint64_t ide_stream_info,
+				  rp_ide_key_info_t *ide_key_info_ptr,
+				  uint64_t request_id, uint64_t cookie);
+int plat_rmmd_el3_ide_key_set_go(uint64_t ecam_address, uint64_t root_port_id,
+				 uint64_t ide_stream_info, uint64_t request_id,
+				 uint64_t cookie);
+int plat_rmmd_el3_ide_key_set_stop(uint64_t ecam_address, uint64_t root_port_id,
+				   uint64_t ide_stream_info, uint64_t request_id,
+				   uint64_t cookie);
+int plat_rmmd_el3_ide_km_pull_response(uint64_t ecam_address, uint64_t root_port_id,
+				   uint64_t *req_resp, uint64_t *request_id,
+				   uint64_t *cookie);
+#endif /* ENABLE_RME */
 
 /*******************************************************************************
  * Optional BL31 functions (may be overridden)
@@ -465,13 +486,6 @@
 void plat_flush_next_bl_params(void);
 
 /*
- * The below function enable Trusted Firmware components like SPDs which
- * haven't migrated to the new platform API to compile on platforms which
- * have the compatibility layer disabled.
- */
-unsigned int platform_core_pos_helper(unsigned long mpidr);
-
-/*
  * Optional function to get SOC version
  */
 int32_t plat_get_soc_version(void);

diff --git a/include/services/arm_arch_svc.h b/include/services/arm_arch_svc.h
index 699a8d7..ea7de0e 100644
--- a/include/services/arm_arch_svc.h
+++ b/include/services/arm_arch_svc.h

@@ -95,6 +95,12 @@
 #define SCR_FEAT_AMUv1p1 (0)
 #endif
 
+#if ENABLE_FEAT_TWED
+#define SCR_FEAT_TWED SCR_TWEDEn_BIT
+#else
+#define SCR_FEAT_TWED (0)
+#endif
+
 #if ENABLE_FEAT_ECV
 #define SCR_FEAT_ECV SCR_ECVEN_BIT
 #else
@@ -119,7 +125,7 @@
 #define SCR_FEAT_CSV2_2 (0)
 #endif
 
-#if ENABLE_FEAT_RAS
+#if !RAS_TRAP_NS_ERR_REC_ACCESS
 #define SCR_FEAT_RAS SCR_TERR_BIT
 #else
 #define SCR_FEAT_RAS (0)
@@ -182,6 +188,7 @@
 	SCR_FEAT_HCX		|						\
 	SCR_FEAT_LS64_ACCDATA	|						\
 	SCR_FEAT_AMUv1p1	|						\
+	SCR_FEAT_TWED		|						\
 	SCR_FEAT_ECV		|						\
 	SCR_FEAT_FGT		|						\
 	SCR_FEAT_MTE2		|						\
@@ -289,6 +296,7 @@
 	MDCR_FEAT_SPE		|						\
 	MDCR_TDOSA_BIT		|						\
 	MDCR_TDA_BIT		|						\
+	MDCR_EnPM2_BIT		|						\
 	MDCR_TPM_BIT		| /* FEAT_PMUv3 */				\
 	MDCR_PLAT_FEATS)
 #define MDCR_EL3_FLIPPED (							\
@@ -300,6 +308,7 @@
 	MDCR_PLAT_FLIPPED)
 #define MDCR_EL3_IGNORED (							\
 	MDCR_EBWE_BIT		|						\
+	MDCR_EnPMS3_BIT		|						\
 	MDCR_EnPMSN_BIT		|						\
 	MDCR_SBRBE(2UL)		|						\
 	MDCR_MTPME_BIT		|						\

diff --git a/include/services/bl31_lfa.h b/include/services/bl31_lfa.h
new file mode 100644
index 0000000..cfe436c
--- /dev/null
+++ b/include/services/bl31_lfa.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BL31_LFA_H
+#define BL31_LFA_H
+
+#include <services/lfa_component_desc.h>
+
+struct lfa_component_ops *get_bl31_activator(void);
+
+#endif /* BL31_LFA_H */

diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 86110db..8e27b18 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h

@@ -102,7 +102,7 @@
 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK	ULL(0xFFFFFFFF)
 
 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT	U(8)
-#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xF)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xFFFF)
 
 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT	U(0)
 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK	ULL(0xFF)
@@ -246,10 +246,10 @@
 #define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_SHIFT		U(1)
 #define DRTM_LAUNCH_FEAT_HASHING_TYPE_SHIFT		U(0)
 
-#define DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_MASK      	U(0x1)
-#define DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_MASK 	U(0x7)
-#define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_MASK   	U(0x3)
-#define DRTM_LAUNCH_FEAT_HASHING_TYPE_MASK       	U(0x1)
+#define DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_WIDTH		U(1)
+#define DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_WIDTH	U(3)
+#define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_WIDTH		U(2)
+#define DRTM_LAUNCH_FEAT_HASHING_TYPE_WIDTH		U(1)
 
 #define DLME_IMG_AUTH					U(0x1)
 #define REG_MEM_PROTECTION_TYPE				U(0x1)

diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index f5a9a2d..0010d2b 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -57,8 +57,8 @@
 	<< FFA_MSG_SEND_ATTRS_BLK_SHIFT)
 
 /* Defines for FF-A framework messages exchanged using direct messages. */
-#define FFA_FWK_MSG_BIT		BIT(31)
-#define FFA_FWK_MSG_MASK	0xFF
+#define FFA_FWK_MSG_BIT		BIT_32(31)
+#define FFA_FWK_MSG_MASK	U(0xFF)
 #define FFA_FWK_MSG_PSCI	U(0x0)
 
 /* Defines for FF-A power management messages framework messages. */

diff --git a/include/services/lfa_component_desc.h b/include/services/lfa_component_desc.h
new file mode 100644
index 0000000..5f198bd
--- /dev/null
+++ b/include/services/lfa_component_desc.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LFA_COMPONENT_DESC_H
+#define LFA_COMPONENT_DESC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef enum {
+	PRIME_NONE = 0,
+	PRIME_STARTED,
+	PRIME_COMPLETE,
+} lfa_prime_status_t;
+
+struct lfa_component_status {
+	uint32_t component_id;
+	lfa_prime_status_t prime_status;
+	bool cpu_rendezvous_required;
+};
+
+typedef int32_t (*component_prime_fn)(struct lfa_component_status *activation);
+typedef int32_t (*component_activate_fn)(struct lfa_component_status *activation,
+					 uint64_t ep_address,
+					 uint64_t context_id);
+
+struct lfa_component_ops {
+	component_prime_fn prime;
+	component_activate_fn activate;
+	bool may_reset_cpu;
+	bool cpu_rendezvous_required;
+};
+
+#endif /* LFA_COMPONENT_DESC_H */

diff --git a/include/services/lfa_holding_pen.h b/include/services/lfa_holding_pen.h
new file mode 100644
index 0000000..9420747
--- /dev/null
+++ b/include/services/lfa_holding_pen.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LFA_HOLDING_PEN_H
+#define LFA_HOLDING_PEN_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <services/lfa_svc.h>
+
+bool lfa_holding_start(void);
+enum lfa_retc lfa_holding_wait(void);
+void lfa_holding_release(enum lfa_retc status);
+
+#endif

diff --git a/include/services/lfa_svc.h b/include/services/lfa_svc.h
new file mode 100644
index 0000000..69d549c
--- /dev/null
+++ b/include/services/lfa_svc.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LFA_SVC_H
+#define LFA_SVC_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/smccc.h>
+#include <services/lfa_component_desc.h>
+#include <tools_share/uuid.h>
+
+/*
+ * SMC function IDs for LFA Service
+ * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4)
+ */
+#define LFA_FID(func_num)				\
+	((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) |		\
+	(SMC_64 << FUNCID_CC_SHIFT) |			\
+	(OEN_STD_START << FUNCID_OEN_SHIFT) |		\
+	((func_num) << FUNCID_NUM_SHIFT))
+
+#define LFA_VERSION			LFA_FID(0x2E0)
+#define LFA_FEATURES			LFA_FID(0x2E1)
+#define LFA_GET_INFO			LFA_FID(0x2E2)
+#define LFA_GET_INVENTORY		LFA_FID(0x2E3)
+#define LFA_PRIME			LFA_FID(0x2E4)
+#define LFA_ACTIVATE			LFA_FID(0x2E5)
+#define LFA_CANCEL			LFA_FID(0x2E6)
+
+/* Check whether FID is in the range */
+#define is_lfa_fid(_fid)	\
+	((_fid >= LFA_VERSION) && (_fid <= LFA_CANCEL))
+
+/* LFA Service Calls version numbers */
+#define LFA_VERSION_MAJOR		U(1)
+#define LFA_VERSION_MAJOR_SHIFT		16
+#define LFA_VERSION_MAJOR_MASK		U(0x7FFF)
+#define LFA_VERSION_MINOR		U(0)
+#define LFA_VERSION_MINOR_SHIFT		0
+#define LFA_VERSION_MINOR_MASK		U(0xFFFF)
+
+#define LFA_VERSION_VAL						\
+	((((LFA_VERSION_MAJOR) & LFA_VERSION_MAJOR_MASK) <<	\
+	LFA_VERSION_MAJOR_SHIFT)				\
+	| (((LFA_VERSION_MINOR) & LFA_VERSION_MINOR_MASK) <<	\
+	LFA_VERSION_MINOR_SHIFT))
+
+#define LFA_INVALID_COMPONENT		U(0xFFFFFFFF)
+
+#define LFA_ACTIVATION_CAPABLE_SHIFT		0
+#define LFA_ACTIVATION_PENDING_SHIFT		1
+#define LFA_MAY_RESET_CPU_SHIFT			2
+#define LFA_CPU_RENDEZVOUS_OPTIONAL_SHIFT	3
+
+#define LFA_SKIP_CPU_RENDEZVOUS_BIT		BIT(0)
+
+/* List of errors as per the specification */
+enum lfa_retc {
+	LFA_SUCCESS			=  0,
+	LFA_NOT_SUPPORTED		= -1,
+	LFA_BUSY			= -2,
+	LFA_AUTH_ERROR			= -3,
+	LFA_NO_MEMORY			= -4,
+	LFA_CRITICAL_ERROR		= -5,
+	LFA_DEVICE_ERROR		= -6,
+	LFA_WRONG_STATE			= -7,
+	LFA_INVALID_PARAMETERS		= -8,
+	LFA_COMPONENT_WRONG_STATE	= -9,
+	LFA_INVALID_ADDRESS		= -10,
+	LFA_ACTIVATION_FAILED		= -11,
+};
+
+/* Initialization routine for the LFA service */
+int lfa_setup(void);
+
+uint64_t lfa_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+			 u_register_t x3, u_register_t x4, void *cookie,
+			 void *handle, u_register_t flags);
+void lfa_reset_activation(void);
+
+#endif /* LFA_SVC_H */

diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h
index 2d6e71f..c094f6a 100644
--- a/include/services/rmm_core_manifest.h
+++ b/include/services/rmm_core_manifest.h

@@ -14,20 +14,21 @@
 #include <lib/cassert.h>
 
 #define RMMD_MANIFEST_VERSION_MAJOR		U(0)
-#define RMMD_MANIFEST_VERSION_MINOR		U(4)
+#define RMMD_MANIFEST_VERSION_MINOR		U(5)
 
 #define RMM_CONSOLE_MAX_NAME_LEN		U(8)
 
 /*
- * Manifest version encoding:
+ * Version encoding:
  *	- Bit[31] RES0
  *	- Bits [30:16] Major version
  *	- Bits [15:0] Minor version
  */
-#define SET_RMMD_MANIFEST_VERSION(_major, _minor)		\
+#define SET_VERSION(_major, _minor)				\
 	((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF))
 
-#define RMMD_MANIFEST_VERSION	SET_RMMD_MANIFEST_VERSION(	\
+/* Boot Manifest version */
+#define RMMD_MANIFEST_VERSION	SET_VERSION(			\
 				RMMD_MANIFEST_VERSION_MAJOR,	\
 				RMMD_MANIFEST_VERSION_MINOR)
 
@@ -37,9 +38,17 @@
 #define RMMD_GET_MANIFEST_VERSION_MINOR(_version)		\
 	(_version & 0xFFFF)
 
+#define PCIE_RC_INFO_VERSION_MAJOR		U(0)
+#define PCIE_RC_INFO_VERSION_MINOR		U(1)
+
+/* PCIe Root Complex info structure version */
+#define PCIE_RC_INFO_VERSION	SET_VERSION(			\
+				PCIE_RC_INFO_VERSION_MAJOR,	\
+				PCIE_RC_INFO_VERSION_MINOR)
+
 /* Memory bank/device region structure */
 struct memory_bank {
-	uintptr_t base;			/* Base address */
+	uint64_t base;			/* Base address */
 	uint64_t size;			/* Size of memory bank/device region */
 };
 
@@ -64,7 +73,7 @@
 
 /* Console info structure */
 struct console_info {
-	uintptr_t base;			/* Console base address */
+	uint64_t base;			/* Console base address */
 	uint64_t map_pages;		/* Num of pages to be mapped in RMM for the console MMIO */
 	char name[RMM_CONSOLE_MAX_NAME_LEN];	/* Name of console */
 	uint64_t clk_in_hz;		/* UART clock (in Hz) for the console */
@@ -98,11 +107,105 @@
 CASSERT(offsetof(struct console_list, checksum) == 16UL,
 			rmm_manifest_console_list_checksum);
 
-/* Boot manifest core structure as per v0.4 */
+/* SMMUv3 Info structure */
+struct smmu_info {
+	uint64_t smmu_base;		/* SMMUv3 base address */
+	uint64_t smmu_r_base;		/* SMMUv3 Realm Pages base address */
+};
+
+CASSERT(offsetof(struct smmu_info, smmu_base) == 0UL,
+			rmm_manifest_smmu_base);
+CASSERT(offsetof(struct smmu_info, smmu_r_base) == 8UL,
+			rmm_manifest_smmu_r_base);
+
+/* SMMUv3 Info List structure */
+struct smmu_list {
+	uint64_t num_smmus;		/* Number of smmu_info entries */
+	struct smmu_info *smmus;	/* Pointer to smmu_info[] array */
+	uint64_t checksum;		/* Checksum of smmu_list data */
+};
+
+CASSERT(offsetof(struct smmu_list, num_smmus) == 0UL,
+			rmm_manifest_num_smmus);
+CASSERT(offsetof(struct smmu_list, smmus) == 8UL,
+			rmm_manifest_smmus);
+CASSERT(offsetof(struct smmu_list, checksum) == 16UL,
+			rmm_manifest_smmu_list_checksum);
+
+/* PCIe BDF Mapping Info structure */
+struct bdf_mapping_info {
+	uint16_t mapping_base;	/* Base of BDF mapping (inclusive) */
+	uint16_t mapping_top;	/* Top of BDF mapping (exclusive) */
+	uint16_t mapping_off;	/* Mapping offset, as per Arm Base System Architecture: */
+				/* StreamID = zero_extend(RequesterID[N-1:0]) + (1<<N)*Constant_B */
+	uint16_t smmu_idx;	/* SMMU index in smmu_info[] array */
+};
+
+CASSERT(offsetof(struct bdf_mapping_info, mapping_base) == 0UL,
+			rmm_manifest_mapping_base);
+CASSERT(offsetof(struct bdf_mapping_info, mapping_top) == 2UL,
+			rmm_manifest_mapping_top);
+CASSERT(offsetof(struct bdf_mapping_info, mapping_off) == 4UL,
+			rmm_manifest_mapping_off);
+CASSERT(offsetof(struct bdf_mapping_info, smmu_idx) == 6UL,
+			rmm_manifest_smmu_ptr);
+
+/* PCIe Root Port Info structure */
+struct root_port_info {
+	uint16_t root_port_id;			/* Root Port identifier */
+	uint16_t padding;			/* RES0 */
+	uint32_t num_bdf_mappings;		/* Number of BDF mappings */
+	struct bdf_mapping_info *bdf_mappings;	/* Pointer to bdf_mapping_info[] array */
+};
+
+CASSERT(offsetof(struct root_port_info, root_port_id) == 0UL,
+			rmm_manifest_root_port_id);
+CASSERT(offsetof(struct root_port_info, num_bdf_mappings) == 4UL,
+			rmm_manifest_num_bdf_mappingss);
+CASSERT(offsetof(struct root_port_info, bdf_mappings) == 8UL,
+			rmm_manifest_bdf_mappings);
+
+/* PCIe Root Complex info structure v0.1 */
+struct root_complex_info {
+	uint64_t ecam_base;			/* ECAM base address. Size is implicitly 256MB */
+	uint8_t segment;			/* PCIe segment identifier */
+	uint8_t padding[3];			/* RES0 */
+	uint32_t num_root_ports;		/* Number of root ports */
+	struct root_port_info *root_ports;	/* Pointer to root_port_info[] array */
+};
+
+CASSERT(offsetof(struct root_complex_info, ecam_base) == 0UL,
+			rmm_manifest_ecam_base);
+CASSERT(offsetof(struct root_complex_info, segment) == 8UL,
+			rmm_manifest_segment);
+CASSERT(offsetof(struct root_complex_info, num_root_ports) == 12UL,
+			rmm_manifest_num_root_ports);
+CASSERT(offsetof(struct root_complex_info, root_ports) == 16UL,
+			rmm_manifest_root_ports);
+
+/* PCIe Root Complex List structure */
+struct root_complex_list {
+	uint64_t num_root_complex;		/* Number of pci_rc_info entries */
+	uint32_t rc_info_version;		/* PCIe Root Complex info structure version */
+	uint32_t padding;			/* RES0 */
+	struct root_complex_info *root_complex;	/* Pointer to pci_rc_info[] array */
+	uint64_t checksum;			/* Checksum of pci_rc_list data */
+};
+
+CASSERT(offsetof(struct root_complex_list, num_root_complex) == 0UL,
+			rmm_manifest_num_root_complex);
+CASSERT(offsetof(struct root_complex_list, rc_info_version) == 8UL,
+			rmm_manifest_rc_info_version);
+CASSERT(offsetof(struct root_complex_list, root_complex) == 16UL,
+			rmm_manifest_root_complex);
+CASSERT(offsetof(struct root_complex_list, checksum) == 24UL,
+			rmm_manifest_root_complex_list_checksum);
+
+/* Boot manifest core structure as per v0.5 */
 struct rmm_manifest {
 	uint32_t version;			/* Manifest version */
 	uint32_t padding;			/* RES0 */
-	uintptr_t plat_data;			/* Manifest platform data */
+	uint64_t plat_data;			/* Manifest platform data */
 	/* Platform NS DRAM data (v0.2) */
 	struct memory_info plat_dram;
 	/* Platform console list (v0.3) */
@@ -110,6 +213,10 @@
 	/* Platform device address ranges (v0.4) */
 	struct memory_info plat_ncoh_region;
 	struct memory_info plat_coh_region;
+	/* Platform SMMUv3 list (v0.5) */
+	struct smmu_list plat_smmu;
+	/* Platform PCIe Root Complex list (v0.5) */
+	struct root_complex_list plat_root_complex;
 };
 
 CASSERT(offsetof(struct rmm_manifest, version) == 0UL,
@@ -124,5 +231,9 @@
 			rmm_manifest_plat_ncoh_region_unaligned);
 CASSERT(offsetof(struct rmm_manifest, plat_coh_region) == 88UL,
 			rmm_manifest_plat_coh_region_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_smmu) == 112UL,
+			rmm_manifest_plat_smmu_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_root_complex) == 136UL,
+			rmm_manifest_plat_root_complex);
 
 #endif /* RMM_CORE_MANIFEST_H */

diff --git a/include/services/rmmd_rmm_lfa.h b/include/services/rmmd_rmm_lfa.h
new file mode 100644
index 0000000..6720cb5
--- /dev/null
+++ b/include/services/rmmd_rmm_lfa.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RMMD_RMM_LFA_H
+#define RMMD_RMM_LFA_H
+
+#include <services/lfa_component_desc.h>
+
+struct lfa_component_ops *get_rmm_activator(void);
+
+#endif /* RMMD_RMM_LFA_H */

diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index 8bf9319..9b99e92 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h

@@ -92,6 +92,8 @@
 #define E_RMM_NOMEM			-4
 #define E_RMM_INVAL			-5
 #define E_RMM_AGAIN			-6
+#define E_RMM_FAULT			-7
+#define E_RMM_IN_PROGRESS		-8
 
 /* Return error codes from RMI SMCs */
 #define RMI_SUCCESS			0
@@ -179,6 +181,83 @@
 /* Identifier for the hash algorithm used for attestation signing */
 #define EL3_TOKEN_SIGN_HASH_ALG_SHA384		U(1)
 
+/* Starting RMM-EL3 interface version 0.6 */
+/*
+ * Function codes to support RMM IDE Key management Interface.
+ * The arguments to this SMC are:
+ *     arg0 - Function ID.
+ *     arg1 - Enhanced Configuration Access Mechanism address
+ *     arg2 - Root Port ID
+ *     arg3 - IDE selective stream info
+ *     arg4 - Quad word of key[63:0]
+ *     arg5 - Quad word of key[127:64]
+ *     arg6 - Quad word of key[191:128]
+ *     arg7 - Quad word of key[255:192]
+ *     arg8 - Quad word of IV [63:0]
+ *     arg9 - Quad word of IV [95:64]
+ *     arg10 - request_id
+ *     arg11 - cookie
+ * The return arguments are:
+ *     ret0 - Status/Error
+ */
+#define RMM_IDE_KEY_PROG			SMC64_RMMD_EL3_FID(U(7))
+
+/*******************************************************************************
+ * Structure to hold el3_ide_key info
+ ******************************************************************************/
+#ifndef __ASSEMBLER__
+typedef struct rp_ide_key_info {
+	uint64_t keyqw0;
+	uint64_t keyqw1;
+	uint64_t keyqw2;
+	uint64_t keyqw3;
+	uint64_t ifvqw0;
+	uint64_t ifvqw1;
+} rp_ide_key_info_t;
+#endif /* __ASSEMBLER__ */
+
+/*
+ * Function codes to support RMM IDE Key management Interface.
+ * The arguments to this SMC are:
+ *     arg0 - Function ID.
+ *     arg1 - Enhanced Configuration Access Mechanism address
+ *     arg2 - Root Port ID
+ *     arg3 - IDE selective stream info
+ *     arg4 - request_id
+ *     arg5 - cookie
+ * The return arguments are:
+ *     ret0 - Status/Error
+ */
+#define RMM_IDE_KEY_SET_GO			SMC64_RMMD_EL3_FID(U(8))
+
+/*
+ * Function codes to support RMM IDE Key management Interface.
+ * The arguments to this SMC are:
+ *     arg0 - Function ID.
+ *     arg1 - Enhanced Configuration Access Mechanism address
+ *     arg2 - Root Port ID
+ *     arg3 - IDE selective stream info
+ *     arg4 - request_id
+ *     arg5 - cookie
+ * The return arguments are:
+ *     ret0 - Status/Error
+ */
+#define RMM_IDE_KEY_SET_STOP			SMC64_RMMD_EL3_FID(U(9))
+
+/*
+ * Function codes to support RMM IDE Key management Interface.
+ * The arguments to this SMC are:
+ *     arg0 - Function ID.
+ *     arg1 - Enhanced Configuration Access Mechanism address
+ *     arg2 - Root Port ID
+ * The return arguments are:
+ *     ret0 - Status/Error
+ *     ret1 - Retrieved response corresponding to the previous request.
+ *     ret2 - request_id
+ *     ret3 - cookie
+ */
+#define RMM_IDE_KM_PULL_RESPONSE		SMC64_RMMD_EL3_FID(U(10))
+
 /*
  * RMM_BOOT_COMPLETE originates on RMM when the boot finishes (either cold
  * or warm boot). This is handled by the RMM-EL3 interface SMC handler.
@@ -200,7 +279,7 @@
  * Increase this when a bug is fixed, or a feature is added without
  * breaking compatibility.
  */
-#define RMM_EL3_IFC_VERSION_MINOR	(U(5))
+#define RMM_EL3_IFC_VERSION_MINOR	(U(6))
 
 #define RMM_EL3_INTERFACE_VERSION				\
 	(((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) |	\

diff --git a/include/services/trp/platform_trp.h b/include/services/trp/platform_trp.h
index 756e9db..67dfff1 100644
--- a/include/services/trp/platform_trp.h
+++ b/include/services/trp/platform_trp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,4 +16,8 @@
  ******************************************************************************/
 void trp_early_platform_setup(struct rmm_manifest *manifest);
 
+#if RMMD_ENABLE_IDE_KEY_PROG
+uint64_t trp_get_test_rootport(uint64_t *ecam, uint64_t *rootport);
+#endif /* RMMD_ENABLE_IDE_KEY_PROG */
+
 #endif /* PLATFORM_TRP_H */

diff --git a/include/services/trp/trp_helpers.h b/include/services/trp/trp_helpers.h
index 83ec740..2f36720 100644
--- a/include/services/trp/trp_helpers.h
+++ b/include/services/trp/trp_helpers.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,11 @@
 #define TRP_ARG5		0x28
 #define TRP_ARG6		0x30
 #define TRP_ARG7		0x38
-#define TRP_ARGS_END		0x40
+#define TRP_ARG8		0x40
+#define TRP_ARG9		0x48
+#define TRP_ARG10		0x50
+#define TRP_ARG11		0x58
+#define TRP_ARGS_END		0x60
 
 #ifndef __ASSEMBLER__
 
@@ -35,7 +39,11 @@
 			 uint64_t arg4,
 			 uint64_t arg5,
 			 uint64_t arg6,
-			 uint64_t arg7);
+			 uint64_t arg7,
+			 uint64_t arg8,
+			 uint64_t arg9,
+			 uint64_t arg10,
+			 uint64_t arg11);
 
 __dead2 void trp_boot_abort(uint64_t err);
 

diff --git a/include/services/ven_el3_svc.h b/include/services/ven_el3_svc.h
index e030b68..0336059 100644
--- a/include/services/ven_el3_svc.h
+++ b/include/services/ven_el3_svc.h

@@ -21,7 +21,7 @@
 #define VEN_EL3_SVC_VERSION	0x8700ff03
 
 #define VEN_EL3_SVC_VERSION_MAJOR	1
-#define VEN_EL3_SVC_VERSION_MINOR	0
+#define VEN_EL3_SVC_VERSION_MINOR	1
 
 /* DEBUGFS_SMC_32		0x87000010U */
 /* DEBUGFS_SMC_64		0xC7000010U */
@@ -29,4 +29,7 @@
 /* PMF_SMC_GET_TIMESTAMP_32	0x87000020U */
 /* PMF_SMC_GET_TIMESTAMP_64	0xC7000020U */
 
+/* ACS_SMC_HANDLER_32           0x87000030U */
+/* ACS_SMC_HANDLER_64           0xC7000030U */
+
 #endif /* VEN_EL3_SVC_H */

diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S
index ff9a4e6..cc46c53 100644
--- a/lib/aarch64/cache_helpers.S
+++ b/lib/aarch64/cache_helpers.S

@@ -215,7 +215,7 @@
 
 	.macro	dcsw_loop _op
 #if ENABLE_BTI
-	bti	j
+	BTI	j
 #endif
 loop2_\_op:
 	lsl	w7, w6, w2		// w7 = aligned max set number

diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 93771df..f95fb6e 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S

@@ -21,10 +21,6 @@
 	.globl	disable_mmu_icache_el1
 	.globl	disable_mmu_icache_el3
 	.globl	fixup_gdt_reloc
-#if SUPPORT_VFP
-	.globl	enable_vfp
-#endif
-
 func smc
 	smc	#0
 endfunc smc
@@ -456,24 +452,6 @@
 endfunc disable_mmu_icache_el1
 
 /* ---------------------------------------------------------------------------
- * Enable the use of VFP at EL3
- * ---------------------------------------------------------------------------
- */
-#if SUPPORT_VFP
-func enable_vfp
-	mrs	x0, cpacr_el1
-	orr	x0, x0, #CPACR_VFP_BITS
-	msr	cpacr_el1, x0
-	mrs	x0, cptr_el3
-	mov	x1, #AARCH64_CPTR_TFP
-	bic	x0, x0, x1
-	msr	cptr_el3, x0
-	isb
-	ret
-endfunc enable_vfp
-#endif
-
-/* ---------------------------------------------------------------------------
  * Helper to fixup Global Descriptor table (GDT) and dynamic relocations
  * (.rela.dyn) at runtime.
  *

diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 6ec6742..258817f 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S

@@ -128,6 +128,15 @@
 
 check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
 
+workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941
+	errata_dsu_2313941_wa_impl
+workaround_reset_end cortex_a510, ERRATUM(2313941)
+
+check_erratum_custom_start cortex_a510, ERRATUM(2313941)
+	check_errata_dsu_2313941_impl
+	ret
+check_erratum_custom_end cortex_a510, ERRATUM(2313941)
+
 workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
 	/*
 	 * Set CPUACTLR_EL1[17] to 1'b1, which disables
@@ -169,15 +178,6 @@
 
 check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
 
-workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941
-	errata_dsu_2313941_wa_impl
-workaround_reset_end cortex_a510, ERRATUM(2313941)
-
-check_erratum_custom_start cortex_a510, ERRATUM(2313941)
-	check_errata_dsu_2313941_impl
-	ret
-check_erratum_custom_end cortex_a510, ERRATUM(2313941)
-
 .global check_erratum_cortex_a510_2971420
 add_erratum_entry cortex_a510, ERRATUM(2971420), ERRATA_A510_2971420
 check_erratum_range cortex_a510, ERRATUM(2971420), CPU_REV(0, 1), CPU_REV(1, 3)

diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index ac8019e..5e0b711 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_a520.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 
 .global check_erratum_cortex_a520_2938996
@@ -37,6 +38,15 @@
 
 check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
 
+workaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a520, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a520, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_a520, ERRATUM(2900952)
+
 add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996
 
 check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1)

diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index cf91431..f5921a2 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S

@@ -22,24 +22,6 @@
 
 cpu_reset_prologue cortex_a55
 
-workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
-	errata_dsu_798953_wa_impl
-workaround_reset_end cortex_a55, ERRATUM(798953)
-
-check_erratum_custom_start cortex_a55, ERRATUM(798953)
-	check_errata_dsu_798953_impl
-	ret
-check_erratum_custom_end cortex_a55, ERRATUM(798953)
-
-workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
-	errata_dsu_936184_wa_impl
-workaround_reset_end cortex_a55, ERRATUM(936184)
-
-check_erratum_custom_start cortex_a55, ERRATUM(936184)
-	check_errata_dsu_936184_impl
-	ret
-check_erratum_custom_end cortex_a55, ERRATUM(936184)
-
 workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
 	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
 workaround_reset_end cortex_a55, ERRATUM(768277)
@@ -71,6 +53,15 @@
 
 check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
 
+workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
+	errata_dsu_798953_wa_impl
+workaround_reset_end cortex_a55, ERRATUM(798953)
+
+check_erratum_custom_start cortex_a55, ERRATUM(798953)
+	check_errata_dsu_798953_impl
+	ret
+check_erratum_custom_end cortex_a55, ERRATUM(798953)
+
 workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
 	sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
 workaround_reset_end cortex_a55, ERRATUM(846532)
@@ -83,6 +74,15 @@
 
 check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
 
+workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
+	errata_dsu_936184_wa_impl
+workaround_reset_end cortex_a55, ERRATUM(936184)
+
+check_erratum_custom_start cortex_a55, ERRATUM(936184)
+	check_errata_dsu_936184_impl
+	ret
+check_erratum_custom_end cortex_a55, ERRATUM(936184)
+
 workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
 	mov	x0, #0x0020
 	movk	x0, #0x0850, lsl #16

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index adacc5c..553f6f9 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S

@@ -65,15 +65,20 @@
 	ret
 endfunc cortex_a57_disable_ext_debug
 
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
 /*
  * Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't
- * provide and erratum number, so assign it an obvious 1
+ * provide and erratum number, so assign it an obvious 99999
  */
-workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT
+workaround_reset_start cortex_a57, ERRATUM(99999), A57_DISABLE_NON_TEMPORAL_HINT
 	sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-workaround_reset_end cortex_a57, ERRATUM(1)
+workaround_reset_end cortex_a57, ERRATUM(99999)
 
-check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2)
+check_erratum_ls cortex_a57, ERRATUM(99999), CPU_REV(1, 2)
 
 workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969
 	sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
@@ -187,11 +192,6 @@
 	sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
 cpu_reset_func_end cortex_a57
 
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
-
 	/* ----------------------------------------------------
 	 * The CPU Ops core power down function for Cortex-A57.
 	 * ----------------------------------------------------
@@ -307,10 +307,7 @@
 	ret
 endfunc cortex_a57_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
+declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
 	cortex_a57_reset_func, \
-	check_erratum_cortex_a57_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a57_core_pwr_dwn, \
 	cortex_a57_cluster_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index e8f5a80..728c51f 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S

@@ -31,12 +31,23 @@
 
 cpu_reset_prologue cortex_a710
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_a710,  CVE(2024, 5660)
+workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946
+	sysreg_bit_set	CORTEX_A710_CPUACTLR4_EL1, BIT(15)
+workaround_reset_end cortex_a710, ERRATUM(1901946)
 
-check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
+check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945
+	sysreg_bit_set	CORTEX_A710_CPUECTLR_EL1, BIT(8)
+workaround_reset_end cortex_a710, ERRATUM(1916945)
+
+check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258
+	sysreg_bit_set	CORTEX_A710_CPUACTLR4_EL1, BIT(43)
+workaround_reset_end cortex_a710, ERRATUM(1917258)
+
+check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0)
 
 workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
 	ldr x0,=0x6
@@ -94,13 +105,6 @@
 
 check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0)
 
-workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
-	sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
-		CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end cortex_a710, ERRATUM(2058056)
-
-check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1)
-
 workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
 	ldr	x0,=0x3
 	msr	S3_6_c15_c8_0,x0
@@ -213,6 +217,10 @@
 
 check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
 
+add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
+
+check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
+
 workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -225,9 +233,12 @@
 
 check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
-add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_a710,  CVE(2024, 5660)
 
-check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
+check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down

diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index fee28ee..23b27ab 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S

@@ -76,14 +76,17 @@
 	ret
 endfunc cortex_a72_disable_ext_debug
 
-func check_smccc_arch_workaround_3
+check_erratum_custom_start cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
 	cpu_check_csv2	x0, 1f
 	mov	x0, #ERRATA_APPLIES
 	ret
 1:
 	mov	x0, #ERRATA_NOT_APPLIES
 	ret
-endfunc check_smccc_arch_workaround_3
+check_erratum_custom_end cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
+
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a72, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
 
 workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
 	sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
@@ -294,10 +297,7 @@
 	ret
 endfunc cortex_a72_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
+declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
 	cortex_a72_reset_func, \
-	check_erratum_cortex_a72_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a72_core_pwr_dwn, \
 	cortex_a72_cluster_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index e639996..0c713c3 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_a720.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 #include "wa_cve_2022_23960_bhb_vector.S"
 
@@ -42,6 +43,15 @@
 
 check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
 
+workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a720, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a720, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_a720, ERRATUM(2900952)
+
 workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
 /* Erratum 2926083 workaround is required only if SPE is enabled */
 #if ENABLE_SPE_FOR_NS != 0

diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index 682ca45..e940bde 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_a725.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
@@ -25,6 +26,15 @@
 
 .global check_erratum_cortex_a725_3699564
 
+workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a725, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a725, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_a725, ERRATUM(2900952)
+
 add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564
 
 check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)

diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index d1fc6d4..9cc6fdb 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S

@@ -33,10 +33,10 @@
 	ret
 endfunc cortex_a73_disable_smp
 
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
 
 workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
 	sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
@@ -200,10 +200,7 @@
 	ret
 endfunc cortex_a73_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
+declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \
 	cortex_a73_reset_func, \
-	check_erratum_cortex_a73_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a73_core_pwr_dwn, \
 	cortex_a73_cluster_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 13599ca..ef9c067 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S

@@ -20,6 +20,11 @@
 
 cpu_reset_prologue cortex_a75
 
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
 workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
 	sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
 workaround_reset_end cortex_a75, ERRATUM(764081)
@@ -131,11 +136,6 @@
 #endif
 cpu_reset_func_end cortex_a75
 
-func check_smccc_arch_workaround_3
-	mov	x0, #ERRATA_APPLIES
-	ret
-endfunc check_smccc_arch_workaround_3
-
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
@@ -170,9 +170,6 @@
 	ret
 endfunc cortex_a75_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
+declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \
 	cortex_a75_reset_func, \
-	check_erratum_cortex_a75_5715, \
-	CPU_NO_EXTRA2_FUNC, \
-	check_smccc_arch_workaround_3, \
 	cortex_a75_core_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 822ef05..ca5ccf7 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S

@@ -301,6 +301,29 @@
 endfunc apply_cve_2018_3639_sync_wa
 #endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
 
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_2*/
+add_erratum_entry cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
+check_erratum_chosen cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
+	errata_dsu_798953_wa_impl
+workaround_reset_end cortex_a76, ERRATUM(798953)
+
+check_erratum_custom_start cortex_a76, ERRATUM(798953)
+	check_errata_dsu_798953_impl
+	ret
+check_erratum_custom_end cortex_a76, ERRATUM(798953)
+
+workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184
+	errata_dsu_936184_wa_impl
+workaround_reset_end cortex_a76, ERRATUM(936184)
+
+check_erratum_custom_start cortex_a76, ERRATUM(936184)
+	check_errata_dsu_936184_impl
+	ret
+check_erratum_custom_end cortex_a76, ERRATUM(936184)
+
 workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348
 	sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
 workaround_reset_end cortex_a76, ERRATUM(1073348)
@@ -314,6 +337,24 @@
 
 check_erratum_ls cortex_a76, ERRATUM(1130799), CPU_REV(2, 0)
 
+/* --------------------------------------------------------------
+ * Errata Workaround for Cortex A76 Errata #1165522.
+ * This applies only to revisions <= r3p0 of Cortex A76.
+ * Due to the nature of the errata it is applied unconditionally
+ * when built in, report it as applicable in this case
+ * --------------------------------------------------------------
+ */
+check_erratum_custom_start cortex_a76, ERRATUM(1165522)
+#if ERRATA_A76_1165522
+	mov	x0, #ERRATA_APPLIES
+#else
+	cpu_rev_var_ls	CPU_REV(3, 0)
+#endif
+	ret
+check_erratum_custom_end cortex_a76, ERRATUM(1165522)
+
+add_erratum_entry cortex_a76, ERRATUM(1165522), ERRATA_A76_1165522
+
 workaround_reset_start cortex_a76, ERRATUM(1220197), ERRATA_A76_1220197
 	sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
 workaround_reset_end cortex_a76, ERRATUM(1220197)
@@ -353,6 +394,8 @@
 	ret
 check_erratum_custom_end cortex_a76, ERRATUM(1286807)
 
+add_erratum_entry cortex_a76, ERRATUM(1286807), ERRATA_A76_1286807
+
 workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580
 	sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
 workaround_reset_end cortex_a76, ERRATUM(1791580)
@@ -411,45 +454,11 @@
 	ret
 endfunc cortex_a76_disable_wa_cve_2018_3639
 
-/* --------------------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1165522.
- * This applies only to revisions <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * --------------------------------------------------------------
- */
-check_erratum_custom_start cortex_a76, ERRATUM(1165522)
-#if ERRATA_A76_1165522
-	mov	x0, #ERRATA_APPLIES
-#else
-	cpu_rev_var_ls	CPU_REV(3, 0)
-#endif
-	ret
-check_erratum_custom_end cortex_a76, ERRATUM(1165522)
-
 check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
 /* erratum has no workaround in the cpu. Generic code must take care */
 add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
-workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
-	errata_dsu_798953_wa_impl
-workaround_reset_end cortex_a76, ERRATUM(798953)
-
-check_erratum_custom_start cortex_a76, ERRATUM(798953)
-	check_errata_dsu_798953_impl
-	ret
-check_erratum_custom_end cortex_a76, ERRATUM(798953)
-
-workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184
-	errata_dsu_936184_wa_impl
-workaround_reset_end cortex_a76, ERRATUM(936184)
-
-check_erratum_custom_start cortex_a76, ERRATUM(936184)
-	check_errata_dsu_936184_impl
-	ret
-check_erratum_custom_end cortex_a76, ERRATUM(936184)
-
 cpu_reset_func_start cortex_a76
 
 #if WORKAROUND_CVE_2018_3639
@@ -531,9 +540,6 @@
 	ret
 endfunc cortex_a76_cpu_reg_dump
 
-declare_cpu_ops_wa cortex_a76, CORTEX_A76_MIDR, \
+declare_cpu_ops cortex_a76, CORTEX_A76_MIDR, \
 	cortex_a76_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	cortex_a76_disable_wa_cve_2018_3639, \
-	CPU_NO_EXTRA3_FUNC, \
 	cortex_a76_core_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 7fb964d..82a20ec 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S

@@ -28,13 +28,6 @@
 	wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
 #endif /* WORKAROUND_CVE_2022_23960 */
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_a77, CVE(2024, 5660)
-
-check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1)
-
 workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
 	/* move cpu revision in again and compare against r0p0 */
 	mov	x0, x7
@@ -150,6 +143,13 @@
 
 check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_a77, CVE(2024, 5660)
+
+check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1)
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
 	 * -------------------------------------------------

diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index a66214b..b166823 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S

@@ -26,13 +26,6 @@
 
 cpu_reset_prologue cortex_a78
 
-/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_a78, CVE(2024, 5660)
-
-check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2)
-
 workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
 	sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
 workaround_reset_end cortex_a78, ERRATUM(1688305)
@@ -106,16 +99,6 @@
 
 check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
 
-workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
-	/* Apply the workaround. */
-	mrs	x1, CORTEX_A78_CPUECTLR_EL1
-	mov	x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
-	bfi	x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
-	msr	CORTEX_A78_CPUECTLR_EL1, x1
-workaround_reset_end cortex_a78, ERRATUM(2132060)
-
-check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
-
 workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
 	ldr	x0, =0x5
 	msr	S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
@@ -176,6 +159,13 @@
 
 check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_a78, CVE(2024, 5660)
+
+check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2)
+
 cpu_reset_func_start cortex_a78
 #if ENABLE_FEAT_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */

diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
index c537967..63bc936 100644
--- a/lib/cpus/aarch64/cortex_a78_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S

@@ -24,13 +24,6 @@
 
 cpu_reset_prologue cortex_a78_ae
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_a78_ae, CVE(2024, 5660)
-
-check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3)
-
 workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
 	sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
 workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
@@ -105,6 +98,13 @@
 
 check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_a78_ae, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_a78_ae, CVE(2024, 5660)
+
+check_erratum_ls cortex_a78_ae, CVE(2024, 5660), CPU_REV(0, 3)
+
 cpu_reset_func_start cortex_a78_ae
 #if ENABLE_FEAT_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */

diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index aba7d25..19d988e 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S

@@ -23,13 +23,6 @@
 
 cpu_reset_prologue cortex_a78c
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_a78c, CVE(2024, 5660)
-
-check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2)
-
 workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
 	/* Disable allocation of splintered pages in the L2 TLB */
 	sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
@@ -44,18 +37,6 @@
 
 check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
 
-workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
-	/* --------------------------------------------------------
-	 * Place the data prefetcher in the most conservative mode
-	 * to reduce prefetches by writing the following bits to
-	 * the value indicated: ecltr[7:6], PF_MODE = 2'b11
-	 * --------------------------------------------------------
-	 */
-	sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
-workaround_reset_end cortex_a78c, ERRATUM(2132064)
-
-check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
-
 workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
 	ldr	x0, =0x5
 	msr	CORTEX_A78C_IMP_CPUPSELR_EL3, x0
@@ -127,6 +108,13 @@
 #endif /* IMAGE_BL31 */
 workaround_reset_end cortex_a78c, CVE(2022, 23960)
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_a78c, CVE(2024, 5660)
+
+check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2)
+
 cpu_reset_func_start cortex_a78c
 cpu_reset_func_end cortex_a78c
 

diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S
index 27d181a..cb759cc 100644
--- a/lib/cpus/aarch64/cortex_x1.S
+++ b/lib/cpus/aarch64/cortex_x1.S

@@ -25,13 +25,6 @@
 
 cpu_reset_prologue cortex_x1
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_x1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_x1, CVE(2024, 5660)
-
-check_erratum_ls cortex_x1, CVE(2024, 5660), CPU_REV(1, 2)
-
 workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305
 	sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1)
 workaround_reset_end cortex_x1, ERRATUM(1688305)
@@ -62,6 +55,13 @@
 #endif /* IMAGE_BL31 */
 workaround_reset_end cortex_x1, CVE(2022, 23960)
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_x1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_x1, CVE(2024, 5660)
+
+check_erratum_ls cortex_x1, CVE(2024, 5660), CPU_REV(1, 2)
+
 cpu_reset_func_start cortex_x1
 cpu_reset_func_end cortex_x1
 

diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index b11c37d..910a6a9 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S

@@ -25,23 +25,12 @@
 
 .global check_erratum_cortex_x2_3701772
 
-add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
-
-check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
-
 #if WORKAROUND_CVE_2022_23960
 	wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
 #endif /* WORKAROUND_CVE_2022_23960 */
 
 cpu_reset_prologue cortex_x2
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_x2, CVE(2024, 5660)
-
-check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
-
 workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
 	ldr	x0, =0x6
 	msr	S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
@@ -61,13 +50,6 @@
 
 check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
 
-workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
-	sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
-	CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end cortex_x2, ERRATUM(2058056)
-
-check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1)
-
 workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
 	/* Apply instruction patching sequence */
 	ldr	x0, =0x3
@@ -127,6 +109,15 @@
 
 check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
 
+workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
+	errata_dsu_2313941_wa_impl
+workaround_reset_end cortex_x2, ERRATUM(2313941)
+
+check_erratum_custom_start cortex_x2, ERRATUM(2313941)
+	check_errata_dsu_2313941_impl
+	ret
+check_erratum_custom_end cortex_x2, ERRATUM(2313941)
+
 workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
 	/* Set bit 40 in CPUACTLR2_EL1 */
 	sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
@@ -155,6 +146,10 @@
 
 check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1)
 
+add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
+
+check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
+
 workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -167,14 +162,12 @@
 
 check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
-workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
-	errata_dsu_2313941_wa_impl
-workaround_reset_end cortex_x2, ERRATUM(2313941)
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_x2, CVE(2024, 5660)
 
-check_erratum_custom_start cortex_x2, ERRATUM(2313941)
-	check_errata_dsu_2313941_impl
-	ret
-check_erratum_custom_end cortex_x2, ERRATUM(2313941)
+check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
 
 	/* ----------------------------------------------------
 	 * HW will do the cache maintenance while powering down

diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 3d52dae..158ee0e 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S

@@ -24,30 +24,12 @@
 
 .global check_erratum_cortex_x3_3701769
 
-add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769
-
-check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
-
 #if WORKAROUND_CVE_2022_23960
 	wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
 #endif /* WORKAROUND_CVE_2022_23960 */
 
 cpu_reset_prologue cortex_x3
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_x3, CVE(2024, 5660)
-
-check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2)
-
-workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301
-	sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \
-	CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end cortex_x3, ERRATUM(2070301)
-
-check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
-
 workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
         sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
 workaround_reset_end cortex_x3, ERRATUM(2266875)
@@ -114,6 +96,10 @@
 
 check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
 
+add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769
+
+check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
+
 workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	override_vector_table wa_cve_vbar_cortex_x3
@@ -122,6 +108,13 @@
 
 check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_x3, CVE(2024, 5660)
+
+check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2)
+
 workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
 	/* ---------------------------------
 	 * Sets BIT41 of CPUACTLR6_EL1 which
@@ -174,10 +167,6 @@
 	ret
 endfunc cortex_x3_cpu_reg_dump
 
-declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
+declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
 	cortex_x3_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_cortex_x3_7881, \
 	cortex_x3_core_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index c067981..b1dc52c 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_x4.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 #include "wa_cve_2022_23960_bhb_vector.S"
 
@@ -35,13 +36,6 @@
 
 check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1)
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
-workaround_reset_end cortex_x4, CVE(2024, 5660)
-
-check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
-
 workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
 	/* dsb before isb of power down sequence */
 	dsb	sy
@@ -71,6 +65,15 @@
 
 check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
 
+workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x4, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x4, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_x4, ERRATUM(2900952)
+
 workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
 	sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
 workaround_reset_end cortex_x4, ERRATUM(2923985)
@@ -100,6 +103,10 @@
 
 check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
 
+add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
+
+check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
+
 workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -112,6 +119,13 @@
 
 check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
+workaround_reset_end cortex_x4, CVE(2024, 5660)
+
+check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
+
 workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
 	/* ---------------------------------
 	 * Sets BIT41 of CPUACTLR6_EL1 which
@@ -123,10 +137,6 @@
 
 check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
 
-add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
-
-check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
-
 cpu_reset_func_start cortex_x4
 	/* Disable speculative loads */
 	msr	SSBS, xzr
@@ -169,10 +179,6 @@
 	ret
 endfunc cortex_x4_cpu_reg_dump
 
-declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
+declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
 	cortex_x4_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_cortex_x4_7881, \
 	cortex_x4_core_pwr_dwn

diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 093d91d..003dc97 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_x925.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
@@ -23,6 +24,15 @@
 
 cpu_reset_prologue cortex_x925
 
+workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x925, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x925, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_x925, ERRATUM(2900952)
+
 add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
 
 check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
@@ -99,10 +109,6 @@
 	ret
 endfunc cortex_x925_cpu_reg_dump
 
-declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
+declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \
 	cortex_x925_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_cortex_x925_7881, \
 	cortex_x925_core_pwr_dwn

diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index e608422..105da5c 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S

@@ -188,143 +188,3 @@
 	get_rev_var x0, x1
 	ret
 endfunc cpu_get_rev_var
-
-/*
- * int check_wa_cve_2017_5715(void);
- *
- * This function returns:
- *  - ERRATA_APPLIES when firmware mitigation is required.
- *  - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- *  - ERRATA_MISSING when firmware mitigation would be required but
- *    is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-	.globl	check_wa_cve_2017_5715
-func check_wa_cve_2017_5715
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA1_FUNC]
-	/*
-	 * If the reserved function pointer is NULL, this CPU
-	 * is unaffected by CVE-2017-5715 so bail out.
-	 */
-	cmp	x0, #CPU_NO_EXTRA1_FUNC
-	beq	1f
-	br	x0
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_wa_cve_2017_5715
-
-/*
- * int check_wa_cve_2024_7881(void);
- *
- * This function returns:
- *  - ERRATA_APPLIES when firmware mitigation is required.
- *  - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- *  - ERRATA_MISSING when firmware mitigation would be required but
- *    is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-.globl	check_wa_cve_2024_7881
-func check_wa_cve_2024_7881
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA4_FUNC]
-	/*
-	 * If the reserved function pointer is NULL, this CPU
-	 * is unaffected by CVE-2024-7881 so bail out.
-	 */
-	cmp	x0, #CPU_NO_EXTRA4_FUNC
-	beq	1f
-	br	x0
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_wa_cve_2024_7881
-
-/*
- * void *wa_cve_2018_3639_get_disable_ptr(void);
- *
- * Returns a function pointer which is used to disable mitigation
- * for CVE-2018-3639.
- * The function pointer is only returned on cores that employ
- * dynamic mitigation.  If the core uses static mitigation or is
- * unaffected by CVE-2018-3639 this function returns NULL.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-	.globl	wa_cve_2018_3639_get_disable_ptr
-func wa_cve_2018_3639_get_disable_ptr
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA2_FUNC]
-	ret
-endfunc wa_cve_2018_3639_get_disable_ptr
-
-/*
- * int check_smccc_arch_wa3_applies(void);
- *
- * This function checks whether SMCCC_ARCH_WORKAROUND_3 is enabled to mitigate
- * CVE-2022-23960 for this CPU. It returns:
- *  - ERRATA_APPLIES when SMCCC_ARCH_WORKAROUND_3 can be invoked to mitigate
- *    the CVE.
- *  - ERRATA_NOT_APPLIES when SMCCC_ARCH_WORKAROUND_3 should not be invoked to
- *    mitigate the CVE.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- *       in per-CPU data.
- */
-	.globl	check_smccc_arch_wa3_applies
-func check_smccc_arch_wa3_applies
-	mrs	x0, tpidr_el3
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif
-	ldr	x0, [x0, #CPU_EXTRA3_FUNC]
-	/*
-	 * If the reserved function pointer is NULL, this CPU
-	 * is unaffected by CVE-2022-23960 so bail out.
-	 */
-	cmp	x0, #CPU_NO_EXTRA3_FUNC
-	beq	1f
-	br	x0
-1:
-	mov	x0, #ERRATA_NOT_APPLIES
-	ret
-endfunc check_smccc_arch_wa3_applies

diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 64158e7..22cd3ba 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S

@@ -319,11 +319,8 @@
 
 /* macro to declare cpu_ops for Denver SKUs */
 .macro	denver_cpu_ops_wa midr
-	declare_cpu_ops_wa denver, \midr, \
+	declare_cpu_ops denver, \midr, \
 		denver_reset_func, \
-		check_erratum_denver_5715, \
-		CPU_NO_EXTRA2_FUNC, \
-		CPU_NO_EXTRA3_FUNC, \
 		denver_core_pwr_dwn, \
 		denver_cluster_pwr_dwn
 .endm

diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 5868bf2..e821ecb 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S

@@ -268,13 +268,6 @@
 	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
 	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
 
-	/*
-	 * Issue Error Synchronization Barrier to synchronize SErrors before
-	 * exiting EL3. We're running with EAs unmasked, so any synchronized
-	 * errors would be taken immediately; therefore no need to inspect
-	 * DISR_EL1 register.
-	 */
-	esb
 	exception_return
 1:
 	ret

diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 9c6f01a..7d9d7f1 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S

@@ -23,34 +23,12 @@
 
 .global check_erratum_neoverse_n2_3701773
 
-add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
-
-check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
-
 #if WORKAROUND_CVE_2022_23960
 	wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
 #endif /* WORKAROUND_CVE_2022_23960 */
 
 cpu_reset_prologue neoverse_n2
 
-workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
-	errata_dsu_2313941_wa_impl
-workaround_reset_end neoverse_n2, ERRATUM(2313941)
-
-check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
-	branch_if_scu_not_present 2f /* label 1 is used in the macro */
-	check_errata_dsu_2313941_impl
-	2:
-	ret
-check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
-
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
-workaround_reset_end neoverse_n2, CVE(2024, 5660)
-
-check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
-
 workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
 	/* Apply instruction patching sequence */
 	ldr x0,=0x6
@@ -73,18 +51,6 @@
 
 check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
 
-workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
-	sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
-workaround_reset_end neoverse_n2, ERRATUM(2025414)
-
-check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
-
-workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
-	sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
-workaround_reset_end neoverse_n2, ERRATUM(2067956)
-
-check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
-
 workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
 	/* Stash ERRSELR_EL1 in x2 */
 	mrs     x2, ERRSELR_EL1
@@ -101,15 +67,17 @@
 
 check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
 
-workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
-	/* Apply instruction patching sequence */
-	mrs	x1, NEOVERSE_N2_CPUECTLR2_EL1
-	mov	x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
-	bfi	x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
-	msr	NEOVERSE_N2_CPUECTLR2_EL1, x1
-workaround_reset_end neoverse_n2, ERRATUM(2138953)
+workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
+	sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end neoverse_n2, ERRATUM(2025414)
 
-check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3)
+check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
+
+workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
+	sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
+workaround_reset_end neoverse_n2, ERRATUM(2067956)
+
+check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
 
 workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
 	/* Apply instruction patching sequence */
@@ -175,6 +143,17 @@
 
 check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
 
+workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
+	errata_dsu_2313941_wa_impl
+workaround_reset_end neoverse_n2, ERRATUM(2313941)
+
+check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
+	branch_if_scu_not_present 2f /* label 1 is used in the macro */
+	check_errata_dsu_2313941_impl
+	2:
+	ret
+check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
+
 .global erratum_neoverse_n2_2326639_wa
 workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
 	/* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying
@@ -240,6 +219,10 @@
 
 check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
 
+add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
+
+check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
+
 workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -252,6 +235,13 @@
 
 check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
+workaround_reset_end neoverse_n2, CVE(2024, 5660)
+
+check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
+
 	/* -------------------------------------------
 	 * The CPU Ops reset function for Neoverse N2.
 	 * -------------------------------------------

diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index e1e8214..f975be0 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S

@@ -28,13 +28,6 @@
 	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
 #endif /* WORKAROUND_CVE_2022_23960 */
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46)
-workaround_reset_end neoverse_v1, CVE(2024, 5660)
-
-check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2)
-
 workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
 	/* Inserts a DMB SY before and after MRS PAR_EL1 */
 	ldr	x0, =0x0
@@ -163,15 +156,6 @@
 
 check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
 
-workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
-	mrs	x1, NEOVERSE_V1_CPUECTLR_EL1
-	mov	x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
-	bfi	x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
-	msr	NEOVERSE_V1_CPUECTLR_EL1, x1
-workaround_reset_end neoverse_v1, ERRATUM(2108267)
-
-check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2)
-
 workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
 	mov	x0, #0x3
 	msr	S3_6_C15_C8_0, x0
@@ -252,6 +236,13 @@
 
 check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46)
+workaround_reset_end neoverse_v1, CVE(2024, 5660)
+
+check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2)
+
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------

diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 06521ec..9526b80 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S

@@ -24,20 +24,6 @@
 
 cpu_reset_prologue neoverse_v2
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
-workaround_reset_end neoverse_v2, CVE(2024, 5660)
-
-check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
-
-workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
-	sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
-		NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end neoverse_v2, ERRATUM(2331132)
-
-check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
-
 workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597
         /* Disable retention control for WFI and WFE. */
         mrs     x0, NEOVERSE_V2_CPUPWRCTLR_EL1
@@ -95,6 +81,13 @@
 
 check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
+workaround_reset_end neoverse_v2, CVE(2024, 5660)
+
+check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
+
 #if WORKAROUND_CVE_2022_23960
 	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
 #endif /* WORKAROUND_CVE_2022_23960 */
@@ -155,10 +148,6 @@
 	ret
 endfunc neoverse_v2_cpu_reg_dump
 
-declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \
+declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
 	neoverse_v2_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_neoverse_v2_7881, \
 	neoverse_v2_core_pwr_dwn

diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
index 29bfd0e..ca108e7 100644
--- a/lib/cpus/aarch64/neoverse_v3.S
+++ b/lib/cpus/aarch64/neoverse_v3.S

@@ -26,10 +26,6 @@
 
 .global check_erratum_neoverse_v3_3701767
 
-add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767
-
-check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)
-
 workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647
 	/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
 	ldr x0, =0x1
@@ -45,17 +41,14 @@
 
 check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0)
 
+add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767
+
+check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)
+
 #if WORKAROUND_CVE_2022_23960
 	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
 #endif /* WORKAROUND_CVE_2022_23960 */
 
-/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
-workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
-	sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46)
-workaround_reset_end neoverse_v3, CVE(2024, 5660)
-
-check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1)
-
 workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	/*
@@ -69,6 +62,13 @@
 
 check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 
+/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
+workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
+	sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46)
+workaround_reset_end neoverse_v3, CVE(2024, 5660)
+
+check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1)
+
 workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
        /* ---------------------------------
         * Sets BIT41 of CPUACTLR6_EL1 which
@@ -124,10 +124,6 @@
 	neoverse_v3_reset_func, \
 	neoverse_v3_core_pwr_dwn
 
-declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
 	neoverse_v3_reset_func, \
-	CPU_NO_EXTRA1_FUNC, \
-	CPU_NO_EXTRA2_FUNC, \
-	CPU_NO_EXTRA3_FUNC, \
-	check_erratum_neoverse_v3_7881, \
 	neoverse_v3_core_pwr_dwn

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4cfa765..a0cb872 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk

@@ -315,10 +315,6 @@
 # to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
 CPU_FLAG_LIST += ERRATA_A78_1952683
 
-# Flag to apply erratum 2132060 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
-CPU_FLAG_LIST += ERRATA_A78_2132060
-
 # Flag to apply erratum 2242635 workaround during reset. This erratum applies
 # to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is
 # present in r0p0 as well but there is no workaround for that revision.
@@ -380,10 +376,6 @@
 # It is still open.
 CPU_FLAG_LIST += ERRATA_A78_AE_2712574
 
-# Flag to apply erratum 2132064 workaround during reset. This erratum applies
-# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
-CPU_FLAG_LIST += ERRATA_A78C_2132064
-
 # Flag to apply erratum 2242638 workaround during reset. This erratum applies
 # to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
 CPU_FLAG_LIST += ERRATA_A78C_2242638
@@ -523,10 +515,6 @@
 # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_V1_2139242
 
-# Flag to apply erratum 2108267 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
-CPU_FLAG_LIST += ERRATA_V1_2108267
-
 # Flag to apply erratum 2216392 workaround during reset. This erratum applies
 # to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This
 # issue exists in r0p0 as well but there is no workaround for that revision.
@@ -573,6 +561,18 @@
 # the Neoverse V3 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_V3_3701767
 
+# Flag to apply erratum 1901946 workaround during reset. This erratum applies
+# to revision r1p0 and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1901946
+
+# Flag to apply erratum 1916945 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1916945
+
+# Flag to apply erratum 1917258 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1917258
+
 # Flag to apply erratum 1987031 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_A710_1987031
@@ -585,11 +585,6 @@
 # to revision r2p0 of the Cortex-A710 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_A710_2083908
 
-# Flag to apply erratum 2058056 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still
-# open.
-CPU_FLAG_LIST += ERRATA_A710_2058056
-
 # Flag to apply erratum 2055002 workaround during reset. This erratum applies
 # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_A710_2055002
@@ -680,10 +675,6 @@
 # to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_N2_2138956
 
-# Flag to apply erratum 2138953 workaround during reset. This erratum applies
-# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
-CPU_FLAG_LIST += ERRATA_N2_2138953
-
 # Flag to apply erratum 2242415 workaround during reset. This erratum applies
 # to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_N2_2242415
@@ -751,10 +742,6 @@
 # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_X2_2002765
 
-# Flag to apply erratum 2058056 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open.
-CPU_FLAG_LIST += ERRATA_X2_2058056
-
 # Flag to apply erratum 2083908 workaround during reset. This erratum applies
 # to revision r2p0 of the Cortex-X2 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_X2_2083908
@@ -810,11 +797,6 @@
 # of the Cortex-X2 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_X2_3701772
 
-# Flag to apply erratum 2070301 workaround on reset. This erratum applies
-# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is
-# still open.
-CPU_FLAG_LIST += ERRATA_X3_2070301
-
 # Flag to apply erratum 2266875 workaround during reset. This erratum applies
 # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
 CPU_FLAG_LIST += ERRATA_X3_2266875
@@ -983,10 +965,6 @@
 # applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is fixed in r0p2.
 CPU_FLAG_LIST += ERRATA_A520_2938996
 
-# Flag to apply erratum 2331132 workaround during reset. This erratum applies
-# to revisions r0p0, r0p1 and r0p2. It is still open.
-CPU_FLAG_LIST += ERRATA_V2_2331132
-
 # Flag to apply erratum 2618597 workaround during reset. This erratum applies
 # to revisions r0p0 and r0p1. It is fixed in r0p2.
 CPU_FLAG_LIST += ERRATA_V2_2618597
@@ -1097,6 +1075,13 @@
 # results in higher DSU power consumption on idle.
 CPU_FLAG_LIST += ERRATA_DSU_2313941
 
+# Flag to apply DSU erratum 2900952 during reset. This erratum applies
+# to some implementations of DSU-120 revision r2p0. Erratum might be fixed
+# in some implementations of r2p0. This can be determined by reading
+# the IMP_CLUSTERREVIDR_EL1 register where a set bit indicates that
+# the erratum is fixed in this part. It is fixed in r2p1.
+CPU_FLAG_LIST += ERRATA_DSU_2900952
+
 ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
 	ifeq (${WORKAROUND_CVE_2018_3639},0)
 		$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")

diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 0530647..a1e6d60 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c

@@ -6,6 +6,8 @@
 
 /* Runtime C routines for errata workarounds and common routines */
 
+#include <assert.h>
+
 #include <arch.h>
 #include <arch_helpers.h>
 #include <cortex_a75.h>
@@ -26,6 +28,31 @@
 #include <neoverse_n3.h>
 #include <neoverse_v3.h>
 
+struct erratum_entry *find_erratum_entry(uint32_t errata_id)
+{
+	struct cpu_ops *cpu_ops;
+	struct erratum_entry *entry, *end;
+
+	cpu_ops = get_cpu_ops_ptr();
+	assert(cpu_ops != NULL);
+
+	entry = cpu_ops->errata_list_start;
+	assert(entry != NULL);
+
+	end = cpu_ops->errata_list_end;
+	assert(end != NULL);
+
+	end--; /* point to the last erratum entry of the queried cpu */
+
+	while ((entry <= end)) {
+		if (entry->id == errata_id) {
+			return entry;
+		}
+		entry += 1;
+	}
+	return NULL;
+}
+
 bool check_if_trbe_disable_affected_core(void)
 {
 	switch (EXTRACT_PARTNUM(read_midr())) {
@@ -151,3 +178,21 @@
 
 	return false;
 }
+
+int check_erratum_applies(uint32_t cve, int errata_id)
+{
+	struct erratum_entry *entry;
+	long rev_var;
+
+	rev_var = cpu_get_rev_var();
+
+	entry = find_erratum_entry(errata_id);
+
+	if (entry == NULL) {
+		return ERRATA_NOT_APPLIES;
+	}
+
+	assert(entry->cve == cve);
+
+	return entry->check_func(rev_var);
+}

diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index e0a9076..47e8699 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,7 +31,7 @@
 /* Errata format: BL stage, CPU, errata ID, message */
 #define ERRATA_FORMAT	"%s: %s: CPU workaround for %s was %s\n"
 
-#define CVE_FORMAT	"%s: %s: CPU workaround for CVE %u_%u was %s\n"
+#define CVE_FORMAT	"%s: %s: CPU workaround for CVE %u_%04u was %s\n"
 #define ERRATUM_FORMAT	"%s: %s: CPU workaround for erratum %u was %s\n"
 
 
@@ -63,9 +63,6 @@
 #else /* !REPORT_ERRATA */
 /*
  * New errata status message printer
- * The order checking function is hidden behind the FEATURE_DETECTION flag to
- * save space. This functionality is only useful on development and platform
- * bringup builds, when FEATURE_DETECTION should be used anyway
  */
 void generic_errata_report(void)
 {
@@ -73,12 +70,6 @@
 	struct erratum_entry *entry = cpu_ops->errata_list_start;
 	struct erratum_entry *end = cpu_ops->errata_list_end;
 	long rev_var = cpu_get_rev_var();
-#if FEATURE_DETECTION
-	uint32_t last_erratum_id = 0;
-	uint16_t last_cve_yr = 0;
-	bool check_cve = false;
-	bool failed = false;
-#endif /* FEATURE_DETECTION */
 
 	for (; entry != end; entry += 1) {
 		uint64_t status = entry->check_func(rev_var);
@@ -95,35 +86,7 @@
 		}
 
 		print_status(status, cpu_ops->cpu_str, entry->cve, entry->id);
-
-#if FEATURE_DETECTION
-		if (entry->cve) {
-			if (last_cve_yr > entry->cve ||
-			   (last_cve_yr == entry->cve && last_erratum_id >= entry->id)) {
-				ERROR("CVE %u_%u was out of order!\n",
-				      entry->cve, entry->id);
-				failed = true;
-			}
-			check_cve = true;
-			last_cve_yr = entry->cve;
-		} else {
-			if (last_erratum_id >= entry->id || check_cve) {
-				ERROR("Erratum %u was out of order!\n",
-				      entry->id);
-				failed = true;
-			}
-		}
-		last_erratum_id = entry->id;
-#endif /* FEATURE_DETECTION */
 	}
-
-#if FEATURE_DETECTION
-	/*
-	 * enforce errata and CVEs are in ascending order and that CVEs are
-	 * after errata
-	 */
-	assert(!failed);
-#endif /* FEATURE_DETECTION */
 }
 
 /*

diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 132888c..00d9c01 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -155,21 +155,6 @@
 #endif /*  IMAGE_BL32 */
 }
 
-#if !IMAGE_BL1
-/*******************************************************************************
- * The following function initializes the cpu_context for a CPU specified by
- * its `cpu_idx` for first use, and sets the initial entrypoint state as
- * specified by the entry_point_info structure.
- ******************************************************************************/
-void cm_init_context_by_index(unsigned int cpu_idx,
-			      const entry_point_info_t *ep)
-{
-	cpu_context_t *ctx;
-	ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
-	cm_setup_context(ctx, ep);
-}
-#endif /* !IMAGE_BL1 */
-
 /*******************************************************************************
  * The following function initializes the cpu_context for the current CPU
  * for first use, and sets the initial entrypoint state as specified by the

diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S
deleted file mode 100644
index e59b7fd..0000000
--- a/lib/el3_runtime/aarch32/cpu_data.S
+++ /dev/null

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
-	.globl	_cpu_data
-	.globl	_cpu_data_by_index
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data(void)
- *
- * Return the cpu_data structure for the current CPU.
- * -----------------------------------------------------------------
- */
-func _cpu_data
-	/* r12 is pushed to meet the 8 byte stack alignment requirement */
-	push	{r12, lr}
-	bl	plat_my_core_pos
-	pop	{r12, lr}
-	b	_cpu_data_by_index
-endfunc _cpu_data
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
- *
- * Return the cpu_data structure for the CPU with given linear index
- *
- * This can be called without a valid stack.
- * clobbers: r0, r1
- * -----------------------------------------------------------------
- */
-func _cpu_data_by_index
-	mov_imm	r1, CPU_DATA_SIZE
-	mul	r0, r0, r1
-	ldr	r1, =percpu_data
-	add	r0, r0, r1
-	bx	lr
-endfunc _cpu_data_by_index

diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 1e6a42e..7929901 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S

@@ -75,6 +75,9 @@
  */
 #if CTX_INCLUDE_FPREGS
 func fpregs_context_save
+.arch_extension fp
+	/* Temporarily enable floating point */
+
 	/* Save x0 and pass its original value to fpregs_state_save */
 	mov	x1, x0
 
@@ -97,6 +100,7 @@
 
 	fpregs_state_save x1, x9
 
+.arch_extension nofp
 	ret
 endfunc fpregs_context_save
 
@@ -115,6 +119,9 @@
  * ------------------------------------------------------------------
  */
 func fpregs_context_restore
+.arch_extension fp
+	/* Temporarily enable floating point */
+
 	/* Save x0 and pass its original value to fpregs_state_restore */
 	mov	x1, x0
 
@@ -137,6 +144,7 @@
 
 	fpregs_state_restore x1, x9
 
+.arch_extension nofp
 	ret
 endfunc fpregs_context_restore
 #endif /* CTX_INCLUDE_FPREGS */
@@ -335,11 +343,11 @@
 	.endm /* restore_mpam3_el3 */
 
 /* ------------------------------------------------------------------
- * The following macro is used to save and restore all the general
- * purpose and ARMv8.3-PAuth (if enabled) registers.
- * It also checks if the Secure Cycle Counter (PMCCNTR_EL0)
- * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0
- * needs not to be saved/restored during world switch.
+ * The following macro is used to save all the general purpose
+ * registers and swap the FEAT_PAUTH keys with BL31's keys in
+ * cpu_data. It also checks if the Secure Cycle Counter (PMCCNTR_EL0)
+ * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 needs
+ * not to be saved/restored during world switch.
  *
  * Ideally we would only save and restore the callee saved registers
  * when a world switch occurs but that type of implementation is more
@@ -371,6 +379,11 @@
 	mrs	x9, pmcr_el0
 	str	x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
 #if CTX_INCLUDE_PAUTH_REGS
+#if CTX_INCLUDE_PAUTH_REGS == 2
+	/* Skip if not present in hardware */
+	is_feat_pauth_present_asm x9, x10
+	beq	no_pauth_\@
+#endif
 	/* ----------------------------------------------------------
  	 * Save the ARMv8.3-PAuth keys as they are not banked
  	 * by exception level
@@ -394,6 +407,25 @@
 	stp	x24, x25, [x19, #CTX_PACDAKEY_LO]
 	stp	x26, x27, [x19, #CTX_PACDBKEY_LO]
 	stp	x28, x29, [x19, #CTX_PACGAKEY_LO]
+#if ENABLE_PAUTH
+#if IMAGE_BL31
+	/* tpidr_el3 contains the address of the cpu_data structure */
+	mrs	x9, tpidr_el3
+	/* Load APIAKey from cpu_data */
+	ldp	x10, x11, [x9, #CPU_DATA_APIAKEY_OFFSET]
+#endif /* IMAGE_BL31 */
+
+#if IMAGE_BL1
+	/* BL1 does not use cpu_data and has dedicated storage */
+	adr_l	x9, bl1_apiakey
+	ldp	x10, x11, [x9]
+#endif /* IMAGE_BL1 */
+
+	/* Program instruction key A */
+	msr	APIAKeyLo_EL1, x10
+	msr	APIAKeyHi_EL1, x11
+no_pauth_\@:
+#endif /* ENABLE_PAUTH */
 #endif /* CTX_INCLUDE_PAUTH_REGS */
 	.endm /* save_gp_pmcr_pauth_regs */
 
@@ -434,6 +466,11 @@
  */
 func restore_gp_pmcr_pauth_regs
 #if CTX_INCLUDE_PAUTH_REGS
+#if CTX_INCLUDE_PAUTH_REGS == 2
+	/* Skip if not present in hardware */
+	is_feat_pauth_present_asm x0, x1
+	beq	no_pauth
+#endif
  	/* Restore the ARMv8.3 PAuth keys */
 	add	x10, sp, #CTX_PAUTH_REGS_OFFSET
 
@@ -453,6 +490,7 @@
 	msr	APDBKeyHi_EL1, x7
 	msr	APGAKeyLo_EL1, x8
 	msr	APGAKeyHi_EL1, x9
+no_pauth:
 #endif /* CTX_INCLUDE_PAUTH_REGS */
 
 	/* PMUv3 is presumed to be always present */

diff --git a/lib/el3_runtime/aarch64/context_debug.c b/lib/el3_runtime/aarch64/context_debug.c
index b37bcb7..1addb45 100644
--- a/lib/el3_runtime/aarch64/context_debug.c
+++ b/lib/el3_runtime/aarch64/context_debug.c

@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <string.h>
 
+#include <arch_features.h>
 #include <common/debug.h>
 #include <context.h>
 #include <lib/el3_runtime/context_mgmt.h>
@@ -65,11 +66,11 @@
 #else
 	size_t el1_total = 0U;
 #endif /* CTX_INCLUDE_EL2_REGS */
-
-#if CTX_INCLUDE_PAUTH_REGS
 	size_t pauth_total = 0U;
-	PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
-#endif
+
+	if (is_ctx_pauth_supported()) {
+		PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
+	}
 
 	PRINT_MEM_USAGE_SEPARATOR();
 
@@ -80,9 +81,9 @@
 	printf("|    EL1    ");
 #endif /* CTX_INCLUDE_EL2_REGS */
 
-#if CTX_INCLUDE_PAUTH_REGS
-	printf("|   PAUTH   ");
-#endif
+	if (is_ctx_pauth_supported()) {
+		printf("|   PAUTH   ");
+	}
 
 	printf("|   Other   |   Total   |\n");
 
@@ -97,10 +98,9 @@
 		size_t el1_size = 0U;
 #endif /* CTX_INCLUDE_EL2_REGS */
 
-#if CTX_INCLUDE_PAUTH_REGS
-		size_t pauth_size = 0U;
-		PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
-#endif
+		if (is_ctx_pauth_supported()) {
+			PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
+		}
 
 		PRINT_MEM_USAGE_SEPARATOR();
 
@@ -125,10 +125,12 @@
 #endif /* CTX_INCLUDE_EL2_REGS */
 
 #if CTX_INCLUDE_PAUTH_REGS
-		pauth_size = sizeof(ctx->pauth_ctx);
-		size_other -= pauth_size;
-		pauth_total += pauth_size;
-		printf("| %8luB ", pauth_size);
+		if (is_ctx_pauth_supported()) {
+			size_t pauth_size = sizeof(ctx->pauth_ctx);
+			size_other -= pauth_size;
+			pauth_total += pauth_size;
+			printf("| %8luB ", pauth_size);
+		}
 #endif
 		printf("| %8luB | %8luB |\n", size_other, core_total);
 
@@ -138,15 +140,15 @@
 		total += core_total;
 	}
 
-#if CTX_INCLUDE_PAUTH_REGS
-	PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
-#endif
+	if (is_ctx_pauth_supported()) {
+		PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
+	}
 
 	PRINT_MEM_USAGE_SEPARATOR();
 
-#if CTX_INCLUDE_PAUTH_REGS
-	PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
-#endif
+	if (is_ctx_pauth_supported()) {
+		PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
+	}
 
 	PRINT_MEM_USAGE_SEPARATOR();
 
@@ -158,15 +160,15 @@
 	printf("| %8luB ", el1_total);
 #endif /* CTX_INCLUDE_EL2_REGS */
 
-#if CTX_INCLUDE_PAUTH_REGS
-	printf("| %8luB ", pauth_total);
-#endif
+	if (is_ctx_pauth_supported()) {
+		printf("| %8luB ", pauth_total);
+	}
 
 	printf("| %8luB | %8luB |\n", other_total, total);
 
-#if CTX_INCLUDE_PAUTH_REGS
-	PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
-#endif
+	if (is_ctx_pauth_supported()) {
+		PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
+	}
 	PRINT_MEM_USAGE_SEPARATOR();
 	printf("\n");
 

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index f4fec42..7795fcf 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c

@@ -30,6 +30,7 @@
 #include <lib/extensions/fgt2.h>
 #include <lib/extensions/fpmr.h>
 #include <lib/extensions/mpam.h>
+#include <lib/extensions/pauth.h>
 #include <lib/extensions/pmuv3.h>
 #include <lib/extensions/sme.h>
 #include <lib/extensions/spe.h>
@@ -190,6 +191,15 @@
 		scr_el3 |= SCR_SCTLR2En_BIT;
 	}
 
+	if (is_feat_d128_supported()) {
+		/*
+		 * Set the D128En bit in SCR_EL3 to enable access to 128-bit
+		 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
+		 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
+		 */
+		scr_el3 |= SCR_D128En_BIT;
+	}
+
 	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
 
 	if (is_feat_fgt2_supported()) {
@@ -227,17 +237,15 @@
 		scr_el3 |= SCR_ATA_BIT;
 	}
 
-#if !CTX_INCLUDE_PAUTH_REGS
 	/*
-	 * Pointer Authentication feature, if present, is always enabled by default
-	 * for Non secure lower exception levels. We do not have an explicit
-	 * flag to set it.
+	 * Pointer Authentication feature, if present, is always enabled by
+	 * default for Non secure lower exception levels. We do not have an
+	 * explicit flag to set it. To prevent the leakage between the worlds
+	 * during world switch, we enable it only for the non-secure world.
+	 *
 	 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
 	 * exception levels of secure and realm worlds.
 	 *
-	 * To prevent the leakage between the worlds during world switch,
-	 * we enable it only for the non-secure world.
-	 *
 	 * If the Secure/realm world wants to use pointer authentication,
 	 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
 	 * it will be enabled globally for all the contexts.
@@ -248,10 +256,9 @@
 	 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
 	 *  than EL3
 	 */
-	if (is_armv8_3_pauth_present()) {
+	if (!is_ctx_pauth_supported()) {
 		scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
 	}
-#endif /* CTX_INCLUDE_PAUTH_REGS */
 
 #if HANDLE_EA_EL3_FIRST_NS
 	/* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
@@ -468,7 +475,6 @@
 	scr_el3 |= SCR_FIEN_BIT;
 #endif
 
-#if CTX_INCLUDE_PAUTH_REGS
 	/*
 	 * Enable Pointer Authentication globally for all the worlds.
 	 *
@@ -478,17 +484,9 @@
 	 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
 	 *  than EL3
 	 */
-	if (is_armv8_3_pauth_present()) {
+	if (is_ctx_pauth_supported()) {
 		scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
 	}
-#endif /* CTX_INCLUDE_PAUTH_REGS */
-
-	/*
-	 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present.
-	 */
-	if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) {
-		scr_el3 |= SCR_TCR2EN_BIT;
-	}
 
 	/*
 	 * SCR_EL3.PIEN: Enable permission indirection and overlay
@@ -591,6 +589,10 @@
 		trf_enable(ctx);
 	}
 
+	if (is_feat_tcr2_supported()) {
+		tcr2_enable(ctx);
+	}
+
 	pmuv3_enable(ctx);
 #endif /* IMAGE_BL31 */
 
@@ -839,8 +841,10 @@
 		spe_enable(ctx);
 	}
 
-	if (is_feat_trbe_supported()) {
-		trbe_enable(ctx);
+	if (!check_if_trbe_disable_affected_core()) {
+		if (is_feat_trbe_supported()) {
+			trbe_enable(ctx);
+		}
 	}
 
 	if (is_feat_brbe_supported()) {
@@ -849,20 +853,6 @@
 #endif /* IMAGE_BL31 */
 }
 
-/* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */
-static __unused void enable_pauth_el2(void)
-{
-	u_register_t hcr_el2 = read_hcr_el2();
-	/*
-	 * For Armv8.3 pointer authentication feature, disable traps to EL2 when
-	 *  accessing key registers or using pointer authentication instructions
-	 *  from lower ELs.
-	 */
-	hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
-
-	write_hcr_el2(hcr_el2);
-}
-
 #if INIT_UNUSED_NS_EL2
 /*******************************************************************************
  * Enable architecture extensions in-place at EL2 on first entry to Non-secure
@@ -909,9 +899,9 @@
 		write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT);
 	}
 
-#if ENABLE_PAUTH
-	enable_pauth_el2();
-#endif /* ENABLE_PAUTH */
+	if (is_feat_pauth_supported()) {
+		pauth_enable_el2();
+	}
 #endif /* IMAGE_BL31 */
 }
 #endif /* INIT_UNUSED_NS_EL2 */
@@ -955,21 +945,6 @@
 #endif /* IMAGE_BL31 */
 }
 
-#if !IMAGE_BL1
-/*******************************************************************************
- * The following function initializes the cpu_context for a CPU specified by
- * its `cpu_idx` for first use, and sets the initial entrypoint state as
- * specified by the entry_point_info structure.
- ******************************************************************************/
-void cm_init_context_by_index(unsigned int cpu_idx,
-			      const entry_point_info_t *ep)
-{
-	cpu_context_t *ctx;
-	ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
-	cm_setup_context(ctx, ep);
-}
-#endif /* !IMAGE_BL1 */
-
 /*******************************************************************************
  * The following function initializes the cpu_context for the current CPU
  * for first use, and sets the initial entrypoint state as specified by the
@@ -1647,52 +1622,6 @@
 }
 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
 
-#if IMAGE_BL31
-/*********************************************************************************
-* This function allows Architecture features asymmetry among cores.
-* TF-A assumes that all the cores in the platform has architecture feature parity
-* and hence the context is setup on different core (e.g. primary sets up the
-* context for secondary cores).This assumption may not be true for systems where
-* cores are not conforming to same Arch version or there is CPU Erratum which
-* requires certain feature to be be disabled only on a given core.
-*
-* This function is called on secondary cores to override any disparity in context
-* setup by primary, this would be called during warmboot path.
-*********************************************************************************/
-void cm_handle_asymmetric_features(void)
-{
-	cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE);
-
-	assert(ctx != NULL);
-
-#if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC
-	if (is_feat_spe_supported()) {
-		spe_enable(ctx);
-	} else {
-		spe_disable(ctx);
-	}
-#endif
-
-	if (check_if_trbe_disable_affected_core()) {
-		if (is_feat_trbe_supported()) {
-			trbe_disable(ctx);
-		}
-	}
-
-#if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC
-	el3_state_t *el3_state = get_el3state_ctx(ctx);
-	u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3);
-
-	if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) {
-		tcr2_enable(ctx);
-	} else {
-		tcr2_disable(ctx);
-	}
-#endif
-
-}
-#endif
-
 /*******************************************************************************
  * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
  * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
@@ -1701,18 +1630,6 @@
  ******************************************************************************/
 void cm_prepare_el3_exit_ns(void)
 {
-#if IMAGE_BL31
-	/*
-	 * Check and handle Architecture feature asymmetry among cores.
-	 *
-	 * In warmboot path secondary cores context is initialized on core which
-	 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle
-	 * it in this function call.
-	 * For Symmetric cores this is an empty function.
-	 */
-	cm_handle_asymmetric_features();
-#endif
-
 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
 #if ENABLE_ASSERTIONS
 	cpu_context_t *ctx = cm_get_context(NON_SECURE);
@@ -2071,8 +1988,8 @@
  ******************************************************************************/
 u_register_t cm_get_scr_el3(uint32_t security_state)
 {
-	cpu_context_t *ctx;
-	el3_state_t *state;
+	const cpu_context_t *ctx;
+	const el3_state_t *state;
 
 	ctx = cm_get_context(security_state);
 	assert(ctx != NULL);

diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
deleted file mode 100644
index 02d9415..0000000
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
-.globl	_cpu_data_by_index
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
- *
- * Return the cpu_data structure for the CPU with given linear index
- *
- * This can be called without a valid stack.
- * clobbers: x0, x1
- * -----------------------------------------------------------------
- */
-func _cpu_data_by_index
-	mov_imm	x1, CPU_DATA_SIZE
-	mul	x0, x0, x1
-	adrp	x1, percpu_data
-	add	x1, x1, :lo12:percpu_data
-	add	x0, x0, x1
-	ret
-endfunc _cpu_data_by_index

diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c
index 2056182..f2e97f0 100644
--- a/lib/el3_runtime/cpu_data_array.c
+++ b/lib/el3_runtime/cpu_data_array.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,14 @@
 
 #include <lib/cassert.h>
 #include <lib/el3_runtime/cpu_data.h>
+#include <plat/common/platform.h>
 
 /* The per_cpu_ptr_cache_t space allocation */
 cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
+
+#ifndef __aarch64__
+cpu_data_t *_cpu_data(void)
+{
+	return _cpu_data_by_index(plat_my_core_pos());
+}
+#endif

diff --git a/lib/extensions/pauth/pauth.c b/lib/extensions/pauth/pauth.c
new file mode 100644
index 0000000..fbbcaa2
--- /dev/null
+++ b/lib/extensions/pauth/pauth.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+#include <lib/el3_runtime/cpu_data.h>
+#include <lib/extensions/pauth.h>
+
+extern uint64_t bl1_apiakey[2];
+
+void __no_pauth pauth_init_enable_el3(void)
+{
+	if (is_feat_pauth_supported()) {
+		pauth_init();
+		pauth_enable_el3();
+	}
+}
+
+void __no_pauth pauth_init_enable_el1(void)
+{
+	if (is_feat_pauth_supported()) {
+		pauth_init();
+		pauth_enable_el1();
+	}
+}
+
+void pauth_init(void)
+{
+	uint128_t keys = plat_init_apkey();
+	uint64_t key_lo = LO_64(keys);
+	uint64_t key_hi = HI_64(keys);
+
+	/* Program instruction key A used by the Trusted Firmware */
+	write_apiakeylo_el1(key_lo);
+	write_apiakeyhi_el1(key_hi);
+
+#if IMAGE_BL31
+	set_cpu_data(apiakey[0], key_lo);
+	set_cpu_data(apiakey[1], key_hi);
+
+	/*
+	 * In the warmboot entrypoint, cpu_data may have been written before
+	 * data caching was enabled. Flush the caches so nothing stale is read.
+	 */
+#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
+	flush_cpu_data(apiakey);
+#endif
+#elif IMAGE_BL1
+	bl1_apiakey[0] = key_lo;
+	bl1_apiakey[1] = key_hi;
+#endif
+}
+
+/*
+ * Begin checking function calls at the current EL. This function must not have
+ * PAuth guards because the signing will be a NOP and attempting to authenticate
+ * will fail. Includes an ISB to avoid accidental failures.
+ */
+void __no_pauth pauth_enable_el3(void)
+{
+	write_sctlr_el3(read_sctlr_el3() | SCTLR_EnIA_BIT);
+
+	if (is_feat_pauth_lr_supported()) {
+		write_sctlr2_el3(read_sctlr2_el3() | SCTLR2_EnPACM_BIT);
+	}
+
+	isb();
+}
+
+void __no_pauth pauth_enable_el1(void)
+{
+	write_sctlr_el1(read_sctlr_el1() | SCTLR_EnIA_BIT);
+
+	if (is_feat_pauth_lr_supported()) {
+		write_sctlr2_el1(read_sctlr2_el1() | SCTLR2_EnPACM_BIT);
+	}
+
+	isb();
+}
+
+void pauth_enable_el2(void)
+{
+	u_register_t hcr_el2 = read_hcr_el2();
+	/*
+	 * For Armv8.3 pointer authentication feature, disable traps to EL2 when
+	 * accessing key registers or using pointer authentication instructions
+	 * from lower ELs.
+	 */
+	hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
+
+	write_hcr_el2(hcr_el2);
+}
+
+void __no_pauth pauth_disable_el1(void)
+{
+	write_sctlr_el1(read_sctlr_el1() & ~SCTLR_EnIA_BIT);
+	isb(); /* usually called by caller, here it's for compatibility */
+}
+
+void __no_pauth pauth_disable_el3(void)
+{
+	write_sctlr_el3(read_sctlr_el3() & ~SCTLR_EnIA_BIT);
+	isb(); /* usually called by caller, here it's for compatibility */
+}

diff --git a/lib/extensions/pauth/pauth_helpers.S b/lib/extensions/pauth/pauth_helpers.S
deleted file mode 100644
index fb5fa97..0000000
--- a/lib/extensions/pauth/pauth_helpers.S
+++ /dev/null

@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
-	.global	pauth_init_enable_el1
-	.global	pauth_disable_el1
-	.global	pauth_init_enable_el3
-	.global	pauth_disable_el3
-	.globl	pauth_load_bl31_apiakey
-	.globl	pauth_load_bl1_apiakey_enable
-
-/* -------------------------------------------------------------
- * Program APIAKey_EL1 and enable pointer authentication in EL1
- * -------------------------------------------------------------
- */
-func pauth_init_enable_el1
-	stp	x29, x30, [sp, #-16]!
-
-	/* Initialize platform key */
-	bl	plat_init_apkey
-
-	/* Program instruction key A used by the Trusted Firmware */
-	msr	APIAKeyLo_EL1, x0
-	msr	APIAKeyHi_EL1, x1
-
-	/* Enable pointer authentication */
-	mrs	x0, sctlr_el1
-	orr	x0, x0, #SCTLR_EnIA_BIT
-
-#if ENABLE_BTI
-	 /* Enable PAC branch type compatibility */
-	bic	x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
-#endif
-	msr	sctlr_el1, x0
-	isb
-
-	ldp	x29, x30, [sp], #16
-	ret
-endfunc pauth_init_enable_el1
-
-/* -------------------------------------------------------------
- * Disable pointer authentication in EL1
- * -------------------------------------------------------------
- */
-func pauth_disable_el1
-	mrs	x0, sctlr_el1
-	bic	x0, x0, #SCTLR_EnIA_BIT
-	msr	sctlr_el1, x0
-	isb
-	ret
-endfunc pauth_disable_el1
-
-/* -------------------------------------------------------------
- * Program APIAKey_EL1 and enable pointer authentication in EL3
- * -------------------------------------------------------------
- */
-func pauth_init_enable_el3
-	stp	x29, x30, [sp, #-16]!
-
-	/* Initialize platform key */
-	bl	plat_init_apkey
-
-	/* Program instruction key A used by the Trusted Firmware */
-	msr	APIAKeyLo_EL1, x0
-	msr	APIAKeyHi_EL1, x1
-
-	/* Enable pointer authentication */
-	mrs	x0, sctlr_el3
-	orr	x0, x0, #SCTLR_EnIA_BIT
-
-#if ENABLE_BTI
-	 /* Enable PAC branch type compatibility */
-	bic	x0, x0, #SCTLR_BT_BIT
-#endif
-	msr	sctlr_el3, x0
-	isb
-
-	ldp	x29, x30, [sp], #16
-	ret
-endfunc pauth_init_enable_el3
-
-/* -------------------------------------------------------------
- * Disable pointer authentication in EL3
- * -------------------------------------------------------------
- */
-func pauth_disable_el3
-	mrs	x0, sctlr_el3
-	bic	x0, x0, #SCTLR_EnIA_BIT
-	msr	sctlr_el3, x0
-	isb
-	ret
-endfunc pauth_disable_el3
-
-/* -------------------------------------------------------------
- * The following functions strictly follow the AArch64 PCS
- * to use x9-x17 (temporary caller-saved registers) to load
- * the APIAKey_EL1 and enable pointer authentication.
- * -------------------------------------------------------------
- */
-func pauth_load_bl31_apiakey
-	/* tpidr_el3 contains the address of cpu_data structure */
-	mrs	x9, tpidr_el3
-
-	/* Load apiakey from cpu_data */
-	ldp	x10, x11, [x9, #CPU_DATA_APIAKEY_OFFSET]
-
-	/* Program instruction key A */
-	msr	APIAKeyLo_EL1, x10
-	msr	APIAKeyHi_EL1, x11
-	isb
-	ret
-endfunc pauth_load_bl31_apiakey
-
-func pauth_load_bl1_apiakey_enable
-	/* Load instruction key A used by the Trusted Firmware */
-	adrp	x9, bl1_apiakey
-	add	x9, x9, :lo12:bl1_apiakey
-	ldp	x10, x11, [x9]
-
-	/* Program instruction key A */
-	msr	APIAKeyLo_EL1, x10
-	msr	APIAKeyHi_EL1, x11
-
-	/* Enable pointer authentication */
-	mrs	x9, sctlr_el3
-	orr	x9, x9, #SCTLR_EnIA_BIT
-
-#if ENABLE_BTI
-	 /* Enable PAC branch type compatibility */
-	bic	x9, x9, #SCTLR_BT_BIT
-#endif
-	msr	sctlr_el3, x9
-	isb
-	ret
-endfunc pauth_load_bl1_apiakey_enable

diff --git a/lib/extensions/pmuv3/aarch64/pmuv3.c b/lib/extensions/pmuv3/aarch64/pmuv3.c
index 61d1258..b47b664 100644
--- a/lib/extensions/pmuv3/aarch64/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch64/pmuv3.c

@@ -78,11 +78,14 @@
 	 *   1  |  1   |    enabled   | disabled only for counters 0 to
 	 *                              MDCR_EL2.HPMN - 1. Enabled for the rest
 	 *
+	 * MDCR_EL3.EnPM2: Set to one so that various PMUv3p9 related system
+	 * register accesses do not trap to EL3.
+	 *
 	 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
 	 *  accesses to all Performance Monitors registers do not trap to EL3.
 	 */
-	mdcr_el3_val = (mdcr_el3_val | MDCR_SCCD_BIT | MDCR_MCCD_BIT) &
-		  ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT);
+	mdcr_el3_val |= MDCR_SCCD_BIT | MDCR_MCCD_BIT | MDCR_EnPM2_BIT;
+	mdcr_el3_val &=	~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT);
 	mdcr_el3_val = mtpmu_disable_el3(mdcr_el3_val);
 
 	write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);

diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index d7df267..e499486 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c

@@ -26,12 +26,12 @@
 	 * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
 	 * When FEAT_RME is not implemented, this field is RES0.
 	 *
-	 * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
-	 * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
-	 * Setting this bit to 1 doesn't have any effect on it when
-	 * FEAT_SPEv1p2 not implemented.
+	 * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Do not trap access to
+	 * PMSNEVFR_EL1 or PMSDSFR_EL1 register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2
+	 * or FEAT_SPE_FDS are implemented. Setting these bits to 1 doesn't have any
+	 * effect on it when the features aren't implemented.
 	 */
-	mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
+	mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT | MDCR_EnPMS3_BIT;
 	mdcr_el3_val &= ~(MDCR_NSPBE_BIT);
 	write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
 }
@@ -46,10 +46,11 @@
 	 *  Disable access of profiling buffer control registers from lower ELs
 	 *  in any security state. Secure state owns the buffer.
 	 *
-	 * MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1
-	 * from EL2/EL1 to EL3.
+	 * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Clear the bits to trap access
+	 * of PMSNEVFR_EL1 and PMSDSFR_EL1 from EL2/EL1 to EL3.
 	 */
-	mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT);
+	mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT |
+			  MDCR_EnPMS3_BIT);
 	write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
 }
 

diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c
index d36853a..dbafca1 100644
--- a/lib/extensions/trf/aarch64/trf.c
+++ b/lib/extensions/trf/aarch64/trf.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,8 +22,12 @@
 	 * MDCR_EL3.TTRF = b0
 	 * Allow access of trace filter control registers from NS-EL2
 	 * and NS-EL1 when NS-EL2 is implemented but not used
+	 *
+	 * MDCR_EL3.RLTE = b0
+	 * Trace prohibited in Realm state, unless overridden by the
+	 * IMPLEMENTATION DEFINED authentication interface.
 	 */
-	mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
+	mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT | MDCR_RLTE_BIT);
 	write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
 }
 

diff --git a/lib/libc/memchr.c b/lib/libc/memchr.c
index 66d7ba1..e009a5f 100644
--- a/lib/libc/memchr.c
+++ b/lib/libc/memchr.c

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <stddef.h>
-#include <string.h>
+#include <string_private.h>
 
 void *memchr(const void *src, int c, size_t len)
 {

diff --git a/lib/libc/memcmp.c b/lib/libc/memcmp.c
index db2701b..1458208 100644
--- a/lib/libc/memcmp.c
+++ b/lib/libc/memcmp.c

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <stddef.h>
-#include <string.h>
+#include <string_private.h>
 
 int memcmp(const void *s1, const void *s2, size_t len)
 {

diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index af9ed45..e8be154 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c

@@ -1,19 +1,20 @@
 /*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <stddef.h>
-#include <string.h>
+#include <string_private.h>
 
 void *memcpy(void *dst, const void *src, size_t len)
 {
 	const char *s = src;
 	char *d = dst;
 
-	while (len--)
+	while (len--) {
 		*d++ = *s++;
+	}
 
 	return dst;
 }

diff --git a/lib/libc/memcpy_s.c b/lib/libc/memcpy_s.c
index 26953bf..ee87637 100644
--- a/lib/libc/memcpy_s.c
+++ b/lib/libc/memcpy_s.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -53,12 +53,7 @@
 		}
 	}
 
-	/*
-	 * Start copy process when there is no error
-	 */
-	while (ssize--) {
-		d[ssize] = s[ssize];
-	}
+	(void)memcpy(dst, src, ssize);
 
 	return 0;
 }

diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 5c2b661..7aee83f 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c

@@ -16,7 +16,7 @@
 	 * that issue is probably moot as such usage is probably undefined
 	 * behaviour and a bug anyway.
 	 */
-	if ((size_t)dst - (size_t)src >= len) {
+	if (((size_t)dst - (size_t)src) >= len) {
 		/* destination not in source data, so can safely use memcpy */
 		return memcpy(dst, src, len);
 	} else {
@@ -24,8 +24,9 @@
 		const char *end = dst;
 		const char *s = (const char *)src + len;
 		char *d = (char *)dst + len;
-		while (d != end)
+		while (d != end) {
 			*--d = *--s;
+		}
 	}
 	return dst;
 }

diff --git a/lib/libc/memset.c b/lib/libc/memset.c
index c5bac8d..2513221 100644
--- a/lib/libc/memset.c
+++ b/lib/libc/memset.c

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <stddef.h>
-#include <string.h>
+#include <string_private.h>
 #include <stdint.h>
 
 void *memset(void *dst, int val, size_t count)

diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index a856345..65c5238 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c

@@ -44,19 +44,19 @@
 	unsigned int rem;
 
 	/* num_buf is only large enough for radix >= 10 */
-	if (radix < 10) {
+	if (radix < 10U) {
 		assert(0);
 		return 0;
 	}
 
 	do {
-		rem = unum % radix;
-		if (rem < 0xa) {
+		rem = (uint32_t)(unum % radix);
+		if (rem < 0xaU) {
 			num_buf[i] = '0' + rem;
 		} else if (uppercase) {
-			num_buf[i] = 'A' + (rem - 0xa);
+			num_buf[i] = 'A' + (rem - 0xaU);
 		} else {
-			num_buf[i] = 'a' + (rem - 0xa);
+			num_buf[i] = 'a' + (rem - 0xaU);
 		}
 		i++;
 		unum /= radix;
@@ -64,14 +64,14 @@
 
 	if (padn > 0) {
 		while (i < padn) {
-			(void)putchar(padc);
+			(void)putchar((int32_t)padc);
 			count++;
 			padn--;
 		}
 	}
 
 	while (--i >= 0) {
-		(void)putchar(num_buf[i]);
+		(void)putchar((int32_t)num_buf[i]);
 		count++;
 	}
 
@@ -105,7 +105,7 @@
 	int l_count;
 	long long int num;
 	unsigned long long int unum;
-	char *str;
+	const char *str;
 	char padc = '\0'; /* Padding character */
 	int padn; /* Number of characters to pad */
 	int count = 0; /* Number of printed characters */
@@ -122,17 +122,18 @@
 loop:
 			switch (*fmt) {
 			case '%':
-				(void)putchar('%');
+				(void)putchar((int32_t)'%');
 				break;
 			case 'i': /* Fall through to next one */
 			case 'd':
 				num = get_num_va_args(args, l_count);
 				if (num < 0) {
-					(void)putchar('-');
+					(void)putchar((int32_t)'-');
 					unum = (unsigned long long int)-num;
 					padn--;
-				} else
+				} else {
 					unum = (unsigned long long int)num;
+				}
 
 				count += unsigned_num_print(unum, 10,
 							    padc, padn, uppercase);
@@ -142,7 +143,7 @@
 				count++;
 				break;
 			case 's':
-				str = va_arg(args, char *);
+				str = va_arg(args, const char *);
 				count += string_print(str);
 				break;
 			case 'p':
@@ -164,8 +165,9 @@
 							    padc, padn, uppercase);
 				break;
 			case 'z':
-				if (sizeof(size_t) == 8U)
+				if (sizeof(size_t) == 8U) {
 					l_count = 2;
+				}
 
 				fmt++;
 				goto loop;

diff --git a/lib/libc/strchr.c b/lib/libc/strchr.c
index 1cd03ca..b3bebe4 100644
--- a/lib/libc/strchr.c
+++ b/lib/libc/strchr.c

@@ -30,12 +30,12 @@
  */
 
 /*
- * Portions copyright (c) 2018, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
  * All rights reserved.
  */
 
 #include <stddef.h>
-#include <string.h>
+#include <string_private.h>
 
 char *
 strchr(const char *p, int ch)

diff --git a/lib/libc/strcmp.c b/lib/libc/strcmp.c
index 290db4c..5afd0e9 100644
--- a/lib/libc/strcmp.c
+++ b/lib/libc/strcmp.c

@@ -33,11 +33,11 @@
  */
 
 /*
- * Portions copyright (c) 2018, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
  * All rights reserved.
  */
 
-#include <string.h>
+#include <string_private.h>
 
 /*
  * Compare strings.

diff --git a/lib/libc/strlen.c b/lib/libc/strlen.c
index e4b79d9..cc1d1df 100644
--- a/lib/libc/strlen.c
+++ b/lib/libc/strlen.c

@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <string.h>
+#include <string_private.h>
 
 size_t strlen(const char *s)
 {

diff --git a/lib/libc/strncmp.c b/lib/libc/strncmp.c
index f0bbadc..828e0c5 100644
--- a/lib/libc/strncmp.c
+++ b/lib/libc/strncmp.c

@@ -30,11 +30,11 @@
  */
 
 /*
- * Portions copyright (c) 2018, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
  * All rights reserved.
  */
 
-#include <string.h>
+#include <string_private.h>
 
 int
 strncmp(const char *s1, const char *s2, size_t n)

diff --git a/lib/libc/strrchr.c b/lib/libc/strrchr.c
index cd435ff..98f76c6 100644
--- a/lib/libc/strrchr.c
+++ b/lib/libc/strrchr.c

@@ -30,7 +30,7 @@
  */
 
 #include <stddef.h>
-#include <string.h>
+#include <string_private.h>
 
 char *
 strrchr(const char *p, int ch)

diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 234a195..1021ef6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c

@@ -215,7 +215,7 @@
  ******************************************************************************/
 bool psci_is_last_on_cpu(unsigned int my_idx)
 {
-	for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+	for (unsigned int cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
 		if (cpu_idx == my_idx) {
 			assert(psci_get_aff_info_state() == AFF_STATE_ON);
 			continue;
@@ -239,7 +239,7 @@
 {
 	unsigned int cpu_idx;
 
-	for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+	for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
 		if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) {
 			return false;
 		}
@@ -249,6 +249,33 @@
 }
 
 /*******************************************************************************
+ * Counts the number of CPUs in the system that are currently in the ON or
+ * ON_PENDING state.
+ *
+ * @note This function does not acquire any power domain locks. It must only be
+ *       called in contexts where it is guaranteed that PSCI state transitions
+ *       are not concurrently happening, or where locks are already held.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+static unsigned int psci_num_cpus_running(void)
+{
+	unsigned int cpu_idx;
+	unsigned int no_of_cpus = 0U;
+	aff_info_state_t aff_state;
+
+	for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
+		aff_state = psci_get_aff_info_state_by_idx(cpu_idx);
+		if (aff_state == AFF_STATE_ON ||
+		    aff_state == AFF_STATE_ON_PENDING) {
+			no_of_cpus++;
+		}
+	}
+
+	return no_of_cpus;
+}
+
+/*******************************************************************************
  * Routine to return the maximum power level to traverse to after a cpu has
  * been physically powered up. It is expected to be called immediately after
  * reset from assembler code.
@@ -546,7 +573,7 @@
 	unsigned int lvl, parent_idx;
 	unsigned int start_idx;
 	unsigned int ncpus;
-	plat_local_state_t target_state, *req_states;
+	plat_local_state_t target_state;
 
 	assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
 	parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
@@ -561,7 +588,8 @@
 
 		/* Get the requested power states for this power level */
 		start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
-		req_states = psci_get_req_local_pwr_states(lvl, start_idx);
+		plat_local_state_t const *req_states = psci_get_req_local_pwr_states(lvl,
+										start_idx);
 
 		/*
 		 * Let the platform coordinate amongst the requested states at
@@ -1031,6 +1059,13 @@
 	}
 
 	/*
+	 * Caches and (importantly) coherency are on so we can rely on seeing
+	 * whatever the primary gave us without explicit cache maintenance
+	 */
+	entry_point_info_t *ep = get_cpu_data(warmboot_ep_info);
+	cm_init_my_context(ep);
+
+	/*
 	 * Generic management: Now we just need to retrieve the
 	 * information that we had stashed away during the cpu_on
 	 * call to set this cpu on its way.
@@ -1298,7 +1333,8 @@
 
 	/* Need to wait for other cores to shutdown */
 	if (wait_ms != 0U) {
-		while ((wait_ms-- != 0U) && (!psci_is_last_on_cpu(this_cpu_idx))) {
+		for (uint32_t delay_ms = wait_ms; ((delay_ms != 0U) &&
+					(!psci_is_last_on_cpu(this_cpu_idx))); delay_ms--) {
 			mdelay(1U);
 		}
 
@@ -1362,3 +1398,30 @@
 
 	return true;
 }
+
+/*******************************************************************************
+ * Safely counts the number of CPUs in the system that are currently in the ON
+ * or ON_PENDING state.
+ *
+ * This function acquires and releases the necessary power domain locks to
+ * ensure consistency of the CPU state information.
+ *
+ * @param this_core The index of the current core making the query.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core)
+{
+	unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
+	unsigned int no_of_cpus;
+
+	psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes);
+
+	psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+	no_of_cpus = psci_num_cpus_running();
+
+	psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+	return no_of_cpus;
+}

diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index 527ad3a..e1dbec2 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk

@@ -1,11 +1,10 @@
 #
-# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 PSCI_LIB_SOURCES	:=	lib/el3_runtime/cpu_data_array.c	\
-				lib/el3_runtime/${ARCH}/cpu_data.S	\
 				lib/el3_runtime/${ARCH}/context_mgmt.c	\
 				lib/cpus/${ARCH}/cpu_helpers.S		\
 				lib/cpus/errata_report.c		\

diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 34de10f..dfec9a1 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,15 +28,17 @@
 
 {
 	int rc;
-	entry_point_info_t ep;
+	entry_point_info_t *ep;
+	unsigned int target_idx = (unsigned int)plat_core_pos_by_mpidr(target_cpu);
 
 	/* Validate the target CPU */
 	if (!is_valid_mpidr(target_cpu)) {
 		return PSCI_E_INVALID_PARAMS;
 	}
 
-	/* Validate the entry point and get the entry_point_info */
-	rc = psci_validate_entry_point(&ep, entrypoint, context_id);
+	ep = get_cpu_data_by_index(target_idx, warmboot_ep_info);
+	/* Validate the lower EL entry point and put it in the entry_point_info */
+	rc = psci_validate_entry_point(ep, entrypoint, context_id);
 	if (rc != PSCI_E_SUCCESS) {
 		return rc;
 	}
@@ -45,7 +47,7 @@
 	 * To turn this cpu on, specify which power
 	 * levels need to be turned on
 	 */
-	return psci_cpu_on_start(target_cpu, &ep);
+	return psci_cpu_on_start(target_cpu, ep);
 }
 
 unsigned int psci_version(void)
@@ -59,7 +61,6 @@
 {
 	int rc;
 	unsigned int target_pwrlvl, is_power_down_state;
-	entry_point_info_t ep;
 	psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
 	plat_local_state_t cpu_pd_state;
 	unsigned int cpu_idx = plat_my_core_pos();
@@ -173,7 +174,9 @@
 	 * point and program entry information.
 	 */
 	if (is_power_down_state != 0U) {
-		rc = psci_validate_entry_point(&ep, entrypoint, context_id);
+		entry_point_info_t *ep = get_cpu_data_by_index(cpu_idx, warmboot_ep_info);
+
+		rc = psci_validate_entry_point(ep, entrypoint, context_id);
 		if (rc != PSCI_E_SUCCESS) {
 			return rc;
 		}
@@ -186,7 +189,6 @@
 	 * arrival of an interrupt
 	 */
 	rc = psci_cpu_suspend_start(cpu_idx,
-				    &ep,
 				    target_pwrlvl,
 				    &state_info,
 				    is_power_down_state);
@@ -199,8 +201,8 @@
 {
 	int rc;
 	psci_power_state_t state_info;
-	entry_point_info_t ep;
 	unsigned int cpu_idx = plat_my_core_pos();
+	entry_point_info_t *ep = get_cpu_data_by_index(cpu_idx, warmboot_ep_info);
 
 	/* Check if the current CPU is the last ON CPU in the system */
 	if (!psci_is_last_on_cpu(cpu_idx)) {
@@ -208,7 +210,7 @@
 	}
 
 	/* Validate the entry point and get the entry_point_info */
-	rc = psci_validate_entry_point(&ep, entrypoint, context_id);
+	rc = psci_validate_entry_point(ep, entrypoint, context_id);
 	if (rc != PSCI_E_SUCCESS) {
 		return rc;
 	}
@@ -235,7 +237,6 @@
 	 * arrival of an interrupt
 	 */
 	rc = psci_cpu_suspend_start(cpu_idx,
-				    &ep,
 				    PLAT_MAX_PWR_LVL,
 				    &state_info,
 				    PSTATE_TYPE_POWERDOWN);
@@ -299,13 +300,13 @@
 	flush_cpu_data_by_index(target_idx,
 				psci_svc_cpu_data.aff_info_state);
 
-	return psci_get_aff_info_state_by_idx(target_idx);
+	return (int)psci_get_aff_info_state_by_idx(target_idx);
 }
 
 int psci_migrate(u_register_t target_cpu)
 {
 	int rc;
-	u_register_t resident_cpu_mpidr;
+	u_register_t resident_cpu_mpidr = 0;
 
 	/* Validate the target cpu */
 	if (!is_valid_mpidr(target_cpu))
@@ -347,7 +348,7 @@
 
 u_register_t psci_migrate_info_up_cpu(void)
 {
-	u_register_t resident_cpu_mpidr;
+	u_register_t resident_cpu_mpidr = 0;
 	int rc;
 
 	/*

diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 577fdd7..2485601 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -11,6 +11,7 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/arm/gic.h>
 #include <lib/pmf/pmf.h>
 #include <lib/runtime_instr.h>
 #include <plat/common/platform.h>
@@ -94,7 +95,7 @@
 	if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_off != NULL)) {
 		rc = psci_spd_pm->svc_off(0);
 		if (rc != PSCI_E_SUCCESS)
-			goto exit;
+			goto off_exit;
 	}
 
 	/*
@@ -117,6 +118,13 @@
 	 */
 	psci_pwrdown_cpu_start(psci_find_max_off_lvl(&state_info));
 
+#if USE_GIC_DRIVER
+	/* turn the GIC off before we hand off to the platform */
+	gic_cpuif_disable(idx);
+	/* we don't want any wakeups until explicitly turned on */
+	gic_pcpu_off(idx);
+#endif /* USE_GIC_DRIVER */
+
 	/*
 	 * Plat. management: Perform platform specific actions to turn this
 	 * cpu off e.g. exit cpu coherency, program the power controller etc.
@@ -127,7 +135,7 @@
 	plat_psci_stat_accounting_start(&state_info);
 #endif
 
-exit:
+off_exit:
 	/*
 	 * Release the locks corresponding to each power level in the
 	 * reverse order to which they were acquired.

diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 7e161dd..4ae07e1 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <drivers/arm/gic.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/el3_runtime/pubsub_events.h>
 #include <plat/common/platform.h>
@@ -93,7 +94,7 @@
 				psci_svc_cpu_data.aff_info_state);
 	rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
 	if (rc != PSCI_E_SUCCESS)
-		goto exit;
+		goto on_exit;
 
 	/*
 	 * Call the cpu on handler registered by the Secure Payload Dispatcher
@@ -141,17 +142,14 @@
 	rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
 	assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
 
-	if (rc == PSCI_E_SUCCESS) {
-		/* Store the re-entry information for the non-secure world. */
-		cm_init_context_by_index(target_idx, ep);
-	} else {
+	if (rc != PSCI_E_SUCCESS) {
 		/* Restore the state on error. */
 		psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
 		flush_cpu_data_by_index(target_idx,
 					psci_svc_cpu_data.aff_info_state);
 	}
 
-exit:
+on_exit:
 	psci_spin_unlock_cpu(target_idx);
 	return rc;
 }
@@ -186,6 +184,13 @@
 	if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) {
 		psci_plat_pm_ops->pwr_domain_on_finish_late(state_info);
 	}
+
+#if USE_GIC_DRIVER
+	/* GIC init after platform has had a say with MMU on */
+	gic_pcpu_init(cpu_idx);
+	gic_cpuif_enable(cpu_idx);
+#endif /* USE_GIC_DRIVER */
+
 	/*
 	 * All the platform specific actions for turning this cpu
 	 * on have completed. Perform enough arch.initialization

diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index 49b19c9..f3f5a5c 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -344,7 +344,6 @@
 
 /* Private exported functions from psci_suspend.c */
 int psci_cpu_suspend_start(unsigned int idx,
-			   const entry_point_info_t *ep,
 			   unsigned int end_pwrlvl,
 			   psci_power_state_t *state_info,
 			   unsigned int is_power_down_state);

diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 3604549..44c9bdb 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,6 +30,7 @@
  * of relying on platform defined constants.
  ******************************************************************************/
 static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
+static entry_point_info_t warmboot_ep_info[PLATFORM_CORE_COUNT];
 
 /******************************************************************************
  * Define the psci capability variable.
@@ -62,8 +63,7 @@
 		/* Initialize with an invalid mpidr */
 		psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
 
-		svc_cpu_data =
-			&(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
+		svc_cpu_data = &get_cpu_data_by_index(node_idx, psci_svc_cpu_data);
 
 		/* Set the Affinity Info for the cores as OFF */
 		svc_cpu_data->aff_info_state = AFF_STATE_OFF;
@@ -114,6 +114,13 @@
 	}
 }
 
+static void __init populate_cpu_data(void)
+{
+	for (unsigned int idx = 0; idx < psci_plat_core_count; idx++) {
+		set_cpu_data_by_index(idx, warmboot_ep_info, &warmboot_ep_info[idx]);
+	}
+}
+
 /*******************************************************************************
  * Core routine to populate the power domain tree. The tree descriptor passed by
  * the platform is populated breadth-first and the first entry in the map
@@ -218,6 +225,9 @@
 	/* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
 	psci_update_pwrlvl_limits();
 
+	/* Initialise the warmboot entrypoints */
+	populate_cpu_data();
+
 	/* Populate the mpidr field of cpu node for this CPU */
 	psci_cpu_pd_nodes[cpu_idx].mpidr =
 		read_mpidr() & MPIDR_AFFINITY_MASK;
@@ -308,11 +318,6 @@
 	/* Having initialized cpu_ops, we can now print errata status */
 	print_errata_status();
 
-#if ENABLE_PAUTH
-	/* Store APIAKey_EL1 key */
-	set_cpu_data(apiakey[0], read_apiakeylo_el1());
-	set_cpu_data(apiakey[1], read_apiakeyhi_el1());
-#endif /* ENABLE_PAUTH */
 }
 
 /******************************************************************************

diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index 0fb1ed3..73b9a67 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c

@@ -12,6 +12,7 @@
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <context.h>
+#include <drivers/arm/gic.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/el3_runtime/cpu_data.h>
 #include <lib/el3_runtime/pubsub_events.h>
@@ -45,7 +46,6 @@
 static void psci_suspend_to_pwrdown_start(unsigned int idx,
 					  unsigned int end_pwrlvl,
 					  unsigned int max_off_lvl,
-					  const entry_point_info_t *ep,
 					  const psci_power_state_t *state_info)
 {
 	PUBLISH_EVENT_ARG(psci_suspend_pwrdown_start, &idx);
@@ -85,12 +85,6 @@
 	if (psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early != NULL)
 		psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early(state_info);
 #endif
-
-	/*
-	 * Store the re-entry information for the non-secure world.
-	 */
-	cm_init_my_context(ep);
-
 	/*
 	 * Arch. management. Initiate power down sequence.
 	 */
@@ -116,7 +110,6 @@
  * not possible to undo any of the actions taken beyond that point.
  ******************************************************************************/
 int psci_cpu_suspend_start(unsigned int idx,
-			   const entry_point_info_t *ep,
 			   unsigned int end_pwrlvl,
 			   psci_power_state_t *state_info,
 			   unsigned int is_power_down_state)
@@ -124,10 +117,6 @@
 	int rc = PSCI_E_SUCCESS;
 	unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
 	unsigned int max_off_lvl = 0;
-#if FEAT_PABANDON
-	cpu_context_t *ctx = cm_get_context(NON_SECURE);
-	cpu_context_t old_ctx;
-#endif
 
 	/*
 	 * This function must only be called on platforms where the
@@ -152,7 +141,7 @@
 	 * detection that a wake-up interrupt has fired.
 	 */
 	if (read_isr_el1() != 0U) {
-		goto exit;
+		goto suspend_exit;
 	}
 
 #if PSCI_OS_INIT_MODE
@@ -163,7 +152,7 @@
 		 */
 		rc = psci_validate_state_coordination(idx, end_pwrlvl, state_info);
 		if (rc != PSCI_E_SUCCESS) {
-			goto exit;
+			goto suspend_exit;
 		}
 	} else {
 #endif
@@ -181,7 +170,7 @@
 	if (psci_plat_pm_ops->pwr_domain_validate_suspend != NULL) {
 		rc = psci_plat_pm_ops->pwr_domain_validate_suspend(state_info);
 		if (rc != PSCI_E_SUCCESS) {
-			goto exit;
+			goto suspend_exit;
 		}
 	}
 #endif
@@ -205,35 +194,22 @@
 #if !CTX_INCLUDE_EL2_REGS
 		cm_el1_sysregs_context_save(NON_SECURE);
 #endif
-		/*
-		 * when the core wakes it expects its context to already be in
-		 * place so we must overwrite it before powerdown. But if
-		 * powerdown never happens we want the old context. Save it in
-		 * case we wake up. EL2/El1 will not be touched by PSCI so don't
-		 * copy */
-		memcpy(&ctx->gpregs_ctx, &old_ctx.gpregs_ctx, sizeof(gp_regs_t));
-		memcpy(&ctx->el3state_ctx, &old_ctx.el3state_ctx, sizeof(el3_state_t));
-#if DYNAMIC_WORKAROUND_CVE_2018_3639
-		memcpy(&ctx->cve_2018_3639_ctx, &old_ctx.cve_2018_3639_ctx, sizeof(cve_2018_3639_t));
-#endif
-#if ERRATA_SPECULATIVE_AT
-		memcpy(&ctx->errata_speculative_at_ctx, &old_ctx.errata_speculative_at_ctx, sizeof(errata_speculative_at_t));
-#endif
-#if CTX_INCLUDE_PAUTH_REGS
-		memcpy(&ctx->pauth_ctx, &old_ctx.pauth_ctx, sizeof(pauth_t));
-#endif
 #endif
 		max_off_lvl = psci_find_max_off_lvl(state_info);
-		psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, ep, state_info);
+		psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info);
 	}
 
+#if USE_GIC_DRIVER
+	/* turn the GIC off before we hand off to the platform */
+	gic_cpuif_disable(idx);
+#endif /* USE_GIC_DRIVER */
+
 	/*
 	 * Plat. management: Allow the platform to perform the
 	 * necessary actions to turn off this cpu e.g. set the
 	 * platform defined mailbox with the psci entrypoint,
 	 * program the power controller etc.
 	 */
-
 	psci_plat_pm_ops->pwr_domain_suspend(state_info);
 
 #if ENABLE_PSCI_STAT
@@ -301,18 +277,6 @@
 #if FEAT_PABANDON
 		psci_cpu_suspend_to_powerdown_finish(idx, max_off_lvl, state_info);
 
-		/* we overwrote context ourselves, put it back */
-		memcpy(&ctx->gpregs_ctx, &old_ctx.gpregs_ctx, sizeof(gp_regs_t));
-		memcpy(&ctx->el3state_ctx, &old_ctx.el3state_ctx, sizeof(el3_state_t));
-#if DYNAMIC_WORKAROUND_CVE_2018_3639
-		memcpy(&ctx->cve_2018_3639_ctx, &old_ctx.cve_2018_3639_ctx, sizeof(cve_2018_3639_t));
-#endif
-#if ERRATA_SPECULATIVE_AT
-		memcpy(&ctx->errata_speculative_at_ctx, &old_ctx.errata_speculative_at_ctx, sizeof(errata_speculative_at_t));
-#endif
-#if CTX_INCLUDE_PAUTH_REGS
-		memcpy(&ctx->pauth_ctx, &old_ctx.pauth_ctx, sizeof(pauth_t));
-#endif
 #if !CTX_INCLUDE_EL2_REGS
 		cm_el1_sysregs_context_restore(NON_SECURE);
 #endif
@@ -321,13 +285,18 @@
 		psci_cpu_suspend_to_standby_finish(end_pwrlvl, state_info);
 	}
 
+#if USE_GIC_DRIVER
+	/* Turn GIC on after platform has had a chance to do state management */
+	gic_cpuif_enable(idx);
+#endif /* USE_GIC_DRIVER */
+
 	/*
 	 * Set the requested and target state of this CPU and all the higher
 	 * power domain levels for this CPU to run.
 	 */
 	psci_set_pwr_domains_to_run(idx, end_pwrlvl);
 
-exit:
+suspend_exit:
 	psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
 
 	return rc;
@@ -361,16 +330,15 @@
 	psci_do_pwrup_cache_maintenance();
 #endif
 
+#if USE_GIC_DRIVER
+	/* GIC on after platform has had its say and MMU is on */
+	gic_cpuif_enable(cpu_idx);
+#endif /* USE_GIC_DRIVER */
+
 	/* Re-init the cntfrq_el0 register */
 	counter_freq = plat_get_syscnt_freq2();
 	write_cntfrq_el0(counter_freq);
 
-#if ENABLE_PAUTH
-	/* Store APIAKey_EL1 key */
-	set_cpu_data(apiakey[0], read_apiakeylo_el1());
-	set_cpu_data(apiakey[1], read_apiakeyhi_el1());
-#endif /* ENABLE_PAUTH */
-
 	/*
 	 * Call the cpu suspend finish handler registered by the Secure Payload
 	 * Dispatcher to let it do any bookeeping. If the handler encounters an

diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c
index 1dcaa23..19f2476 100644
--- a/lib/psci/psci_system_off.c
+++ b/lib/psci/psci_system_off.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,6 +9,7 @@
 
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/arm/gic.h>
 #include <drivers/console.h>
 #include <plat/common/platform.h>
 
@@ -27,6 +28,11 @@
 
 	console_flush();
 
+#if USE_GIC_DRIVER
+	/* turn the GIC off before we hand off to the platform */
+	gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
 	/* Call the platform specific hook */
 	psci_plat_pm_ops->system_off();
 
@@ -46,6 +52,11 @@
 
 	console_flush();
 
+#if USE_GIC_DRIVER
+	/* turn the GIC off before we hand off to the platform */
+	gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
 	/* Call the platform specific hook */
 	psci_plat_pm_ops->system_reset();
 
@@ -80,6 +91,11 @@
 	}
 	console_flush();
 
+#if USE_GIC_DRIVER
+	/* turn the GIC off before we hand off to the platform */
+	gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
 	u_register_t ret =
 		(u_register_t) psci_plat_pm_ops->system_reset2((int) is_vendor, reset_type, cookie);
 	if (ret != PSCI_E_SUCCESS)

diff --git a/lib/transfer_list/transfer_list.c b/lib/transfer_list/transfer_list.c
index 3817861..4d4a167 100644
--- a/lib/transfer_list/transfer_list.c
+++ b/lib/transfer_list/transfer_list.c

@@ -176,35 +176,32 @@
 	}
 
 	if (tl->signature != TRANSFER_LIST_SIGNATURE) {
-		ERROR("Bad transfer list signature 0x%x\n", tl->signature);
+		VERBOSE("Bad transfer list signature 0x%x\n", tl->signature);
 		return TL_OPS_NON;
 	}
 
 	if (!tl->max_size) {
-		ERROR("Bad transfer list max size 0x%x\n",
-		      tl->max_size);
+		VERBOSE("Bad transfer list max size 0x%x\n", tl->max_size);
 		return TL_OPS_NON;
 	}
 
 	if (tl->size > tl->max_size) {
-		ERROR("Bad transfer list size 0x%x\n", tl->size);
+		VERBOSE("Bad transfer list size 0x%x\n", tl->size);
 		return TL_OPS_NON;
 	}
 
 	if (tl->hdr_size != sizeof(struct transfer_list_header)) {
-		ERROR("Bad transfer list header size 0x%x\n",
-		      tl->hdr_size);
+		VERBOSE("Bad transfer list header size 0x%x\n", tl->hdr_size);
 		return TL_OPS_NON;
 	}
 
 	if (!transfer_list_verify_checksum(tl)) {
-		ERROR("Bad transfer list checksum 0x%x\n",
-		      tl->checksum);
+		VERBOSE("Bad transfer list checksum 0x%x\n", tl->checksum);
 		return TL_OPS_NON;
 	}
 
 	if (tl->version == 0) {
-		ERROR("Transfer list version is invalid\n");
+		VERBOSE("Transfer list version is invalid\n");
 		return TL_OPS_NON;
 	} else if (tl->version == TRANSFER_LIST_VERSION) {
 		INFO("Transfer list version is valid for all operations\n");

diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S
deleted file mode 100644
index 0dda979..0000000
--- a/lib/xlat_mpu/aarch64/enable_mpu.S
+++ /dev/null

@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <platform_def.h>
-
-	.global	enable_mpu_direct_el2
-
-	/* void enable_mmu_direct_el2(unsigned int flags) */
-func enable_mpu_direct_el2
-#if ENABLE_ASSERTIONS
-	mrs	x1, sctlr_el2
-	tst	x1, #SCTLR_M_BIT
-	ASM_ASSERT(eq)
-#endif
-	mov	x7, x0
-	adrp	x0, mmu_cfg_params
-	add	x0, x0, :lo12:mmu_cfg_params
-
-	/* (MAIRs are already set up) */
-
-	/* TCR */
-	ldr	x2, [x0, #(MMU_CFG_TCR << 3)]
-	msr	tcr_el2, x2
-
-	/*
-	 * Ensure all translation table writes have drained into memory, the TLB
-	 * invalidation is complete, and translation register writes are
-	 * committed before enabling the MMU
-	 */
-	dsb	ish
-	isb
-
-	/* Set and clear required fields of SCTLR */
-	mrs	x4, sctlr_el2
-	mov_imm	x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
-	orr	x4, x4, x5
-
-	/* Additionally, amend SCTLR fields based on flags */
-	bic	x5, x4, #SCTLR_C_BIT
-	tst	x7, #DISABLE_DCACHE
-	csel	x4, x5, x4, ne
-
-	msr	sctlr_el2, x4
-	isb
-
-	ret
-endfunc enable_mpu_direct_el2

diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
deleted file mode 100644
index b462de0..0000000
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ /dev/null

@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "../xlat_mpu_private.h"
-#include <arch.h>
-#include <arch_features.h>
-#include <lib/cassert.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-#include <fvp_r_arch_helpers.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-#if ENABLE_ASSERTIONS
-/*
- * Return minimum virtual address space size supported by the architecture
- */
-uintptr_t xlat_get_min_virt_addr_space_size(void)
-{
-	uintptr_t ret;
-
-	if (is_feat_ttst_present()) {
-		ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
-	} else {
-		ret = MIN_VIRT_ADDR_SPACE_SIZE;
-	}
-	return ret;
-}
-#endif /* ENABLE_ASSERTIONS*/
-
-bool is_mpu_enabled_ctx(const xlat_ctx_t *ctx)
-{
-	if (ctx->xlat_regime == EL1_EL0_REGIME) {
-		assert(xlat_arch_current_el() >= 1U);
-		return (read_sctlr_el1() & SCTLR_M_BIT) != 0U;
-	} else {
-		assert(xlat_arch_current_el() >= 2U);
-		return (read_sctlr_el2() & SCTLR_M_BIT) != 0U;
-	}
-}
-
-bool is_dcache_enabled(void)
-{
-	unsigned int el = get_current_el();
-
-	if (el == 1U) {
-		return (read_sctlr_el1() & SCTLR_C_BIT) != 0U;
-	} else {  /* must be EL2 */
-		return (read_sctlr_el2() & SCTLR_C_BIT) != 0U;
-	}
-}
-
-unsigned int xlat_arch_current_el(void)
-{
-	unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
-
-	assert(el > 0U);
-
-	return el;
-}
-

diff --git a/lib/xlat_mpu/ro_xlat_mpu.mk b/lib/xlat_mpu/ro_xlat_mpu.mk
deleted file mode 100644
index d3af3bd..0000000
--- a/lib/xlat_mpu/ro_xlat_mpu.mk
+++ /dev/null

@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2021, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${USE_DEBUGFS}, 1)
-    $(error "Debugfs requires functionality from the dynamic translation \
-             library and is incompatible with ALLOW_RO_XLAT_TABLES.")
-endif
-
-ifeq (${ARCH},aarch32)
-    $(error "The xlat_mpu library does not currently support AArch32.")
-endif

diff --git a/lib/xlat_mpu/xlat_mpu.mk b/lib/xlat_mpu/xlat_mpu.mk
deleted file mode 100644
index 31bef04..0000000
--- a/lib/xlat_mpu/xlat_mpu.mk
+++ /dev/null

@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-XLAT_MPU_LIB_V1_SRCS	:=	$(addprefix lib/xlat_mpu/,		\
-				${ARCH}/enable_mpu.S			\
-				${ARCH}/xlat_mpu_arch.c			\
-				xlat_mpu_context.c			\
-				xlat_mpu_core.c				\
-				xlat_mpu_utils.c)
-
-XLAT_MPU_LIB_V1	:=	1
-$(eval $(call add_define,XLAT_MPU_LIB_V1))
-
-ifeq (${ALLOW_XLAT_MPU}, 1)
-    include lib/xlat_mpu_v2/ro_xlat_mpu.mk
-endif

diff --git a/lib/xlat_mpu/xlat_mpu_context.c b/lib/xlat_mpu/xlat_mpu_context.c
deleted file mode 100644
index 783f21d..0000000
--- a/lib/xlat_mpu/xlat_mpu_context.c
+++ /dev/null

@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/debug.h>
-
-#include "lib/xlat_mpu/xlat_mpu.h"
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include "xlat_mpu_private.h"
-
-#include <fvp_r_arch_helpers.h>
-#include <platform_def.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-
-/*
- * MMU configuration register values for the active translation context. Used
- * from the MMU assembly helpers.
- */
-uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
-
-/*
- * Allocate and initialise the default translation context for the BL image
- * currently executing.
- */
-REGISTER_XLAT_CONTEXT(tf, MAX_MMAP_REGIONS, MAX_XLAT_TABLES,
-			PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE);
-
-void mmap_add(const mmap_region_t *mm)
-{
-	mmap_add_ctx(&tf_xlat_ctx, mm);
-}
-
-void __init init_xlat_tables(void)
-{
-	assert(tf_xlat_ctx.xlat_regime == EL_REGIME_INVALID);
-
-	unsigned int current_el = xlat_arch_current_el();
-
-	if (current_el == 1U) {
-		tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME;
-	} else {
-		assert(current_el == 2U);
-		tf_xlat_ctx.xlat_regime = EL2_REGIME;
-	}
-	/* Note:  If EL3 is supported in future v8-R64, add EL3 assignment */
-	init_xlat_tables_ctx(&tf_xlat_ctx);
-}
-
-int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr)
-{
-	return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr);
-}
-
-void enable_mpu_el2(unsigned int flags)
-{
-	/* EL2 is strictly MPU on v8-R64, so no need for setup_mpu_cfg() */
-	enable_mpu_direct_el2(flags);
-}

diff --git a/lib/xlat_mpu/xlat_mpu_core.c b/lib/xlat_mpu/xlat_mpu_core.c
deleted file mode 100644
index 33f381d..0000000
--- a/lib/xlat_mpu/xlat_mpu_core.c
+++ /dev/null

@@ -1,408 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <arch_features.h>
-#include <common/debug.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include "xlat_mpu_private.h"
-
-#include <fvp_r_arch_helpers.h>
-#include <platform_def.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-
-/* Helper function that cleans the data cache only if it is enabled. */
-static inline __attribute__((unused))
-	void xlat_clean_dcache_range(uintptr_t addr, size_t size)
-{
-	if (is_dcache_enabled()) {
-		clean_dcache_range(addr, size);
-	}
-}
-
-
-
-/* Calculate region-attributes byte for PRBAR part of MPU-region descriptor: */
-uint64_t prbar_attr_value(uint32_t attr)
-{
-	uint64_t retValue = UL(0);
-	uint64_t extract;  /* temp var holding bit extracted from attr */
-
-	/* Extract and stuff SH: */
-	extract = (uint64_t) ((attr >> MT_SHAREABILITY_SHIFT)
-				& MT_SHAREABILITY_MASK);
-	retValue |= (extract << PRBAR_SH_SHIFT);
-
-	/* Extract and stuff AP: */
-	extract = (uint64_t) ((attr >> MT_PERM_SHIFT) & MT_PERM_MASK);
-	if (extract == 0U) {
-		retValue |= (UL(2) << PRBAR_AP_SHIFT);
-	} else /* extract == 1 */ {
-		retValue |= (UL(0) << PRBAR_AP_SHIFT);
-	}
-
-	/* Extract and stuff XN: */
-	extract = (uint64_t) ((attr >> MT_EXECUTE_SHIFT) & MT_EXECUTE_MASK);
-	retValue |= (extract << PRBAR_XN_SHIFT);
-	/* However, also don't execute in peripheral space: */
-	extract = (uint64_t) ((attr >> MT_TYPE_SHIFT) & MT_TYPE_MASK);
-	if (extract == 0U) {
-		retValue |= (UL(1) << PRBAR_XN_SHIFT);
-	}
-	return retValue;
-}
-
-/* Calculate region-attributes byte for PRLAR part of MPU-region descriptor: */
-uint64_t prlar_attr_value(uint32_t attr)
-{
-	uint64_t retValue = UL(0);
-	uint64_t extract;  /* temp var holding bit extracted from attr */
-
-	/* Extract and stuff AttrIndx: */
-	extract = (uint64_t) ((attr >> MT_TYPE_SHIFT)
-				& MT_TYPE_MASK);
-	switch (extract) {
-	case UL(0):
-		retValue |= (UL(1) << PRLAR_ATTR_SHIFT);
-		break;
-	case UL(2):
-		/* 0, so OR in nothing */
-		break;
-	case UL(3):
-		retValue |= (UL(2) << PRLAR_ATTR_SHIFT);
-		break;
-	default:
-		retValue |= (extract << PRLAR_ATTR_SHIFT);
-		break;
-	}
-
-	/* Stuff EN: */
-	retValue |= (UL(1) << PRLAR_EN_SHIFT);
-
-	/* Force NS to 0 (Secure);  v8-R64 only supports Secure: */
-	extract = ~(1U << PRLAR_NS_SHIFT);
-	retValue &= extract;
-
-	return retValue;
-}
-
-/*
- * Function that writes an MPU "translation" into the MPU registers. If not
- * possible (e.g., if no more MPU regions available) boot is aborted.
- */
-static void mpu_map_region(mmap_region_t *mm)
-{
-	uint64_t prenr_el2_value = 0UL;
-	uint64_t prbar_attrs = 0UL;
-	uint64_t prlar_attrs = 0UL;
-	int region_to_use = 0;
-
-	/* If all MPU regions in use, then abort boot: */
-	prenr_el2_value = read_prenr_el2();
-	assert(prenr_el2_value != 0xffffffff);
-
-	/* Find and select first-available MPU region (PRENR has an enable bit
-	 * for each MPU region, 1 for in-use or 0 for unused):
-	 */
-	for (region_to_use = 0;  region_to_use < N_MPU_REGIONS;
-	     region_to_use++) {
-		if (((prenr_el2_value >> region_to_use) & 1) == 0) {
-			break;
-		}
-	}
-	write_prselr_el2((uint64_t) (region_to_use));
-	isb();
-
-	/* Set base and limit addresses: */
-	write_prbar_el2(mm->base_pa & PRBAR_PRLAR_ADDR_MASK);
-	write_prlar_el2((mm->base_pa + mm->size - 1UL)
-			& PRBAR_PRLAR_ADDR_MASK);
-	dsbsy();
-	isb();
-
-	/* Set attributes: */
-	prbar_attrs = prbar_attr_value(mm->attr);
-	write_prbar_el2(read_prbar_el2() | prbar_attrs);
-	prlar_attrs = prlar_attr_value(mm->attr);
-	write_prlar_el2(read_prlar_el2() | prlar_attrs);
-	dsbsy();
-	isb();
-
-	/* Mark this MPU region as used: */
-	prenr_el2_value |= (1 << region_to_use);
-	write_prenr_el2(prenr_el2_value);
-	isb();
-}
-
-/*
- * Function that verifies that a region can be mapped.
- * Returns:
- *        0: Success, the mapping is allowed.
- *   EINVAL: Invalid values were used as arguments.
- *   ERANGE: The memory limits were surpassed.
- *   ENOMEM: There is not enough memory in the mmap array.
- *    EPERM: Region overlaps another one in an invalid way.
- */
-static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm)
-{
-	unsigned long long base_pa = mm->base_pa;
-	uintptr_t base_va = mm->base_va;
-	size_t size = mm->size;
-
-	unsigned long long end_pa = base_pa + size - 1U;
-	uintptr_t end_va = base_va + size - 1U;
-
-	if (base_pa != base_va) {
-		return -EINVAL;  /* MPU does not perform address translation */
-	}
-	if ((base_pa % 64ULL) != 0ULL) {
-		return -EINVAL;  /* MPU requires 64-byte alignment */
-	}
-	/* Check for overflows */
-	if ((base_pa > end_pa) || (base_va > end_va)) {
-		return -ERANGE;
-	}
-	if (end_pa > ctx->pa_max_address) {
-		return -ERANGE;
-	}
-	/* Check that there is space in the ctx->mmap array */
-	if (ctx->mmap[ctx->mmap_num - 1].size != 0U) {
-		return -ENOMEM;
-	}
-	/* Check for PAs and VAs overlaps with all other regions */
-	for (const mmap_region_t *mm_cursor = ctx->mmap;
-	     mm_cursor->size != 0U; ++mm_cursor) {
-
-		uintptr_t mm_cursor_end_va =
-			mm_cursor->base_va + mm_cursor->size - 1U;
-
-		/*
-		 * Check if one of the regions is completely inside the other
-		 * one.
-		 */
-		bool fully_overlapped_va =
-			((base_va >= mm_cursor->base_va) &&
-					(end_va <= mm_cursor_end_va)) ||
-			((mm_cursor->base_va >= base_va) &&
-						(mm_cursor_end_va <= end_va));
-
-		/*
-		 * Full VA overlaps are only allowed if both regions are
-		 * identity mapped (zero offset) or have the same VA to PA
-		 * offset. Also, make sure that it's not the exact same area.
-		 * This can only be done with static regions.
-		 */
-		if (fully_overlapped_va) {
-
-#if PLAT_XLAT_TABLES_DYNAMIC
-			if (((mm->attr & MT_DYNAMIC) != 0U) ||
-			    ((mm_cursor->attr & MT_DYNAMIC) != 0U)) {
-				return -EPERM;
-			}
-#endif /* PLAT_XLAT_TABLES_DYNAMIC */
-			if ((mm_cursor->base_va - mm_cursor->base_pa)
-					!= (base_va - base_pa)) {
-				return -EPERM;
-			}
-			if ((base_va == mm_cursor->base_va) &&
-					(size == mm_cursor->size)) {
-				return -EPERM;
-			}
-		} else {
-			/*
-			 * If the regions do not have fully overlapping VAs,
-			 * then they must have fully separated VAs and PAs.
-			 * Partial overlaps are not allowed
-			 */
-
-			unsigned long long mm_cursor_end_pa =
-				     mm_cursor->base_pa + mm_cursor->size - 1U;
-
-			bool separated_pa = (end_pa < mm_cursor->base_pa) ||
-				(base_pa > mm_cursor_end_pa);
-			bool separated_va = (end_va < mm_cursor->base_va) ||
-				(base_va > mm_cursor_end_va);
-
-			if (!separated_va || !separated_pa) {
-				return -EPERM;
-			}
-		}
-	}
-
-	return 0;
-}
-
-void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm)
-{
-	mmap_region_t *mm_cursor = ctx->mmap, *mm_destination;
-	const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num;
-	const mmap_region_t *mm_last;
-	unsigned long long end_pa = mm->base_pa + mm->size - 1U;
-	uintptr_t end_va = mm->base_va + mm->size - 1U;
-	int ret;
-
-	/* Ignore empty regions */
-	if (mm->size == 0U) {
-		return;
-	}
-
-	/* Static regions must be added before initializing the xlat tables. */
-	assert(!ctx->initialized);
-
-	ret = mmap_add_region_check(ctx, mm);
-	if (ret != 0) {
-		ERROR("mmap_add_region_check() failed. error %d\n", ret);
-		assert(false);
-		return;
-	}
-
-	/*
-	 * Find the last entry marker in the mmap
-	 */
-	mm_last = ctx->mmap;
-	while ((mm_last->size != 0U) && (mm_last < mm_end)) {
-		++mm_last;
-	}
-
-	/*
-	 * Check if we have enough space in the memory mapping table.
-	 * This shouldn't happen as we have checked in mmap_add_region_check
-	 * that there is free space.
-	 */
-	assert(mm_last->size == 0U);
-
-	/* Make room for new region by moving other regions up by one place */
-	mm_destination = mm_cursor + 1;
-	(void)memmove(mm_destination, mm_cursor,
-		(uintptr_t)mm_last - (uintptr_t)mm_cursor);
-
-	/*
-	 * Check we haven't lost the empty sentinel from the end of the array.
-	 * This shouldn't happen as we have checked in mmap_add_region_check
-	 * that there is free space.
-	 */
-	assert(mm_end->size == 0U);
-
-	*mm_cursor = *mm;
-
-	if (end_pa > ctx->max_pa) {
-		ctx->max_pa = end_pa;
-	}
-	if (end_va > ctx->max_va) {
-		ctx->max_va = end_va;
-	}
-}
-
-void mmap_add_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm)
-{
-	const mmap_region_t *mm_cursor = mm;
-
-	while (mm_cursor->granularity != 0U) {
-		mmap_add_region_ctx(ctx, mm_cursor);
-		mm_cursor++;
-	}
-}
-
-void __init init_xlat_tables_ctx(xlat_ctx_t *ctx)
-{
-	uint64_t mair = UL(0);
-
-	assert(ctx != NULL);
-	assert(!ctx->initialized);
-	assert((ctx->xlat_regime == EL2_REGIME) ||
-		(ctx->xlat_regime == EL1_EL0_REGIME));
-	/* Note:  Add EL3_REGIME if EL3 is supported in future v8-R64 cores. */
-	assert(!is_mpu_enabled_ctx(ctx));
-
-	mmap_region_t *mm = ctx->mmap;
-
-	assert(ctx->va_max_address >=
-		(xlat_get_min_virt_addr_space_size() - 1U));
-	assert(ctx->va_max_address <= (MAX_VIRT_ADDR_SPACE_SIZE - 1U));
-	assert(IS_POWER_OF_TWO(ctx->va_max_address + 1U));
-
-	xlat_mmap_print(mm);
-
-	/* All tables must be zeroed before mapping any region. */
-
-	for (unsigned int i = 0U; i < ctx->base_table_entries; i++)
-		ctx->base_table[i] = INVALID_DESC;
-
-	/* Also mark all MPU regions as invalid in the MPU hardware itself: */
-	write_prenr_el2(0);
-		/* Sufficient for current, max-32-region implementations. */
-	dsbsy();
-	isb();
-	while (mm->size != 0U) {
-		if (read_prenr_el2() == ALL_MPU_EL2_REGIONS_USED) {
-			ERROR("Not enough MPU regions to map region:\n"
-				" VA:0x%lx  PA:0x%llx  size:0x%zx  attr:0x%x\n",
-				mm->base_va, mm->base_pa, mm->size, mm->attr);
-			panic();
-		} else {
-#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
-			xlat_clean_dcache_range((uintptr_t)mm->base_va,
-				mm->size);
-#endif
-			mpu_map_region(mm);
-		}
-		mm++;
-	}
-
-	ctx->initialized = true;
-
-	xlat_tables_print(ctx);
-
-	/* Set attributes in the right indices of the MAIR */
-	mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
-	mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
-			ATTR_IWBWA_OWBWA_NTR_INDEX);
-	mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE,
-			ATTR_NON_CACHEABLE_INDEX);
-	write_mair_el2(mair);
-	dsbsy();
-	isb();
-}
-
-/*
- * Function to wipe clean and disable all MPU regions.  This function expects
- * that the MPU has already been turned off, and caching concerns addressed,
- * but it nevertheless also explicitly turns off the MPU.
- */
-void clear_all_mpu_regions(void)
-{
-	uint64_t sctlr_el2_value = 0UL;
-	uint64_t region_n = 0UL;
-
-	/*
-	 * MPU should already be disabled, but explicitly disable it
-	 * nevertheless:
-	 */
-	sctlr_el2_value = read_sctlr_el2() & ~(1UL);
-	write_sctlr_el2(sctlr_el2_value);
-
-	/* Disable all regions: */
-	write_prenr_el2(0UL);
-
-	/* Sequence through all regions, zeroing them out and turning off: */
-	for (region_n = 0UL;  region_n < N_MPU_REGIONS;  region_n++) {
-		write_prselr_el2(region_n);
-		isb();
-		write_prbar_el2((uint64_t) 0);
-		write_prlar_el2((uint64_t) 0);
-		dsbsy();
-		isb();
-	}
-}

diff --git a/lib/xlat_mpu/xlat_mpu_private.h b/lib/xlat_mpu/xlat_mpu_private.h
deleted file mode 100644
index 14800e9..0000000
--- a/lib/xlat_mpu/xlat_mpu_private.h
+++ /dev/null

@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef XLAT_MPU_PRIVATE_H
-#define XLAT_MPU_PRIVATE_H
-
-#include <stdbool.h>
-
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-#include <platform_def.h>
-
-#if PLAT_XLAT_TABLES_DYNAMIC
-/*
- * Private shifts and masks to access fields of an mmap attribute
- */
-/* Dynamic or static */
-#define MT_DYN_SHIFT		U(31)
-
-/*
- * Memory mapping private attributes
- *
- * Private attributes not exposed in the public header.
- */
-
-#endif /* PLAT_XLAT_TABLES_DYNAMIC */
-
-/* Calculate region-attributes byte for PRBAR part of MPU-region descriptor: */
-uint64_t prbar_attr_value(uint32_t attr);
-/* Calculate region-attributes byte for PRLAR part of MPU-region descriptor: */
-uint64_t prlar_attr_value(uint32_t attr);
-/* Calculates the attr value for a given PRBAR and PRLAR entry value: */
-uint32_t region_attr(uint64_t prbar_attr, uint64_t prlar_attr);
-
-#define PRBAR_PRLAR_ADDR_MASK	UL(0xffffffffffc0)
-	/* mask for PRBAR & PRLAR MPU-region field */
-/* MPU region attribute bit fields: */
-#define PRBAR_SH_SHIFT		UL(4)
-#define PRBAR_SH_MASK		UL(0x3)
-#define PRBAR_AP_SHIFT		UL(2)
-#define PRBAR_AP_MASK		UL(0x3)
-#define PRBAR_XN_SHIFT		UL(1)
-#define PRBAR_XN_MASK		UL(0x3)
-#define PRLAR_NS_SHIFT		UL(4)
-#define PRLAR_NS_MASK		UL(0x3)
-#define PRBAR_ATTR_SHIFT	UL(0)
-#define PRBAR_ATTR_MASK		UL(0x3f)
-#define PRLAR_ATTR_SHIFT	UL(1)
-#define PRLAR_ATTR_MASK		UL(0x7)
-#define PRLAR_EN_SHIFT		UL(0)
-#define PRLAR_EN_MASK		UL(0x1)
-/* Aspects of the source attributes not defined elsewhere: */
-#define MT_PERM_MASK		UL(0x1)
-#define MT_SEC_MASK		UL(0x1)
-#define MT_EXECUTE_MASK		UL(0x3)
-#define MT_TYPE_SHIFT		UL(0)
-
-extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
-
-/*
- * Return the execute-never mask that will prevent instruction fetch at the
- * given translation regime.
- */
-uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime);
-
-/* Print VA, PA, size and attributes of all regions in the mmap array. */
-void xlat_mmap_print(const mmap_region_t *mmap);
-
-/*
- * Print the current state of the translation tables by reading them from
- * memory.
- */
-void xlat_tables_print(xlat_ctx_t *ctx);
-
-/*
- * Returns a block/page table descriptor for the given level and attributes.
- */
-uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
-		   unsigned long long addr_pa, unsigned int level);
-
-/*
- * Architecture-specific initialization code.
- */
-
-/* Returns the current Exception Level. The returned EL must be 1 or higher. */
-unsigned int xlat_arch_current_el(void);
-
-/*
- * Returns true if the MMU of the translation regime managed by the given
- * xlat_ctx_t is enabled, false otherwise.
- */
-bool is_mpu_enabled_ctx(const xlat_ctx_t *ctx);
-
-/*
- * Returns minimum virtual address space size supported by the architecture
- */
-uintptr_t xlat_get_min_virt_addr_space_size(void);
-
-#endif /* XLAT_MPU_PRIVATE_H */

diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c
deleted file mode 100644
index dc5f956..0000000
--- a/lib/xlat_mpu/xlat_mpu_utils.c
+++ /dev/null

@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-
-#include <common/debug.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include "xlat_mpu_private.h"
-
-#include <fvp_r_arch_helpers.h>
-#include <platform_def.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-
-void xlat_mmap_print(__unused const mmap_region_t *mmap)
-{
-	/* Empty */
-}
-
-#if LOG_LEVEL < LOG_LEVEL_VERBOSE
-
-void xlat_tables_print(__unused xlat_ctx_t *ctx)
-{
-	/* Empty */
-}
-
-#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
-
-static void xlat_tables_print_internal(__unused xlat_ctx_t *ctx)
-{
-	int region_to_use = 0;
-	uintptr_t region_base;
-	size_t region_size;
-	uint64_t prenr_el2_value = 0U;
-
-	/*
-	 * Keep track of how many invalid descriptors are counted in a row.
-	 * Whenever multiple invalid descriptors are found, only the first one
-	 * is printed, and a line is added to inform about how many descriptors
-	 * have been omitted.
-	 */
-
-	/*
-	 * TODO:  Remove this WARN() and comment when these API calls are more
-	 *        completely implemented and tested!
-	 */
-	WARN("%s in this early version of xlat_mpu library may not produce reliable results!",
-	     __func__);
-
-	/*
-	 * Sequence through all regions and print those in-use (PRENR has an
-	 * enable bit for each MPU region, 1 for in-use or 0 for unused):
-	 */
-	prenr_el2_value = read_prenr_el2();
-	for (region_to_use = 0;  region_to_use < N_MPU_REGIONS;
-	     region_to_use++) {
-		if (((prenr_el2_value >> region_to_use) & 1U) == 0U) {
-			continue;
-		}
-		region_base = read_prbar_el2() & PRBAR_PRLAR_ADDR_MASK;
-		region_size = read_prlar_el2() & PRBAR_PRLAR_ADDR_MASK;
-		printf("Address:  0x%llx, size:  0x%llx ",
-			(long long) region_base,
-			(long long) region_size);
-	}
-}
-
-void xlat_tables_print(__unused xlat_ctx_t *ctx)
-{
-	xlat_tables_print_internal(ctx);
-}
-
-#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */

diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index bd7f017..76aba50 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c

@@ -210,17 +210,14 @@
 				desc |= LOWER_ATTRS(ISH);
 			}
 
-			/* Check if Branch Target Identification is enabled */
-#if ENABLE_BTI
 			/* Set GP bit for block and page code entries
 			 * if BTI mechanism is implemented.
 			 */
-			if (is_feat_bti_present() &&
+			if (is_feat_bti_supported() &&
 			   ((attr & (MT_TYPE_MASK | MT_RW |
 				MT_EXECUTE_NEVER)) == MT_CODE)) {
 				desc |= GP;
 			}
-#endif
 		} else {
 			assert(mem_type == MT_NON_CACHEABLE);
 			desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH);

diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 56bfb64..a6fd6be 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -58,11 +58,6 @@
 armv8-5-a-feats         += ${armv8-4-a-feats}
 
 FEAT_LIST               := ${armv8-5-a-feats}
-# Enable Memory tagging, Branch Target Identification for aarch64 only.
-ifeq ($(ARCH), aarch64)
-	mem_tag_arch_support		?= 	yes
-endif #(ARCH=aarch64)
-
 endif
 
 # Enable the features which are mandatory from ARCH version 8.6 and upwards.
@@ -160,6 +155,11 @@
 # direct setting. Use BRANCH_PROTECTION to enable PAUTH.
 ENABLE_PAUTH			?=	0
 
+# FEAT_PAUTH_LR is an optional architectural feature, so this flag must be set
+# manually in addition to the BRANCH_PROTECTION flag which is used for other
+# branch protection and pointer authentication features.
+ENABLE_FEAT_PAUTH_LR		?=	0
+
 # Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
 # must be set to 1 if the platform wants to use this feature in the Secure
 # world. It is not necessary for use in the Non-secure world.
@@ -428,6 +428,9 @@
 # Flag to enable access to Arm v9.3 FEAT_D128 extension
 ENABLE_FEAT_D128			?=	0
 
+# Flag to enable access to GICv5 CPU interface extension (FEAT_GCIE)
+ENABLE_FEAT_GCIE			?=	0
+
 #----
 #9.4
 #----

diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 906e5d7..b9df27e 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk

@@ -156,6 +156,9 @@
 # default, they are for Secure EL1.
 GICV2_G0_FOR_EL3		:= 0
 
+# Generic implementation of a GICvX driver
+USE_GIC_DRIVER			:= 0
+
 # Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
 # by lower ELs.
 HANDLE_EA_EL3_FIRST_NS		:= 0
@@ -343,11 +346,6 @@
 # CTX_INCLUDE_EL2_REGS.
 CTX_INCLUDE_EL2_REGS		:= 0
 
-# Enable Memory tag extension which is supported for architecture greater
-# than Armv8.5-A
-# By default it is set to "no"
-SUPPORT_STACK_MEMTAG		:= no
-
 # Select workaround for AT speculative behaviour.
 ERRATA_SPECULATIVE_AT		:= 0
 
@@ -432,3 +430,14 @@
 
 # Enable RMMD to forward attestation requests from RMM to EL3.
 RMMD_ENABLE_EL3_TOKEN_SIGN	:= 0
+
+# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP).
+# This flag is temporary and it is expected once the interface is
+# finalized, this flag will be removed.
+RMMD_ENABLE_IDE_KEY_PROG	:= 0
+
+# Live firmware activation support
+LFA_SUPPORT			:= 0
+
+# Enable support for arm DSU driver.
+USE_DSU_DRIVER			:= 0

diff --git a/package-lock.json b/package-lock.json
index 57b44de..92921f9 100644
--- a/package-lock.json
+++ b/package-lock.json

@@ -1,12 +1,12 @@
 {
   "name": "trusted-firmware-a",
-  "version": "2.12.0",
+  "version": "2.13.0",
   "lockfileVersion": 3,
   "requires": true,
   "packages": {
     "": {
       "name": "trusted-firmware-a",
-      "version": "2.12.0",
+      "version": "2.13.0",
       "license": "BSD-3-Clause",
       "devDependencies": {
         "@commitlint/cli": "^19.0.0",

diff --git a/package.json b/package.json
index 0908528..6061bf8 100644
--- a/package.json
+++ b/package.json

@@ -1,6 +1,6 @@
 {
   "name": "trusted-firmware-a",
-  "version": "2.12.0",
+  "version": "2.13.0",
   "license": "BSD-3-Clause",
   "type": "module",
   "private": true,

diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
index cab7e46..b47149f 100644
--- a/plat/allwinner/sun50i_h616/sunxi_power.c
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited. All rights reserved.
  * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -49,7 +49,7 @@
 
 int axp_read(uint8_t reg)
 {
-	uint8_t val;
+	uint8_t val = 0;
 	int ret;
 
 	if (is_using_rsb()) {

diff --git a/plat/amd/common/plat_fdt.c b/plat/amd/common/plat_fdt.c
index e72c0dd..194d538 100644
--- a/plat/amd/common/plat_fdt.c
+++ b/plat/amd/common/plat_fdt.c

@@ -10,7 +10,9 @@
 #include <platform_def.h>
 
 #include <plat_fdt.h>
+#ifdef TRANSFER_LIST
 #include <plat_xfer_list.h>
+#endif
 
 #define FIT_CONFS_PATH	"/configurations"
 

diff --git a/plat/amd/common/plat_xfer_list.c b/plat/amd/common/plat_xfer_list.c
index 7af6726..19c882b 100644
--- a/plat/amd/common/plat_xfer_list.c
+++ b/plat/amd/common/plat_xfer_list.c

@@ -45,9 +45,18 @@
 					continue;
 				case SECURE:
 					*bl32 = *ep;
-					if (!transfer_list_set_handoff_args(tl_hdr, ep)) {
+#if defined(SPD_opteed)
+					/*
+					 * Populate the args expected by opteed,
+					 * arg0 - dt address,
+					 * arg1 - Xfer List Convention Version,
+					 * arg3 - Xfer List address
+					 * remaining args are set to 0.
+					 */
+					if (transfer_list_set_handoff_args(tl_hdr, bl32) == NULL) {
 						ERROR("Invalid transfer list\n");
 					}
+#endif /* SPD_opteed */
 					continue;
 				default:
 					ERROR("Unrecognized Image Security State %lu\n",

diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 8d9e05c..9e52f9d 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c

@@ -8,12 +8,12 @@
 
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <def.h>
 #include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
-
-#include <def.h>
+#include <plat_clkfunc.h>
 #include <plat_common.h>
 #include <plat_ipi.h>
 #include <plat_private.h>
@@ -123,7 +123,7 @@
 	uintptr_t crl_base, iou_scntrs_base, psx_base;
 
 	crl_base = CRL;
-	iou_scntrs_base = IOU_SCNTRS;
+	iou_scntrs_base = IOU_SCNTRS_BASE;
 	psx_base = PSX_CRF;
 
 	/* Reset for system timestamp generator in FPX */
@@ -143,13 +143,11 @@
 	mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
 		      IOU_SCNTRS_CONTROL_EN);
 
+	/* set cntfrq_el0 value so that software can discover the frequency of the system counter */
+	set_cnt_freq();
+
 	generic_delay_timer_init();
 
 	/* Configure IPI data */
 	soc_ipi_config_table_init();
 }
-
-uint32_t plat_get_syscnt_freq2(void)
-{
-	return cpu_clock;
-}

diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 3a856cb..28bcaa1 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
  * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
@@ -27,10 +27,14 @@
 #include <plat_fdt.h>
 #include <plat_private.h>
 #include <plat_startup.h>
+#if TRANSFER_LIST
 #include <plat_xfer_list.h>
+#endif
 #include <pm_api_sys.h>
 #include <pm_client.h>
 
+#include <plat_ocm_coherency.h>
+
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
 
@@ -120,9 +124,6 @@
 		cpu_clock = 112203;
 		break;
 	case QEMU:
-		/* Random values now */
-		cpu_clock = 3333333;
-		break;
 	case SILICON:
 		cpu_clock = 100000000;
 		break;
@@ -143,6 +144,10 @@
 
 	setup_console();
 
+	if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) {
+		NOTICE("OCM coherency check not supported\n");
+	}
+
 	NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n",
 		board_name_decode(),
 		(platform_version >> 1), platform_version % 10U,
@@ -178,7 +183,9 @@
 	INFO("CPU Revision = 0x%lx\n", rev_var);
 	INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock);
 	NOTICE("BL31: Executing from 0x%x\n", BL31_BASE);
+#if (defined(SPD_tspd) || defined(SPD_opteed))
 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
+#endif /* SPD_tspd || SPD_opteed */
 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
 
 }

diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index 9bef9d0..3b42b15 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h

@@ -126,8 +126,14 @@
 
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	(1U << 25U)
 
-/* IOU SCNTRS */
-#define IOU_SCNTRS					U(0xEC920000)
+#define FPD_SYSTMR_CTRL_BASE				U(0xEC920000)
+
+/*
+ * Note: There is no IOU_SCNTRS in Versal Gen 2, the equivalent
+ * functionality is provided through FPD_SYSTMR_CTRL. For compatibility
+ * with existing code, maintain the same macro names.
+ */
+#define IOU_SCNTRS_BASE					FPD_SYSTMR_CTRL_BASE
 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET	U(0)
 #define IOU_SCNTRS_BASE_FREQ_OFFSET			U(0x20)
 

diff --git a/plat/amd/versal2/include/plat_ipi.h b/plat/amd/versal2/include/plat_ipi.h
index 503ec1f..c110fb8 100644
--- a/plat/amd/versal2/include/plat_ipi.h
+++ b/plat/amd/versal2/include/plat_ipi.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,7 @@
 #define PLAT_IPI_H
 
 #include <stdint.h>
+#include <lib/utils_def.h>
 
 #include <ipi.h>
 
@@ -24,7 +25,15 @@
 #define IPI_ID_3	5U
 #define IPI_ID_4	6U
 #define IPI_ID_5	7U
-#define IPI_ID_MAX	8U
+#define IPI_ID_PMC_NOBUF	8U
+#define IPI_ID_6_NOBUF_95	9U
+#define IPI_ID_1_NOBUF	10U
+#define IPI_ID_2_NOBUF	11U
+#define IPI_ID_3_NOBUF	12U
+#define IPI_ID_4_NOBUF	13U
+#define IPI_ID_5_NOBUF	14U
+#define IPI_ID_6_NOBUF_101	15U
+#define IPI_ID_MAX	16U
 
 /*********************************************************************
  * IPI message buffers
@@ -56,17 +65,34 @@
  * IPI registers and bitfields
  ******************************************************************************/
 #define IPI0_REG_BASE		(0xEB330000U)
-#define IPI0_TRIG_BIT		(1 << 2)
-#define PMC_IPI_TRIG_BIT	(1 << 1)
+#define IPI0_TRIG_BIT		BIT_32(2)
+#define PMC_IPI_TRIG_BIT	BIT_32(1)
 #define IPI1_REG_BASE		(0xEB340000U)
-#define IPI1_TRIG_BIT		(1 << 3)
+#define IPI1_TRIG_BIT		BIT_32(3)
 #define IPI2_REG_BASE		(0xEB350000U)
-#define IPI2_TRIG_BIT		(1 << 4)
+#define IPI2_TRIG_BIT		BIT_32(4)
 #define IPI3_REG_BASE		(0xEB360000U)
-#define IPI3_TRIG_BIT		(1 << 5)
+#define IPI3_TRIG_BIT		BIT_32(5)
 #define IPI4_REG_BASE		(0xEB370000U)
-#define IPI4_TRIG_BIT		(1 << 6)
+#define IPI4_TRIG_BIT		BIT_32(6)
 #define IPI5_REG_BASE		(0xEB380000U)
-#define IPI5_TRIG_BIT		(1 << 7)
+#define IPI5_TRIG_BIT		BIT_32(7)
+
+#define PMC_NOBUF_REG_BASE	(0xEB390000U)
+#define PMC_NOBUF_TRIG_BIT	BIT_32(8)
+#define IPI6_NOBUF_95_REG_BASE	(0xEB3A0000U)
+#define IPI6_NOBUF_95_TRIG_BIT	BIT_32(9)
+#define IPI1_NOBUF_REG_BASE	(0xEB3B0000U)
+#define IPI1_NOBUF_TRIG_BIT	BIT_32(10)
+#define IPI2_NOBUF_REG_BASE	(0xEB3B1000U)
+#define IPI2_NOBUF_TRIG_BIT	BIT_32(11)
+#define IPI3_NOBUF_REG_BASE	(0xEB3B2000U)
+#define IPI3_NOBUF_TRIG_BIT	BIT_32(12)
+#define IPI4_NOBUF_REG_BASE	(0xEB3B3000U)
+#define IPI4_NOBUF_TRIG_BIT	BIT_32(13)
+#define IPI5_NOBUF_REG_BASE	(0xEB3B4000U)
+#define IPI5_NOBUF_TRIG_BIT	BIT_32(14)
+#define IPI6_NOBUF_101_REG_BASE	(0xEB3B5000U)
+#define IPI6_NOBUF_101_TRIG_BIT	BIT_32(15)
 
 #endif /* PLAT_IPI_H */

diff --git a/plat/amd/versal2/include/plat_ocm_coherency.h b/plat/amd/versal2/include/plat_ocm_coherency.h
new file mode 100644
index 0000000..b88c2eb
--- /dev/null
+++ b/plat/amd/versal2/include/plat_ocm_coherency.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_OCM_COHERENCY_H
+#define PLAT_OCM_COHERENCY_H
+
+#define COHERENCY_CHECK_NOT_SUPPORTED	-1
+
+#if (DEBUG == 1)
+int32_t check_ocm_coherency(void);
+#else
+static inline int32_t check_ocm_coherency(void)
+{
+	return COHERENCY_CHECK_NOT_SUPPORTED;
+}
+#endif
+
+#endif/*PLAT_OCM_COHERENCY_H*/

diff --git a/plat/amd/versal2/plat_ocm_coherency.c b/plat/amd/versal2/plat_ocm_coherency.c
new file mode 100644
index 0000000..872ee23
--- /dev/null
+++ b/plat/amd/versal2/plat_ocm_coherency.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <plat_ocm_coherency.h>
+#include <platform_def.h>
+
+/*
+ * Register non hash mem regions addresses
+ */
+#define POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12    U(0xF8168000)
+#define NON_HASH_MEM_REGION_REG0        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC08)
+#define NON_HASH_MEM_REGION_REG1        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC0C)
+#define NON_HASH_MEM_REGION_REG2        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC10)
+#define NON_HASH_MEM_REGION_REG3        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC14)
+#define NON_HASH_MEM_REGION_REG4        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC18)
+#define NON_HASH_MEM_REGION_REG5        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC1C)
+#define NON_HASH_MEM_REGION_REG6        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC20)
+#define NON_HASH_MEM_REGION_REG7        U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC24)
+
+#define REGION_BASE_ADDR_VALUE	U(0x2E)
+#define REGION_BASE_ADDR_SHIFT	9
+
+#define REGION_BASE_ADDRESS_MASK	GENMASK(30, REGION_BASE_ADDR_SHIFT)
+#define REGION_VALID_BIT		BIT(0)
+
+/*
+ * verify the register configured as non-hashed
+ */
+#define IS_NON_HASHED_REGION(reg) \
+((FIELD_GET(REGION_BASE_ADDRESS_MASK, mmio_read_32(reg)) == REGION_BASE_ADDR_VALUE) && \
+						(mmio_read_32(reg) & REGION_VALID_BIT))
+
+/*
+ * Splitter registers
+ */
+#define FPX_SPLITTER_0          U(0xECC20000)
+#define FPX_SPLITTER_1          U(0xECD20000)
+#define FPX_SPLITTER_2          U(0xECE20000)
+#define FPX_SPLITTER_3          U(0xECF20000)
+#define OCM_ADDR_DIST_MODE      BIT(16)
+
+#define OCM_COHERENT	0
+#define OCM_NOT_COHERENT	1
+#define TFA_NOT_IN_OCM	2
+
+/*
+ * Function that verifies the OCM is coherent or not with the following checks:
+ * verify that OCM is in non hashed region or not if not then verify
+ * OCM_ADDR_DIST_MODE bit in splitter registers is set.
+ */
+int32_t check_ocm_coherency(void)
+{
+	int32_t status = OCM_COHERENT;
+	/* isolation should be disabled in order to read these registers */
+	if ((IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG0) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG1) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG2) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG3) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG4) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG5) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG6) ||
+	     IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG7))) {
+		WARN("OCM is not configured as coherent\n");
+		status = OCM_NOT_COHERENT;
+	} else {
+		/* verify OCM_ADDR_DIST_MODE bit in splitter registers is set */
+		if (!((mmio_read_32(FPX_SPLITTER_0) & OCM_ADDR_DIST_MODE) &&
+		      (mmio_read_32(FPX_SPLITTER_1) & OCM_ADDR_DIST_MODE) &&
+		      (mmio_read_32(FPX_SPLITTER_2) & OCM_ADDR_DIST_MODE) &&
+		      (mmio_read_32(FPX_SPLITTER_3) & OCM_ADDR_DIST_MODE))) {
+			WARN("OCM is not configured as coherent\n");
+			status = OCM_NOT_COHERENT;
+		}
+	}
+	return status;
+}
+

diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
index d53d751..cded1f3 100644
--- a/plat/amd/versal2/plat_psci.c
+++ b/plat/amd/versal2/plat_psci.c

@@ -19,7 +19,6 @@
 #include <plat_private.h>
 #include <pm_defs.h>
 
-#define PM_RET_ERROR_NOFEATURE U(19)
 #define ALWAYSTRUE true
 #define LINEAR_MODE BIT(1)
 
@@ -192,7 +191,7 @@
 	case IOCTL_USB_SET_STATE:
 		break;
 	default:
-		ret = PM_RET_ERROR_NOFEATURE;
+		ret = PM_RET_ERROR_IOCTL_NOT_SUPPORTED;
 		break;
 	}
 

diff --git a/plat/amd/versal2/plat_psci_pm.c b/plat/amd/versal2/plat_psci_pm.c
index 50614d5..3cc6b95 100644
--- a/plat/amd/versal2/plat_psci_pm.c
+++ b/plat/amd/versal2/plat_psci_pm.c

@@ -110,7 +110,7 @@
 	 * Send the system reset request to the firmware if power down request
 	 * is not received from firmware.
 	 */
-	if (pwrdwn_req_received == true) {
+	if (pwrdwn_req_received == false) {
 		/*
 		 * TODO: shutdown scope for this reset needs be revised once
 		 * we have a clearer understanding of the overall reset scoping

diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 7cd864e..475e8ff 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk

@@ -116,6 +116,7 @@
 				drivers/delay_timer/generic_delay_timer.c	\
 				${GICV3_SOURCES}				\
 				drivers/arm/pl011/aarch64/pl011_console.S	\
+				plat/xilinx/common/plat_clkfunc.c		\
 				plat/common/aarch64/crash_console_helpers.S	\
 				plat/arm/common/arm_common.c			\
 				plat/common/plat_gicv3.c			\
@@ -160,6 +161,11 @@
 				${PLAT_PATH}/sip_svc_setup.c			\
 				${PLAT_PATH}/gicv3.c
 
+
+ifeq ($(DEBUG),1)
+BL31_SOURCES            +=      ${PLAT_PATH}/plat_ocm_coherency.c
+endif
+
 ifeq (${ERRATA_ABI_SUPPORT}, 1)
 # enable the cpu macros for errata abi interface
 CORTEX_A78_AE_H_INC     := 1

diff --git a/plat/amd/versal2/pm_service/pm_client.c b/plat/amd/versal2/pm_service/pm_client.c
index 8d6b9b1..67099a6 100644
--- a/plat/amd/versal2/pm_service/pm_client.c
+++ b/plat/amd/versal2/pm_service/pm_client.c

@@ -336,6 +336,23 @@
 	uintptr_t val;
 
 	if (cpuid != (uint32_t) UNDEFINED_CPUID) {
+		/*
+		 * Get the core index and use it to calculate offset for
+		 * disabling power down and wakeup interrupts.
+		 * i.e., Convert cpu-id to core_index with the following mapping:
+		 *  cpu-id -> core_index
+		 *       0 -> 0
+		 *       1 -> 1
+		 *       2 -> 4
+		 *       3 -> 5
+		 *       4 -> 8
+		 *       5 -> 9
+		 *       6 -> 12
+		 *       7 -> 13
+		 * to match with register database.
+		 */
+		uint32_t core_index = cpuid + ((cpuid / 2U) * 2U);
+
 		pm_client_lock_get();
 
 		/* Clear powerdown request */
@@ -346,10 +363,10 @@
 		isb();
 
 		/* Disabled power down interrupt */
-		mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+		mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(core_index),
 			      APU_PCIL_CORE_X_IDS_POWER_MASK);
 		/* Disable wake interrupt */
-		mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+		mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(core_index),
 			      APU_PCIL_CORE_X_IDS_WAKE_MASK);
 
 		pm_client_lock_release();

diff --git a/plat/amd/versal2/pm_service/pm_svc_main.c b/plat/amd/versal2/pm_service/pm_svc_main.c
index 88848e2..55fd963 100644
--- a/plat/amd/versal2/pm_service/pm_svc_main.c
+++ b/plat/amd/versal2/pm_service/pm_svc_main.c

@@ -133,7 +133,7 @@
 
 	/* Check status register for each IPI except PMC */
 	for (i = IPI_ID_APU; i <= IPI_ID_5; i++) {
-		ipi_status = (uint32_t)ipi_mb_enquire_status(IPI_ID_APU, i);
+		ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
 
 		/* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
 		if ((ipi_status & (uint32_t)IPI_MB_STATUS_RECV_PENDING) > (uint32_t) 0) {
@@ -143,8 +143,8 @@
 	}
 
 	/* If PMC has not generated interrupt then end ISR */
-	ipi_status = (uint32_t)ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
-	if ((ipi_status & (uint32_t) IPI_MB_STATUS_RECV_PENDING) == (uint32_t) 0) {
+	ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
+	if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == (uint32_t)0) {
 		plat_ic_end_of_interrupt(id);
 		goto end;
 	}
@@ -163,7 +163,8 @@
 		break;
 	case PM_NOTIFY_CB:
 		if (sgi != INVALID_SGI) {
-			if (payload[2] == EVENT_CPU_PWRDWN) {
+			if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			    (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 				if (pwrdwn_req_received) {
 					pwrdwn_req_received = false;
 					request_cpu_pwrdwn();
@@ -182,7 +183,8 @@
 				 */
 			}
 			notify_os();
-		} else if (payload[2] == EVENT_CPU_PWRDWN) {
+		} else if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			  (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 			request_cpu_pwrdwn();
 			(void)psci_cpu_off();
 		} else {

diff --git a/plat/amd/versal2/soc_ipi.c b/plat/amd/versal2/soc_ipi.c
index 85d1bcd..24ff969 100644
--- a/plat/amd/versal2/soc_ipi.c
+++ b/plat/amd/versal2/soc_ipi.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,6 @@
  * SoC IPI agent registers access management
  */
 
-#include <lib/utils_def.h>
 #include <plat_ipi.h>
 
 /* versal2 ipi configuration table */
@@ -62,6 +61,62 @@
 		.ipi_reg_base = IPI5_REG_BASE,
 		.secure_only = 0,
 	},
+
+	/* PMC_NOBUF IPI */
+	[IPI_ID_PMC_NOBUF] = {
+		.ipi_bit_mask = PMC_NOBUF_TRIG_BIT,
+		.ipi_reg_base = PMC_NOBUF_REG_BASE,
+		.secure_only = IPI_SECURE_MASK,
+	},
+
+	/* IPI6 IPI */
+	[IPI_ID_6_NOBUF_95] = {
+		.ipi_bit_mask = IPI6_NOBUF_95_TRIG_BIT,
+		.ipi_reg_base = IPI6_NOBUF_95_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI1 NO BUF IPI */
+	[IPI_ID_1_NOBUF] = {
+		.ipi_bit_mask = IPI1_NOBUF_TRIG_BIT,
+		.ipi_reg_base = IPI1_NOBUF_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI2 NO BUF IPI */
+	[IPI_ID_2_NOBUF] = {
+		.ipi_bit_mask = IPI2_NOBUF_TRIG_BIT,
+		.ipi_reg_base = IPI2_NOBUF_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI3 NO BUF IPI */
+	[IPI_ID_3_NOBUF] = {
+		.ipi_bit_mask = IPI3_NOBUF_TRIG_BIT,
+		.ipi_reg_base = IPI3_NOBUF_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI4 NO BUF IPI */
+	[IPI_ID_4_NOBUF] = {
+		.ipi_bit_mask = IPI4_NOBUF_TRIG_BIT,
+		.ipi_reg_base = IPI4_NOBUF_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI5 NO BUF IPI */
+	[IPI_ID_5_NOBUF] = {
+		.ipi_bit_mask = IPI5_NOBUF_TRIG_BIT,
+		.ipi_reg_base = IPI5_NOBUF_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI6 NO BUF IPI */
+	[IPI_ID_6_NOBUF_101] = {
+		.ipi_bit_mask = IPI6_NOBUF_101_TRIG_BIT,
+		.ipi_reg_base = IPI6_NOBUF_101_REG_BASE,
+		.secure_only = 0,
+	},
 };
 
 /**

diff --git a/plat/arm/board/a5ds/a5ds_bl2_setup.c b/plat/arm/board/a5ds/a5ds_bl2_setup.c
index a0aa639..3e26188 100644
--- a/plat/arm/board/a5ds/a5ds_bl2_setup.c
+++ b/plat/arm/board/a5ds/a5ds_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,7 @@
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 	u_register_t arg2, u_register_t arg3)
 {
-	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+	arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
 }
 
 void bl2_platform_setup(void)

diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 6d60cbe..32e089d 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk

@@ -19,12 +19,7 @@
 
 DYN_CFG_SOURCES		+=	${FDT_WRAPPERS_SOURCES}
 
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-A5DS_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER		:=	2
 
 A5DS_SECURITY_SOURCES	:=	plat/arm/board/a5ds/a5ds_security.c
 

diff --git a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
index a951dc7..1b8699a 100644
--- a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
+++ b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,7 +11,7 @@
 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
-	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* enable snoop control unit */
 	enable_snoop_ctrl_unit(A5DS_SCU_BASE);

diff --git a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
index 4b0c97d..c3ce916 100644
--- a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
+++ b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,5 +18,4 @@
 			plat/common/aarch32/platform_mp_stack.S		\
 			plat/common/plat_psci_common.c			\
 			${A5DS_CPU_LIBS}				\
-			${A5DS_GIC_SOURCES}				\
 			${A5DS_SECURITY_SOURCES}

diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
index 12b1e8c..98242e6 100644
--- a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk

@@ -28,7 +28,8 @@
 ENABLE_FEAT_ECV				:=	1
 ENABLE_FEAT_FGT				:=	1
 ENABLE_FEAT_MTE2			:=	1
-ENABLE_MPAM_FOR_LOWER_ELS		:=	1
+ENABLE_FEAT_MPAM			:=	1
+USE_GIC_DRIVER				:=	3
 GIC_ENABLE_V4_EXTN			:=	1
 GICV3_SUPPORT_GIC600			:=	1
 HW_ASSISTED_COHERENCY			:=	1
@@ -40,11 +41,6 @@
 
 RD1AE_CPU_SOURCES	:=	lib/cpus/aarch64/neoverse_v3.S
 
-include drivers/arm/gic/v3/gicv3.mk
-RD1AE_GIC_SOURCES	:=	${GICV3_SOURCES}	\
-				plat/common/plat_gicv3.c	\
-				plat/arm/common/arm_gicv3.c
-
 PLAT_BL_COMMON_SOURCES	+=	${RD1AE_BASE}/rd1ae_plat.c	\
 				${RD1AE_BASE}/include/rd1ae_helpers.S
 
@@ -56,7 +52,6 @@
 			drivers/arm/sbsa/sbsa.c
 
 BL31_SOURCES	+=	${RD1AE_CPU_SOURCES}	\
-			${RD1AE_GIC_SOURCES}	\
 			${RD1AE_BASE}/rd1ae_bl31_setup.c	\
 			${RD1AE_BASE}/rd1ae_topology.c	\
 			drivers/cfi/v2m/v2m_flash.c	\

diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 3a6637f..f350957 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk

@@ -13,14 +13,14 @@
 
 ifneq (${TRUSTED_BOARD_BOOT},0)
 ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_dev_rotpk.S
-ARM_ROTPK = $(BUILD_PLAT)/arm_rotpk.bin
 ARM_ROTPK_IS_HASH := 1
-$(eval $(call add_define_val,ARM_ROTPK,'"$(ARM_ROTPK)"'))
 
 # ROTPK hash location
 ifeq (${ARM_ROTPK_LOCATION}, regs)
 	ARM_ROTPK_LOCATION_ID = ARM_ROTPK_REGS_ID
 else
+ARM_ROTPK = $(BUILD_PLAT)/arm_rotpk.bin
+$(eval $(call add_define_val,ARM_ROTPK,'"$(ARM_ROTPK)"'))
 # The ROTPK is a development key
 ifeq (${ARM_ROTPK_LOCATION}, devel_rsa)
 	CRYPTO_ALG=rsa

diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index 5264187..ac80887 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -65,7 +65,6 @@
 void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
 	(void)target_state;
-	plat_arm_gic_init();
 }
 #endif
 

diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
index dfde5aa..65be9c1 100644
--- a/plat/arm/board/corstone1000/platform.mk
+++ b/plat/arm/board/corstone1000/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2024 Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -43,13 +43,7 @@
 endif
 endif
 
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-CORSTONE1000_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
-
+USE_GIC_DRIVER			:=	2
 
 BL2_SOURCES		+=	plat/arm/board/corstone1000/common/corstone1000_security.c		\
 				plat/arm/board/corstone1000/common/corstone1000_err.c		\
@@ -70,8 +64,7 @@
 			plat/arm/board/corstone1000/common/corstone1000_plat.c		\
 			plat/arm/board/corstone1000/common/corstone1000_pm.c		\
 			plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c	\
-			${CORSTONE1000_CPU_LIBS}					\
-			${CORSTONE1000_GIC_SOURCES}
+			${CORSTONE1000_CPU_LIBS}
 
 ifneq (${ENABLE_STACK_PROTECTOR},0)
 	ifneq (${ENABLE_STACK_PROTECTOR},none)

diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk
index d6d3bef..b76ef20 100644
--- a/plat/arm/board/corstone700/platform.mk
+++ b/plat/arm/board/corstone700/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -29,12 +29,7 @@
     $(error Variable AARCH32_SP has to be set for AArch32)
 endif
 
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-CORSTONE700_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER		:=	2
 
 # BL1/BL2 Image not a part of the capsule Image for Corstone700
 override NEED_BL1	:=	no

diff --git a/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
index 2fc0e0d..221e132 100644
--- a/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
+++ b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,5 +9,5 @@
 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
-	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
 }

diff --git a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
index 75dc0f1..3e282cd 100644
--- a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
+++ b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,8 +12,7 @@
 			plat/arm/board/corstone700/common/corstone700_security.c	\
 			plat/arm/board/corstone700/common/corstone700_plat.c		\
 			plat/arm/board/corstone700/common/corstone700_pm.c		\
-			plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c	\
-			${CORSTONE700_GIC_SOURCES}
+			plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
 
 ifneq (${ENABLE_STACK_PROTECTOR},0)
 	ifneq (${ENABLE_STACK_PROTECTOR},none)

diff --git a/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
new file mode 100644
index 0000000..7cb88ed
--- /dev/null
+++ b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <drivers/arm/gicv3.h>
+
+#include <fconf_hw_config_getter.h>
+
+struct gicv3_config_t gicv3_config;
+
+int fconf_populate_gicv3_config(uintptr_t config)
+{
+	int err;
+	int node;
+	uintptr_t addr;
+
+	/* Necessary to work with libfdt APIs */
+	const void *hw_config_dtb = (const void *)config;
+
+	/*
+	 * Find the offset of the node containing "arm,gic-v3" compatible property.
+	 * Populating fconf strucutures dynamically is not supported for legacy
+	 * systems which use GICv2 IP. Simply skip extracting GIC properties.
+	 */
+	node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
+	if (node < 0) {
+		WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
+		return 0;
+	}
+	/* The GICv3 DT binding holds at least two address/size pairs,
+	 * the first describing the distributor, the second the redistributors.
+	 * See: bindings/interrupt-controller/arm,gic-v3.yaml
+	 */
+	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
+	if (err < 0) {
+		ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
+		return err;
+	}
+	gicv3_config.gicd_base = addr;
+
+	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
+	if (err < 0) {
+		ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
+	} else {
+		gicv3_config.gicr_base = addr;
+	}
+
+	return err;
+}
+FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);

diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index 662b8a4..abc78ce 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c

@@ -14,7 +14,6 @@
 #include <libfdt.h>
 #include <plat/common/platform.h>
 
-struct gicv3_config_t gicv3_config;
 struct hw_topology_t soc_topology;
 struct uart_serial_config_t uart_serial_config;
 struct cpu_timer_t cpu_timer;
@@ -32,45 +31,6 @@
 
 #define ILLEGAL_ADDR	ULL(~0)
 
-int fconf_populate_gicv3_config(uintptr_t config)
-{
-	int err;
-	int node;
-	uintptr_t addr;
-
-	/* Necessary to work with libfdt APIs */
-	const void *hw_config_dtb = (const void *)config;
-
-	/*
-	 * Find the offset of the node containing "arm,gic-v3" compatible property.
-	 * Populating fconf strucutures dynamically is not supported for legacy
-	 * systems which use GICv2 IP. Simply skip extracting GIC properties.
-	 */
-	node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
-	if (node < 0) {
-		WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
-		return 0;
-	}
-	/* The GICv3 DT binding holds at least two address/size pairs,
-	 * the first describing the distributor, the second the redistributors.
-	 * See: bindings/interrupt-controller/arm,gic-v3.yaml
-	 */
-	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
-	if (err < 0) {
-		ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
-		return err;
-	}
-	gicv3_config.gicd_base = addr;
-
-	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
-	if (err < 0) {
-		ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
-	} else {
-		gicv3_config.gicr_base = addr;
-	}
-
-	return err;
-}
 
 int fconf_populate_topology(uintptr_t config)
 {
@@ -84,8 +44,12 @@
 	/* Find the offset of the node containing "arm,psci-1.0" compatible property */
 	node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-1.0");
 	if (node < 0) {
-		ERROR("FCONF: Unable to locate node with arm,psci-1.0 compatible property\n");
-		return node;
+		/* Fall back to 0.2 */
+		node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-0.2");
+		if (node < 0) {
+			ERROR("FCONF: Unable to locate node with arm,psci compatible property\n");
+			return node;
+		}
 	}
 
 	err = fdt_read_uint32(hw_config_dtb, node, "max-pwr-lvl", &max_pwr_lvl);
@@ -343,7 +307,7 @@
 	for (unsigned long i = 0UL; i < dram_layout.num_banks; i++) {
 		int err = fdt_get_reg_props_by_index(
 				hw_config_dtb, node, (int)i,
-				&dram_layout.dram_bank[i].base,
+				(uintptr_t *)&dram_layout.dram_bank[i].base,
 				(size_t *)&dram_layout.dram_bank[i].size);
 		if (err < 0) {
 			ERROR("FCONF: Failed to read 'reg' property #%lu of 'memory' node\n", i);
@@ -443,7 +407,6 @@
 	return 0;
 }
 
-FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
 FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
 FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
 FCONF_REGISTER_POPULATOR(HW_CONFIG, cpu_timer, fconf_populate_cpu_timer);

diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index a11c1de..fd6cf78 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts

@@ -27,7 +27,7 @@
 			load-address = <0x0 0x07f00000>;
 			max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
 			id = <HW_CONFIG_ID>;
-			secondary-load-address = <0x0 0x82000000>;
+			secondary-load-address = <0x0 FVP_HW_CONFIG_ADDR>;
 		};
 
 		/*

diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
index f14dbff..d6b6863 100644
--- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,11 +8,16 @@
 
 #include <drivers/measured_boot/event_log/event_log.h>
 #include <drivers/measured_boot/metadata.h>
-#include <plat/arm/common/plat_arm.h>
 #include <tools_share/zero_oid.h>
 
+#include <plat/arm/common/plat_arm.h>
+
 /* Event Log data */
+#if TRANSFER_LIST
+static uint8_t *event_log;
+#else
 static uint8_t event_log[PLAT_ARM_EVENT_LOG_MAX_SIZE];
+#endif
 
 /* FVP table with platform specific image IDs, names and PCRs */
 const event_log_metadata_t fvp_event_log_metadata[] = {
@@ -20,29 +25,60 @@
 	{ TB_FW_CONFIG_ID, MBOOT_TB_FW_CONFIG_STRING, PCR_0 },
 	{ BL2_IMAGE_ID, MBOOT_BL2_IMAGE_STRING, PCR_0 },
 
-	{ EVLOG_INVALID_ID, NULL, (unsigned int)(-1) }	/* Terminator */
+	{ EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
 };
 
 void bl1_plat_mboot_init(void)
 {
-	event_log_init(event_log, event_log + sizeof(event_log));
-	event_log_write_header();
+	size_t event_log_max_size;
+	int rc;
+
+#if TRANSFER_LIST
+	event_log = transfer_list_event_log_extend(
+		secure_tl, PLAT_ARM_EVENT_LOG_MAX_SIZE,
+		&event_log_max_size);
+	assert(event_log != NULL);
+#else
+	event_log_max_size = sizeof(event_log);
+#endif
+
+	rc = event_log_init(event_log, event_log + event_log_max_size);
+	if (rc < 0) {
+		ERROR("Failed to initialize event log (%d).\n", rc);
+		panic();
+	}
+
+	rc = event_log_write_header();
+	if (rc < 0) {
+		ERROR("Failed to write event log header (%d).\n", rc);
+		panic();
+	}
 }
 
 void bl1_plat_mboot_finish(void)
 {
-	size_t event_log_cur_size;
+	size_t event_log_cur_size = event_log_get_cur_size(event_log);
 
-	event_log_cur_size = event_log_get_cur_size(event_log);
-	int rc = arm_set_tb_fw_info((uintptr_t)event_log,
-				    event_log_cur_size,
-				    PLAT_ARM_EVENT_LOG_MAX_SIZE);
-	if (rc != 0) {
-		/*
-		 * It is a fatal error because on FVP platform, BL2 software
-		 * assumes that a valid Event Log buffer exist and it will use
-		 * same Event Log buffer to append image measurements.
-		 */
-		panic();
+#if TRANSFER_LIST
+	uint8_t *rc = transfer_list_event_log_finish(
+		secure_tl, (uintptr_t)event_log + event_log_cur_size);
+
+	if (rc != NULL) {
+		return;
 	}
+#else
+	int rc = arm_set_tb_fw_info((uintptr_t)event_log, event_log_cur_size,
+				PLAT_ARM_EVENT_LOG_MAX_SIZE);
+	if (rc == 0) {
+		return;
+	}
+#endif
+
+	/*
+	 * Panic if we fail to set up the event log for the next stage. This is a fatal
+	 * error because, on the FVP platform, BL2 software assumes that a valid
+	 * Event Log buffer exists and will use the same Event Log buffer to append image
+	 * measurements.
+	 */
+	panic();
 }

diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 8bf7dad..1fae0cf 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,7 +19,7 @@
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/common_def.h>
 
-#if defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)
+#if !TRANSFER_LIST && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
 CASSERT(ARM_EVENT_LOG_DRAM1_SIZE >= PLAT_ARM_EVENT_LOG_MAX_SIZE, \
 	assert_res_eventlog_mem_insufficient);
 #endif /* defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd) */
@@ -61,10 +61,17 @@
 {
 	uint8_t *event_log_start;
 	uint8_t *event_log_finish;
-	size_t bl1_event_log_size;
-	size_t event_log_max_size;
-	int rc;
+	size_t bl1_event_log_size __unused;
+	size_t event_log_max_size __unused;
+	int rc __unused;
 
+#if TRANSFER_LIST
+	event_log_start = transfer_list_event_log_extend(
+		secure_tl, PLAT_ARM_EVENT_LOG_MAX_SIZE, &event_log_max_size);
+	event_log_finish = event_log_start + event_log_max_size;
+
+	event_log_base = (uintptr_t)event_log_start;
+#else
 	rc = arm_get_tb_fw_info(&event_log_base, &bl1_event_log_size,
 				&event_log_max_size);
 	if (rc != 0) {
@@ -82,10 +89,11 @@
 	 * BL1 and BL2 share the same Event Log buffer and that BL2 will
 	 * append its measurements after BL1's
 	 */
-	event_log_start = (uint8_t *)((uintptr_t)event_log_base +
-				      bl1_event_log_size);
-	event_log_finish = (uint8_t *)((uintptr_t)event_log_base +
-				       event_log_max_size);
+	event_log_start =
+		(uint8_t *)((uintptr_t)event_log_base + bl1_event_log_size);
+	event_log_finish =
+		(uint8_t *)((uintptr_t)event_log_base + event_log_max_size);
+#endif
 
 	event_log_init((uint8_t *)event_log_start, event_log_finish);
 }
@@ -160,7 +168,7 @@
 	int rc;
 
 	/* Event Log address in Non-Secure memory */
-	uintptr_t ns_log_addr;
+	uintptr_t ns_log_addr __unused;
 
 	/* Event Log filled size */
 	size_t event_log_cur_size;
@@ -172,6 +180,15 @@
 
 	event_log_cur_size = event_log_get_cur_size((uint8_t *)event_log_base);
 
+#if TRANSFER_LIST
+	/*
+	 * Re-size the event log for the next stage and update the size to include
+	 * the entire event log (i.e., not just what this stage has added.)
+	 */
+	event_log_base = (uintptr_t)transfer_list_event_log_finish(
+		secure_tl, (uintptr_t)event_log_base + event_log_cur_size);
+	event_log_cur_size = event_log_get_cur_size((uint8_t *)event_log_base);
+#else
 #if defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)
 	/* Copy Event Log to TZC secured DRAM memory */
 	(void)memcpy((void *)ARM_EVENT_LOG_DRAM1_BASE,
@@ -217,6 +234,7 @@
 		panic();
 	}
 #endif /* defined(SPD_tspd) || defined(SPD_spmd) */
+#endif /* TRANSFER_LIST */
 
-	dump_event_log((uint8_t *)event_log_base, event_log_cur_size);
+	event_log_dump((uint8_t *)event_log_base, event_log_cur_size);
 }

diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 90d9608..989f058 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c

@@ -52,10 +52,7 @@
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
 {
-#if TRANSFER_LIST
-	arg0 = arg3;
-#endif
-	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+	arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Initialize the platform config for future decision making */
 	fvp_config_setup();

diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index e087565..d75abb4 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,10 +28,7 @@
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();
 
-#if TRANSFER_LIST
-	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
-#else
-#if !RESET_TO_BL31 && !RESET_TO_BL2
+#if !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2)
 	const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
 
 	INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
@@ -53,9 +50,9 @@
 	assert(hw_config_info != NULL);
 	assert(hw_config_info->secondary_config_addr != 0UL);
 	arg2 = hw_config_info->secondary_config_addr;
-#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 */
-	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
-#endif /* TRANSFER_LIST */
+#endif /* !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2)*/
+
+	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Initialize the platform config for future decision making */
 	fvp_config_setup();
@@ -94,6 +91,16 @@
 	}
 }
 
+void __init bl31_platform_setup(void)
+{
+	arm_bl31_platform_setup();
+
+#if USE_GIC_DRIVER == 3
+	fvp_pcpu_init();
+	fvp_gic_driver_pre_init();
+#endif
+}
+
 #if !TRANSFER_LIST
 void __init bl31_plat_arch_setup(void)
 {

diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 98d4bbc..9c80283 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c

@@ -14,6 +14,7 @@
 #include <drivers/arm/ccn.h>
 #include <drivers/arm/gicv2.h>
 #include <drivers/arm/sp804_delay_timer.h>
+#include <drivers/arm/smmu_v3.h>
 #include <drivers/generic_delay_timer.h>
 #include <fconf_hw_config_getter.h>
 #include <lib/mmio.h>
@@ -43,6 +44,15 @@
 #define FVP_RMM_CONSOLE_NAME		"pl011"
 #define FVP_RMM_CONSOLE_COUNT		UL(1)
 
+/* Defines for RMM PCIe ECAM */
+#define FVP_RMM_ECAM_BASE		PCIE_EXP_BASE
+#define FVP_RMM_ECAM_SEGMENT		UL(0x0)
+#define FVP_RMM_ECAM_BDF		UL(0x0)
+
+/* Defines for RMM SMMUv3 */
+#define FVP_RMM_SMMU_BASE		PLAT_FVP_SMMUV3_BASE
+#define FVP_RMM_SMMU_COUNT		UL(1)
+
 /*******************************************************************************
  * arm_config holds the characteristics of the differences between the three FVP
  * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
@@ -58,6 +68,10 @@
 
 #define MAP_DEVICE1	MAP_REGION_FLAT(DEVICE1_BASE,			\
 					DEVICE1_SIZE,			\
+					MT_DEVICE | MT_RW | EL3_PAS)
+
+#define MAP_CCN		MAP_REGION_FLAT(CCN_BASE,			\
+					CCN_SIZE,			\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
 #if FVP_GICR_REGION_PROTECTION
@@ -105,7 +119,7 @@
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
-	MAP_DEVICE1,
+	MAP_CCN,
 #endif
 #if TRUSTED_BOARD_BOOT
 	/* To access the Root of Trust Public Key registers. */
@@ -123,7 +137,7 @@
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
-	MAP_DEVICE1,
+	MAP_CCN,
 #endif
 	ARM_MAP_NS_DRAM1,
 #ifdef __aarch64__
@@ -198,6 +212,9 @@
 	MAP_GICD_MEM,
 	MAP_GICR_MEM,
 #else
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+	MAP_CCN,
+#endif
 	MAP_DEVICE1,
 #endif /* FVP_GICR_REGION_PROTECTION */
 	ARM_V2M_MAP_MEM_PROTECT,
@@ -244,6 +261,9 @@
 #endif
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+	MAP_CCN,
+#endif
 	MAP_DEVICE1,
 	{0}
 };
@@ -563,6 +583,41 @@
 }
 
 #if ENABLE_RME
+
+/* BDF mappings for RP0 RC0 */
+const struct bdf_mapping_info rc0rp0_bdf_data[] = {
+	/* BDF0 */
+	{0U,		/* mapping_base */
+	 0x8000U,	/* mapping_top */
+	 0U,		/* mapping_off */
+	 0U		/* smmu_idx */
+	}
+};
+
+/* Root ports for RC0 */
+const struct root_port_info rc0rp_data[] = {
+	/* RP0 */
+	{0U,						/* root_port_id */
+	 0U,						/* padding */
+	 ARRAY_SIZE(rc0rp0_bdf_data),			/* num_bdf_mappings */
+	 (struct bdf_mapping_info *)rc0rp0_bdf_data	/* bdf_mappings */
+	}
+};
+
+/* Root complexes */
+const struct root_complex_info rc_data[] = {
+	/* RC0 */
+	{PCIE_EXP_BASE,				/* ecam_base */
+	 0U,					/* segment */
+	 {0U, 0U, 0U},				/* padding */
+	 ARRAY_SIZE(rc0rp_data),		/* num_root_ports */
+	 (struct root_port_info *)rc0rp_data	/* root_ports */
+	}
+};
+
+/* Number of PCIe Root Complexes */
+#define FVP_RMM_RC_COUNT	ARRAY_SIZE(rc_data)
+
 /*
  * Get a pointer to the RMM-EL3 Shared buffer and return it
  * through the pointer passed as parameter.
@@ -593,14 +648,14 @@
 	return sum;
 }
 /*
- * Boot Manifest structure illustration, with two DRAM banks,
+ * Boot Manifest v0.5 structure illustration, with two DRAM banks,
  * a single console and one device memory with two PCIe device
  * non-coherent address ranges.
  *
  * +--------------------------------------------------+
  * | offset |        field       |      comment       |
  * +--------+--------------------+--------------------+
- * |   0    |       version      |     0x00000004     |
+ * |   0    |       version      |     0x00000005     |
  * +--------+--------------------+--------------------+
  * |   4    |       padding      |     0x00000000     |
  * +--------+--------------------+--------------------+
@@ -629,42 +684,95 @@
  * |   96   |       banks        |   plat_coh_region  |  |  |  |
  * +--------+--------------------+                    |  |  |  |
  * |   104  |      checksum      |                    |  |  |  |
- * +--------+--------------------+--------------------+<-+  |  |
- * |   112  |       base 0       |                    |     |  |
- * +--------+--------------------+     mem_bank[0]    |     |  |
- * |   120  |       size 0       |                    |     |  |
- * +--------+--------------------+--------------------+     |  |
- * |   128  |       base 1       |                    |     |  |
- * +--------+--------------------+     mem_bank[1]    |     |  |
- * |   136  |       size 1       |                    |     |  |
- * +--------+--------------------+--------------------+<----+  |
- * |   144  |       base         |                    |        |
- * +--------+--------------------+                    |        |
- * |   152  |      map_pages     |                    |        |
- * +--------+--------------------+                    |        |
- * |   160  |       name         |                    |        |
- * +--------+--------------------+     consoles[0]    |        |
- * |   168  |     clk_in_hz      |                    |        |
- * +--------+--------------------+                    |        |
- * |   176  |     baud_rate      |                    |        |
- * +--------+--------------------+                    |        |
- * |   184  |       flags        |                    |        |
- * +--------+--------------------+--------------------+<-------+
- * |   192  |       base 0       |                    |
- * +--------+--------------------+   ncoh_region[0]   |
- * |   200  |       size 0       |                    |
- * +--------+--------------------+--------------------+
- * |   208  |       base 1       |                    |
- * +--------+--------------------+   ncoh_region[1]   |
- * |   216  |       size 1       |                    |
+ * +--------+--------------------+--------------------+  |  |  |
+ * |   112  |     num_smmus      |                    |  |  |  |
+ * +--------+--------------------+                    |  |  |  |
+ * |   120  |       smmus        |     plat_smmu      +--|--|--|--+
+ * +--------+--------------------+                    |  |  |  |  |
+ * |   128  |      checksum      |                    |  |  |  |  |
+ * +--------+--------------------+--------------------+  |  |  |  |
+ * |   136  |  num_root_complex  |                    |  |  |  |  |
+ * +--------+--------------------+                    |  |  |  |  |
+ * |   144  |   rc_info_version  |                    |  |  |  |  |
+ * +--------+--------------------+                    |  |  |  |  |
+ * |   148  |      padding       | plat_root_complex  +--|--|--|--|--+
+ * +--------+--------------------+                    |  |  |  |  |  |
+ * |   152  |    root_complex    |                    |  |  |  |  |  |
+ * +--------+--------------------+                    |  |  |  |  |  |
+ * |   160  |      checksum      |                    |  |  |  |  |  |
+ * +--------+--------------------+--------------------+<-+  |  |  |  |
+ * |   168  |       base 0       |                    |     |  |  |  |
+ * +--------+--------------------+     mem_bank[0]    |     |  |  |  |
+ * |   176  |       size 0       |                    |     |  |  |  |
+ * +--------+--------------------+--------------------+     |  |  |  |
+ * |   184  |       base 1       |                    |     |  |  |  |
+ * +--------+--------------------+     mem_bank[1]    |     |  |  |  |
+ * |   192  |       size 1       |                    |     |  |  |  |
+ * +--------+--------------------+--------------------+<----+  |  |  |
+ * |   200  |       base         |                    |        |  |  |
+ * +--------+--------------------+                    |        |  |  |
+ * |   208  |      map_pages     |                    |        |  |  |
+ * +--------+--------------------+                    |        |  |  |
+ * |   216  |       name         |                    |        |  |  |
+ * +--------+--------------------+     consoles[0]    |        |  |  |
+ * |   224  |     clk_in_hz      |                    |        |  |  |
+ * +--------+--------------------+                    |        |  |  |
+ * |   232  |     baud_rate      |                    |        |  |  |
+ * +--------+--------------------+                    |        |  |  |
+ * |   240  |       flags        |                    |        |  |  |
+ * +--------+--------------------+--------------------+<-------+  |  |
+ * |   248  |       base 0       |                    |           |  |
+ * +--------+--------------------+    ncoh_region[0]  |           |  |
+ * |   256  |       size 0       |                    |           |  |
+ * +--------+--------------------+--------------------+           |  |
+ * |   264  |       base 1       |                    |           |  |
+ * +--------+--------------------+    ncoh_region[1]  |           |  |
+ * |   272  |       size 1       |                    |           |  |
+ * +--------+--------------------+--------------------+<----------+  |
+ * |   280  |     smmu_base      |                    |              |
+ * +--------+--------------------+      smmus[0]      |              |
+ * |   288  |     smmu_r_base    |                    |              |
+ * +--------+--------------------+--------------------+<-------------+
+ * |   296  |     ecam_base      |                    |
+ * +--------+--------------------+                    |
+ * |   304  |      segment       |                    |
+ * +--------+--------------------+                    |
+ * |   305  |      padding       |   root_complex[0]  +--+
+ * +--------+--------------------+                    |  |
+ * |   308  |   num_root_ports   |                    |  |
+ * +--------+--------------------+                    |  |
+ * |   312  |     root_ports     |                    |  |
+ * +--------+--------------------+--------------------+<-+
+ * |   320  |    root_port_id    |                    |
+ * +--------+--------------------+                    |
+ * |   322  |      padding       |                    |
+ * +--------+--------------------+   root_ports[0]    +--+
+ * |   324  |  num_bdf_mappings  |                    |  |
+ * +--------+--------------------+                    |  |
+ * |   328  |    bdf_mappings    |                    |  |
+ * +--------+--------------------+--------------------+<-+
+ * |   336  |    mapping_base    |                    |
+ * +--------+--------------------+                    |
+ * |   338  |    mapping_top     |                    |
+ * +--------+--------------------+   bdf_mappings[0]  |
+ * |   340  |    mapping_off     |                    |
+ * +--------+--------------------+                    |
+ * |   342  |     smmu_idx       |                    |
  * +--------+--------------------+--------------------+
  */
 int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
 {
 	uint64_t checksum, num_banks, num_consoles;
 	uint64_t num_ncoh_regions, num_coh_regions;
-	struct memory_bank *bank_ptr, *ncoh_region_ptr;
+	uint64_t num_smmus, num_root_complex;
+	unsigned int num_root_ports, num_bdf_mappings;
+	uint32_t o_realm;
+	struct memory_bank *bank_ptr, *ncoh_region_ptr, *coh_region_ptr;
 	struct console_info *console_ptr;
+	struct smmu_info *smmu_ptr;
+	struct root_complex_info *root_complex_ptr, *rc_ptr;
+	struct root_port_info *root_port_ptr, *rp_ptr;
+	struct bdf_mapping_info *bdf_mapping_ptr, *bdf_ptr;
 
 	assert(manifest != NULL);
 
@@ -675,8 +783,28 @@
 	/* Set number of consoles */
 	num_consoles = FVP_RMM_CONSOLE_COUNT;
 
-	/* Set number of device non-coherent address ranges based on DT */
-	num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+	/* Set number of device non-coherent address ranges for FVP RevC */
+	num_ncoh_regions = 2;
+
+	/* Set number of SMMUs */
+	num_smmus = FVP_RMM_SMMU_COUNT;
+
+	/* Set number of PCIe root complexes */
+	num_root_complex = FVP_RMM_RC_COUNT;
+
+	/* Calculate and set number of all PCIe root ports and BDF mappings */
+	num_root_ports = 0U;
+	num_bdf_mappings = 0U;
+
+	/* Scan all root complex entries */
+	for (unsigned long i = 0UL; i < num_root_complex; i++) {
+		num_root_ports += rc_data[i].num_root_ports;
+
+		/* Scan all root ports entries in root complex */
+		for (unsigned int j = 0U; j < rc_data[i].num_root_ports; j++) {
+			num_bdf_mappings += rc_data[i].root_ports[j].num_bdf_mappings;
+		}
+	}
 
 	manifest->version = RMMD_MANIFEST_VERSION;
 	manifest->padding = 0U; /* RES0 */
@@ -684,6 +812,10 @@
 	manifest->plat_dram.num_banks = num_banks;
 	manifest->plat_console.num_consoles = num_consoles;
 	manifest->plat_ncoh_region.num_banks = num_ncoh_regions;
+	manifest->plat_smmu.num_smmus = num_smmus;
+	manifest->plat_root_complex.num_root_complex = num_root_complex;
+	manifest->plat_root_complex.rc_info_version = PCIE_RC_INFO_VERSION;
+	manifest->plat_root_complex.padding = 0U; /* RES0 */
 
 	/* FVP does not support device coherent address ranges */
 	num_coh_regions = 0UL;
@@ -699,9 +831,27 @@
 	ncoh_region_ptr = (struct memory_bank *)
 			((uintptr_t)console_ptr + (num_consoles *
 						sizeof(struct console_info)));
+	coh_region_ptr = (struct memory_bank *)
+			((uintptr_t)ncoh_region_ptr + (num_ncoh_regions *
+						sizeof(struct memory_bank)));
+	smmu_ptr = (struct smmu_info *)
+			((uintptr_t)coh_region_ptr + (num_coh_regions *
+						sizeof(struct memory_bank)));
+	root_complex_ptr = (struct root_complex_info *)
+			((uintptr_t)smmu_ptr + (num_smmus *
+						sizeof(struct smmu_info)));
+	root_port_ptr = (struct	root_port_info *)
+			((uintptr_t)root_complex_ptr + (num_root_complex *
+						sizeof(struct root_complex_info)));
+	bdf_mapping_ptr = (struct bdf_mapping_info *)
+			((uintptr_t)root_port_ptr + (num_root_ports *
+						sizeof(struct root_port_info)));
+
 	manifest->plat_dram.banks = bank_ptr;
 	manifest->plat_console.consoles = console_ptr;
 	manifest->plat_ncoh_region.banks = ncoh_region_ptr;
+	manifest->plat_smmu.smmus = smmu_ptr;
+	manifest->plat_root_complex.root_complex = root_complex_ptr;
 
 	/* Ensure the manifest is not larger than the shared buffer */
 	assert((sizeof(struct rmm_manifest) +
@@ -712,7 +862,13 @@
 		(sizeof(struct memory_bank) *
 			manifest->plat_ncoh_region.num_banks) +
 		(sizeof(struct memory_bank) *
-			manifest->plat_coh_region.num_banks))
+			manifest->plat_coh_region.num_banks) +
+		(sizeof(struct smmu_info) *
+			manifest->plat_smmu.num_smmus) +
+		(sizeof(struct root_complex_info) *
+			manifest->plat_root_complex.num_root_complex) +
+		(sizeof(struct root_port_info) * num_root_ports) +
+		(sizeof(struct bdf_mapping_info) * num_bdf_mappings))
 		<= ARM_EL3_RMM_SHARED_SIZE);
 
 	/* Calculate checksum of plat_dram structure */
@@ -761,6 +917,11 @@
 	(void)memset((void *)ncoh_region_ptr, 0,
 			sizeof(struct memory_bank) * num_ncoh_regions);
 
+	/* Set number of device non-coherent address ranges based on DT */
+	num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+	/* At least 1 PCIe region need to be described in DT */
+	assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
+
 	for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
 		ncoh_region_ptr[i].base =
 			FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
@@ -768,6 +929,17 @@
 			FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
 	}
 
+	/*
+	 * Workaround if the DT does not specify the 2nd PCIe region. This code can be
+	 * removed when upstream DT is updated to have 2nd PCIe region.
+	 */
+	if (num_ncoh_regions == 1) {
+		num_ncoh_regions++;
+		/* Add 3GB of 2nd PCIe region */
+		ncoh_region_ptr[1].base = 0x4000000000;
+		ncoh_region_ptr[1].size = 0xc0000000;
+	}
+
 	/* Update checksum */
 	checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
 			sizeof(struct memory_bank) * num_ncoh_regions);
@@ -775,6 +947,87 @@
 	/* Checksum must be 0 */
 	manifest->plat_ncoh_region.checksum = ~checksum + 1UL;
 
+	/* Calculate the checksum of the plat_smmu structure */
+	checksum = num_smmus + (uint64_t)smmu_ptr;
+
+	smmu_ptr[0].smmu_base = FVP_RMM_SMMU_BASE;
+
+	/* Read SMMU_ROOT_IDR0.BA_REALM[31:22] register field */
+	o_realm = mmio_read_32(FVP_RMM_SMMU_BASE + SMMU_ROOT_IDR0) &
+				SMMU_ROOT_IDR0_BA_REALM_MASK;
+	/*
+	 * Calculate the base address offset of Realm Register Page 0.
+	 * O_REALM = 0x20000 + (BA_REALM * 0x10000)
+	 * SMMU_REALM_BASE = SMMU_PAGE_0_BASE + O_REALM
+	 */
+	o_realm = 0x20000 + (o_realm >> (SMMU_ROOT_IDR0_BA_REALM_SHIFT - 16U));
+
+	smmu_ptr[0].smmu_r_base = FVP_RMM_SMMU_BASE + o_realm;
+
+	/* Update checksum */
+	checksum += checksum_calc((uint64_t *)smmu_ptr,
+					sizeof(struct smmu_info) * num_smmus);
+	/* Checksum must be 0 */
+	manifest->plat_smmu.checksum = ~checksum + 1UL;
+
+	/* Calculate the checksum of the plat_root_complex structure */
+	checksum = num_root_complex + (uint64_t)root_complex_ptr;
+
+	/* Zero out PCIe root complex info structures */
+	(void)memset((void *)root_complex_ptr, 0,
+			sizeof(struct root_complex_info) * num_root_complex);
+
+	/* Set pointers for data in manifest */
+	rc_ptr = root_complex_ptr;
+	rp_ptr = root_port_ptr;
+	bdf_ptr = bdf_mapping_ptr;
+
+	/* Fill PCIe root complex info structures */
+	for (unsigned long i = 0U; i < num_root_complex; i++) {
+		const struct root_complex_info *rc_info = &rc_data[i];
+		const struct root_port_info *rp_info = rc_info->root_ports;
+
+		/* Copy root complex data, except root_ports pointer */
+		(void)memcpy((void *)rc_ptr, (void *)rc_info,
+			sizeof(struct root_complex_info) - sizeof(struct root_port_info *));
+
+		/* Set root_ports for root complex */
+		rc_ptr->root_ports = rp_ptr;
+
+		/* Scan root ports */
+		for (unsigned int j = 0U; j < rc_ptr->num_root_ports; j++) {
+			const struct bdf_mapping_info *bdf_info = rp_info->bdf_mappings;
+
+			/* Copy root port data, except bdf_mappings pointer */
+			(void)memcpy((void *)rp_ptr, (void *)rp_info,
+				sizeof(struct root_port_info) - sizeof(struct bdf_mapping_info *));
+
+			/* Set bdf_mappings for root port */
+			rp_ptr->bdf_mappings = bdf_ptr;
+
+			/* Copy all BDF mappings for root port */
+			(void)memcpy((void *)bdf_ptr, (void *)bdf_info,
+				sizeof(struct bdf_mapping_info) * rp_ptr->num_bdf_mappings);
+
+			bdf_ptr += rp_ptr->num_bdf_mappings;
+			rp_ptr++;
+			rp_info++;
+		}
+		rc_ptr++;
+	}
+
+	/* Check that all data are written in manifest */
+	assert(rc_ptr == (root_complex_ptr + num_root_complex));
+	assert(rp_ptr == (root_port_ptr + num_root_ports));
+	assert(bdf_ptr == (bdf_mapping_ptr + num_bdf_mappings));
+
+	/* Update checksum for all PCIe data */
+	checksum += checksum_calc((uint64_t *)root_complex_ptr,
+				(uintptr_t)bdf_ptr - (uintptr_t)root_complex_ptr);
+
+	/* Checksum must be 0 */
+	manifest->plat_root_complex.checksum = ~checksum + 1UL;
+
 	return 0;
 }
 
@@ -789,4 +1042,4 @@
 	 */
 	return 0;
 }
-#endif	/* ENABLE_RME */
+#endif /* ENABLE_RME */

diff --git a/plat/arm/board/fvp/fvp_cpu_pwr.c b/plat/arm/board/fvp/fvp_cpu_pwr.c
index f2771c2..a294534 100644
--- a/plat/arm/board/fvp/fvp_cpu_pwr.c
+++ b/plat/arm/board/fvp/fvp_cpu_pwr.c

@@ -20,8 +20,8 @@
 
 bool check_cpupwrctrl_el1_is_available(void)
 {
-	/* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
-	const unsigned int midr_no_cpupwrctl[] = {
+	/* Populate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
+	static const unsigned int midr_no_cpupwrctl[] = {
 		BASE_AEM_MIDR,
 		CORTEX_A35_MIDR,
 		CORTEX_A53_MIDR,

diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index 831eb35..d87be31 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -53,12 +53,12 @@
  *  In case of FVP models with CCN, the CCN register space overlaps into
  *  the NSRAM area.
  */
-#if FVP_INTERCONNECT_DRIVER == FVP_CCN
-#define DEVICE1_BASE			UL(0x2e000000)
-#define DEVICE1_SIZE			UL(0x1A00000)
-#else
-#define DEVICE1_BASE			BASE_GICD_BASE
+#define CCN_BASE			UL(0x2e000000)
+#define CCN_SIZE			UL(0x1000000)
 
+/* TODO: this covers gicv5, but macros should be adjusted */
+#if USE_GIC_DRIVER != 5
+#define DEVICE1_BASE			BASE_GICD_BASE
 #if GIC_ENABLE_V4_EXTN
 /* GICv4 mapping: GICD + CORE_COUNT * 256KB */
 #define DEVICE1_SIZE			((BASE_GICR_BASE - BASE_GICD_BASE) + \
@@ -68,10 +68,11 @@
 #define DEVICE1_SIZE			((BASE_GICR_BASE - BASE_GICD_BASE) + \
 					 (PLATFORM_CORE_COUNT * 0x20000))
 #endif /* GIC_ENABLE_V4_EXTN */
-
-#define NSRAM_BASE			UL(0x2e000000)
-#define NSRAM_SIZE			UL(0x10000)
+#else
+#define DEVICE1_BASE			BASE_IWB_BASE
+#define DEVICE1_SIZE			((BASE_IRS_BASE - BASE_IWB_BASE) + SZ_64K)
 #endif
+
 /* Devices in the second GB */
 #define DEVICE2_BASE			UL(0x7fe00000)
 #define DEVICE2_SIZE			UL(0x00200000)
@@ -124,6 +125,15 @@
 #define FVP_SP810_CTRL_TIM2_OV		BIT_32(20)
 #define FVP_SP810_CTRL_TIM3_OV		BIT_32(22)
 
+
+#define NSRAM_BASE			UL(0x2e000000)
+#define NSRAM_SIZE			UL(0x10000)
+/*
+ *  In case of FVP models with CCN, the CCN register space overlaps into
+ *  the NSRAM area.
+ */
+#define CCN_BASE			UL(0x2e000000)
+#define CCN_SIZE			UL(0x1000000)
 /*******************************************************************************
  * GIC & interrupt handling related constants
  ******************************************************************************/
@@ -138,6 +148,9 @@
 #define BASE_GICD_SIZE			UL(0x10000)
 #define BASE_GICR_BASE			UL(0x2f100000)
 
+#define BASE_IWB_BASE			UL(0x2f000000)
+#define BASE_IRS_BASE			UL(0x2f1c0000)
+
 #if GIC_ENABLE_V4_EXTN
 /* GICv4 redistributor size: 256KB */
 #define BASE_GICR_SIZE			UL(0x40000)

diff --git a/plat/arm/board/fvp/fvp_gicv3.c b/plat/arm/board/fvp/fvp_gicv3.c
index e780f21..4167229 100644
--- a/plat/arm/board/fvp/fvp_gicv3.c
+++ b/plat/arm/board/fvp/fvp_gicv3.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,51 +21,15 @@
 static bool fvp_gicr_rw_region_init[PLATFORM_CORE_COUNT] = {false};
 #endif /* FVP_GICR_REGION_PROTECTION */
 
-/* The GICv3 driver only needs to be initialized in EL3 */
-static uintptr_t fvp_rdistif_base_addrs[PLATFORM_CORE_COUNT];
-
 /* Default GICR base address to be used for GICR probe. */
-static uint64_t fvp_gicr_base_addrs[2] = { 0U };
+static uintptr_t __unused fvp_gicr_base_addrs[2] = { 0U };
 
-/* List of zero terminated GICR frame addresses which CPUs will probe */
-static uint64_t *fvp_gicr_frames = fvp_gicr_base_addrs;
-
-#if  !(SEC_INT_DESC_IN_FCONF && ((!defined(__aarch64__) && defined(IMAGE_BL32)) || \
-	(defined(__aarch64__) && defined(IMAGE_BL31))))
-static const interrupt_prop_t fvp_interrupt_props[] = {
+static const interrupt_prop_t __unused fvp_interrupt_props[] = {
 	PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
 	PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
 };
-#endif
 
-/*
- * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
- * to core position.
- *
- * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
- * values read from GICR_TYPER don't have an MT field. To reuse the same
- * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
- * that read from GICR_TYPER.
- *
- * Assumptions:
- *
- *   - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
- *   - No CPUs implemented in the system use affinity level 3.
- */
-static unsigned int fvp_gicv3_mpidr_hash(u_register_t mpidr)
-{
-	u_register_t temp_mpidr = mpidr;
-
-	temp_mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
-	return plat_arm_calc_core_pos(temp_mpidr);
-}
-
-
-static gicv3_driver_data_t fvp_gic_data = {
-	.rdistif_num = PLATFORM_CORE_COUNT,
-	.rdistif_base_addrs = fvp_rdistif_base_addrs,
-	.mpidr_to_core_pos = fvp_gicv3_mpidr_hash
-};
+extern gicv3_driver_data_t gic_data;
 
 /******************************************************************************
  * This function gets called per core to make its redistributor frame rw
@@ -97,78 +61,41 @@
 #endif /* FVP_GICR_REGION_PROTECTION */
 }
 
-void plat_arm_gic_driver_init(void)
+void fvp_pcpu_init(void)
 {
 	fvp_gicv3_make_rdistrif_rw();
+}
+
+void fvp_gic_driver_pre_init(void)
+{
+/* FCONF won't be used in these cases, so we couldn't do this */
+#if !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2)
 	/*
 	 * Get GICD and GICR base addressed through FCONF APIs.
 	 * FCONF is not supported in BL32 for FVP.
 	 */
 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
 	(defined(__aarch64__) && defined(IMAGE_BL31))
-	fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config,
+	gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config,
 							       gicv3_config,
 							       gicd_base);
 	fvp_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config,
 						    gicr_base);
 #if SEC_INT_DESC_IN_FCONF
-	fvp_gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config,
+	gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config,
 					sec_intr_prop, descriptor);
-	fvp_gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config,
+	gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config,
 					sec_intr_prop, count);
 #else
-	fvp_gic_data.interrupt_props = fvp_interrupt_props;
-	fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
+	gic_data.interrupt_props = fvp_interrupt_props;
+	gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
 #endif
 #else
-	fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE;
+	gic_data.gicd_base = PLAT_ARM_GICD_BASE;
 	fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE;
-	fvp_gic_data.interrupt_props = fvp_interrupt_props;
-	fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
+	gic_data.interrupt_props = fvp_interrupt_props;
+	gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
 #endif
-
-	/*
-	 * The GICv3 driver is initialized in EL3 and does not need
-	 * to be initialized again in SEL1. This is because the S-EL1
-	 * can use GIC system registers to manage interrupts and does
-	 * not need GIC interface base addresses to be configured.
-	 */
-
-#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
-	(defined(__aarch64__) && defined(IMAGE_BL31))
-	gicv3_driver_init(&fvp_gic_data);
-	if (gicv3_rdistif_probe((uintptr_t)fvp_gicr_base_addrs[0]) == -1) {
-		ERROR("No GICR base frame found for Primary CPU\n");
-		panic();
-	}
-#endif
-}
-
-/******************************************************************************
- * Function to iterate over all GICR frames and discover the corresponding
- * per-cpu redistributor frame as well as initialize the corresponding
- * interface in GICv3.
- *****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
-{
-	int result;
-	const uint64_t *plat_gicr_frames = fvp_gicr_frames;
-
-	fvp_gicv3_make_rdistrif_rw();
-
-	do {
-		result = gicv3_rdistif_probe(*plat_gicr_frames);
-
-		/* If the probe is successful, no need to proceed further */
-		if (result == 0)
-			break;
-
-		plat_gicr_frames++;
-	} while (*plat_gicr_frames != 0U);
-
-	if (result == -1) {
-		ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
-		panic();
-	}
-	gicv3_rdistif_init(plat_my_core_pos());
+	plat_arm_override_gicr_frames(fvp_gicr_base_addrs);
+#endif /* !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2) */
 }

diff --git a/plat/arm/board/fvp/fvp_gicv5.c b/plat/arm/board/fvp/fvp_gicv5.c
new file mode 100644
index 0000000..73bd9c5
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_gicv5.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv5.h>
+#include <platform_def.h>
+
+/* wire 26 is the timer interrupt. Will be assigned NS by default */
+struct gicv5_wire_props irs0_spis[] = {
+};
+
+struct gicv5_wire_props iwb0_wires[] = {
+};
+
+struct gicv5_irs irss[] = {{
+	.el3_config_frame = BASE_IRS_BASE,
+	.spis = irs0_spis,
+	.num_spis = ARRAY_SIZE(irs0_spis),
+}};
+
+struct gicv5_iwb iwbs[] = {{
+	.config_frame = BASE_IWB_BASE,
+	.wires = iwb0_wires,
+	.num_wires = ARRAY_SIZE(iwb0_wires)
+}};
+
+const struct gicv5_driver_data plat_gicv5_driver_data = {
+	.irss = irss,
+	.iwbs = iwbs,
+	.num_irss = ARRAY_SIZE(irss),
+	.num_iwbs = ARRAY_SIZE(iwbs)
+};
+
+void fvp_gic_driver_pre_init(void)
+{
+}
+
+void fvp_pcpu_init(void)
+{
+}

diff --git a/plat/arm/board/fvp/fvp_ide_keymgmt.c b/plat/arm/board/fvp/fvp_ide_keymgmt.c
new file mode 100644
index 0000000..ff05351
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_ide_keymgmt.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+int plat_rmmd_el3_ide_key_program(uint64_t ecam_address, uint64_t root_port_id,
+				  uint64_t ide_stream_info,
+				  rp_ide_key_info_t *ide_key_info_ptr, uint64_t request_id,
+				  uint64_t cookie)
+{
+	/* placeholder to add further implementation */
+
+	return 0;
+
+}
+
+int plat_rmmd_el3_ide_key_set_go(uint64_t ecam_address, uint64_t root_port_id,
+				 uint64_t ide_stream_info, uint64_t request_id,
+				 uint64_t cookie)
+{
+	/* placeholder to add further implementation */
+
+	return 0;
+
+}
+
+int plat_rmmd_el3_ide_key_set_stop(uint64_t ecam_address, uint64_t root_port_id,
+				   uint64_t ide_stream_info, uint64_t request_id,
+				   uint64_t cookie)
+{
+	/* placeholder to add further implementation */
+
+	return 0;
+}
+
+int plat_rmmd_el3_ide_km_pull_response(uint64_t ecam_address, uint64_t root_port_id,
+				   uint64_t *req_resp, uint64_t *request,
+				   uint64_t *cookie)
+{
+	/* placeholder to add further implementation */
+	return E_RMM_UNK;
+}

diff --git a/plat/arm/board/fvp/fvp_lfa.c b/plat/arm/board/fvp/fvp_lfa.c
new file mode 100644
index 0000000..3c5321d
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_lfa.c

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <plat/common/platform.h>
+#include <services/bl31_lfa.h>
+#include <services/rmmd_rmm_lfa.h>
+#include <tools_share/firmware_image_package.h>
+
+#include <fvp_lfa_components.h>
+
+/* Keep this array consistent with enum fvp_lfa_component_id_t */
+static plat_lfa_component_info_t fvp_lfa_components[LFA_MAX_DEFINED_COMPONENTS] = {
+	[LFA_BL31_COMPONENT] = {LFA_BL31_COMPONENT, UUID_EL3_RUNTIME_FIRMWARE_BL31,
+				NULL, false},
+#if BL32_BASE
+	[LFA_BL32_COMPONENT] = {LFA_BL32_COMPONENT, UUID_SECURE_PAYLOAD_BL32,
+				NULL, false},
+#endif /* BL32_BASE */
+	[LFA_BL33_COMPONENT] = {LFA_BL33_COMPONENT, UUID_NON_TRUSTED_FIRMWARE_BL33,
+				NULL, false},
+#if ENABLE_RME
+	[LFA_RMM_COMPONENT]  = {LFA_RMM_COMPONENT, UUID_REALM_MONITOR_MGMT_FIRMWARE,
+				NULL, false},
+#endif /* ENABLE_RME */
+};
+
+uint32_t plat_lfa_get_components(plat_lfa_component_info_t **components)
+{
+	if (components == NULL) {
+		return -EINVAL;
+	}
+
+	fvp_lfa_components[LFA_BL31_COMPONENT].activator = get_bl31_activator();
+#if ENABLE_RME
+	fvp_lfa_components[LFA_RMM_COMPONENT].activator = get_rmm_activator();
+#endif /* ENABLE_RME */
+
+	*components = fvp_lfa_components;
+	return LFA_MAX_DEFINED_COMPONENTS;
+}
+
+bool is_plat_lfa_activation_pending(uint32_t lfa_component_id)
+{
+#if ENABLE_RME
+	if (lfa_component_id == LFA_RMM_COMPONENT) {
+		return true;
+	}
+#endif /* ENABLE_RME */
+
+	return false;
+}
+
+int plat_lfa_cancel(uint32_t lfa_component_id)
+{
+	/* placeholder function to do cancel LFA of given component */
+	return 0;
+}
+
+int plat_lfa_load_auth_image(uint32_t img_id)
+{
+	/*
+	 * In AEM FVP, we don't want to bloat the code by adding
+	 * loading and authentication mechanism, so here we assumed
+	 * that the components are pre-loaded and authenticated already.
+	 */
+	return 0;
+}

diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 2a0bb93..fb72105 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -180,12 +180,6 @@
 	 * by the cluster specific operations if applicable.
 	 */
 
-	/* Prevent interrupts from spuriously waking up this cpu */
-	plat_arm_gic_cpuif_disable();
-
-	/* Turn redistributor off */
-	plat_arm_gic_redistif_off();
-
 	/* Program the power controller to power off this cpu. */
 	fvp_pwrc_write_ppoffr(read_mpidr_el1());
 
@@ -220,9 +214,6 @@
 	/* Program the power controller to enable wakeup interrupts. */
 	fvp_pwrc_set_wen(mpidr);
 
-	/* Prevent interrupts from spuriously waking up this cpu */
-	plat_arm_gic_cpuif_disable();
-
 	/*
 	 * The Redistributor is not powered off as it can potentially prevent
 	 * wake up events reaching the CPUIF and/or might lead to losing
@@ -253,7 +244,6 @@
 static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
 	fvp_power_domain_on_finish_common(target_state);
-
 }
 
 /*******************************************************************************
@@ -263,11 +253,9 @@
  ******************************************************************************/
 static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
 {
-	/* Program GIC per-cpu distributor or re-distributor interface */
-	plat_arm_gic_pcpu_init();
-
-	/* Enable GIC CPU interface */
-	plat_arm_gic_cpuif_enable();
+#if USE_GIC_DRIVER == 3
+	fvp_pcpu_init();
+#endif
 }
 
 /*******************************************************************************
@@ -287,9 +275,6 @@
 		return;
 
 	fvp_power_domain_on_finish_common(target_state);
-
-	/* Enable GIC CPU interface */
-	plat_arm_gic_cpuif_enable();
 }
 
 /*******************************************************************************

diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h
index 3590370..7e53a65 100644
--- a/plat/arm/board/fvp/fvp_private.h
+++ b/plat/arm/board/fvp/fvp_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,6 +19,7 @@
 void fvp_interconnect_enable(void);
 void fvp_interconnect_disable(void);
 void fvp_timer_init(void);
-void tsp_early_platform_setup(void);
+void fvp_pcpu_init(void);
+void fvp_gic_driver_pre_init(void);
 
 #endif /* FVP_PRIVATE_H */

diff --git a/plat/arm/board/fvp/include/fvp_lfa_components.h b/plat/arm/board/fvp/include/fvp_lfa_components.h
new file mode 100644
index 0000000..09dcdfd
--- /dev/null
+++ b/plat/arm/board/fvp/include/fvp_lfa_components.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_LFA_COMPONENTS_H
+#define FVP_LFA_COMPONENTS_H
+
+/*
+ * Define platform-specific numeric IDs for LFA FVP components.
+ */
+typedef enum {
+	LFA_BL31_COMPONENT = 0,
+#if BL32_BASE
+	LFA_BL32_COMPONENT,
+#endif /* BL32_BASE */
+	LFA_BL33_COMPONENT,
+#if ENABLE_RME
+	LFA_RMM_COMPONENT,
+#endif /* ENABLE_RME */
+	LFA_MAX_DEFINED_COMPONENTS
+} fvp_lfa_component_id_t;
+
+#endif /* FVP_LFA_COMPONENTS_H */

diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index f5be8f2..002674c 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h

@@ -93,15 +93,6 @@
 #define FVP_DRAM6_SIZE	ULL(0x7800000000000) /* 1920 TB */
 #define FVP_DRAM6_END	(FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U)
 
-/* Range of kernel DTB load address */
-#define FVP_DTB_DRAM_MAP_START		ULL(0x82000000)
-#define FVP_DTB_DRAM_MAP_SIZE		ULL(0x02000000)	/* 32 MB */
-
-#define ARM_DTB_DRAM_NS			MAP_REGION_FLAT(		\
-					FVP_DTB_DRAM_MAP_START,		\
-					FVP_DTB_DRAM_MAP_SIZE,		\
-					MT_MEMORY | MT_RO | MT_NS)
-
 /*
  * On the FVP platform when using the EL3 SPMC implementation allocate the
  * datastore for tracking shared memory descriptors in the TZC DRAM section
@@ -206,7 +197,7 @@
 #  define PLAT_ARM_MMAP_ENTRIES		12
 #  define MAX_XLAT_TABLES		6
 # else
-#  define PLAT_ARM_MMAP_ENTRIES		11
+#  define PLAT_ARM_MMAP_ENTRIES		12
 #  define MAX_XLAT_TABLES		5
 # endif /* (IMAGE_BL2 && ENABLE_RME) */
 #else
@@ -227,7 +218,7 @@
  */
 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \
 FVP_TRUSTED_SRAM_SIZE == 512
-#define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xC000)
+#define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xD000)
 #else
 #define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xB000)
 #endif
@@ -307,9 +298,15 @@
  * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
  * BL2 and BL1-RW
  */
+#if TRANSFER_LIST
+# define PLAT_ARM_MAX_BL32_SIZE		(PLAT_ARM_TRUSTED_SRAM_SIZE - \
+					 ARM_SHARED_RAM_SIZE - \
+					 PLAT_ARM_FW_HANDOFF_SIZE)
+#else
 # define PLAT_ARM_MAX_BL32_SIZE		(PLAT_ARM_TRUSTED_SRAM_SIZE - \
 					 ARM_SHARED_RAM_SIZE - \
 					 ARM_FW_CONFIGS_SIZE)
+#endif /* TRANSFER_LIST */
 #endif /* RESET_TO_SP_MIN */
 #endif
 
@@ -503,12 +500,19 @@
 
 /*
  * Maximum size of Event Log buffer used in Measured Boot Event Log driver
+ * TODO: calculate maximum EventLog size using the calculation:
+ * Maximum size of Event Log * Number of images
  */
-#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
-/* Account for additional measurements of secure partitions and SPM. */
-#define	PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x800)
+#if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed)))
+/*
+ * Account for additional measurements of secure partitions and SPM.
+ * Also, account for OP-TEE running with maximum number of SPs.
+ */
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x800)
+#elif defined(IMAGE_BL1) && TRANSFER_LIST
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x200)
 #else
-#define	PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x400)
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x400)
 #endif
 
 /*

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index e43d025..7f1dfc6 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk

@@ -22,13 +22,6 @@
 # only; enable redistributor frames of all CPU cores by default.
 FVP_GICR_REGION_PROTECTION	:= 0
 
-ifeq (${HW_ASSISTED_COHERENCY}, 0)
-FVP_DT_PREFIX			:= fvp-base-gicv3-psci
-else
-FVP_DT_PREFIX			:= fvp-base-gicv3-psci-dynamiq
-endif
-# fdts is wrong otherwise
-
 # Size (in kilobytes) of the Trusted SRAM region to utilize when building for
 # the FVP platform.
 ifeq (${ENABLE_RME},1)
@@ -95,6 +88,7 @@
 
 ifeq (${ENABLE_RME},1)
     ENABLE_FEAT_MEC		:= 2
+    RMMD_ENABLE_IDE_KEY_PROG	:= 1
 endif
 
 # The FVP platform depends on this macro to build with correct GIC driver.
@@ -129,36 +123,40 @@
 
 # Choose the GIC sources depending upon the how the FVP will be invoked
 ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
+USE_GIC_DRIVER			:=	3
 
 # The GIC model (GIC-600 or GIC-500) will be detected at runtime
 GICV3_SUPPORT_GIC600		:=	1
 GICV3_OVERRIDE_DISTIF_PWR_OPS	:=	1
 
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
+FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
+ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
+BL31_SOURCES		+=	plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
+endif
 
-FVP_GIC_SOURCES		:=	${GICV3_SOURCES}			\
-				plat/common/plat_gicv3.c		\
-				plat/arm/common/arm_gicv3.c
-
-	ifeq ($(filter 1,${RESET_TO_BL2} \
-		${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
-		FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
-	endif
-
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+FVP_DT_PREFIX			:= fvp-base-gicv3-psci
+else
+FVP_DT_PREFIX			:= fvp-base-gicv3-psci-dynamiq
+endif
+else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5)
+USE_GIC_DRIVER		:=	5
+ENABLE_FEAT_GCIE	:=	1
+BL31_SOURCES		+=	plat/arm/board/fvp/fvp_gicv5.c
+FVP_DT_PREFIX		:=	"FVP does not provide a GICv5 dts yet"
+ifneq ($(SPD),none)
+        $(error Error: GICv5 is not compatible with SPDs)
+endif
+ifeq ($(ENABLE_RME),1)
+       $(error Error: GICv5 is not compatible with RME)
+endif
 else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
+USE_GIC_DRIVER		:=	2
 
 # No GICv4 extension
 GIC_ENABLE_V4_EXTN	:=	0
 $(eval $(call add_define,GIC_ENABLE_V4_EXTN))
 
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-FVP_GIC_SOURCES		:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
-
 FVP_DT_PREFIX		:=	fvp-base-gicv2-psci
 else
 $(error "Incorrect GIC driver chosen on FVP port")
@@ -173,7 +171,7 @@
 $(error "Incorrect CCN driver chosen on FVP port")
 endif
 
-FVP_SECURITY_SOURCES	:=	drivers/arm/tzc/tzc400.c		\
+FVP_SECURITY_SOURCES	+=	drivers/arm/tzc/tzc400.c		\
 				plat/arm/board/fvp/fvp_security.c	\
 				plat/arm/common/arm_tzc400.c
 
@@ -302,10 +300,11 @@
 
 BL31_SOURCES		+=	plat/arm/board/fvp/fvp_plat_attest_token.c	\
 				plat/arm/board/fvp/fvp_realm_attest_key.c	\
-				plat/arm/board/fvp/fvp_el3_token_sign.c
+				plat/arm/board/fvp/fvp_el3_token_sign.c		\
+				plat/arm/board/fvp/fvp_ide_keymgmt.c
 endif
 
-ifeq (${ENABLE_FEAT_RNG_TRAP},1)
+ifneq (${ENABLE_FEAT_RNG_TRAP},0)
 BL31_SOURCES		+=	plat/arm/board/fvp/fvp_sync_traps.c
 endif
 
@@ -341,7 +340,6 @@
 				plat/arm/board/fvp/fvp_cpu_pwr.c		\
 				plat/arm/common/arm_nor_psci_mem_protect.c	\
 				${FVP_CPU_LIBS}					\
-				${FVP_GIC_SOURCES}				\
 				${FVP_INTERCONNECT_SOURCES}			\
 				${FVP_SECURITY_SOURCES}
 
@@ -373,6 +371,10 @@
 $(eval FVP_HW_CONFIG	:=	${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
 HW_CONFIG		:=	${FVP_HW_CONFIG}
 
+# Allow hw_config's secondary-load-address in the DT to be changed
+FVP_HW_CONFIG_ADDR	?=	0x82000000
+DTC_CPPFLAGS		+=	-DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR)
+
 # Set default initrd base 128MiB offset of the default kernel address in FVP
 INITRD_BASE		?=	0x90000000
 
@@ -433,7 +435,6 @@
 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
 
 ifeq (${TRANSFER_LIST}, 1)
-include lib/transfer_list/transfer_list.mk
 
 ifeq ($(RESET_TO_BL31), 1)
 FW_HANDOFF_SIZE			:=	20000
@@ -590,3 +591,7 @@
 
 # Build macro necessary for running SPM tests on FVP platform
 $(eval $(call add_define,PLAT_TEST_SPM))
+
+ifeq (${LFA_SUPPORT},1)
+BL31_SOURCES            +=      plat/arm/board/fvp/fvp_lfa.c
+endif

diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
index 705ec38..8c193fa 100644
--- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
+++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,16 +14,34 @@
 
 #include "../fvp_private.h"
 
+static uintptr_t hw_config __unused;
+
 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
 	const struct dyn_cfg_dtb_info_t *tos_fw_config_info __unused;
+	struct transfer_list_header *tl __unused;
 
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();
 
-#if !RESET_TO_SP_MIN && !RESET_TO_BL2
+#if TRANSFER_LIST
+	/*
+	 * Register usage at function entry:
+	 *   r0 - Reserved (must be zero)
+	 *   r1 - Register convention and TL signature
+	 *   r2 - Pointer to the FDT located within the TL
+	 *   r3 - Base address of the TL
+	 *
+	 * Initialize TL pointer from r3 and validate that the FDT pointer (arg2)
+	 * lies within the bounds of the Transfer List memory region.
+	 */
+	tl = (struct transfer_list_header *)arg3;
 
+	assert(arg2 > (uintptr_t)tl && arg2 < (uintptr_t)tl + tl->size);
+	hw_config = (uintptr_t)arg2;
+#else
+#if !RESET_TO_SP_MIN && !RESET_TO_BL2
 	INFO("SP_MIN FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
 	/* Fill the properties struct with the info from the config dtb */
 	fconf_populate("FW_CONFIG", arg1);
@@ -33,8 +51,9 @@
 		arg1 = tos_fw_config_info->config_addr;
 	}
 #endif /* !RESET_TO_SP_MIN && !RESET_TO_BL2 */
+#endif /* TRANSFER_LIST */
 
-	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Initialize the platform config for future decision making */
 	fvp_config_setup();
@@ -75,7 +94,10 @@
 	 * TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support
 	 * gets deprecated.
 	 */
-#if !RESET_TO_SP_MIN && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1
+#if TRANSFER_LIST
+	INFO("SP_MIN FCONF: HW_CONFIG address = %p\n", (void *)hw_config);
+	fconf_populate("HW_CONFIG", hw_config);
+#elif !RESET_TO_SP_MIN && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1
 	hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
 	assert(hw_config_info != NULL);
 	assert(hw_config_info->config_addr != 0UL);
@@ -118,5 +140,6 @@
 		      rc);
 		panic();
 	}
-#endif /*!RESET_TO_SP_MIN && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1*/
+
+#endif /* TRANSFER_LIST */
 }

diff --git a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
index 4ddba6f..0328864 100644
--- a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
+++ b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -17,7 +17,7 @@
 				plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c	\
 				plat/arm/common/arm_nor_psci_mem_protect.c	\
 				${FVP_CPU_LIBS}					\
-				${FVP_GIC_SOURCES}				\
+				${GIC_SOURCES}					\
 				${FVP_INTERCONNECT_SOURCES}			\
 				${FVP_SECURITY_SOURCES}
 

diff --git a/plat/arm/board/fvp/trp/test_ide_km_interface.c b/plat/arm/board/fvp/trp/test_ide_km_interface.c
new file mode 100644
index 0000000..2a1f0e2
--- /dev/null
+++ b/plat/arm/board/fvp/trp/test_ide_km_interface.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <plat/common/platform.h>
+#include <services/trp/platform_trp.h>
+
+#include <platform_def.h>
+
+/*
+ * Helper function for ecam address and root port ID
+ *
+ */
+uint64_t trp_get_test_rootport(uint64_t *ecam_address, uint64_t *rp_id)
+{
+
+	*ecam_address = 0xE001C000;
+	*rp_id = 0x001C0001;
+
+	return 0;
+}
+

diff --git a/plat/arm/board/fvp/trp/trp-fvp.mk b/plat/arm/board/fvp/trp/trp-fvp.mk
index a450541..3c1b96b 100644
--- a/plat/arm/board/fvp/trp/trp-fvp.mk
+++ b/plat/arm/board/fvp/trp/trp-fvp.mk

@@ -6,7 +6,8 @@
 
 # TRP source files specific to FVP platform
 
-RMM_SOURCES		+=	plat/arm/board/fvp/aarch64/fvp_helpers.S
+RMM_SOURCES		+=	plat/arm/board/fvp/aarch64/fvp_helpers.S	\
+				plat/arm/board/fvp/trp/test_ide_km_interface.c
 
 include plat/arm/common/trp/arm_trp.mk
 

diff --git a/plat/arm/board/fvp/tsp/fvp_tsp_setup.c b/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
index 3c8a963..53a84c6 100644
--- a/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
+++ b/plat/arm/board/fvp/tsp/fvp_tsp_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,9 +8,10 @@
 
 #include "../fvp_private.h"
 
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3)
 {
-	arm_tsp_early_platform_setup();
+	arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Initialize the platform config for future decision making */
 	fvp_config_setup();

diff --git a/plat/arm/board/fvp/tsp/tsp-fvp.mk b/plat/arm/board/fvp/tsp/tsp-fvp.mk
index ab3f225..8557ec1 100644
--- a/plat/arm/board/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/board/fvp/tsp/tsp-fvp.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -9,6 +9,6 @@
 				plat/arm/board/fvp/aarch64/fvp_helpers.S	\
 				plat/arm/board/fvp/fvp_topology.c		\
 				plat/arm/board/fvp/tsp/fvp_tsp_setup.c		\
-				${FVP_GIC_SOURCES}
+				${GIC_SOURCES}
 
 include plat/arm/common/tsp/arm_tsp.mk

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
deleted file mode 100644
index 820470b..0000000
--- a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
+++ /dev/null

@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "../../../../bl1/bl1_private.h"
-#include <arch.h>
-
-#include <fvp_r_arch_helpers.h>
-
-/*******************************************************************************
- * Function that does the first bit of architectural setup that affects
- * execution in the non-secure address space.
- ******************************************************************************/
-void bl1_arch_setup(void)
-{
-	/* v8-R64 does not include SCRs. */
-}

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S b/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S
deleted file mode 100644
index 15f4c43..0000000
--- a/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S
+++ /dev/null

@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <el2_common_macros.S>
-#include <lib/xlat_mpu/xlat_mpu.h>
-
-	.globl	bl1_entrypoint
-	.globl	bl1_run_next_image
-
-
-	/* -----------------------------------------------------
-	 * bl1_entrypoint() is the entry point into the trusted
-	 * firmware code when a cpu is released from warm or
-	 * cold reset.
-	 * -----------------------------------------------------
-	 */
-
-func bl1_entrypoint
-	/* ---------------------------------------------------------------------
-	 * If the reset address is programmable then bl1_entrypoint() is
-	 * executed only on the cold boot path. Therefore, we can skip the warm
-	 * boot mailbox mechanism.
-	 * ---------------------------------------------------------------------
-	 */
-	el2_entrypoint_common					\
-		_init_sctlr=1					\
-		_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS	\
-		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU	\
-		_init_memory=1					\
-		_init_c_runtime=1				\
-		_exception_vectors=bl1_exceptions		\
-		_pie_fixup_size=0
-
-	/* --------------------------------------------------------------------
-	 * Perform BL1 setup
-	 * --------------------------------------------------------------------
-	 */
-	bl	bl1_setup
-
-	/* --------------------------------------------------------------------
-	 * Initialize platform and jump to our c-entry point
-	 * for this type of reset.
-	 * --------------------------------------------------------------------
-	 */
-	bl	bl1_main
-
-	/* ---------------------------------------------
-	 * Should never reach this point.
-	 * ---------------------------------------------
-	 */
-	no_ret	plat_panic_handler
-endfunc bl1_entrypoint
-
-func bl1_run_next_image
-	mov	x20,x0
-
-	/* ---------------------------------------------
-	 * MPU needs to be disabled because both BL1 and BL33 execute
-	 * in EL2, and therefore share the same address space.
-	 * BL33 will initialize the address space according to its
-	 * own requirement.
-	 * ---------------------------------------------
-	 */
-	bl	disable_mpu_icache_el2
-
-	/* ---------------------------------------------
-	 * Wipe clean and disable all MPU regions.  This function expects
-	 * that the MPU has already been turned off, and caching concerns
-	 * addressed, but it also explicitly turns off the MPU.
-	 * ---------------------------------------------
-	 */
-	bl	clear_all_mpu_regions
-
-	/* --------------------------------------------------
-	 * Do the transition to next boot image.
-	 * --------------------------------------------------
-	 */
-	ldp	x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
-	msr	elr_el2, x0
-	msr	spsr_el2, x1
-
-	ldp	x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
-	ldp	x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
-	ldp	x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
-	ldp	x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
-	exception_return
-endfunc bl1_run_next_image

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S b/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S
deleted file mode 100644
index 43c2e01..0000000
--- a/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S
+++ /dev/null

@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <bl1/bl1.h>
-#include <common/bl_common.h>
-#include <context.h>
-
-/* -----------------------------------------------------------------------------
- * File contains an EL2 equivalent of the EL3 vector table from:
- * 	.../bl1/aarch64/bl1_exceptions.S
- * -----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------
- * Very simple stackless exception handlers used by BL1.
- * -----------------------------------------------------------------------------
- */
-	.globl	bl1_exceptions
-
-vector_base bl1_exceptions
-
-	/* -----------------------------------------------------
-	 * Current EL with SP0 : 0x0 - 0x200
-	 * -----------------------------------------------------
-	 */
-vector_entry SynchronousExceptionSP0
-	mov	x0, #SYNC_EXCEPTION_SP_EL0
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry SynchronousExceptionSP0
-
-vector_entry IrqSP0
-	mov	x0, #IRQ_SP_EL0
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry IrqSP0
-
-vector_entry FiqSP0
-	mov	x0, #FIQ_SP_EL0
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry FiqSP0
-
-vector_entry SErrorSP0
-	mov	x0, #SERROR_SP_EL0
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry SErrorSP0
-
-	/* -----------------------------------------------------
-	 * Current EL with SPx: 0x200 - 0x400
-	 * -----------------------------------------------------
-	 */
-vector_entry SynchronousExceptionSPx
-	mov	x0, #SYNC_EXCEPTION_SP_ELX
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry SynchronousExceptionSPx
-
-vector_entry IrqSPx
-	mov	x0, #IRQ_SP_ELX
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry IrqSPx
-
-vector_entry FiqSPx
-	mov	x0, #FIQ_SP_ELX
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry FiqSPx
-
-vector_entry SErrorSPx
-	mov	x0, #SERROR_SP_ELX
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry SErrorSPx
-
-	/* -----------------------------------------------------
-	 * Lower EL using AArch64 : 0x400 - 0x600
-	 * -----------------------------------------------------
-	 */
-vector_entry SynchronousExceptionA64
-	/* The current v8-R64 implementation does not support conduit calls */
-	b	el2_panic
-end_vector_entry SynchronousExceptionA64
-
-vector_entry IrqA64
-	mov	x0, #IRQ_AARCH64
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry IrqA64
-
-vector_entry FiqA64
-	mov	x0, #FIQ_AARCH64
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry FiqA64
-
-vector_entry SErrorA64
-	mov	x0, #SERROR_AARCH64
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-end_vector_entry SErrorA64
-
-
-unexpected_sync_exception:
-	mov	x0, #SYNC_EXCEPTION_AARCH64
-	bl	plat_report_exception
-	no_ret	plat_panic_handler
-
-	/* -----------------------------------------------------
-	 * Save Secure/Normal world context and jump to
-	 * BL1 SMC handler.
-	 * -----------------------------------------------------
-	 */

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_main.c b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
deleted file mode 100644
index 6fe2b5b..0000000
--- a/plat/arm/board/fvp_r/fvp_r_bl1_main.c
+++ /dev/null

@@ -1,247 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include "../../../../bl1/bl1_private.h"
-#include <arch.h>
-#include <arch_features.h>
-#include <arch_helpers.h>
-#include <bl1/bl1.h>
-#include <common/bl_common.h>
-#include <common/build_message.h>
-#include <common/debug.h>
-#include <drivers/auth/auth_mod.h>
-#include <drivers/console.h>
-#include <lib/cpus/errata.h>
-#include <lib/utils.h>
-#include <smccc_helpers.h>
-#include <tools_share/uuid.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <platform_def.h>
-
-
-void cm_prepare_el2_exit(void);
-
-void bl1_run_next_image(const struct entry_point_info *bl_ep_info);
-
-/*******************************************************************************
- * Function to perform late architectural and platform specific initialization.
- * It also queries the platform to load and run next BL image. Only called
- * by the primary cpu after a cold boot.
- ******************************************************************************/
-void bl1_transfer_bl33(void)
-{
-	unsigned int image_id;
-
-	/* Get the image id of next image to load and run. */
-	image_id = bl1_plat_get_next_image_id();
-
-#if !ARM_DISABLE_TRUSTED_WDOG
-	/* Disable watchdog before leaving BL1 */
-	plat_arm_secure_wdt_stop();
-#endif
-
-	bl1_run_next_image(&bl1_plat_get_image_desc(image_id)->ep_info);
-}
-
-/*******************************************************************************
- * This function locates and loads the BL33 raw binary image in the trusted SRAM.
- * Called by the primary cpu after a cold boot.
- * TODO: Add support for alternative image load mechanism e.g using virtio/elf
- * loader etc.
- ******************************************************************************/
-void bl1_load_bl33(void)
-{
-	image_desc_t *desc;
-	image_info_t *info;
-	int err;
-
-	/* Get the image descriptor */
-	desc = bl1_plat_get_image_desc(BL33_IMAGE_ID);
-	assert(desc != NULL);
-
-	/* Get the image info */
-	info = &desc->image_info;
-	INFO("BL1: Loading BL33\n");
-
-	err = bl1_plat_handle_pre_image_load(BL33_IMAGE_ID);
-	if (err != 0) {
-		ERROR("Failure in pre image load handling of BL33 (%d)\n", err);
-		plat_error_handler(err);
-	}
-
-	err = load_auth_image(BL33_IMAGE_ID, info);
-	if (err != 0) {
-		ERROR("Failed to load BL33 firmware.\n");
-		plat_error_handler(err);
-	}
-
-	/* Allow platform to handle image information. */
-	err = bl1_plat_handle_post_image_load(BL33_IMAGE_ID);
-	if (err != 0) {
-		ERROR("Failure in post image load handling of BL33 (%d)\n", err);
-		plat_error_handler(err);
-	}
-
-	NOTICE("BL1: Booting BL33\n");
-}
-
-/*******************************************************************************
- * This function prepares for entry to BL33
- ******************************************************************************/
-void bl1_prepare_next_image(unsigned int image_id)
-{
-	unsigned int mode = MODE_EL1;
-	image_desc_t *desc;
-	entry_point_info_t *next_bl_ep;
-
-#if CTX_INCLUDE_AARCH32_REGS
-	/*
-	 * Ensure that the build flag to save AArch32 system registers in CPU
-	 * context is not set for AArch64-only platforms.
-	 */
-	if (el_implemented(1) == EL_IMPL_A64ONLY) {
-		ERROR("EL1 supports AArch64-only. Please set build flag %s",
-				"CTX_INCLUDE_AARCH32_REGS = 0\n");
-		panic();
-	}
-#endif
-
-	/* Get the image descriptor. */
-	desc = bl1_plat_get_image_desc(image_id);
-	assert(desc != NULL);
-
-	/* Get the entry point info. */
-	next_bl_ep = &desc->ep_info;
-
-	/* FVP-R is only secure */
-	assert(GET_SECURITY_STATE(next_bl_ep->h.attr) == SECURE);
-
-	/* Prepare the SPSR for the next BL image. */
-	next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
-		(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-
-	/* Allow platform to make change */
-	bl1_plat_set_ep_info(image_id, next_bl_ep);
-
-	/* Prepare context for the next EL */
-	cm_prepare_el2_exit();
-
-	/* Indicate that image is in execution state. */
-	desc->state = IMAGE_STATE_EXECUTED;
-
-	print_entry_point_info(next_bl_ep);
-}
-
-/*******************************************************************************
- * Setup function for BL1.
- ******************************************************************************/
-void bl1_setup(void)
-{
-	/* Perform early platform-specific setup */
-	bl1_early_platform_setup();
-
-	/* Perform late platform-specific setup */
-	bl1_plat_arch_setup();
-}
-
-/*******************************************************************************
- * Function to perform late architectural and platform specific initialization.
- * It also queries the platform to load and run next BL image. Only called
- * by the primary cpu after a cold boot.
- ******************************************************************************/
-void bl1_main(void)
-{
-	unsigned int image_id;
-
-	/* Announce our arrival */
-	NOTICE(FIRMWARE_WELCOME_STR);
-	NOTICE("BL1: %s\n", build_version_string);
-	NOTICE("BL1: %s\n", build_message);
-
-	INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
-
-	print_errata_status();
-
-#if ENABLE_ASSERTIONS
-	u_register_t val;
-	/*
-	 * Ensure that MMU/Caches and coherency are turned on
-	 */
-	val = read_sctlr_el2();
-
-	assert((val & SCTLR_M_BIT) != 0U);
-	assert((val & SCTLR_C_BIT) != 0U);
-	assert((val & SCTLR_I_BIT) != 0U);
-	/*
-	 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
-	 * provided platform value
-	 */
-	val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
-	/*
-	 * If CWG is zero, then no CWG information is available but we can
-	 * at least check the platform value is less than the architectural
-	 * maximum.
-	 */
-	if (val != 0) {
-		assert(SIZE_FROM_LOG2_WORDS(val) == CACHE_WRITEBACK_GRANULE);
-	} else {
-		assert(MAX_CACHE_LINE_SIZE >= CACHE_WRITEBACK_GRANULE);
-	}
-#endif /* ENABLE_ASSERTIONS */
-
-	/* Perform remaining generic architectural setup from ELmax */
-	bl1_arch_setup();
-
-#if TRUSTED_BOARD_BOOT
-	/* Initialize authentication module */
-	auth_mod_init();
-#endif /* TRUSTED_BOARD_BOOT */
-
-	/* Perform platform setup in BL1. */
-	bl1_platform_setup();
-
-	/* Get the image id of next image to load and run. */
-	image_id = bl1_plat_get_next_image_id();
-
-	/*
-	 * We currently interpret any image id other than
-	 * BL2_IMAGE_ID as the start of firmware update.
-	 */
-	if (image_id == BL33_IMAGE_ID) {
-		bl1_load_bl33();
-	} else {
-		NOTICE("BL1-FWU: *******FWU Process Started*******\n");
-	}
-
-	bl1_prepare_next_image(image_id);
-
-	console_flush();
-
-	bl1_transfer_bl33();
-}
-
-/*******************************************************************************
- * Function called just before handing over to the next BL to inform the user
- * about the boot progress. In debug mode, also print details about the BL
- * image's execution context.
- ******************************************************************************/
-void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
-{
-	NOTICE("BL1: Booting BL31\n");
-	print_entry_point_info(bl_ep_info);
-}
-
-#if SPIN_ON_BL1_EXIT
-void print_debug_loop_message(void)
-{
-	NOTICE("BL1: Debug loop, spinning forever\n");
-	NOTICE("BL1: Please connect the debugger to continue\n");
-}
-#endif

diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
deleted file mode 100644
index dcf5e04..0000000
--- a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
+++ /dev/null

@@ -1,245 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* Use the xlat_tables_v2 data structures: */
-#define XLAT_TABLES_LIB_V2	1
-
-#include <assert.h>
-
-#include <bl1/bl1.h>
-#include <common/tbbr/tbbr_img_def.h>
-#include <drivers/arm/sp805.h>
-#include <lib/fconf/fconf.h>
-#include <lib/fconf/fconf_dyn_cfg_getter.h>
-#include <lib/xlat_mpu/xlat_mpu.h>
-
-#include "fvp_r_private.h"
-#include <plat/arm/common/arm_config.h>
-#include <plat/arm/common/arm_def.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-#define MAP_BL1_TOTAL		MAP_REGION_FLAT(			\
-					bl1_tzram_layout.total_base,	\
-					bl1_tzram_layout.total_size,	\
-					MT_MEMORY | MT_RW | MT_SECURE)
-/*
- * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
- * otherwise one region is defined containing both
- */
-#if SEPARATE_CODE_AND_RODATA
-#define MAP_BL1_RO		MAP_REGION_FLAT(			\
-					BL_CODE_BASE,			\
-					BL1_CODE_END - BL_CODE_BASE,	\
-					MT_CODE | MT_SECURE),		\
-				MAP_REGION_FLAT(			\
-					BL1_RO_DATA_BASE,		\
-					BL1_RO_DATA_END			\
-						- BL_RO_DATA_BASE,	\
-					MT_RO_DATA | MT_SECURE)
-#else
-#define MAP_BL1_RO		MAP_REGION_FLAT(			\
-					BL_CODE_BASE,			\
-					BL1_CODE_END - BL_CODE_BASE,	\
-					MT_CODE | MT_SECURE)
-#endif
-
-/* Data structure which holds the extents of the trusted SRAM for BL1*/
-static meminfo_t bl1_tzram_layout;
-
-struct meminfo *bl1_plat_sec_mem_layout(void)
-{
-	return &bl1_tzram_layout;
-}
-
-void arm_bl1_early_platform_setup(void)
-{
-
-#if !ARM_DISABLE_TRUSTED_WDOG
-	/* Enable watchdog */
-	plat_arm_secure_wdt_start();
-#endif
-
-	/* Initialize the console to provide early debug support */
-	arm_console_boot_init();
-
-	/* Allow BL1 to see the whole Trusted RAM */
-	bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
-	bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
-}
-
-/* Boolean variable to hold condition whether firmware update needed or not */
-static bool is_fwu_needed;
-
-/*******************************************************************************
- * Perform any BL1 specific platform actions.
- ******************************************************************************/
-void bl1_early_platform_setup(void)
-{
-	arm_bl1_early_platform_setup();
-
-	/* Initialize the platform config for future decision making */
-	fvp_config_setup();
-
-	/*
-	 * Initialize Interconnect for this cluster during cold boot.
-	 * No need for locks as no other CPU is active.
-	 */
-	fvp_interconnect_init();
-	/*
-	 * Enable coherency in Interconnect for the primary CPU's cluster.
-	 */
-	fvp_interconnect_enable();
-}
-
-void arm_bl1_plat_arch_setup(void)
-{
-	const mmap_region_t bl_regions[] = {
-		MAP_BL1_TOTAL,
-		MAP_BL1_RO,
-#if USE_ROMLIB
-		ARM_MAP_ROMLIB_CODE,
-		ARM_MAP_ROMLIB_DATA,
-#endif
-		/* DRAM1_region: */
-		MAP_REGION_FLAT(
-			PLAT_ARM_DRAM1_BASE,
-			PLAT_ARM_DRAM1_SIZE,
-			MT_MEMORY | MT_SECURE | MT_EXECUTE
-			| MT_RW | MT_NON_CACHEABLE),
-		/* NULL terminator: */
-		{0}
-	};
-
-	setup_page_tables(bl_regions, plat_arm_get_mmap());
-	enable_mpu_el2(0);
-
-	arm_setup_romlib();
-}
-
-void plat_arm_secure_wdt_start(void)
-{
-	sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
-}
-
-void plat_arm_secure_wdt_stop(void)
-{
-	sp805_stop(ARM_SP805_TWDG_BASE);
-}
-
-/*
- * Perform the platform specific architecture setup shared between
- * ARM standard platforms.
- */
-void arm_bl1_platform_setup(void)
-{
-	uint32_t fw_config_max_size;
-
-	/* Initialise the IO layer and register platform IO devices */
-	plat_arm_io_setup();
-
-	/* Check if we need FWU before further processing */
-	is_fwu_needed = plat_arm_bl1_fwu_needed();
-	if (is_fwu_needed) {
-		ERROR("Skip platform setup as FWU detected\n");
-		return;
-	}
-
-	/* Set global DTB info for fixed fw_config information */
-	fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
-	set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size,
-			FW_CONFIG_ID);
-
-	assert(bl1_plat_get_image_desc(BL33_IMAGE_ID) != NULL);
-
-	/*
-	 * Allow access to the System counter timer module and program
-	 * counter frequency for non secure images during FWU
-	 */
-#ifdef ARM_SYS_TIMCTL_BASE
-	arm_configure_sys_timer();
-#endif
-#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
-	write_cntfrq_el0(plat_get_syscnt_freq2());
-#endif
-}
-
-void bl1_platform_setup(void)
-{
-	arm_bl1_platform_setup();
-
-	/* Initialize System level generic or SP804 timer */
-	fvp_timer_init();
-}
-
-__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
-{
-	/* Setup the watchdog to reset the system as soon as possible */
-	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
-
-	while (true) {
-		wfi();
-	}
-}
-
-unsigned int bl1_plat_get_next_image_id(void)
-{
-	return  is_fwu_needed ? NS_BL1U_IMAGE_ID : BL33_IMAGE_ID;
-}
-
-/*
- * Returns BL33 image details.
- */
-struct image_desc *bl1_plat_get_image_desc(unsigned int image_id)
-{
-	static image_desc_t bl33_img_desc = BL33_IMAGE_DESC;
-
-	return &bl33_img_desc;
-}
-
-/*
- * This function populates the default arguments to BL33.
- * The BL33 memory layout structure is allocated and the
- * calculated layout is populated in arg1 to BL33.
- */
-int bl1_plat_handle_post_image_load(unsigned int image_id)
-{
-	meminfo_t *bl33_secram_layout;
-	meminfo_t *bl1_secram_layout;
-	image_desc_t *image_desc;
-	entry_point_info_t *ep_info;
-
-	if (image_id != BL33_IMAGE_ID) {
-		return 0;
-	}
-	/* Get the image descriptor */
-	image_desc = bl1_plat_get_image_desc(BL33_IMAGE_ID);
-	assert(image_desc != NULL);
-
-	/* Get the entry point info */
-	ep_info = &image_desc->ep_info;
-
-	/* Find out how much free trusted ram remains after BL1 load */
-	bl1_secram_layout = bl1_plat_sec_mem_layout();
-
-	/*
-	 * Create a new layout of memory for BL33 as seen by BL1 i.e.
-	 * tell it the amount of total and free memory available.
-	 * This layout is created at the first free address visible
-	 * to BL33. BL33 will read the memory layout before using its
-	 * memory for other purposes.
-	 */
-	bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
-
-	bl1_plat_calc_bl2_layout(bl1_secram_layout, bl33_secram_layout);
-
-	ep_info->args.arg1 = (uintptr_t)bl33_secram_layout;
-
-	VERBOSE("BL1: BL3 memory layout address = %p\n",
-		(void *) bl33_secram_layout);
-	return 0;
-}

diff --git a/plat/arm/board/fvp_r/fvp_r_common.c b/plat/arm/board/fvp_r/fvp_r_common.c
deleted file mode 100644
index edcf658..0000000
--- a/plat/arm/board/fvp_r/fvp_r_common.c
+++ /dev/null

@@ -1,289 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* This uses xlat_mpu, but tables are set up using V2 mmap_region_t */
-#define XLAT_TABLES_LIB_V2	1
-
-#include <assert.h>
-#include <common/debug.h>
-
-#include <drivers/arm/cci.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/arm/sp804_delay_timer.h>
-#include <drivers/generic_delay_timer.h>
-#include <lib/mmio.h>
-#include <lib/smccc.h>
-#include <lib/xlat_tables/xlat_tables_compat.h>
-#include <services/arm_arch_svc.h>
-
-#include "fvp_r_private.h"
-#include <plat/arm/common/arm_config.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-
-/* Defines for GIC Driver build time selection */
-#define FVP_R_GICV3		2
-
-/*******************************************************************************
- * arm_config holds the characteristics of the differences between the FVP_R
- * platforms. It will be populated during cold boot at each boot stage by the
- * primary before enabling the MPU (to allow interconnect configuration) &
- * used thereafter. Each BL will have its own copy to allow independent
- * operation.
- ******************************************************************************/
-arm_config_t arm_config;
-
-#define MAP_DEVICE0	MAP_REGION_FLAT(DEVICE0_BASE,			\
-					DEVICE0_SIZE,			\
-					MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DEVICE1	MAP_REGION_FLAT(DEVICE1_BASE,			\
-					DEVICE1_SIZE,			\
-					MT_DEVICE | MT_RW | MT_SECURE)
-
-/*
- * Need to be mapped with write permissions in order to set a new non-volatile
- * counter value.
- */
-#define MAP_DEVICE2	MAP_REGION_FLAT(DEVICE2_BASE,			\
-					DEVICE2_SIZE,			\
-					MT_DEVICE | MT_RW | MT_SECURE)
-
-/*
- * Table of memory regions for various BL stages to map using the MPU.
- * This doesn't include Trusted SRAM as setup_page_tables() already takes care
- * of mapping it.
- *
- * The flash needs to be mapped as writable in order to erase the FIP's Table of
- * Contents in case of unrecoverable error (see plat_error_handler()).
- */
-#ifdef IMAGE_BL1
-const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	V2M_MAP_FLASH0_RW,
-	V2M_MAP_IOFPGA,
-	MAP_DEVICE0,
-	MAP_DEVICE1,
-#if TRUSTED_BOARD_BOOT
-	/* To access the Root of Trust Public Key registers. */
-	MAP_DEVICE2,
-#endif
-	{0}
-};
-#endif
-
-ARM_CASSERT_MMAP
-
-static const int fvp_cci400_map[] = {
-	PLAT_FVP_R_CCI400_CLUS0_SL_PORT,
-	PLAT_FVP_R_CCI400_CLUS1_SL_PORT,
-};
-
-static const int fvp_cci5xx_map[] = {
-	PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT,
-	PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT,
-};
-
-static unsigned int get_interconnect_master(void)
-{
-	unsigned int master;
-	u_register_t mpidr;
-
-	mpidr = read_mpidr_el1();
-	master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
-		MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
-
-	assert(master < FVP_R_CLUSTER_COUNT);
-	return master;
-}
-
-/*******************************************************************************
- * Initialize the platform config for future decision making
- ******************************************************************************/
-void __init fvp_config_setup(void)
-{
-	unsigned int rev, hbi, bld, arch, sys_id;
-
-	arm_config.flags |= ARM_CONFIG_BASE_MMAP;
-	sys_id = mmio_read_32(V2M_FVP_R_SYSREGS_BASE + V2M_SYS_ID);
-	rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
-	hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
-	bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
-	arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
-
-	if (arch != ARCH_MODEL) {
-		ERROR("This firmware is for FVP_R models\n");
-		panic();
-	}
-
-	/*
-	 * The build field in the SYS_ID tells which variant of the GIC
-	 * memory is implemented by the model.
-	 */
-	switch (bld) {
-	case BLD_GIC_VE_MMAP:
-		ERROR("Legacy Versatile Express memory map for GIC %s",
-				"peripheral is not supported\n");
-		panic();
-		break;
-	case BLD_GIC_A53A57_MMAP:
-		break;
-	default:
-		ERROR("Unsupported board build %x\n", bld);
-		panic();
-	}
-
-	/*
-	 * The hbi field in the SYS_ID is 0x020 for the Base FVP_R & 0x010
-	 * for the Foundation FVP_R.
-	 */
-	switch (hbi) {
-	case HBI_FOUNDATION_FVP_R:
-		arm_config.flags = 0;
-
-		/*
-		 * Check for supported revisions of Foundation FVP_R
-		 * Allow future revisions to run but emit warning diagnostic
-		 */
-		switch (rev) {
-		case REV_FOUNDATION_FVP_R_V2_0:
-		case REV_FOUNDATION_FVP_R_V2_1:
-		case REV_FOUNDATION_FVP_R_v9_1:
-		case REV_FOUNDATION_FVP_R_v9_6:
-			break;
-		default:
-			WARN("Unrecognized Foundation FVP_R revision %x\n", rev);
-			break;
-		}
-		break;
-	case HBI_BASE_FVP_R:
-		arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
-
-		/*
-		 * Check for supported revisions
-		 * Allow future revisions to run but emit warning diagnostic
-		 */
-		switch (rev) {
-		case REV_BASE_FVP_R_V0:
-			arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
-			break;
-		default:
-			WARN("Unrecognized Base FVP_R revision %x\n", rev);
-			break;
-		}
-		break;
-	default:
-		ERROR("Unsupported board HBI number 0x%x\n", hbi);
-		panic();
-	}
-
-	/*
-	 * We assume that the presence of MT bit, and therefore shifted
-	 * affinities, is uniform across the platform: either all CPUs, or no
-	 * CPUs implement it.
-	 */
-	if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) {
-		arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
-	}
-}
-
-
-void __init fvp_interconnect_init(void)
-{
-	uintptr_t cci_base = 0U;
-	const int *cci_map = NULL;
-	unsigned int map_size = 0U;
-
-	/* Initialize the right interconnect */
-	if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
-		cci_base = PLAT_FVP_R_CCI5XX_BASE;
-		cci_map = fvp_cci5xx_map;
-		map_size = ARRAY_SIZE(fvp_cci5xx_map);
-	} else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
-		cci_base = PLAT_FVP_R_CCI400_BASE;
-		cci_map = fvp_cci400_map;
-		map_size = ARRAY_SIZE(fvp_cci400_map);
-	} else {
-		return;
-	}
-
-	assert(cci_base != 0U);
-	assert(cci_map != NULL);
-	cci_init(cci_base, cci_map, map_size);
-}
-
-void fvp_interconnect_enable(void)
-{
-	unsigned int master;
-
-	if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
-				 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
-		master = get_interconnect_master();
-		cci_enable_snoop_dvm_reqs(master);
-	}
-}
-
-void fvp_interconnect_disable(void)
-{
-	unsigned int master;
-
-	if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
-				 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
-		master = get_interconnect_master();
-		cci_disable_snoop_dvm_reqs(master);
-	}
-}
-
-#if TRUSTED_BOARD_BOOT
-int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
-{
-	assert(heap_addr != NULL);
-	assert(heap_size != NULL);
-
-	return arm_get_mbedtls_heap(heap_addr, heap_size);
-}
-#endif
-
-void fvp_timer_init(void)
-{
-#if USE_SP804_TIMER
-	/* Enable the clock override for SP804 timer 0, which means that no
-	 * clock dividers are applied and the raw (35MHz) clock will be used.
-	 */
-	mmio_write_32(V2M_SP810_BASE, FVP_R_SP810_CTRL_TIM0_OV);
-
-	/* Initialize delay timer driver using SP804 dual timer 0 */
-	sp804_timer_init(V2M_SP804_TIMER0_BASE,
-			SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
-#else
-	generic_delay_timer_init();
-
-	/* Enable System level generic timer */
-	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
-			CNTCR_FCREQ(0U) | CNTCR_EN);
-#endif /* USE_SP804_TIMER */
-}
-
-/* Get SOC version */
-int32_t plat_get_soc_version(void)
-{
-	return (int32_t)
-		((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
-		 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
-		 | FVP_R_SOC_ID);
-}
-
-/* Get SOC revision */
-int32_t plat_get_soc_revision(void)
-{
-	unsigned int sys_id;
-
-	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
-	return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
-			V2M_SYS_ID_REV_MASK);
-}

diff --git a/plat/arm/board/fvp_r/fvp_r_context_mgmt.c b/plat/arm/board/fvp_r/fvp_r_context_mgmt.c
deleted file mode 100644
index d172d2d..0000000
--- a/plat/arm/board/fvp_r/fvp_r_context_mgmt.c
+++ /dev/null

@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-
-/************************************************************
- * For R-class everything is in secure world.
- * Prepare the CPU system registers for first entry into EL1
- ************************************************************/
-void cm_prepare_el2_exit(void)
-{
-	uint64_t hcr_el2 = 0U;
-
-	/*
-	 * The use of ARMv8.3 pointer authentication (PAuth) is governed
-	 * by fields in HCR_EL2, which trigger a 'trap to EL2' if not
-	 * enabled. This register initialized at boot up, update PAuth
-	 * bits.
-	 *
-	 * HCR_API_BIT: Set to one to disable traps to EL2 if lower ELs
-	 * access PAuth registers
-	 *
-	 * HCR_APK_BIT: Set to one to disable traps to EL2 if lower ELs
-	 * access PAuth instructions
-	 */
-	hcr_el2 = read_hcr_el2();
-	write_hcr_el2(hcr_el2 | HCR_API_BIT | HCR_APK_BIT);
-
-	/*
-	 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN
-	 * on reset and are set to zero except for field(s) listed below.
-	 *
-	 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to EL2
-	 * if lower ELs accesses to the physical timer registers.
-	 *
-	 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to EL2
-	 * if lower ELs access to the physical counter registers.
-	 */
-	write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
-
-	/*
-	 * On Armv8-R, the EL1&0 memory system architecture is configurable
-	 * as a VMSA or PMSA. All the fields architecturally UNKNOWN on reset
-	* and are set to zero except for field listed below.
-	*
-	* VCTR_EL2.MSA: Set to one to ensure the VMSA is enabled so that
-	* rich OS can boot.
-	*/
-	write_vtcr_el2(VTCR_RESET_VAL | VTCR_EL2_MSA);
-}

diff --git a/plat/arm/board/fvp_r/fvp_r_debug.S b/plat/arm/board/fvp_r/fvp_r_debug.S
deleted file mode 100644
index cc5ffc0..0000000
--- a/plat/arm/board/fvp_r/fvp_r_debug.S
+++ /dev/null

@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/debug.h>
-
-	.globl el2_panic
-
-	/***********************************************************
-	 * The common implementation of el3_panic for all BL stages
-	 ***********************************************************/
-
-.section .rodata.panic_str, "aS"
-	panic_msg: .asciz "PANIC at PC : 0x"
-
-/*
- * el2_panic will be redefined by the
- * crash reporting mechanism (if enabled)
- */
-el2_panic:
-	mov	x6, x30
-	bl	plat_crash_console_init
-
-	/* Check if the console is initialized */
-	cbz	x0, _panic_handler
-
-	/* The console is initialized */
-	adr	x4, panic_msg
-	bl	asm_print_str
-	mov	x4, x6
-
-	/* The panic location is lr -4 */
-	sub	x4, x4, #4
-	bl	asm_print_hex
-
-	bl	plat_crash_console_flush
-
-_panic_handler:
-	/* Pass to plat_panic_handler the address from where el2_panic was
-	 * called, not the address of the call from el2_panic.
-	 */
-	mov	x30, x6
-	b	plat_panic_handler

diff --git a/plat/arm/board/fvp_r/fvp_r_def.h b/plat/arm/board/fvp_r/fvp_r_def.h
deleted file mode 100644
index eda39cf..0000000
--- a/plat/arm/board/fvp_r/fvp_r_def.h
+++ /dev/null

@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FVP_R_DEF_H
-#define FVP_R_DEF_H
-
-#include <lib/utils_def.h>
-
-/******************************************************************************
- * FVP-R topology constants
- *****************************************************************************/
-#define FVP_R_CLUSTER_COUNT		2
-#define FVP_R_MAX_CPUS_PER_CLUSTER	4
-#define FVP_R_MAX_PE_PER_CPU		1
-#define FVP_R_PRIMARY_CPU		0x0
-
-/******************************************************************************
- * Definition of platform soc id
- *****************************************************************************/
-#define FVP_R_SOC_ID			0
-
-/*******************************************************************************
- * FVP_R memory map related constants
- ******************************************************************************/
-
-#define FLASH1_BASE			UL(0x8c000000)
-#define FLASH1_SIZE			UL(0x04000000)
-
-#define PSRAM_BASE			UL(0x94000000)
-#define PSRAM_SIZE			UL(0x04000000)
-
-#define VRAM_BASE			UL(0x98000000)
-#define VRAM_SIZE			UL(0x02000000)
-
-/* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE			UL(0xa0000000)
-#define DEVICE0_SIZE			UL(0x0c200000)
-
-/*
- *  In case of FVP_R models with CCN, the CCN register space overlaps into
- *  the NSRAM area.
- */
-#define DEVICE1_BASE			UL(0xae000000)
-#define DEVICE1_SIZE			UL(0x1A00000)
-
-#define NSRAM_BASE			UL(0xae000000)
-#define NSRAM_SIZE			UL(0x10000)
-/* Devices in the second GB */
-#define DEVICE2_BASE			UL(0xffe00000)
-#define DEVICE2_SIZE			UL(0x00200000)
-
-#define PCIE_EXP_BASE			UL(0xc0000000)
-#define TZRNG_BASE			UL(0x7fe60000)
-
-/* Non-volatile counters */
-#define TRUSTED_NVCTR_BASE		UL(0xffe70000)
-#define TFW_NVCTR_BASE			(TRUSTED_NVCTR_BASE + UL(0x0000))
-#define TFW_NVCTR_SIZE			UL(4)
-#define NTFW_CTR_BASE			(TRUSTED_NVCTR_BASE + UL(0x0004))
-#define NTFW_CTR_SIZE			UL(4)
-
-/* Keys */
-#define SOC_KEYS_BASE			UL(0xffe80000)
-#define TZ_PUB_KEY_HASH_BASE		(SOC_KEYS_BASE + UL(0x0000))
-#define TZ_PUB_KEY_HASH_SIZE		UL(32)
-#define HU_KEY_BASE			(SOC_KEYS_BASE + UL(0x0020))
-#define HU_KEY_SIZE			UL(16)
-#define END_KEY_BASE			(SOC_KEYS_BASE + UL(0x0044))
-#define END_KEY_SIZE			UL(32)
-
-/* Constants to distinguish FVP_R type */
-#define HBI_BASE_FVP_R			U(0x020)
-#define REV_BASE_FVP_R_V0		U(0x0)
-#define REV_BASE_FVP_R_REVC		U(0x2)
-
-#define HBI_FOUNDATION_FVP_R		U(0x010)
-#define REV_FOUNDATION_FVP_R_V2_0	U(0x0)
-#define REV_FOUNDATION_FVP_R_V2_1	U(0x1)
-#define REV_FOUNDATION_FVP_R_v9_1	U(0x2)
-#define REV_FOUNDATION_FVP_R_v9_6	U(0x3)
-
-#define BLD_GIC_VE_MMAP			U(0x0)
-#define BLD_GIC_A53A57_MMAP		U(0x1)
-
-#define ARCH_MODEL			U(0x1)
-
-/* FVP_R Power controller base address*/
-#define PWRC_BASE			UL(0x1c100000)
-
-/* FVP_R SP804 timer frequency is 35 MHz*/
-#define SP804_TIMER_CLKMULT		1
-#define SP804_TIMER_CLKDIV		35
-
-/* SP810 controller. FVP_R specific flags */
-#define FVP_R_SP810_CTRL_TIM0_OV		BIT_32(16)
-#define FVP_R_SP810_CTRL_TIM1_OV		BIT_32(18)
-#define FVP_R_SP810_CTRL_TIM2_OV		BIT_32(20)
-#define FVP_R_SP810_CTRL_TIM3_OV		BIT_32(22)
-
-#endif /* FVP_R_DEF_H */

diff --git a/plat/arm/board/fvp_r/fvp_r_err.c b/plat/arm/board/fvp_r/fvp_r_err.c
deleted file mode 100644
index 7ee752b..0000000
--- a/plat/arm/board/fvp_r/fvp_r_err.c
+++ /dev/null

@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <errno.h>
-
-#include <common/debug.h>
-#include <drivers/arm/sp805.h>
-#include <drivers/cfi/v2m_flash.h>
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-/*
- * FVP_R error handler
- */
-__dead2 void plat_arm_error_handler(int err)
-{
-	int ret;
-
-	switch (err) {
-	case -ENOENT:
-	case -EAUTH:
-		/* Image load or authentication error. Erase the ToC */
-		INFO("Erasing FIP ToC from flash...\n");
-		(void)nor_unlock(PLAT_ARM_FLASH_IMAGE_BASE);
-		ret = nor_word_program(PLAT_ARM_FLASH_IMAGE_BASE, 0);
-		if (ret != 0) {
-			ERROR("Cannot erase ToC\n");
-		} else {
-			INFO("Done\n");
-		}
-		break;
-	default:
-		/* Unexpected error */
-		break;
-	}
-
-	(void)console_flush();
-
-	/* Setup the watchdog to reset the system as soon as possible */
-	sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
-
-	while (true) {
-		wfi();
-	}
-}

diff --git a/plat/arm/board/fvp_r/fvp_r_helpers.S b/plat/arm/board/fvp_r/fvp_r_helpers.S
deleted file mode 100644
index ba85777..0000000
--- a/plat/arm/board/fvp_r/fvp_r_helpers.S
+++ /dev/null

@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <drivers/arm/fvp/fvp_pwrc.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/arm/gicv3.h>
-
-#include <platform_def.h>
-
-
-	.globl	plat_secondary_cold_boot_setup
-	.globl	plat_get_my_entrypoint
-	.globl	plat_is_my_cpu_primary
-
-	/* -----------------------------------------------------
-	 * void plat_secondary_cold_boot_setup (void);
-	 *
-	 * This function performs any platform specific actions
-	 * needed for a secondary cpu after a cold reset e.g
-	 * mark the cpu's presence, mechanism to place it in a
-	 * holding pen etc.
-	 * TODO: Should we read the PSYS register to make sure
-	 * that the request has gone through.
-	 * -----------------------------------------------------
-	 */
-func plat_secondary_cold_boot_setup
-	/* ---------------------------------------------
-	 * Power down this cpu.
-	 * TODO: Do we need to worry about powering the
-	 * cluster down as well here? That will need
-	 * locks which we won't have unless an elf-
-	 * loader zeroes out the zi section.
-	 * ---------------------------------------------
-	 */
-	mrs	x0, mpidr_el1
-	mov_imm	x1, PWRC_BASE
-	str	w0, [x1, #PPOFFR_OFF]
-
-	/* ---------------------------------------------
-	 * There is no sane reason to come out of this
-	 * wfi so panic if we do. This cpu will be pow-
-	 * ered on and reset by the cpu_on pm api
-	 * ---------------------------------------------
-	 */
-	dsb	sy
-	wfi
-	no_ret	plat_panic_handler
-endfunc plat_secondary_cold_boot_setup
-
-	/* ---------------------------------------------------------------------
-	 * uintptr_t plat_get_my_entrypoint (void);
-	 *
-	 * Main job of this routine is to distinguish between a cold and warm
-	 * boot. On FVP_R, this information can be queried from the power
-	 * controller. The Power Control SYS Status Register (PSYSR) indicates
-	 * the wake-up reason for the CPU.
-	 *
-	 * For a cold boot, return 0.
-	 * For a warm boot, read the mailbox and return the address it contains.
-	 *
-	 * TODO: PSYSR is a common register and should be
-	 * 	accessed using locks. Since it is not possible
-	 * 	to use locks immediately after a cold reset
-	 * 	we are relying on the fact that after a cold
-	 * 	reset all cpus will read the same WK field
-	 * ---------------------------------------------------------------------
-	 */
-func plat_get_my_entrypoint
-	/* ---------------------------------------------------------------------
-	 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
-	 * WakeRequest signal" then it is a warm boot.
-	 * ---------------------------------------------------------------------
-	 */
-	mrs	x2, mpidr_el1
-	mov_imm	x1, PWRC_BASE
-	str	w2, [x1, #PSYSR_OFF]
-	ldr	w2, [x1, #PSYSR_OFF]
-	ubfx	w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
-	cmp	w2, #WKUP_PPONR
-	beq	warm_reset
-	cmp	w2, #WKUP_GICREQ
-	beq	warm_reset
-
-	/* Cold reset */
-	mov	x0, #0
-	ret
-
-warm_reset:
-	/* ---------------------------------------------------------------------
-	 * A mailbox is maintained in the trusted SRAM. It is flushed out of the
-	 * caches after every update using normal memory so it is safe to read
-	 * it here with SO attributes.
-	 * ---------------------------------------------------------------------
-	 */
-	mov_imm	x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
-	ldr	x0, [x0]
-	cbz	x0, _panic_handler
-	ret
-
-	/* ---------------------------------------------------------------------
-	 * The power controller indicates this is a warm reset but the mailbox
-	 * is empty. This should never happen!
-	 * ---------------------------------------------------------------------
-	 */
-_panic_handler:
-	no_ret	plat_panic_handler
-endfunc plat_get_my_entrypoint
-
-	/* -----------------------------------------------------
-	 * unsigned int plat_is_my_cpu_primary (void);
-	 *
-	 * Find out whether the current cpu is the primary
-	 * cpu.
-	 * -----------------------------------------------------
-	 */
-func plat_is_my_cpu_primary
-	mrs	x0, mpidr_el1
-	mov_imm	x1, MPIDR_AFFINITY_MASK
-	and	x0, x0, x1
-	cmp	x0, #FVP_R_PRIMARY_CPU
-	cset	w0, eq
-	ret
-endfunc plat_is_my_cpu_primary

diff --git a/plat/arm/board/fvp_r/fvp_r_io_storage.c b/plat/arm/board/fvp_r/fvp_r_io_storage.c
deleted file mode 100644
index 3b44828..0000000
--- a/plat/arm/board/fvp_r/fvp_r_io_storage.c
+++ /dev/null

@@ -1,105 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_semihosting.h>
-#include <drivers/io/io_storage.h>
-#include <lib/semihosting.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/common_def.h>
-
-/* Semihosting filenames */
-#define BL33_IMAGE_NAME			"bl33.bin"
-
-#if TRUSTED_BOARD_BOOT
-#define TRUSTED_KEY_CERT_NAME		"trusted_key.crt"
-#define NT_FW_KEY_CERT_NAME		"nt_fw_key.crt"
-#define NT_FW_CONTENT_CERT_NAME		"nt_fw_content.crt"
-#endif /* TRUSTED_BOARD_BOOT */
-
-/* IO devices */
-static const io_dev_connector_t *sh_dev_con;
-static uintptr_t sh_dev_handle;
-
-static const io_file_spec_t sh_file_spec[] = {
-	[BL33_IMAGE_ID] = {
-		.path = BL33_IMAGE_NAME,
-		.mode = FOPEN_MODE_RB
-	},
-#if TRUSTED_BOARD_BOOT
-	[TRUSTED_KEY_CERT_ID] = {
-		.path = TRUSTED_KEY_CERT_NAME,
-		.mode = FOPEN_MODE_RB
-	},
-	[NON_TRUSTED_FW_KEY_CERT_ID] = {
-		.path = NT_FW_KEY_CERT_NAME,
-		.mode = FOPEN_MODE_RB
-	},
-	[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
-		.path = NT_FW_CONTENT_CERT_NAME,
-		.mode = FOPEN_MODE_RB
-	},
-#endif /* TRUSTED_BOARD_BOOT */
-};
-
-
-static int open_semihosting(const uintptr_t spec)
-{
-	int result;
-	uintptr_t local_image_handle;
-
-	/* See if the file exists on semi-hosting.*/
-	result = io_dev_init(sh_dev_handle, (uintptr_t)NULL);
-	if (result == 0) {
-		result = io_open(sh_dev_handle, spec, &local_image_handle);
-		if (result == 0) {
-			VERBOSE("Using Semi-hosting IO\n");
-			io_close(local_image_handle);
-		}
-	}
-	return result;
-}
-
-void plat_arm_io_setup(void)
-{
-	int io_result;
-
-	io_result = arm_io_setup();
-	if (io_result < 0) {
-		panic();
-	}
-
-	/* Register the additional IO devices on this platform */
-	io_result = register_io_dev_sh(&sh_dev_con);
-	if (io_result < 0) {
-		panic();
-	}
-
-	/* Open connections to devices and cache the handles */
-	io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle);
-	if (io_result < 0) {
-		panic();
-	}
-}
-
-/*
- * FVP_R provides semihosting as an alternative to load images
- */
-int plat_arm_get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle,
-				  uintptr_t *image_spec)
-{
-	int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]);
-
-	if (result == 0) {
-		*dev_handle = sh_dev_handle;
-		*image_spec = (uintptr_t)&sh_file_spec[image_id];
-	}
-
-	return result;
-}

diff --git a/plat/arm/board/fvp_r/fvp_r_misc_helpers.S b/plat/arm/board/fvp_r/fvp_r_misc_helpers.S
deleted file mode 100644
index 67ad164..0000000
--- a/plat/arm/board/fvp_r/fvp_r_misc_helpers.S
+++ /dev/null

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-
-	.globl	disable_mpu_el2
-	.globl	disable_mpu_icache_el2
-
-/* ---------------------------------------------------------------------------
- * Disable the MPU at EL2.
- * ---------------------------------------------------------------------------
- */
-
-func disable_mpu_el2
-	mov	x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
-do_disable_mpu_el2:
-	mrs	x0, sctlr_el2
-	bic	x0, x0, x1
-	msr	sctlr_el2, x0
-	isb	/* ensure MMU is off */
-	dsb	sy
-	ret
-endfunc disable_mpu_el2
-
-
-func disable_mpu_icache_el2
-	mov	x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
-	b	do_disable_mpu_el2
-endfunc disable_mpu_icache_el2

diff --git a/plat/arm/board/fvp_r/fvp_r_private.h b/plat/arm/board/fvp_r/fvp_r_private.h
deleted file mode 100644
index 48f6e89..0000000
--- a/plat/arm/board/fvp_r/fvp_r_private.h
+++ /dev/null

@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FVP_R_PRIVATE_H
-#define FVP_R_PRIVATE_H
-
-#include <plat/arm/common/plat_arm.h>
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-
-void fvp_config_setup(void);
-
-void fvp_interconnect_init(void);
-void fvp_interconnect_enable(void);
-void fvp_interconnect_disable(void);
-void fvp_timer_init(void);
-
-#endif /* FVP_R_PRIVATE_H */

diff --git a/plat/arm/board/fvp_r/fvp_r_stack_protector.c b/plat/arm/board/fvp_r/fvp_r_stack_protector.c
deleted file mode 100644
index 69b6312..0000000
--- a/plat/arm/board/fvp_r/fvp_r_stack_protector.c
+++ /dev/null

@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <fvp_r_arch_helpers.h>
-#include <plat/common/platform.h>
-
-#define RANDOM_CANARY_VALUE ((u_register_t) 8092347823957523895ULL)
-
-u_register_t plat_get_stack_protector_canary(void)
-{
-	/*
-	 * Ideally, a random number should be returned instead of the
-	 * combination of a timer's value and a compile-time constant. As the
-	 * FVP_R does not have any random number generator, this is better than
-	 * nothing but not necessarily really secure.
-	 */
-	return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
-}
-

diff --git a/plat/arm/board/fvp_r/fvp_r_trusted_boot.c b/plat/arm/board/fvp_r/fvp_r_trusted_boot.c
deleted file mode 100644
index de0b28f..0000000
--- a/plat/arm/board/fvp_r/fvp_r_trusted_boot.c
+++ /dev/null

@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <lib/fconf/fconf.h>
-#include <lib/mmio.h>
-#include <tools_share/tbbr_oid.h>
-
-#include <plat/arm/common/fconf_nv_cntr_getter.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier  ::=  SEQUENCE  {
- *     algorithm	OBJECT IDENTIFIER,
- *     parameters	ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- *     digestAlgorithm	AlgorithmIdentifier,
- *     digest		OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-			unsigned int *flags)
-{
-	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
-
-/*
- * Store a new non-volatile counter value.
- *
- * On some FVP_R versions, the non-volatile counters are read-only so this
- * function will always fail.
- *
- * Return: 0 = success, Otherwise = error
- */
-int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
-{
-	const char *oid;
-	uintptr_t nv_ctr_addr;
-
-	assert(cookie != NULL);
-
-	oid = (const char *)cookie;
-	if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) {
-		nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
-						TRUSTED_NV_CTR_ID);
-	} else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
-		nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
-						NON_TRUSTED_NV_CTR_ID);
-	} else {
-		return 1;
-	}
-
-	mmio_write_32(nv_ctr_addr, nv_ctr);
-
-	/*
-	 * If the FVP_R models a locked counter then its value cannot be updated
-	 * and the above write operation has been silently ignored.
-	 */
-	return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1;
-}

diff --git a/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h b/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h
deleted file mode 100644
index 92bf484..0000000
--- a/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FVP_R_ARCH_HELPERS_H
-#define FVP_R_ARCH_HELPERS_H
-
-#include <arch_helpers.h>
-
-/*******************************************************************************
- * MPU register definitions
- ******************************************************************************/
-#define MPUIR_EL2		S3_4_C0_C0_4
-#define PRBAR_EL2		S3_4_C6_C8_0
-#define PRLAR_EL2		S3_4_C6_C8_1
-#define PRSELR_EL2		S3_4_C6_C2_1
-#define PRENR_EL2		S3_4_C6_C1_1
-
-/* v8-R64 MPU registers */
-DEFINE_RENAME_SYSREG_RW_FUNCS(mpuir_el2, MPUIR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prenr_el2, PRENR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prselr_el2, PRSELR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prbar_el2, PRBAR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prlar_el2, PRLAR_EL2)
-
-#endif /* FVP_R_ARCH_HELPERS_H */

diff --git a/plat/arm/board/fvp_r/include/platform_def.h b/plat/arm/board/fvp_r/include/platform_def.h
deleted file mode 100644
index 1fdec15..0000000
--- a/plat/arm/board/fvp_r/include/platform_def.h
+++ /dev/null

@@ -1,261 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FVP_R_PLATFORM_DEF_H
-#define FVP_R_PLATFORM_DEF_H
-
-#define PLAT_V2M_OFFSET			0x80000000
-
-#define BL33_IMAGE_DESC {				\
-	.image_id = BL33_IMAGE_ID,			\
-	SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,	\
-		VERSION_2, image_info_t, 0),		\
-	.image_info.image_base = PLAT_ARM_DRAM1_BASE + 0x1000,		\
-	.image_info.image_max_size = UL(0x3ffff000), \
-	SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,	\
-		VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\
-	.ep_info.pc = PLAT_ARM_DRAM1_BASE + 0x1000,				\
-	.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),	\
-}
-
-#include "../fvp_r_def.h"
-#include <drivers/arm/tzc400.h>
-#include <lib/utils_def.h>
-#include <plat/arm/board/common/v2m_def.h>
-
-/* These are referenced by arm_def.h #included next, so #define first. */
-#define PLAT_ARM_TRUSTED_ROM_BASE	UL(0x80000000)
-#define PLAT_ARM_TRUSTED_SRAM_BASE	UL(0x84000000)
-#define PLAT_ARM_TRUSTED_DRAM_BASE	UL(0x86000000)
-#define PLAT_ARM_DRAM1_BASE		ULL(0x0)
-#define PLAT_ARM_DRAM2_BASE		ULL(0x080000000)
-
-#define PLAT_HW_CONFIG_DTB_BASE		ULL(0x12000000)
-#define PLAT_ARM_SYS_CNTCTL_BASE	UL(0xaa430000)
-#define PLAT_ARM_SYS_CNTREAD_BASE	UL(0xaa800000)
-#define PLAT_ARM_SYS_TIMCTL_BASE	UL(0xaa810000)
-#define PLAT_ARM_SYS_CNT_BASE_S		UL(0xaa820000)
-#define PLAT_ARM_SYS_CNT_BASE_NS	UL(0xaa830000)
-#define PLAT_ARM_SP805_TWDG_BASE	UL(0xaa490000)
-
-#include <plat/arm/common/arm_def.h>
-#include <plat/common/common_def.h>
-
-
-/* Required to create plat_regions: */
-#define MIN_LVL_BLOCK_DESC	U(1)
-
-/* Required platform porting definitions */
-#define PLATFORM_CORE_COUNT  (U(FVP_R_CLUSTER_COUNT) * \
-			      U(FVP_R_MAX_CPUS_PER_CLUSTER) * \
-			      U(FVP_R_MAX_PE_PER_CPU))
-
-#define PLAT_NUM_PWR_DOMAINS (U(FVP_R_CLUSTER_COUNT) + \
-			      PLATFORM_CORE_COUNT + U(1))
-
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL2
-
-/*
- * Other platform porting definitions are provided by included headers
- */
-
-/*
- * Required ARM standard platform porting definitions
- */
-#define PLAT_ARM_CLUSTER_COUNT		U(FVP_R_CLUSTER_COUNT)
-#define PLAT_ARM_DRAM1_SIZE		ULL(0x7fffffff)
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	UL(0x00040000)	/* 256 KB */
-#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x04000000)	/* 64 MB */
-#define PLAT_ARM_TRUSTED_DRAM_SIZE	UL(0x02000000)	/* 32 MB */
-
-/* These two are defined thus in arm_def.h, but doesn't seem to see it... */
-#define PLAT_BL1_RO_LIMIT               (BL1_RO_BASE \
-					+ PLAT_ARM_TRUSTED_ROM_SIZE)
-
-/* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
-
-/* No SCP in FVP_R */
-#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x0)
-
-#define PLAT_ARM_DRAM2_SIZE		UL(0x80000000)
-
-#define PLAT_ARM_HW_CONFIG_SIZE		ULL(0x8000)
-
-#define ARM_DTB_DRAM_NS			MAP_REGION_FLAT(		\
-					PLAT_HW_CONFIG_DTB_BASE,	\
-					PLAT_ARM_HW_CONFIG_SIZE,	\
-					MT_MEMORY | MT_RO | MT_NS)
-
-#define V2M_FVP_R_SYSREGS_BASE		UL(0x9c010000)
-
-/*
- * Load address of BL33 for this platform port,
- * U-Boot specifically must be loaded at a 4K aligned address.
- */
-#define PLAT_ARM_NS_IMAGE_BASE		(PLAT_ARM_DRAM1_BASE + 0x1000)
-
-/*
- * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
- * plat_arm_mmap array defined for each BL stage.
- */
-#if !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES		11
-# define MAX_XLAT_TABLES		5
-#else
-# define PLAT_ARM_MMAP_ENTRIES		12
-# define MAX_XLAT_TABLES		6
-#endif
-# define N_MPU_REGIONS			16  /* number of MPU regions */
-# define ALL_MPU_EL2_REGIONS_USED	0xffffffff
-	/* this is the PRENR_EL2 value if all MPU regions are in use */
-
-/*
- * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
- * plus a little space for growth.
- */
-#define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xB000)
-
-/*
- * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
- */
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0xe000)
-#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0)
-#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0)
-#endif
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-#if COT_DESC_IN_DTB
-# define PLAT_ARM_MAX_BL2_SIZE	(UL(0x1E000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
-#else
-# define PLAT_ARM_MAX_BL2_SIZE	(UL(0x1D000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
-#endif
-#else
-# define PLAT_ARM_MAX_BL2_SIZE	(UL(0x13000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of
- * BL2 and BL1-RW
- */
-#define PLAT_ARM_MAX_BL31_SIZE		UL(0x3D000)
-
-/*
- * Size of cacheable stacks
- */
-#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE		UL(0x1000)
-# else
-#  define PLATFORM_STACK_SIZE		UL(0x500)
-# endif
-#endif
-
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
-
-/*
- * These nominally reserve the last block of flash for PSCI MEM PROTECT flag,
- * but no PSCI in FVP_R platform, so reserve nothing:
- */
-#define PLAT_ARM_FLASH_IMAGE_BASE	(PLAT_ARM_DRAM1_BASE + UL(0x40000000))
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(PLAT_ARM_DRAM1_SIZE - UL(0x40000000))
-
-#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-/*
- * PL011 related constants
- */
-#define PLAT_ARM_BOOT_UART_BASE		V2M_IOFPGA_UART0_BASE
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	V2M_IOFPGA_UART0_CLK_IN_HZ
-
-#define PLAT_ARM_RUN_UART_BASE		V2M_IOFPGA_UART1_BASE
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ	V2M_IOFPGA_UART1_CLK_IN_HZ
-
-#define PLAT_ARM_CRASH_UART_BASE	PLAT_ARM_RUN_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ	PLAT_ARM_RUN_UART_CLK_IN_HZ
-
-#define PLAT_ARM_TSP_UART_BASE		V2M_IOFPGA_UART2_BASE
-#define PLAT_ARM_TSP_UART_CLK_IN_HZ	V2M_IOFPGA_UART2_CLK_IN_HZ
-
-/* CCI related constants */
-#define PLAT_FVP_R_CCI400_BASE		UL(0xac090000)
-#define PLAT_FVP_R_CCI400_CLUS0_SL_PORT	3
-#define PLAT_FVP_R_CCI400_CLUS1_SL_PORT	4
-
-/* CCI-500/CCI-550 on Base platform */
-#define PLAT_FVP_R_CCI5XX_BASE		UL(0xaa000000)
-#define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT	5
-#define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT	6
-
-/* System timer related constants */
-#define PLAT_ARM_NSTIMER_FRAME_ID	U(1)
-
-/* Mailbox base address */
-#define PLAT_ARM_TRUSTED_MAILBOX_BASE	ARM_TRUSTED_SRAM_BASE
-
-
-/* TrustZone controller related constants
- *
- * Currently only filters 0 and 2 are connected on Base FVP_R.
- * Filter 0 : CPU clusters (no access to DRAM by default)
- * Filter 1 : not connected
- * Filter 2 : LCDs (access to VRAM allowed by default)
- * Filter 3 : not connected
- * Programming unconnected filters will have no effect at the
- * moment. These filter could, however, be connected in future.
- * So care should be taken not to configure the unused filters.
- *
- * Allow only non-secure access to all DRAM to supported devices.
- * Give access to the CPUs and Virtio. Some devices
- * would normally use the default ID so allow that too.
- */
-#define PLAT_ARM_TZC_BASE		UL(0xaa4a0000)
-#define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
-		TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT)	|	\
-		TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI)		|	\
-		TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP)		|	\
-		TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO)	|	\
-		TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_OLD))
-
-/*
- * GIC related constants to cater for both GICv2 and GICv3 instances of an
- * FVP_R. They could be overridden at runtime in case the FVP_R implements the
- * legacy VE memory map.
- */
-#define PLAT_ARM_GICD_BASE		BASE_GICD_BASE
-#define PLAT_ARM_GICR_BASE		BASE_GICR_BASE
-#define PLAT_ARM_GICC_BASE		BASE_GICC_BASE
-
-#define PLAT_ARM_SP_IMAGE_STACK_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +	\
-					 PLAT_SP_IMAGE_NS_BUF_SIZE)
-
-#define PLAT_SP_PRI			PLAT_RAS_PRI
-
-/*
- * Physical and virtual address space limits for MPU in AARCH64 & AARCH32 modes
- */
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
-
-#define ARM_SOC_CONTINUATION_SHIFT	U(24)
-#define ARM_SOC_IDENTIFICATION_SHIFT	U(16)
-
-#endif /* FVP_R_PLATFORM_DEF_H */

diff --git a/plat/arm/board/fvp_r/platform.mk b/plat/arm/board/fvp_r/platform.mk
deleted file mode 100644
index 71cb9e2..0000000
--- a/plat/arm/board/fvp_r/platform.mk
+++ /dev/null

@@ -1,100 +0,0 @@
-#
-# Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Only aarch64 ARCH supported for FVP_R
-ARCH	:= aarch64
-
-# Override to exclude BL2, BL2U, BL31, and BL33 for FVP_R
-override NEED_BL2	:= no
-override NEED_BL2U	:= no
-override NEED_BL31	:= no
-NEED_BL32		:= no
-
-override CTX_INCLUDE_AARCH32_REGS	:=	0
-
-# Use MPU-based memory management:
-XLAT_MPU_LIB_V1		:=	1
-
-# FVP R will not have more than 2 clusters so just use CCI interconnect
-FVP_R_INTERCONNECT_SOURCES	:= 	drivers/arm/cci/cci.c
-
-
-include plat/arm/board/common/board_common.mk
-include plat/arm/common/arm_common.mk
-
-PLAT_INCLUDES		+=	-Iplat/arm/board/fvp_r/include
-
-FVP_R_BL_COMMON_SOURCES	:=	plat/arm/board/fvp_r/fvp_r_common.c		\
-				plat/arm/board/fvp_r/fvp_r_context_mgmt.c	\
-				plat/arm/board/fvp_r/fvp_r_debug.S		\
-				plat/arm/board/fvp_r/fvp_r_err.c		\
-				plat/arm/board/fvp_r/fvp_r_helpers.S		\
-				plat/arm/board/fvp_r/fvp_r_misc_helpers.S
-
-FVP_R_BL1_SOURCES	:=	plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c	\
-				plat/arm/board/fvp_r/fvp_r_bl1_setup.c		\
-				plat/arm/board/fvp_r/fvp_r_io_storage.c		\
-				plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S	\
-				plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S	\
-				plat/arm/board/fvp_r/fvp_r_bl1_main.c
-
-FVP_R_CPU_LIBS		:=	lib/cpus/${ARCH}/aem_generic.S
-
-FVP_R_DYNC_CFG_SOURCES	:=	common/fdt_wrappers.c				\
-				plat/arm/common/arm_dyn_cfg.c
-
-ifeq (${TRUSTED_BOARD_BOOT},1)
-FVP_R_AUTH_SOURCES	:=	drivers/auth/auth_mod.c				\
-				drivers/auth/crypto_mod.c			\
-				drivers/auth/img_parser_mod.c			\
-				lib/fconf/fconf_tbbr_getter.c			\
-				plat/common/tbbr/plat_tbbr.c			\
-				drivers/auth/tbbr/tbbr_cot_bl1_r64.c		\
-				drivers/auth/tbbr/tbbr_cot_common.c		\
-				plat/arm/board/common/board_arm_trusted_boot.c	\
-				plat/arm/board/common/rotpk/arm_dev_rotpk.S	\
-				plat/arm/board/fvp_r/fvp_r_trusted_boot.c
-
-FVP_R_BL1_SOURCES	+=	${MBEDTLS_SOURCES}				\
-				${FVP_R_AUTH_SOURCES}
-endif
-
-ifeq (${USE_SP804_TIMER},1)
-FVP_R_BL_COMMON_SOURCES		+=	drivers/arm/sp804/sp804_delay_timer.c
-else
-FVP_R_BL_COMMON_SOURCES		+=	drivers/delay_timer/generic_delay_timer.c
-endif
-
-# Enable Activity Monitor Unit extensions by default
-ENABLE_FEAT_AMU			:=	2
-
-ifneq (${ENABLE_STACK_PROTECTOR},0)
-FVP_R_BL_COMMON_SOURCES	+=	plat/arm/board/fvp_r/fvp_r_stack_protector.c
-endif
-
-override BL1_SOURCES	:=	drivers/arm/sp805/sp805.c			\
-				drivers/cfi/v2m/v2m_flash.c			\
-				drivers/delay_timer/delay_timer.c		\
-				drivers/io/io_fip.c				\
-				drivers/io/io_memmap.c				\
-				drivers/io/io_storage.c				\
-				drivers/io/io_semihosting.c			\
-				lib/cpus/aarch64/cpu_helpers.S			\
-				lib/cpus/errata_report.c			\
-				lib/fconf/fconf_dyn_cfg_getter.c		\
-				lib/semihosting/semihosting.c			\
-				lib/semihosting/${ARCH}/semihosting_call.S	\
-				plat/arm/common/arm_bl1_setup.c			\
-				plat/arm/common/arm_err.c			\
-				plat/arm/common/arm_io_storage.c		\
-				plat/arm/common/fconf/arm_fconf_io.c		\
-				plat/common/plat_bl1_common.c			\
-				plat/common/aarch64/platform_up_stack.S		\
-				${FVP_R_BL1_SOURCES}				\
-				${FVP_R_BL_COMMON_SOURCES}			\
-				${FVP_R_CPU_LIBS}				\
-				${FVP_R_DYNC_CFG_SOURCES}			\
-				${FVP_R_INTERCONNECT_SOURCES}

diff --git a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
index cc29f36..3209a1c 100644
--- a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
+++ b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,7 +15,7 @@
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
 {
-	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+	arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Initialize the platform config for future decision making */
 	fvp_ve_config_setup();

diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index 79cf356..b1fcd52 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,12 +12,7 @@
 BL2_SOURCES		+=	drivers/arm/sp804/sp804_delay_timer.c
 endif
 
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-FVP_VE_GIC_SOURCES	:=	${GICV2_SOURCES}		\
-				plat/common/plat_gicv2.c	\
-				plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER		:=	2
 
 FVP_VE_SECURITY_SOURCES	:=	plat/arm/board/fvp_ve/fvp_ve_security.c
 

diff --git a/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c b/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c
index e6a1bbe..eba122f 100644
--- a/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c
+++ b/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,5 +11,5 @@
 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
-	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
 }

diff --git a/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk b/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk
index 4ca810d..db1a616 100644
--- a/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk
+++ b/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -18,5 +18,4 @@
 				plat/common/aarch32/platform_mp_stack.S		\
 				plat/common/plat_psci_common.c			\
 				${FVP_VE_CPU_LIBS}				\
-				${FVP_VE_GIC_SOURCES}				\
 				${FVP_VE_SECURITY_SOURCES}

diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 777729e..c8439e9 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -156,7 +156,7 @@
  */
 #if TRUSTED_BOARD_BOOT
 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE	(UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE	(UL(0x20000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA
 # define PLAT_ARM_MAX_BL2_SIZE	(UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
 #else

diff --git a/plat/arm/board/juno/juno_bl31_setup.c b/plat/arm/board/juno/juno_bl31_setup.c
index 7a0a6d9..2eec105 100644
--- a/plat/arm/board/juno/juno_bl31_setup.c
+++ b/plat/arm/board/juno/juno_bl31_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,7 @@
 		arg1 = soc_fw_config_info->config_addr;
 	}
 
-	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/*
 	 * Initialize Interconnect for this cluster during cold boot.

diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 9530498..38ba0ed 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk

@@ -1,17 +1,12 @@
 #
-# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 include common/fdt_wrappers.mk
 
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-JUNO_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-				plat/common/plat_gicv2.c		\
-				plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER		:=	2
 
 JUNO_INTERCONNECT_SOURCES	:=	drivers/arm/cci/cci.c		\
 					plat/arm/common/arm_cci.c
@@ -99,7 +94,6 @@
 				plat/arm/board/juno/juno_pm.c		\
 				plat/arm/board/juno/juno_topology.c	\
 				plat/arm/common/arm_nor_psci_mem_protect.c \
-				${JUNO_GIC_SOURCES}			\
 				${JUNO_INTERCONNECT_SOURCES}		\
 				${JUNO_SECURITY_SOURCES}
 

diff --git a/plat/arm/board/juno/sp_min/sp_min-juno.mk b/plat/arm/board/juno/sp_min/sp_min-juno.mk
index b3471c1..45a93c8 100644
--- a/plat/arm/board/juno/sp_min/sp_min-juno.mk
+++ b/plat/arm/board/juno/sp_min/sp_min-juno.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,7 +14,7 @@
 			plat/arm/board/juno/juno_topology.c	\
 			plat/arm/common/arm_nor_psci_mem_protect.c	\
 			plat/arm/soc/common/soc_css_security.c	\
-			${JUNO_GIC_SOURCES}			\
+			${GIC_SOURCES}				\
 			${JUNO_INTERCONNECT_SOURCES}		\
 			${JUNO_SECURITY_SOURCES}
 

diff --git a/plat/arm/board/juno/tsp/tsp-juno.mk b/plat/arm/board/juno/tsp/tsp-juno.mk
index be75c4d..c7debf1 100644
--- a/plat/arm/board/juno/tsp/tsp-juno.mk
+++ b/plat/arm/board/juno/tsp/tsp-juno.mk

@@ -1,12 +1,12 @@
 #
-# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 BL32_SOURCES		+=	plat/arm/board/juno/juno_topology.c	\
 				plat/arm/css/common/css_topology.c	\
-				${JUNO_GIC_SOURCES}			\
+				${GIC_SOURCES}				\
 				${JUNO_SECURITY_SOURCES}
 
 include plat/arm/common/tsp/arm_tsp.mk

diff --git a/plat/arm/board/morello/morello_pm.c b/plat/arm/board/morello/morello_pm.c
index fa7bd1d..30791cc 100644
--- a/plat/arm/board/morello/morello_pm.c
+++ b/plat/arm/board/morello/morello_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,5 +19,4 @@
 void morello_pwr_domain_off(const psci_power_state_t *target_state)
 {
 	css_pwr_domain_off(target_state);
-	plat_arm_gic_redistif_off();
 }

diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 8211c26..7653583 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk

@@ -18,15 +18,9 @@
 MORELLO_CPU_SOURCES	:=	lib/cpus/aarch64/rainier.S
 
 # GIC-600 configuration
+USE_GIC_DRIVER		:=	3
 GICV3_SUPPORT_GIC600	:=	1
 
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-MORELLO_GIC_SOURCES	:=	${GICV3_SOURCES}			\
-				plat/common/plat_gicv3.c		\
-				plat/arm/common/arm_gicv3.c		\
-
 PLAT_BL_COMMON_SOURCES	:=	${MORELLO_BASE}/morello_plat.c		\
 				${MORELLO_BASE}/aarch64/morello_helper.S
 
@@ -47,7 +41,6 @@
 
 BL31_SOURCES		:=	${MORELLO_CPU_SOURCES}			\
 				${INTERCONNECT_SOURCES}			\
-				${MORELLO_GIC_SOURCES}			\
 				${MORELLO_BASE}/morello_bl31_setup.c	\
 				${MORELLO_BASE}/morello_pm.c		\
 				${MORELLO_BASE}/morello_topology.c	\

diff --git a/plat/arm/board/n1sdp/n1sdp_pm.c b/plat/arm/board/n1sdp/n1sdp_pm.c
index 8d45354..d89fb05 100644
--- a/plat/arm/board/n1sdp/n1sdp_pm.c
+++ b/plat/arm/board/n1sdp/n1sdp_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,5 +19,4 @@
 void n1sdp_pwr_domain_off(const psci_power_state_t *target_state)
 {
 	css_pwr_domain_off(target_state);
-	plat_arm_gic_redistif_off();
 }

diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index f937ee7..218081c 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,16 +19,10 @@
 ARM_ARCH_MINOR := 2
 
 # GIC-600 configuration
+USE_GIC_DRIVER			:=	3
 GICV3_SUPPORT_GIC600		:=	1
 GICV3_IMPL_GIC600_MULTICHIP	:=	1
 
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-N1SDP_GIC_SOURCES	:=	${GICV3_SOURCES}			\
-				plat/common/plat_gicv3.c		\
-				plat/arm/common/arm_gicv3.c		\
-
 PLAT_BL_COMMON_SOURCES	:=	${N1SDP_BASE}/n1sdp_plat.c	        \
 				${N1SDP_BASE}/aarch64/n1sdp_helper.S
 
@@ -49,7 +43,6 @@
 
 BL31_SOURCES		:=	${N1SDP_CPU_SOURCES}			\
 				${INTERCONNECT_SOURCES}			\
-				${N1SDP_GIC_SOURCES}			\
 				${N1SDP_BASE}/n1sdp_bl31_setup.c	\
 				${N1SDP_BASE}/n1sdp_pm.c		\
 				${N1SDP_BASE}/n1sdp_topology.c	        \

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
deleted file mode 100644
index 74835f6..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ /dev/null

@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS specific memory and interrupt map
- * definitions for the first generation platforms based on the A75, N1 and V1
- * CPUs. There are minor differences in the memory map of these platforms and
- * those differences are not in the scope of this file.
- */
-
-#ifndef NRD_CSS_DEF1_H
-#define NRD_CSS_DEF1_H
-
-/*******************************************************************************
- * CSS memory map related defines
- ******************************************************************************/
-
-/* On-Chip ROM */
-#define NRD_CSS_TRUSTED_ROM_BASE	UL(0x00000000)
-#define NRD_CSS_TRUSTED_ROM_SIZE	UL(0x00080000)	/* 512KB */
-
-/* On-Chip RAM */
-#define	NRD_CSS_TRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
-#define NRD_CSS_NONTRUSTED_SRAM_BASE	UL(0x06000000)
-#define NRD_CSS_NONTRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
-
-/* PL011 UART */
-#define NRD_CSS_SEC_UART_BASE		UL(0x2A410000)
-#define NRD_CSS_UART_SIZE		UL(0x10000)
-
-/* CSS peripherals */
-#define NRD_CSS_PERIPH_BASE		UL(0x20000000)
-#define NRD_CSS_PERIPH_SIZE		UL(0x40000000)
-
-/* Secure Watchdog */
-#define NRD_CSS_WDOG_BASE		UL(0x2A480000)
-
-/* DRAM2 */
-#define NRD_CSS_DRAM2_BASE		ULL(0x8080000000)
-#define NRD_CSS_DRAM2_SIZE		ULL(0x180000000)
-
-#endif /* NRD_CSS_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
deleted file mode 100644
index 70a7d49..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ /dev/null

@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS firmware specific definitions for
- * the first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD1_CSS_FW_DEF1_H
-#define NRD1_CSS_FW_DEF1_H
-
-#include <nrd_css_def1.h>
-
-/*******************************************************************************
- * BL sizes
- ******************************************************************************/
-
-#define NRD_CSS_BL1_RW_SIZE		UL(64 * 1024)	/* 64KB */
-
-#if TRUSTED_BOARD_BOOT
-# define NRD_CSS_BL2_SIZE		UL(0x28000)
-#else
-# define NRD_CSS_BL2_SIZE		UL(0x14000)
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
- * and BL1-RW.
- */
-#define NRD_CSS_BL31_SIZE		UL(116 * 1024)	/* 116 KB */
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define NRD_CSS_UART_CLK_IN_HZ		UL(7372800)
-
-/*******************************************************************************
- * Watchdog config
- ******************************************************************************/
-
-#define NRD_CSS_WDOG_TIMEOUT		UL(100)
-
-/*******************************************************************************
- * Platform ID
- ******************************************************************************/
-
-/* Platform ID address */
-#define SSC_VERSION		(SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLER__
-/* SSC_VERSION related accessors */
-/* Returns the part number of the platform */
-#define GET_NRD_PART_NUM						\
-			GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
-/* Returns the configuration number of the platform */
-#define GET_NRD_CONFIG_NUM						\
-			GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLER__ */
-
-/*******************************************************************************
- * MMU mappings
- ******************************************************************************/
-
-#define NRD_CSS_PERIPH_MMAP(n)						\
-		MAP_REGION_FLAT(					\
-			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
-			NRD_CSS_PERIPH_BASE,				\
-			NRD_CSS_PERIPH_SIZE,				\
-			MT_DEVICE | MT_RW | MT_SECURE)
-
-#define NRD_CSS_SHARED_RAM_MMAP(n)					\
-		MAP_REGION_FLAT(					\
-			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
-			ARM_SHARED_RAM_BASE,				\
-			ARM_SHARED_RAM_SIZE,				\
-			MT_NON_CACHEABLE | MT_RW | MT_SECURE)
-
-#if SPM_MM
-/*
- * Stand-alone MM logs would be routed via secure UART. Define page table
- * entry for secure UART which would be common to all platforms.
- */
-#define NRD_CSS_SECURE_UART_MMAP					\
-		MAP_REGION_FLAT(					\
-			NRD_CSS_SEC_UART_BASE,				\
-			NRD_CSS_UART_SIZE,				\
-			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-#endif
-
-#endif /* NRD_CSS_FW_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
deleted file mode 100644
index bca095c..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ /dev/null

@@ -1,249 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the platform port definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD_PLAT_ARM_DEF1_H
-#define NRD_PLAT_ARM_DEF1_H
-
-#ifndef __ASSEMBLER__
-#include <lib/mmio.h>
-#endif /* __ASSEMBLER__ */
-
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/common/arm_def.h>
-#include <plat/arm/common/arm_spm_def.h>
-#include <plat/arm/css/common/css_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-#include <plat/common/common_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/*******************************************************************************
- * Core count
- ******************************************************************************/
-
-#define PLATFORM_CORE_COUNT	(NRD_CHIP_COUNT *			\
-				PLAT_ARM_CLUSTER_COUNT *		\
-				NRD_MAX_CPUS_PER_CLUSTER *		\
-				NRD_MAX_PE_PER_CPU)
-
-/*******************************************************************************
- * PA/VA config
- ******************************************************************************/
-
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	NRD_REMOTE_CHIP_MEM_OFFSET( \
-						NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#endif
-
-/*******************************************************************************
- * XLAT definitions
- ******************************************************************************/
-
-#if defined(IMAGE_BL31)
-# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
-#  define PLAT_ARM_MMAP_ENTRIES		(10 + ((NRD_CHIP_COUNT - 1) * 3))
-#  define MAX_XLAT_TABLES		(11 + ((NRD_CHIP_COUNT - 1) * 3))
-#  define PLAT_SP_IMAGE_MMAP_REGIONS	U(12)
-#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	U(14)
-# else
-#  define PLAT_ARM_MMAP_ENTRIES		(5 + ((NRD_CHIP_COUNT - 1) * 3))
-#  define MAX_XLAT_TABLES		(6 + ((NRD_CHIP_COUNT - 1) * 3))
-# endif
-#elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES		U(8)
-# define MAX_XLAT_TABLES		U(5)
-#elif defined(IMAGE_BL2)
-# define PLAT_ARM_MMAP_ENTRIES		(11 + (NRD_CHIP_COUNT - 1))
-
-/*
- * MAX_XLAT_TABLES entries need to be doubled because when the address width
- * exceeds 40 bits an additional level of translation is required. In case of
- * multichip platforms peripherals also fall into address space with width
- * > 40 bits.
- */
-# define MAX_XLAT_TABLES		(11  + ((NRD_CHIP_COUNT - 1) * 2))
-#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES		U(11)
-# define MAX_XLAT_TABLES		U(7)
-#else
-# define PLAT_ARM_MMAP_ENTRIES		U(12)
-# define MAX_XLAT_TABLES		U(6)
-#endif
-
-/*******************************************************************************
- * Stack size
- ******************************************************************************/
-
-#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE		U(0x1000)
-# else
-#  define PLATFORM_STACK_SIZE		U(0x440)
-# endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE		U(0x1000)
-# else
-#  define PLATFORM_STACK_SIZE		U(0x400)
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE		U(0x400)
-#elif defined(IMAGE_BL31)
-# if SPM_MM
-#  define PLATFORM_STACK_SIZE		U(0x500)
-# else
-#  define PLATFORM_STACK_SIZE		U(0x400)
-# endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE		U(0x440)
-#endif
-
-#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
-/*
- * Secure partition stack follows right after the memory region that is shared
- * between EL3 and S-EL0.
- */
-#define PLAT_ARM_SP_IMAGE_STACK_BASE	(PLAT_SP_IMAGE_NS_BUF_BASE +	\
-					 PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */
-
-/*******************************************************************************
- * BL sizes
- ******************************************************************************/
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	U(0x1000)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	U(0xe000)
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	U(0)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	U(0)
-#endif
-
-#define PLAT_ARM_MAX_BL1_RW_SIZE	NRD_CSS_BL1_RW_SIZE
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth. Additional 8KiB space is added per chip in
- * order to accommodate the additional level of translation required for "TZC"
- * peripheral access which lies in >4TB address space.
- *
- */
-#define PLAT_ARM_MAX_BL2_SIZE		(NRD_CSS_BL2_SIZE +		\
-						((NRD_CHIP_COUNT - 1) * 0x2000))
-
-#define PLAT_ARM_MAX_BL31_SIZE		(NRD_CSS_BL31_SIZE +		\
-						PLAT_ARM_MAX_BL2_SIZE +	\
-						PLAT_ARM_MAX_BL1_RW_SIZE)
-
-/*******************************************************************************
- * ROM, SRAM and DRAM config
- ******************************************************************************/
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	NRD_CSS_TRUSTED_SRAM_SIZE
-
-#define PLAT_ARM_TRUSTED_ROM_BASE	NRD_CSS_TRUSTED_ROM_BASE
-#define PLAT_ARM_TRUSTED_ROM_SIZE	NRD_CSS_TRUSTED_ROM_SIZE
-
-#define PLAT_ARM_NSRAM_BASE		NRD_CSS_NONTRUSTED_SRAM_BASE
-#define PLAT_ARM_NSRAM_SIZE		NRD_CSS_NONTRUSTED_SRAM_SIZE
-
-#define PLAT_ARM_DRAM2_BASE		NRD_CSS_DRAM2_BASE
-#define PLAT_ARM_DRAM2_SIZE		NRD_CSS_DRAM2_SIZE
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define PLAT_ARM_BOOT_UART_BASE		NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_RUN_UART_BASE		NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_CRASH_UART_BASE	NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ	NRD_CSS_UART_CLK_IN_HZ
-
-/*******************************************************************************
- * Timer config
- ******************************************************************************/
-
-#define PLAT_ARM_NSTIMER_FRAME_ID	(0)
-
-/*******************************************************************************
- * Power config
- ******************************************************************************/
-
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL1
-
-/*******************************************************************************
- * Flash config
- ******************************************************************************/
-
-#define PLAT_ARM_FLASH_IMAGE_BASE	V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE	(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
-					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-/* IO storage framework */
-#define MAX_IO_DEVICES			U(3)
-#define MAX_IO_HANDLES			U(4)
-
-/*******************************************************************************
- * SCMI config
- ******************************************************************************/
-
-/* Number of SCMI channels on the platform */
-#define PLAT_ARM_SCMI_CHANNEL_COUNT	NRD_CHIP_COUNT
-
-/*******************************************************************************
- * SDS config
- ******************************************************************************/
-
-/* Index of SDS region used in the communication with SCP */
-#define SDS_SCP_AP_REGION_ID		U(0)
-/* SDS ID for unusable CPU MPID list structure */
-#define SDS_ISOLATED_CPU_LIST_ID	U(128)
-
-/*******************************************************************************
- * GIC/EHF config
- ******************************************************************************/
-
-#define PLAT_ARM_G1S_IRQ_PROPS(grp)	CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
-#define PLAT_SP_PRI			U(0x10)
-
-/*******************************************************************************
- * Platform type identification macro
- ******************************************************************************/
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK		U(0x0f)
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		U(0x0)
-#define BOARD_CSS_PLAT_TYPE_EMULATOR		U(0x02)
-
-#ifndef __ASSEMBLER__
-#define BOARD_CSS_GET_PLAT_TYPE(addr)					\
-		((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK)	\
-		>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-#endif /* __ASSEMBLER__ */
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR		NRD_ROS_PLATFORM_BASE +	\
-						UL(0x00fe00e0)
-
-#endif /* NRD_PLAT_ARM_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
deleted file mode 100644
index b86ab21..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ /dev/null

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS specific definitions for the first
- * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
- * is used to refer to the part of the reference design platform that excludes
- * CSS.
- */
-
-#ifndef NRD_ROS_DEF1_H
-#define NRD_ROS_DEF1_H
-
-/*******************************************************************************
- * ROS configs
- ******************************************************************************/
-
-/* RoS Peripherals */
-#define NRD_ROS_PERIPH_BASE		UL(0x60000000)
-#define NRD_ROS_PERIPH_SIZE		UL(0x20000000)
-
-/* System Reg */
-#define NRD_ROS_SYSTEMREG_BASE		UL(0x1C010000)
-#define NRD_ROS_SYSTEMREG_SIZE		UL(0x00010000)
-
-/* NOR Flash 2 */
-#define NRD_ROS_NOR2_FLASH_BASE		UL(0x10000000)
-#define NRD_ROS_NOR2_FLASH_SIZE		UL(0x04000000)
-
-/* RoS Platform */
-#define NRD_ROS_PLATFORM_BASE		UL(0x7F000000)
-#define NRD_ROS_PLATFORM_SIZE		UL(0x20000000)
-
-#endif /* NRD_ROS_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
deleted file mode 100644
index c521043..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
+++ /dev/null

@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS firmware specific definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
- * System) is used to refer to the part of the reference design platform that
- * excludes CSS.
- */
-
-#ifndef NRD_ROS_FW_DEF1_H
-#define NRD_ROS_FW_DEF1_H
-
-#include <nrd_ros_def1.h>
-
-/*******************************************************************************
- * MMU mapping
- ******************************************************************************/
-
-#define NRD_ROS_PERIPH_MMAP(n)						\
-		MAP_REGION_FLAT(					\
-			NRD_REMOTE_CHIP_MEM_OFFSET(n) +			\
-			NRD_ROS_PERIPH_BASE,				\
-			NRD_ROS_PERIPH_SIZE,				\
-			MT_DEVICE | MT_RW | MT_SECURE)
-
-#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP				\
-		MAP_REGION_FLAT(					\
-			NRD_ROS_SYSTEMREG_BASE,				\
-			NRD_ROS_SYSTEMREG_SIZE,				\
-			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#define NRD_ROS_SECURE_NOR2_USER_MMAP					\
-		MAP_REGION_FLAT(					\
-			NRD_ROS_NOR2_FLASH_BASE,			\
-			NRD_ROS_NOR2_FLASH_SIZE,			\
-			MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#define NRD_MAP_FLASH0_RO						\
-		MAP_REGION_FLAT(					\
-			V2M_FLASH0_BASE,				\
-			V2M_FLASH0_SIZE,				\
-			MT_DEVICE | MT_RO | MT_SECURE)
-
-/*******************************************************************************
- * TZ config
- ******************************************************************************/
-
-/*
- * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
- * where both the DRAM regions are marked for non-secure access. This applies
- * to multi-chip platforms.
- */
-#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n)				\
-	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE,		\
-		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END,		\
-		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},	\
-	{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE,		\
-		NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END,		\
-		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-
-#endif  /* NRD_ROS_FW_DEF1_H */

diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index 86d82e2..901cbf1 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,16 +7,6 @@
 #ifndef NRD_VARIANT_H
 #define NRD_VARIANT_H
 
-/* SSC_VERSION values for SGI575 */
-#define SGI575_SSC_VER_PART_NUM			0x0783
-
-/* SID Version values for RD-N1E1-Edge */
-#define RD_N1E1_EDGE_SID_VER_PART_NUM		0x0786
-#define RD_E1_EDGE_CONFIG_ID			0x2
-
-/* SID Version values for RD-V1 */
-#define RD_V1_SID_VER_PART_NUM			0x078a
-
 /* SID Version values for RD-N2 */
 #define RD_N2_SID_VER_PART_NUM			0x07B7
 

diff --git a/plat/arm/board/neoverse_rd/common/nrd-common.mk b/plat/arm/board/neoverse_rd/common/nrd-common.mk
index a09f369..acc5a47 100644
--- a/plat/arm/board/neoverse_rd/common/nrd-common.mk
+++ b/plat/arm/board/neoverse_rd/common/nrd-common.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -30,15 +30,9 @@
 PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include
 
 # GIC-600 configuration
+USE_GIC_DRIVER		:=	3
 GICV3_SUPPORT_GIC600	:=	1
 
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-ENT_GIC_SOURCES		:=	${GICV3_SOURCES}		\
-				plat/common/plat_gicv3.c	\
-				plat/arm/common/arm_gicv3.c
-
 PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/arch/aarch64/nrd_helper.S
 
 BL1_SOURCES		+=	${INTERCONNECT_SOURCES}			\
@@ -49,7 +43,6 @@
 				drivers/arm/css/sds/sds.c
 
 BL31_SOURCES		+=	${INTERCONNECT_SOURCES}			\
-				${ENT_GIC_SOURCES}			\
 				${NRD_COMMON_BASE}/nrd_bl31_setup.c	\
 				${NRD_COMMON_BASE}/nrd_topology.c	\
 				drivers/delay_timer/generic_delay_timer.c

diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 2dd8b45..3ad586b 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c

@@ -24,14 +24,6 @@
 
 nrd_platform_info_t nrd_plat_info;
 
-static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
-		.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
-		.db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
-		.db_preserve_mask = 0xfffffffe,
-		.db_modify_mask = 0x1,
-		.ring_doorbell = &mhu_ring_doorbell,
-};
-
 static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
 	{
 		.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
@@ -123,9 +115,7 @@
 
 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
 {
-	if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
-		nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
-		nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+	if (nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
 		nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
 		nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
 		nrd_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) {
@@ -140,8 +130,6 @@
 			panic();
 		}
 		return &plat3_rd_scmi_info[channel_id];
-	} else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) {
-		return &sgi575_scmi_plat_info;
 	} else {
 		panic();
 	}
@@ -179,7 +167,7 @@
 		arg1 = soc_fw_config_info->config_addr;
 	}
 #endif /* SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */
-	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
 }
 
 /*******************************************************************************
@@ -267,19 +255,5 @@
 
 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
 {
-	/*
-	 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
-	 * supported.
-	 */
-	if (((nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
-	    (nrd_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
-		ops->cpu_standby = NULL;
-		ops->system_off = NULL;
-		ops->system_reset = NULL;
-		ops->get_sys_suspend_power_state = NULL;
-		ops->pwr_domain_suspend = NULL;
-		ops->pwr_domain_suspend_finish = NULL;
-	}
-
 	return css_scmi_override_pm_ops(ops);
 }

diff --git a/plat/arm/board/neoverse_rd/common/nrd_interconnect.c b/plat/arm/board/neoverse_rd/common/nrd_interconnect.c
index 4f9cc85..af8980d 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_interconnect.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_interconnect.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,12 +8,6 @@
 #include <common/debug.h>
 #include <plat/arm/common/plat_arm.h>
 
-/*
- * For SGI575 which support FCM (with automatic interconnect enter/exit),
- * we should not do anything in these interface functions.
- * They are used to override the weak functions in cci drivers.
- */
-
 /******************************************************************************
  * Helper function to initialize ARM interconnect driver.
  *****************************************************************************/

diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat1.c b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
deleted file mode 100644
index 32444f4..0000000
--- a/plat/arm/board/neoverse_rd/common/nrd_plat1.c
+++ /dev/null

@@ -1,181 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/ccn.h>
-#include <drivers/arm/css/sds.h>
-#include <lib/utils_def.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <drivers/arm/sbsa.h>
-
-#if SPM_MM
-#include <services/spm_mm_partition.h>
-#endif
-
-/*
- * Table of regions for different BL stages to map using the MMU.
- * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
- * arm_configure_mmu_elx() will give the available subset of that.
- *
- * Replace or extend the below regions as required
- */
-#if IMAGE_BL1
-const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	NRD_MAP_FLASH0_RO,
-	NRD_CSS_PERIPH_MMAP(0),
-	NRD_ROS_PERIPH_MMAP(0),
-	{0}
-};
-#endif
-#if IMAGE_BL2
-const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	NRD_MAP_FLASH0_RO,
-#ifdef PLAT_ARM_MEM_PROT_ADDR
-	ARM_V2M_MAP_MEM_PROTECT,
-#endif
-	NRD_CSS_PERIPH_MMAP(0),
-	NRD_ROS_PERIPH_MMAP(0),
-	ARM_MAP_NS_DRAM1,
-#if NRD_CHIP_COUNT > 1
-	NRD_CSS_PERIPH_MMAP(1),
-#endif
-#if NRD_CHIP_COUNT > 2
-	NRD_CSS_PERIPH_MMAP(2),
-#endif
-#if NRD_CHIP_COUNT > 3
-	NRD_CSS_PERIPH_MMAP(3),
-#endif
-#if ARM_BL31_IN_DRAM
-	ARM_MAP_BL31_SEC_DRAM,
-#endif
-#if SPM_MM
-	ARM_SP_IMAGE_MMAP,
-#endif
-#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
-	ARM_MAP_BL1_RW,
-#endif
-	{0}
-};
-#endif
-#if IMAGE_BL31
-const mmap_region_t plat_arm_mmap[] = {
-	ARM_MAP_SHARED_RAM,
-	V2M_MAP_IOFPGA,
-	NRD_CSS_PERIPH_MMAP(0),
-#ifdef PLAT_ARM_MEM_PROT_ADDR
-	ARM_V2M_MAP_MEM_PROTECT,
-#endif
-	NRD_ROS_PERIPH_MMAP(0),
-#if SPM_MM
-	ARM_SPM_BUF_EL3_MMAP,
-#endif
-	{0}
-};
-
-#if SPM_MM && defined(IMAGE_BL31)
-const mmap_region_t plat_arm_secure_partition_mmap[] = {
-	NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
-	NRD_ROS_SECURE_NOR2_USER_MMAP,
-	NRD_CSS_SECURE_UART_MMAP,
-	ARM_SP_IMAGE_MMAP,
-	ARM_SP_IMAGE_NS_BUF_MMAP,
-	ARM_SP_IMAGE_RW_MMAP,
-	ARM_SPM_BUF_EL0_MMAP,
-	{0}
-};
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-#endif
-
-ARM_CASSERT_MMAP
-
-#if SPM_MM && defined(IMAGE_BL31)
-/*
- * Boot information passed to a secure partition during initialisation. Linear
- * indices in MP information will be filled at runtime.
- */
-static spm_mm_mp_info_t sp_mp_info[] = {
-	[0] = {0x81000000, 0},
-	[1] = {0x81000100, 0},
-	[2] = {0x81000200, 0},
-	[3] = {0x81000300, 0},
-	[4] = {0x81010000, 0},
-	[5] = {0x81010100, 0},
-	[6] = {0x81010200, 0},
-	[7] = {0x81010300, 0},
-};
-
-const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
-	.h.type              = PARAM_SP_IMAGE_BOOT_INFO,
-	.h.version           = VERSION_1,
-	.h.size              = sizeof(spm_mm_boot_info_t),
-	.h.attr              = 0,
-	.sp_mem_base         = ARM_SP_IMAGE_BASE,
-	.sp_mem_limit        = ARM_SP_IMAGE_LIMIT,
-	.sp_image_base       = ARM_SP_IMAGE_BASE,
-	.sp_stack_base       = PLAT_SP_IMAGE_STACK_BASE,
-	.sp_heap_base        = ARM_SP_IMAGE_HEAP_BASE,
-	.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
-	.sp_shared_buf_base  = PLAT_SPM_BUF_BASE,
-	.sp_image_size       = ARM_SP_IMAGE_SIZE,
-	.sp_pcpu_stack_size  = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
-	.sp_heap_size        = ARM_SP_IMAGE_HEAP_SIZE,
-	.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
-	.sp_shared_buf_size  = PLAT_SPM_BUF_SIZE,
-	.num_sp_mem_regions  = ARM_SP_IMAGE_NUM_MEM_REGIONS,
-	.num_cpus            = PLATFORM_CORE_COUNT,
-	.mp_info             = &sp_mp_info[0],
-};
-
-const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
-{
-	return plat_arm_secure_partition_mmap;
-}
-
-const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
-		void *cookie)
-{
-	return &plat_arm_secure_partition_boot_info;
-}
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-
-#if TRUSTED_BOARD_BOOT
-int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
-{
-	assert(heap_addr != NULL);
-	assert(heap_size != NULL);
-
-	return arm_get_mbedtls_heap(heap_addr, heap_size);
-}
-#endif
-
-void plat_arm_secure_wdt_start(void)
-{
-	sbsa_wdog_start(NRD_CSS_WDOG_BASE, NRD_CSS_WDOG_TIMEOUT);
-}
-
-void plat_arm_secure_wdt_stop(void)
-{
-	sbsa_wdog_stop(NRD_CSS_WDOG_BASE);
-}
-
-static sds_region_desc_t nrd_sds_regions[] = {
-	{ .base = PLAT_ARM_SDS_MEM_BASE },
-};
-
-sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
-{
-	*region_count = ARRAY_SIZE(nrd_sds_regions);
-
-	return nrd_sds_regions;
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts
deleted file mode 100644
index 085a42a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts
+++ /dev/null

@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-/ {
-	dtb-registry {
-		compatible = "fconf,dyn_cfg-dtb_registry";
-
-		tb_fw-config {
-			load-address = <0x0 0x4001300>;
-			max-size = <0x200>;
-			id = <TB_FW_CONFIG_ID>;
-		};
-
-		nt_fw-config {
-			load-address = <0x0 0xFEF00000>;
-			max-size = <0x0100000>;
-			id = <NT_FW_CONFIG_ID>;
-		};
-	};
-};
-

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
deleted file mode 100644
index 3cef0d1..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
+++ /dev/null

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,rd-n1edge";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-		multi-chip-mode = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
deleted file mode 100644
index 78cd5a8..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
+++ /dev/null

@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	tb_fw-config {
-		compatible = "arm,tb_fw";
-
-		/* Disable authentication for development */
-		disable_auth = <0x0>;
-
-		/*
-		 * The following two entries are placeholders for Mbed TLS
-		 * heap information. The default values don't matter since
-		 * they will be overwritten by BL1.
-		 * In case of having shared Mbed TLS heap between BL1 and BL2,
-		 * BL1 will populate these two properties with the respective
-		 * info about the shared heap. This info will be available for
-		 * BL2 in order to locate and re-use the heap.
-		 */
-		mbedtls_heap_addr = <0x0 0x0>;
-		mbedtls_heap_size = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
deleted file mode 100644
index 5357c31..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ /dev/null

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-#include <nrd_sdei.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
-		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT		U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER	U(4)
-#define NRD_MAX_PE_PER_CPU		U(1)
-
-#define PLAT_CSS_MHU_BASE		UL(0x45400000)
-
-/* Base address of DMC-620 instances */
-#define RDN1EDGE_DMC620_BASE0		UL(0x4e000000)
-#define RDN1EDGE_DMC620_BASE1		UL(0x4e100000)
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP	U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICR_BASE		UL(0x300C0000)
-
-/* GIC SPI range for multichip */
-#define NRD_CHIP0_SPI_MIN		U(32)
-#define NRD_CHIP0_SPI_MAX		U(991)
-
-#endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
deleted file mode 100644
index 4892804..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ /dev/null

@@ -1,83 +0,0 @@
-#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# GIC-600 configuration
-GICV3_IMPL_GIC600_MULTICHIP	:=	1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDN1EDGE_BASE		=	plat/arm/board/neoverse_rd/platform/rdn1edge
-
-PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
-				-I${RDN1EDGE_BASE}/include/
-
-NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n1.S
-
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDN1EDGE_BASE}/rdn1edge_err.c
-
-BL2_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_plat.c	\
-				${RDN1EDGE_BASE}/rdn1edge_security.c	\
-				${RDN1EDGE_BASE}/rdn1edge_err.c		\
-				drivers/arm/tzc/tzc_dmc620.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDN1EDGE_BASE}/rdn1edge_plat.c	\
-				${RDN1EDGE_BASE}/rdn1edge_topology.c	\
-				drivers/cfi/v2m/v2m_flash.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
-BL2_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
-endif
-
-# Enable dynamic addition of MMAP regions in BL31
-BL31_CPPFLAGS		+=	-DPLAT_XLAT_TABLES_DYNAMIC
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts	\
-				${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES		+=	${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-$(eval $(call CREATE_SEQ,SEQ,2))
-ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error  "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
-   set to ${NRD_CHIP_COUNT}.")
-endif
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
-     currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
-  $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
-  Please set RESET_TO_BL31 to 0.")
-endif
-
-override CTX_INCLUDE_AARCH32_REGS	:= 0
-override SPMD_SPM_AT_SEL2		:= 0
-
-# Enable the flag since RD-N1-EDGE has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC		:=	1

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c
deleted file mode 100644
index 273e1f4..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c
+++ /dev/null

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdn1edge error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
-	while (true) {
-		wfi();
-	}
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
deleted file mode 100644
index 5cbdd5f..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ /dev/null

@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/gic600_multichip.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-#define RT_OWNER 0
-
-#if defined(IMAGE_BL31)
-static const mmap_region_t rdn1edge_dynamic_mmap[] = {
-	NRD_CSS_SHARED_RAM_MMAP(1),
-	NRD_CSS_PERIPH_MMAP(1),
-	NRD_ROS_PERIPH_MMAP(1)
-};
-
-static struct gic600_multichip_data rdn1e1_multichip_data __init = {
-	.base_addrs = {
-		PLAT_ARM_GICD_BASE
-	},
-	.rt_owner = RT_OWNER,
-	.chip_count = NRD_CHIP_COUNT,
-	.chip_addrs = {
-		[RT_OWNER] = {
-			PLAT_ARM_GICD_BASE >> 16,
-			(PLAT_ARM_GICD_BASE
-				+ NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
-		}
-	},
-	.spi_ids = {
-		{PLAT_ARM_GICD_BASE,
-		NRD_CHIP0_SPI_MIN,
-		NRD_CHIP0_SPI_MAX},
-		{0, 0, 0}
-	}
-};
-
-static uintptr_t rdn1e1_multichip_gicr_frames[] = {
-	PLAT_ARM_GICR_BASE,				/* Chip 0's GICR Base */
-	PLAT_ARM_GICR_BASE +
-		NRD_REMOTE_CHIP_MEM_OFFSET(1),		/* Chip 1's GICR BASE */
-	UL(0)						/* Zero Termination */
-};
-#endif /* IMAGE_BL31 */
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
-				& SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
-	return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
-			SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-/*
- * IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31
- * because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
- * for other stages.
- */
-#if defined(IMAGE_BL31)
-void bl31_platform_setup(void)
-{
-	unsigned int i;
-	int ret;
-
-	if (plat_arm_nrd_get_multi_chip_mode() == 0 && NRD_CHIP_COUNT > 1) {
-		ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
-				NRD_CHIP_COUNT);
-		panic();
-	} else if (plat_arm_nrd_get_multi_chip_mode() == 1 &&
-			NRD_CHIP_COUNT > 1) {
-		INFO("Enabling support for multi-chip in RD-N1-Edge\n");
-
-		for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {
-			ret = mmap_add_dynamic_region(
-					rdn1edge_dynamic_mmap[i].base_pa,
-					rdn1edge_dynamic_mmap[i].base_va,
-					rdn1edge_dynamic_mmap[i].size,
-					rdn1edge_dynamic_mmap[i].attr
-					);
-			if (ret != 0) {
-				ERROR("Failed to add dynamic mmap entry\n");
-				panic();
-			}
-		}
-
-		plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames);
-		gic600_multichip_init(&rdn1e1_multichip_data);
-	}
-
-	nrd_bl31_common_platform_setup();
-}
-#endif /* IMAGE_BL31 */

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
deleted file mode 100644
index f3f6238..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
+++ /dev/null

@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <nrd_dmc620_tzc_regions.h>
-
-uintptr_t rdn1edge_dmc_base[] = {
-	RDN1EDGE_DMC620_BASE0,
-	RDN1EDGE_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
-	.dmc_base = rdn1edge_dmc_base,
-	.dmc_count = ARRAY_SIZE(rdn1edge_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
-	NRD_DMC620_TZC_REGIONS_DEF
-};
-
-static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
-	.plat_drv_data = &rdn1edge_plat_driver_data,
-	.plat_acc_addr_data = rdn1edge_acc_addr_data,
-	.acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	arm_tzc_dmc620_setup(&rdn1edge_plat_config_data);
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
deleted file mode 100644
index 133eb16..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
+++ /dev/null

@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-static const unsigned char rdn1edge_pd_tree_desc[] = {
-	(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_CHIP_COUNT > 1)
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return rdn1edge_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
-#if (NRD_CHIP_COUNT > 1)
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x4)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x5)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x6)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x7)),
-#endif
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c
+++ /dev/null

@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier  ::=  SEQUENCE  {
- *     algorithm         OBJECT IDENTIFIER,
- *     parameters        ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- *     digestAlgorithm   AlgorithmIdentifier,
- *     digest            OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-			unsigned int *flags)
-{
-	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index 5776948..421c14e 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk

@@ -125,7 +125,6 @@
 ERRATA_N2_2025414	:=	1
 ERRATA_N2_2189731	:=	1
 ERRATA_N2_2138956	:=	1
-ERRATA_N2_2138953	:=	1
 ERRATA_N2_2242415	:=	1
 ERRATA_N2_2138958	:=	1
 ERRATA_N2_2242400	:=	1

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts
deleted file mode 100644
index d443443..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts
+++ /dev/null

@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
-	dtb-registry {
-		compatible = "fconf,dyn_cfg-dtb_registry";
-
-		tb_fw-config {
-			load-address = <0x0 0x4001300>;
-			max-size = <0x200>;
-			id = <TB_FW_CONFIG_ID>;
-		};
-
-		nt_fw-config {
-			load-address = <0x0 0xFEF00000>;
-			max-size = <0x0100000>;
-			id = <NT_FW_CONFIG_ID>;
-		};
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts
deleted file mode 100644
index fb08885..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts
+++ /dev/null

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,rd-v1";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-		multi-chip-mode = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
-	tb_fw-config {
-		compatible = "arm,tb_fw";
-
-		/* Disable authentication for development */
-		disable_auth = <0x0>;
-
-		/*
-		 * The following two entries are placeholders for Mbed TLS
-		 * heap information. The default values don't matter since
-		 * they will be overwritten by BL1.
-		 * In case of having shared Mbed TLS heap between BL1 and BL2,
-		 * BL1 will populate these two properties with the respective
-		 * info about the shared heap. This info will be available for
-		 * BL2 in order to locate and re-use the heap.
-		 */
-		mbedtls_heap_addr = <0x0 0x0>;
-		mbedtls_heap_size = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
deleted file mode 100644
index cd40117..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ /dev/null

@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
-		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT		U(16)
-#define NRD_MAX_CPUS_PER_CLUSTER	U(1)
-#define NRD_MAX_PE_PER_CPU		U(1)
-
-#define PLAT_CSS_MHU_BASE		UL(0x45400000)
-#define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE		UL(0x21830000)
-#define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET			UL(0x1000000)
-#define TZC400_COUNT			4
-
-#define TZC400_BASE(n)			(PLAT_ARM_TZC_BASE + \
-					 (n * TZC400_OFFSET))
-
-#define TZC_NSAID_ALL_AP		U(0)
-#define TZC_NSAID_PCI			U(1)
-#define TZC_NSAID_HDLCD0		U(2)
-#define TZC_NSAID_CLCD			U(7)
-#define TZC_NSAID_AP			U(9)
-#define TZC_NSAID_VIRTIO		U(15)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS	\
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI))    | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP))     | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD))   | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP	U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICR_BASE		UL(0x30140000)
-
-#endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
deleted file mode 100644
index 241133f..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ /dev/null

@@ -1,78 +0,0 @@
-# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# RD-V1 platform uses GIC-700 which is based on GICv4.1
-GIC_ENABLE_V4_EXTN	:=	1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDV1_BASE		=	plat/arm/board/neoverse_rd/platform/rdv1
-
-PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
-				-I${RDV1_BASE}/include/
-
-NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
-
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDV1_BASE}/rdv1_err.c
-
-BL2_SOURCES		+=	${RDV1_BASE}/rdv1_plat.c	\
-				${RDV1_BASE}/rdv1_security.c	\
-				${RDV1_BASE}/rdv1_err.c		\
-				lib/utils/mem_region.c			\
-				drivers/arm/tzc/tzc400.c		\
-				plat/arm/common/arm_tzc400.c		\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDV1_BASE}/rdv1_plat.c	\
-				${RDV1_BASE}/rdv1_topology.c	\
-				drivers/cfi/v2m/v2m_flash.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES		+=	${RDV1_BASE}/rdv1_trusted_boot.c
-BL2_SOURCES		+=	${RDV1_BASE}/rdv1_trusted_boot.c
-endif
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${RDV1_BASE}/fdts/${PLAT}_fw_config.dts	\
-				${RDV1_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES		+=	${RDV1_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS	:= 0
-override ENABLE_FEAT_AMU		:= 2
-override SPMD_SPM_AT_SEL2		:= 0
-
-# FEAT_SVE related flags
-override SVE_VECTOR_LEN			:= 256
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \
-     currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
-  $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
-  Please set RESET_TO_BL31 to 0.")
-endif
-
-# Enable the flag since RD-V1 has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC		:=	1

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c
deleted file mode 100644
index d75f525..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c
+++ /dev/null

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdv1 error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
-	while (1) {
-		wfi();
-	}
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c
deleted file mode 100644
index 7cdc19a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c
+++ /dev/null

@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
-				& SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
-	return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
-			SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-void bl31_platform_setup(void)
-{
-	nrd_bl31_common_platform_setup();
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c
deleted file mode 100644
index a936a71..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c
+++ /dev/null

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-static const arm_tzc_regions_info_t tzc_regions[] = {
-	ARM_TZC_REGIONS_DEF,
-	{}
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	int i;
-
-	for (i = 0; i < TZC400_COUNT; i++)
-		arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
deleted file mode 100644
index 20e4266..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
+++ /dev/null

@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char rd_v1_pd_tree_desc[] = {
-	PLAT_ARM_CLUSTER_COUNT,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return rd_v1_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF))
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c
+++ /dev/null

@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier  ::=  SEQUENCE  {
- *     algorithm         OBJECT IDENTIFIER,
- *     parameters        ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- *     digestAlgorithm   AlgorithmIdentifier,
- *     digest            OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-			unsigned int *flags)
-{
-	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts
deleted file mode 100644
index d443443..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts
+++ /dev/null

@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
-	dtb-registry {
-		compatible = "fconf,dyn_cfg-dtb_registry";
-
-		tb_fw-config {
-			load-address = <0x0 0x4001300>;
-			max-size = <0x200>;
-			id = <TB_FW_CONFIG_ID>;
-		};
-
-		nt_fw-config {
-			load-address = <0x0 0xFEF00000>;
-			max-size = <0x0100000>;
-			id = <NT_FW_CONFIG_ID>;
-		};
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
deleted file mode 100644
index 78fa31e..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
+++ /dev/null

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,rd-v1-mc";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-		multi-chip-mode = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
-	tb_fw-config {
-		compatible = "arm,tb_fw";
-
-		/* Disable authentication for development */
-		disable_auth = <0x0>;
-
-		/*
-		 * The following two entries are placeholders for Mbed TLS
-		 * heap information. The default values don't matter since
-		 * they will be overwritten by BL1.
-		 * In case of having shared Mbed TLS heap between BL1 and BL2,
-		 * BL1 will populate these two properties with the respective
-		 * info about the shared heap. This info will be available for
-		 * BL2 in order to locate and re-use the heap.
-		 */
-		mbedtls_heap_addr = <0x0 0x0>;
-		mbedtls_heap_size = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
deleted file mode 100644
index b4c5c0a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ /dev/null

@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
-		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT		U(4)
-#define NRD_MAX_CPUS_PER_CLUSTER	U(1)
-#define NRD_MAX_PE_PER_CPU		U(1)
-
-#define PLAT_CSS_MHU_BASE		UL(0x45400000)
-#define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE		UL(0x21830000)
-#define TZC400_BASE(n)			(PLAT_ARM_TZC_BASE + \
-					 (n * TZC400_OFFSET))
-#define TZC400_OFFSET			UL(0x1000000)
-#define TZC400_COUNT			U(8)
-#define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC_NSAID_ALL_AP		U(0)
-#define TZC_NSAID_PCI			U(1)
-#define TZC_NSAID_HDLCD0		U(2)
-#define TZC_NSAID_CLCD			U(7)
-#define TZC_NSAID_AP			U(9)
-#define TZC_NSAID_VIRTIO		U(15)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS	\
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI))    | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP))     | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD))   | \
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xC0000000)
-
-/* Remote chip address offset (4TB per chip) */
-#define NRD_ADDR_BITS_PER_CHIP	U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICR_BASE		UL(0x30140000)
-
-/* GIC SPI range for multichip */
-#define NRD_CHIP0_SPI_MIN		U(32)
-#define NRD_CHIP0_SPI_MAX		U(991)
-
-#endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
deleted file mode 100644
index 7af0bd8..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ /dev/null

@@ -1,89 +0,0 @@
-# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Enable GICv4 extension with multichip driver
-GIC_ENABLE_V4_EXTN		:=	1
-GICV3_IMPL_GIC600_MULTICHIP	:=	1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDV1MC_BASE	=	plat/arm/board/neoverse_rd/platform/rdv1mc
-
-PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
-				-I${RDV1MC_BASE}/include/
-
-NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_v1.S
-
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDV1MC_BASE}/rdv1mc_err.c
-
-BL2_SOURCES		+=	${RDV1MC_BASE}/rdv1mc_plat.c	\
-				${RDV1MC_BASE}/rdv1mc_security.c	\
-				${RDV1MC_BASE}/rdv1mc_err.c	\
-				drivers/arm/tzc/tzc400.c	\
-				plat/arm/common/arm_tzc400.c	\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDV1MC_BASE}/rdv1mc_plat.c	\
-				${RDV1MC_BASE}/rdv1mc_topology.c	\
-				drivers/cfi/v2m/v2m_flash.c		\
-				drivers/arm/gic/v3/gic600_multichip.c	\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES		+=	${RDV1MC_BASE}/rdv1mc_trusted_boot.c
-BL2_SOURCES		+=	${RDV1MC_BASE}/rdv1mc_trusted_boot.c
-endif
-
-# Enable dynamic addition of MMAP regions in BL31
-BL31_CFLAGS		+=	-DPLAT_XLAT_TABLES_DYNAMIC
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${RDV1MC_BASE}/fdts/${PLAT}_fw_config.dts	\
-				${RDV1MC_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-$(eval $(call CREATE_SEQ,SEQ,4))
-ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error  "Chip count for RD-V1-MC should be either $(SEQ) \
- currently it is set to ${NRD_CHIP_COUNT}.")
-endif
-
-FDT_SOURCES		+=	${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS	:= 0
-override ENABLE_FEAT_AMU		:= 2
-override SPMD_SPM_AT_SEL2		:= 0
-
-# FEAT_SVE related flags
-override SVE_VECTOR_LEN			:= 256
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
-     currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
-  $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
-  Please set RESET_TO_BL31 to 0.")
-endif
-
-# Enable the flag since RD-V1-MC has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC		:=	1

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c
deleted file mode 100644
index b855edd..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c
+++ /dev/null

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdv1mc error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
-	while (true) {
-		wfi();
-	}
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
deleted file mode 100644
index 0a40762..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ /dev/null

@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/gic600_multichip.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-#define RT_OWNER 0
-
-#if defined(IMAGE_BL31)
-static const mmap_region_t rdv1mc_dynamic_mmap[] = {
-	NRD_CSS_SHARED_RAM_MMAP(1),
-	NRD_CSS_PERIPH_MMAP(1),
-	NRD_ROS_PERIPH_MMAP(1),
-#if (NRD_CHIP_COUNT > 2)
-	NRD_CSS_SHARED_RAM_MMAP(2),
-	NRD_CSS_PERIPH_MMAP(2),
-	NRD_ROS_PERIPH_MMAP(2),
-#endif
-#if (NRD_CHIP_COUNT > 3)
-	NRD_CSS_SHARED_RAM_MMAP(3),
-	NRD_CSS_PERIPH_MMAP(3),
-	NRD_ROS_PERIPH_MMAP(3)
-#endif
-};
-
-static struct gic600_multichip_data rdv1mc_multichip_data __init = {
-	.base_addrs = {
-		PLAT_ARM_GICD_BASE
-	},
-	.rt_owner = RT_OWNER,
-	.chip_count = NRD_CHIP_COUNT,
-	.chip_addrs = {
-		[RT_OWNER] = {
-			PLAT_ARM_GICD_BASE >> 16,
-			(PLAT_ARM_GICD_BASE
-				+ NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
-#if (NRD_CHIP_COUNT > 2)
-			(PLAT_ARM_GICD_BASE
-				+ NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
-#endif
-#if (NRD_CHIP_COUNT > 3)
-			(PLAT_ARM_GICD_BASE
-				+ NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
-#endif
-		}
-	},
-	.spi_ids = {
-		{PLAT_ARM_GICD_BASE,
-		NRD_CHIP0_SPI_MIN,
-		NRD_CHIP0_SPI_MAX},
-		{0, 0, 0},
-#if (NRD_CHIP_COUNT > 2)
-		{0, 0, 0},
-#endif
-#if (NRD_CHIP_COUNT > 3)
-		{0, 0, 0},
-#endif
-	}
-};
-
-static uintptr_t rdv1mc_multichip_gicr_frames[] = {
-	/* Chip 0's GICR Base */
-	PLAT_ARM_GICR_BASE,
-	/* Chip 1's GICR BASE */
-	PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
-#if (NRD_CHIP_COUNT > 2)
-	/* Chip 2's GICR BASE */
-	PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
-#endif
-#if (NRD_CHIP_COUNT > 3)
-	/* Chip 3's GICR BASE */
-	PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
-#endif
-	UL(0)	/* Zero Termination */
-};
-#endif /* IMAGE_BL31 */
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
-				& SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
-	return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
-			SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-/*
- * bl31_platform_setup_function is guarded by IMAGE_BL31 macro because
- * PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
- * for other stages.
- */
-#if defined(IMAGE_BL31)
-void bl31_platform_setup(void)
-{
-	int ret;
-	unsigned int i;
-
-	if ((plat_arm_nrd_get_multi_chip_mode() == 0) &&
-			(NRD_CHIP_COUNT > 1)) {
-		ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
-			NRD_CHIP_COUNT);
-		panic();
-	} else if ((plat_arm_nrd_get_multi_chip_mode() == 1) &&
-			(NRD_CHIP_COUNT > 1)) {
-		INFO("Enabling support for multi-chip in RD-V1-MC\n");
-
-		for (i = 0; i < ARRAY_SIZE(rdv1mc_dynamic_mmap); i++) {
-			ret = mmap_add_dynamic_region(
-					rdv1mc_dynamic_mmap[i].base_pa,
-					rdv1mc_dynamic_mmap[i].base_va,
-					rdv1mc_dynamic_mmap[i].size,
-					rdv1mc_dynamic_mmap[i].attr);
-			if (ret != 0) {
-				ERROR("Failed to add dynamic mmap entry "
-						"(ret=%d)\n", ret);
-				panic();
-			}
-		}
-
-		plat_arm_override_gicr_frames(
-			rdv1mc_multichip_gicr_frames);
-		gic600_multichip_init(&rdv1mc_multichip_data);
-	}
-
-	nrd_bl31_common_platform_setup();
-}
-#endif /* IMAGE_BL31 */

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
deleted file mode 100644
index 1e59831..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ /dev/null

@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-/* TZC memory regions for the first chip */
-static const arm_tzc_regions_info_t tzc_regions[] = {
-	ARM_TZC_REGIONS_DEF,
-	{}
-};
-
-#if NRD_CHIP_COUNT > 1
-static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
-	{
-		/* TZC memory regions for second chip */
-		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
-		{}
-	},
-#if NRD_CHIP_COUNT > 2
-	{
-		/* TZC memory regions for third chip */
-		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
-		{}
-	},
-#endif
-#if NRD_CHIP_COUNT > 3
-	{
-		/* TZC memory regions for fourth chip */
-		NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
-		{}
-	},
-#endif
-};
-#endif /* NRD_CHIP_COUNT */
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	unsigned int i;
-
-	INFO("Configuring TrustZone Controller for Chip 0\n");
-
-	for (i = 0; i < TZC400_COUNT; i++) {
-		arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
-	}
-
-#if NRD_CHIP_COUNT > 1
-	unsigned int j;
-
-	for (i = 1; i < NRD_CHIP_COUNT; i++) {
-		INFO("Configuring TrustZone Controller for Chip %u\n", i);
-
-		for (j = 0; j < TZC400_COUNT; j++) {
-			arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
-				+ TZC400_BASE(j), tzc_regions_mc[i-1]);
-		}
-	}
-#endif
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
deleted file mode 100644
index 52514ca..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
+++ /dev/null

@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-#include <nrd_variant.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
-	((PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT)),
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_CHIP_COUNT > 1)
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-#endif
-#if (NRD_CHIP_COUNT > 2)
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-#endif
-#if (NRD_CHIP_COUNT > 3)
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	if (plat_arm_nrd_get_multi_chip_mode() == 1)
-		return rd_v1_mc_pd_tree_desc_multi_chip;
-	panic();
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
-#if (NRD_CHIP_COUNT > 1)
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
-#endif
-#if (NRD_CHIP_COUNT > 2)
-	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
-#endif
-#if (NRD_CHIP_COUNT > 3)
-	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3))
-#endif
-};

diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c
+++ /dev/null

@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier  ::=  SEQUENCE  {
- *     algorithm         OBJECT IDENTIFIER,
- *     parameters        ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- *     digestAlgorithm   AlgorithmIdentifier,
- *     digest            OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-			unsigned int *flags)
-{
-	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}

diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index 1ddd0e4..c587a55 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk

@@ -178,5 +178,6 @@
 ifeq (${SPD},spmd)
 ifeq (${SPMD_SPM_AT_SEL2},1)
 override CTX_INCLUDE_SVE_REGS	:= 0
+override CTX_INCLUDE_FPREGS	:= 0
 endif
 endif

diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c
index b1ee5e6..ac1f893 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c

@@ -193,7 +193,8 @@
 int plat_rmmd_mecid_key_update(uint16_t mecid)
 {
 	/*
-	 * TODO
+	 * RDV3 does not support FEAT_MEC.
+	 * This empty hook is for compilation to succeed.
 	 */
 	return 0;
 }

diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
index f5160ce..c3abc4f 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,7 +34,7 @@
 	return err;
 }
 
-int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, unsigned int pk_len)
 {
 	return rse_mboot_set_signer_id(rdv3_rse_mboot_metadata, pk_oid,
 				       pk_ptr, pk_len);

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_fw_config.dts b/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_fw_config.dts
deleted file mode 100644
index fe62b6d..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_fw_config.dts
+++ /dev/null

@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
-	dtb-registry {
-		compatible = "fconf,dyn_cfg-dtb_registry";
-
-		tb_fw-config {
-			load-address = <0x0 0x4001300>;
-			max-size = <0x200>;
-			id = <TB_FW_CONFIG_ID>;
-		};
-
-		nt_fw-config {
-			load-address = <0x0 0xFEF00000>;
-			max-size = <0x0100000>;
-			id = <NT_FW_CONFIG_ID>;
-		};
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_nt_fw_config.dts
deleted file mode 100644
index 0573488..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_nt_fw_config.dts
+++ /dev/null

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,sgi575";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-		multi-chip-mode = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_tb_fw_config.dts
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
-	tb_fw-config {
-		compatible = "arm,tb_fw";
-
-		/* Disable authentication for development */
-		disable_auth = <0x0>;
-
-		/*
-		 * The following two entries are placeholders for Mbed TLS
-		 * heap information. The default values don't matter since
-		 * they will be overwritten by BL1.
-		 * In case of having shared Mbed TLS heap between BL1 and BL2,
-		 * BL1 will populate these two properties with the respective
-		 * info about the shared heap. This info will be available for
-		 * BL2 in order to locate and re-use the heap.
-		 */
-		mbedtls_heap_addr = <0x0 0x0>;
-		mbedtls_heap_size = <0x0>;
-	};
-};

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
deleted file mode 100644
index 0797017..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ /dev/null

@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-#include <nrd_sdei.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
-		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT		U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER	U(4)
-#define NRD_MAX_PE_PER_CPU		U(1)
-
-#define PLAT_CSS_MHU_BASE		UL(0x45000000)
-
-/* Base address of DMC-620 instances */
-#define SGI575_DMC620_BASE0		UL(0x4e000000)
-#define SGI575_DMC620_BASE1		UL(0x4e100000)
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP	U(36)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICR_BASE		UL(0x300C0000)
-
-#endif /* PLATFORM_DEF_H */

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
deleted file mode 100644
index 1f40107..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ /dev/null

@@ -1,73 +0,0 @@
-#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-SGI575_BASE		=	plat/arm/board/neoverse_rd/platform/sgi575
-
-PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
-				-I${SGI575_BASE}/include/
-
-NRD_CPU_SOURCES		:=	lib/cpus/aarch64/cortex_a75.S
-
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${SGI575_BASE}/sgi575_err.c
-
-BL2_SOURCES		+=	${SGI575_BASE}/sgi575_plat.c		\
-				${SGI575_BASE}/sgi575_security.c	\
-				${SGI575_BASE}/sgi575_err.c		\
-				drivers/arm/tzc/tzc_dmc620.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${SGI575_BASE}/sgi575_plat.c		\
-				${SGI575_BASE}/sgi575_topology.c	\
-				drivers/cfi/v2m/v2m_flash.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES		+=	${SGI575_BASE}/sgi575_trusted_boot.c
-BL2_SOURCES		+=	${SGI575_BASE}/sgi575_trusted_boot.c
-endif
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${SGI575_BASE}/fdts/${PLAT}_fw_config.dts	\
-				${SGI575_BASE}/fdts/${PLAT}_tb_fw_config.dts
-
-FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES		+=	${SGI575_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-ifneq ($(NRD_CHIP_COUNT),1)
- $(error  "Chip count for SGI575 should be 1, currently set to \
-   ${NRD_CHIP_COUNT}.")
-endif
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for SGI575 should always be 0,\
-     currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
-  $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
-  Please set RESET_TO_BL31 to 0.")
-endif
-
-override SPMD_SPM_AT_SEL2		:= 0

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_err.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_err.c
deleted file mode 100644
index 7e656ab..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_err.c
+++ /dev/null

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * sgi575 error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
-	while (true) {
-		wfi();
-	}
-}

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_plat.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_plat.c
deleted file mode 100644
index 8b74616..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_plat.c
+++ /dev/null

@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-#include <nrd_variant.h>
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
-	return mmio_read_32(SSC_VERSION) & SSC_VERSION_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
-	return (mmio_read_32(SSC_VERSION) >> SSC_VERSION_CONFIG_SHIFT)
-			& SSC_VERSION_CONFIG_MASK;
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
-	return 0;
-}
-
-void bl31_platform_setup(void)
-{
-	nrd_bl31_common_platform_setup();
-}

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
deleted file mode 100644
index 8b8a382..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
+++ /dev/null

@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <nrd_dmc620_tzc_regions.h>
-
-uintptr_t sgi575_dmc_base[] = {
-	SGI575_DMC620_BASE0,
-	SGI575_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = {
-	.dmc_base = sgi575_dmc_base,
-	.dmc_count = ARRAY_SIZE(sgi575_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
-	NRD_DMC620_TZC_REGIONS_DEF
-};
-
-static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
-	.plat_drv_data = &sgi575_plat_driver_data,
-	.plat_acc_addr_data = sgi575_acc_addr_data,
-	.acc_addr_count = ARRAY_SIZE(sgi575_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	arm_tzc_dmc620_setup(&sgi575_plat_config_data);
-}

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
deleted file mode 100644
index 15ffc65..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
+++ /dev/null

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-static const unsigned char sgi575_pd_tree_desc[] = {
-	PLAT_ARM_CLUSTER_COUNT,
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return sgi575_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
-	0, 1, 2, 3, 4, 5, 6, 7
-};

diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_trusted_boot.c
+++ /dev/null

@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier  ::=  SEQUENCE  {
- *     algorithm         OBJECT IDENTIFIER,
- *     parameters        ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- *     digestAlgorithm   AlgorithmIdentifier,
- *     digest            OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-			unsigned int *flags)
-{
-	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}

diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 71f7bb3..76bae38 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,6 +34,28 @@
 
 #define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00080000	/* 512 KB */
 
+#if TRANSFER_LIST
+/*
+ * Summation of data size of all Transfer Entries included in the Transfer list.
+ * Note: Update this field whenever new Transfer Entries are added in future.
+ */
+#define PLAT_ARM_FW_HANDOFF_SIZE	U(0x9000)
+#define PLAT_ARM_EL3_FW_HANDOFF_BASE	ARM_BL_RAM_BASE
+#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT	PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+#define FW_NS_HANDOFF_BASE		(PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE)
+
+/* Mappings for Secure and Non-secure Transfer_list */
+#define TC_MAP_EL3_FW_HANDOFF		MAP_REGION_FLAT(		\
+					PLAT_ARM_EL3_FW_HANDOFF_BASE,	\
+					PLAT_ARM_FW_HANDOFF_SIZE,	\
+					MT_MEMORY | MT_RW | EL3_PAS)
+
+#define TC_MAP_FW_NS_HANDOFF		MAP_REGION_FLAT(		\
+					FW_NS_HANDOFF_BASE,		\
+					PLAT_ARM_FW_HANDOFF_SIZE,	\
+					MT_MEMORY | MT_RW | MT_NS)
+#endif /* TRANSFER_LIST */
+
 /*
  * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
  * its base is ARM_AP_TZC_DRAM1_BASE.
@@ -236,11 +258,7 @@
 #define TC_FLASH0_RO	MAP_REGION_FLAT(V2M_FLASH0_BASE,\
 						V2M_FLASH0_SIZE,	\
 						MT_DEVICE | MT_RO | MT_SECURE)
-#if TARGET_PLATFORM == 2
-#define PLAT_ARM_NSTIMER_FRAME_ID	U(0)
-#else
 #define PLAT_ARM_NSTIMER_FRAME_ID	U(1)
-#endif
 
 #define PLAT_ARM_TRUSTED_ROM_BASE	0x0
 
@@ -254,10 +272,7 @@
 #define PLAT_ARM_NSRAM_SIZE		0x00008000	/* 64KB */
 #endif /* TARGET_FLAVOUR_FPGA */
 
-#if TARGET_PLATFORM <= 2
-#define PLAT_ARM_DRAM2_BASE		ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE             ULL(0x180000000)
-#elif TARGET_PLATFORM >= 3
+#if TARGET_PLATFORM >= 3
 
 #if TC_FPGA_FS_IMG_IN_RAM
 /* 10GB reserved for system+userdata+vendor images */
@@ -326,28 +341,19 @@
 					 CSS_SCMI_PAYLOAD_SIZE_MAX)
 
 #define PLAT_ARM_CLUSTER_COUNT		U(1)
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2
-#define PLAT_MAX_CPUS_PER_CLUSTER	U(14)
-#else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
 #define PLAT_MAX_CPUS_PER_CLUSTER	U(8)
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
 #define PLAT_MAX_PE_PER_CPU		U(1)
 
 #define PLATFORM_CORE_COUNT		(PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT)
 
 /* Message Handling Unit (MHU) base addresses */
-#if TARGET_PLATFORM <= 2
-	#define PLAT_CSS_MHU_BASE		UL(0x45400000)
-#elif TARGET_PLATFORM >= 3
+#if TARGET_PLATFORM >= 3
 	#define PLAT_CSS_MHU_BASE		UL(0x46000000)
 #endif /* TARGET_PLATFORM >= 3 */
 #define PLAT_MHUV2_BASE			PLAT_CSS_MHU_BASE
 
 /* AP<->RSS MHUs */
-#if TARGET_PLATFORM <= 2
-#define PLAT_RSE_AP_SND_MHU_BASE	UL(0x2A840000)
-#define PLAT_RSE_AP_RCV_MHU_BASE	UL(0x2A850000)
-#elif TARGET_PLATFORM == 3
+#if TARGET_PLATFORM == 3
 #define PLAT_RSE_AP_SND_MHU_BASE	UL(0x49000000)
 #define PLAT_RSE_AP_RCV_MHU_BASE	UL(0x49100000)
 #elif TARGET_PLATFORM == 4
@@ -381,36 +387,6 @@
  */
 #define PLAT_CSS_MAX_SCP_BL2U_SIZE	0x30000
 
-#if TARGET_PLATFORM <= 2
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE		UL(0x25000000)
-#define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET			UL(0x1000000)
-#define TZC400_COUNT			4
-
-#define TZC400_BASE(n)			(PLAT_ARM_TZC_BASE + \
-					 (n * TZC400_OFFSET))
-
-#define TZC_NSAID_DEFAULT		U(0)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS	\
-		(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
-
-/*
- * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to
- * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as
- * secure. The second and third regions gives non secure access to rest of DRAM.
- */
-#define TC_TZC_REGIONS_DEF	\
-	{TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END,	\
-		TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS},	\
-	{TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS,	\
-		PLAT_ARM_TZC_NS_DEV_ACCESS},	\
-	{PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END,	\
-		ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-#endif
-
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
@@ -446,13 +422,11 @@
 #undef  ARM_CONSOLE_BAUDRATE
 #define ARM_CONSOLE_BAUDRATE		38400
 
-#if TARGET_PLATFORM <= 2
-#define TC_UARTCLK			5000000
-#elif TARGET_PLATFORM == 3
+#if TARGET_PLATFORM == 3
 #define TC_UARTCLK			3750000
 #elif TARGET_PLATFORM == 4
 #define TC_UARTCLK			4000000
-#endif /* TARGET_PLATFORM <=2 */
+#endif /* TARGET_PLATFORM == 3 */
 
 
 #if TARGET_FLAVOUR_FVP

diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index cc2f760..9a8172a 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -74,10 +74,6 @@
 	ret
 endfunc enable_dsu_pmu_el1_access
 
-func TC_HANDLER(2)
-	ret
-endfunc TC_HANDLER(2)
-
 func TC_HANDLER(3)
 	mov	x9, lr
 	bl	mark_extllc_presence

diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index a056bc2..9dd867d 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk

@@ -15,6 +15,7 @@
 CSS_USE_SCMI_SDS_DRIVER		:=	1
 HW_ASSISTED_COHERENCY		:=	1
 USE_COHERENT_MEM		:=	0
+USE_GIC_DRIVER			:=	3
 GIC_ENABLE_V4_EXTN		:=      1
 GICV3_SUPPORT_GIC600		:=	1
 override NEED_BL2U		:=	no
@@ -35,8 +36,8 @@
 ENABLE_AMU_AUXILIARY_COUNTERS	:=	1
 ENABLE_MPMM			:=	1
 ENABLE_FEAT_MTE2		:=	2
-ENABLE_SPE_FOR_NS		:=	3
-ENABLE_FEAT_TCR2		:=	3
+ENABLE_SPE_FOR_NS		:=	2
+ENABLE_FEAT_TCR2		:=	2
 
 ifneq ($(filter ${TARGET_PLATFORM}, 3),)
 ENABLE_FEAT_RNG_TRAP		:=	0
@@ -66,15 +67,10 @@
 endif
 endif
 
-ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
+ifneq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
         $(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.)
 endif
 
-ifneq ($(shell expr $(TARGET_PLATFORM) = 2), 0)
-        $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
-          Some of the features might not work as expected)
-endif
-
 ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0)
         $(error TARGET_PLATFORM must be less than or equal to 4)
 endif
@@ -108,42 +104,13 @@
 # Save DSU PMU registers on cluster off and restore them on cluster on
 PRESERVE_DSU_PMU_REGS		:= 1
 
-# Specify MHU type based on platform
-ifneq ($(filter ${TARGET_PLATFORM}, 2),)
-	PLAT_MHU		:= MHUv2
-else
-	PLAT_MHU		:= MHUv3
-endif
-
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-ENT_GIC_SOURCES		:=	${GICV3_SOURCES}		\
-				plat/common/plat_gicv3.c	\
-				plat/arm/common/arm_gicv3.c
+PLAT_MHU		:= MHUv3
 
 TC_BASE	=	plat/arm/board/tc
 
 PLAT_INCLUDES		+=	-I${TC_BASE}/include/ \
 				-I${TC_BASE}/fdts/
 
-# CPU libraries for TARGET_PLATFORM=1
-ifeq (${TARGET_PLATFORM}, 1)
-TC_CPU_SOURCES	+=	lib/cpus/aarch64/cortex_a510.S \
-			lib/cpus/aarch64/cortex_a715.S \
-			lib/cpus/aarch64/cortex_x3.S
-endif
-
-# CPU libraries for TARGET_PLATFORM=2
-ifeq (${TARGET_PLATFORM}, 2)
-ERRATA_A520_2938996	:=	1
-ERRATA_X4_2726228	:=	1
-
-TC_CPU_SOURCES	+=	lib/cpus/aarch64/cortex_a520.S \
-			lib/cpus/aarch64/cortex_a720.S \
-			lib/cpus/aarch64/cortex_x4.S
-endif
-
 # CPU libraries for TARGET_PLATFORM=3
 ifeq (${TARGET_PLATFORM}, 3)
 ERRATA_A520_2938996	:=	1
@@ -189,18 +156,13 @@
 				drivers/arm/tzc/tzc400.c		\
 				plat/arm/common/arm_nor_psci_mem_protect.c
 
-ifeq ($(shell test $(TARGET_PLATFORM) -le 2; echo $$?),0)
-BL2_SOURCES		+=	plat/arm/common/arm_tzc400.c
-endif
-
 BL31_SOURCES		+=	${INTERCONNECT_SOURCES}	\
 				${TC_CPU_SOURCES}	\
-				${ENT_GIC_SOURCES}			\
 				${TC_BASE}/tc_bl31_setup.c	\
 				${TC_BASE}/tc_topology.c	\
 				lib/fconf/fconf.c			\
 				lib/fconf/fconf_dyn_cfg_getter.c	\
-				drivers/arm/css/dsu/dsu.c			\
+				drivers/arm/dsu/dsu.c			\
 				drivers/cfi/v2m/v2m_flash.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c	\

diff --git a/plat/arm/board/tc/tc_bl2_setup.c b/plat/arm/board/tc/tc_bl2_setup.c
index 74ef569..b5d3a1a 100644
--- a/plat/arm/board/tc/tc_bl2_setup.c
+++ b/plat/arm/board/tc/tc_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2025, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,17 +18,26 @@
  ******************************************************************************/
 struct bl_params *plat_get_next_bl_params(void)
 {
-	struct bl_params *arm_bl_params = arm_get_next_bl_params();
-
-	const struct dyn_cfg_dtb_info_t *fw_config_info;
+	struct bl_params *arm_bl_params;
 	bl_mem_params_node_t *param_node;
-	uintptr_t fw_config_base = 0U;
-	entry_point_info_t *ep_info;
+	const struct dyn_cfg_dtb_info_t *fw_config_info __maybe_unused;
+	uintptr_t fw_config_base __maybe_unused;
+	entry_point_info_t *ep_info __maybe_unused;
+
+	arm_bl_params = arm_get_next_bl_params();
 
 	/* Get BL31 image node */
 	param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
 	assert(param_node != NULL);
+#if TRANSFER_LIST
+	assert(arm_bl_params != NULL);
 
+	arm_bl_params->head = &param_node->params_node_mem;
+	arm_bl_params->head->ep_info = &param_node->ep_info;
+	arm_bl_params->head->image_id = param_node->image_id;
+
+	arm_bl2_setup_next_ep_info(param_node);
+#else
 	/* Get fw_config load address */
 	fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
 	assert(fw_config_info != NULL);
@@ -42,6 +51,7 @@
 	 */
 	ep_info = &param_node->ep_info;
 	ep_info->args.arg1 = (uint32_t)fw_config_base;
+#endif /* TRANSFER_LIST */
 
 	return arm_bl_params;
 }

diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 5d19aeb..7f2014b 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c

@@ -54,15 +54,6 @@
 }
 #endif /* PLATFORM_TEST_TFM_TESTSUITE */
 
-#if TARGET_PLATFORM <= 2
-static scmi_channel_plat_info_t tc_scmi_plat_info = {
-	.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
-	.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
-	.db_preserve_mask = 0xfffffffe,
-	.db_modify_mask = 0x1,
-	.ring_doorbell = &mhuv2_ring_doorbell,
-};
-#elif TARGET_PLATFORM >= 3
 static scmi_channel_plat_info_t tc_scmi_plat_info = {
 	.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
 	.db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
@@ -70,7 +61,6 @@
 	.db_modify_mask = 0x1,
 	.ring_doorbell = &mhu_ring_doorbell,
 };
-#endif
 
 /* the bottom 3 AMU group 1 counters */
 #define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2))
@@ -154,10 +144,15 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	/* Initialize the console to provide early debug support */
+	arm_console_boot_init();
 
+	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
+
+#if !TRANSFER_LIST
 	/* Fill the properties struct with the info from the config dtb */
 	fconf_populate("FW_CONFIG", arg1);
+#endif
 }
 
 #ifdef PLATFORM_TESTS
@@ -202,6 +197,13 @@
 {
 	arm_bl31_plat_arch_setup();
 
+	/*
+	 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List
+	 * as an entry with the tag TL_TAG_FDT. In this case, the configuration
+	 * is already available, so the fconf_populate mechanism is not needed.
+	 * The code block below is only required when TRANSFER_LIST is not used.
+	 */
+#if !TRANSFER_LIST
 	/* HW_CONFIG was also loaded by BL2 */
 	const struct dyn_cfg_dtb_info_t *hw_config_info;
 
@@ -209,6 +211,7 @@
 	assert(hw_config_info != NULL);
 
 	fconf_populate("HW_CONFIG", hw_config_info->config_addr);
+#endif
 }
 
 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)

diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index 1ecfdb9..fcee784 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,6 +33,9 @@
 	TC_MAP_NS_DRAM1,
 	TC_FLASH0_RO,
 	TC_MAP_DEVICE,
+#if TRANSFER_LIST
+	TC_MAP_EL3_FW_HANDOFF,
+#endif
 	{0}
 };
 #endif
@@ -59,6 +62,9 @@
 	ARM_MAP_OPTEE_CORE_MEM,
 	ARM_OPTEE_PAGEABLE_LOAD_MEM,
 #endif
+#if TRANSFER_LIST
+	TC_MAP_EL3_FW_HANDOFF,
+#endif
 	{0}
 };
 #endif
@@ -72,6 +78,10 @@
 #if SPM_MM
 	ARM_SPM_BUF_EL3_MMAP,
 #endif
+#if TRANSFER_LIST
+	TC_MAP_FW_NS_HANDOFF,
+	TC_MAP_EL3_FW_HANDOFF,
+#endif
 	{0}
 };
 

diff --git a/plat/arm/board/tc/tc_security.c b/plat/arm/board/tc/tc_security.c
index 7c7a1a1..804a35b 100644
--- a/plat/arm/board/tc/tc_security.c
+++ b/plat/arm/board/tc/tc_security.c

@@ -7,21 +7,8 @@
 #include <plat/arm/common/plat_arm.h>
 #include <platform_def.h>
 
-#if (TARGET_PLATFORM <= 2)
-static const arm_tzc_regions_info_t tzc_regions[] = {
-	TC_TZC_REGIONS_DEF,
-	{}
-};
-#endif
-
 /* Initialize the secure environment */
 void plat_arm_security_setup(void)
 {
-#if (TARGET_PLATFORM <= 2)
-	unsigned int i;
 
-	for (i = 0U; i < TZC400_COUNT; i++) {
-		arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
-	}
-#endif
 }

diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index b8e5027..06a919c 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -90,7 +90,7 @@
 	bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
 
 #if TRANSFER_LIST
-	secure_tl = transfer_list_ensure((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
+	secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
 					 PLAT_ARM_FW_HANDOFF_SIZE);
 	assert(secure_tl != NULL);
 #endif
@@ -289,18 +289,17 @@
 	return  is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
 }
 
-// Use the default implementation of this function when Firmware Handoff is
-// disabled to avoid duplicating its logic.
 #if TRANSFER_LIST
 int bl1_plat_handle_post_image_load(unsigned int image_id)
 {
-	image_desc_t *image_desc __unused;
-
-	assert(image_id == BL2_IMAGE_ID);
 	struct transfer_list_entry *te;
 
+	if (image_id != BL2_IMAGE_ID) {
+		return 0;
+	}
+
 	/* Convey this information to BL2 via its TL. */
-	te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT64,
+	te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT,
 			       sizeof(meminfo_t), NULL);
 	assert(te != NULL);
 

diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 17dc0ed..522017f 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -66,8 +66,8 @@
  * in x0. This memory layout is sitting at the base of the free trusted SRAM.
  * Copy it to a safe location before its reclaimed by later BL2 functionality.
  ******************************************************************************/
-void arm_bl2_early_platform_setup(uintptr_t fw_config,
-				  struct meminfo *mem_layout)
+void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1,
+				  u_register_t arg2, u_register_t arg3)
 {
 	struct transfer_list_entry *te __unused;
 	int __maybe_unused ret;
@@ -76,20 +76,19 @@
 	arm_console_boot_init();
 
 #if TRANSFER_LIST
-	// TODO: modify the prototype of this function fw_config != bl2_tl
-	secure_tl = (struct transfer_list_header *)fw_config;
+	secure_tl = (struct transfer_list_header *)arg3;
 
-	te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64);
+	te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT);
 	assert(te != NULL);
 
 	bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te);
 	transfer_list_rem(secure_tl, te);
 #else
-	config_base = fw_config;
+	config_base = (uintptr_t)arg0;
 
 	/* Setup the BL2 memory layout */
-	bl2_tzram_layout = *mem_layout;
-#endif
+	bl2_tzram_layout = *(meminfo_t *)arg1;
+#endif /* TRANSFER_LIST */
 
 	/* Initialise the IO layer and register platform IO devices */
 	plat_arm_io_setup();
@@ -105,9 +104,10 @@
 #endif /* ARM_GPT_SUPPORT */
 }
 
-void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+			       u_register_t arg2, u_register_t arg3)
 {
-	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+	arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	generic_delay_timer_init();
 }
@@ -320,6 +320,13 @@
 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node)
 {
 	entry_point_info_t *ep __unused;
+
+	/*
+	 * Information might have been added to the TL before this (i.e. event log)
+	 * make sure the checksum is up to date.
+	 */
+	transfer_list_update_checksum(secure_tl);
+
 	ep = transfer_list_set_handoff_args(secure_tl,
 					    &next_param_node->ep_info);
 	assert(ep != NULL);

diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 0503acf..f196269 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c

@@ -133,7 +133,12 @@
 	}
 #endif
 	else {
+#if TRANSFER_LIST && !RESET_TO_BL31
+		next_image_info = transfer_list_set_handoff_args(
+			secure_tl, &bl32_image_ep_info);
+#else
 		next_image_info = &bl32_image_ep_info;
+#endif
 	}
 
 	/*
@@ -154,10 +159,10 @@
  * while creating page tables. BL2 has flushed this information to memory, so
  * we are guaranteed to pick up good data.
  ******************************************************************************/
-#if TRANSFER_LIST
 void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
 					  u_register_t arg2, u_register_t arg3)
 {
+#if TRANSFER_LIST
 #if RESET_TO_BL31
 	/* Populate entry point information for BL33 */
 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
@@ -208,18 +213,11 @@
 		}
 	}
 #endif /* RESET_TO_BL31 */
-}
-#else
-void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
-				uintptr_t hw_config, void *plat_params_from_bl2)
-{
-	/* Initialize the console to provide early debug support */
-	arm_console_boot_init();
-
+#else /* (!TRANSFER_LIST) */
 #if RESET_TO_BL31
 	/* There are no parameters from BL2 if BL31 is a reset vector */
-	assert(from_bl2 == NULL);
-	assert(plat_params_from_bl2 == NULL);
+	assert((uintptr_t)arg0 == 0U);
+	assert((uintptr_t)arg3 == 0U);
 
 # ifdef BL32_BASE
 	/* Populate entry point information for BL32 */
@@ -258,21 +256,20 @@
 	 */
 	rmm_image_ep_info.pc = RMM_BASE;
 #endif /* ENABLE_RME */
-
 #else /* RESET_TO_BL31 */
-
 	/*
-	 * In debug builds, we pass a special value in 'plat_params_from_bl2'
+	 * In debug builds, we pass a special value in 'arg3'
 	 * to verify platform parameters from BL2 to BL31.
 	 * In release builds, it's not used.
 	 */
-	assert(((unsigned long long)plat_params_from_bl2) ==
-		ARM_BL31_PLAT_PARAM_VAL);
+#if DEBUG
+	assert(((uintptr_t)arg3) == ARM_BL31_PLAT_PARAM_VAL);
+#endif
 
 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
-	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+	bl_params_t *params_from_bl2 = (bl_params_t *)(uintptr_t)arg0;
 	assert(params_from_bl2 != NULL);
 	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
 	assert(params_from_bl2->h.version >= VERSION_2);
@@ -325,7 +322,7 @@
 #endif
 #endif /* RESET_TO_BL31 */
 
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
 	/*
 	 * According to the file ``Documentation/arm64/booting.txt`` of the
 	 * Linux kernel tree, Linux expects the physical address of the device
@@ -339,23 +336,19 @@
 #if RESET_TO_BL31
 	bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
 #else
-	bl33_image_ep_info.args.arg0 = (u_register_t)hw_config;
-#endif
+	bl33_image_ep_info.args.arg0 = arg2;
+#endif /* RESET_TO_BL31 */
 	bl33_image_ep_info.args.arg1 = 0U;
 	bl33_image_ep_info.args.arg2 = 0U;
 	bl33_image_ep_info.args.arg3 = 0U;
-# endif
+#endif /* ARM_LINUX_KERNEL_AS_BL33 */
+#endif /* TRANSFER_LIST */
 }
-#endif
 
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		u_register_t arg2, u_register_t arg3)
 {
-#if TRANSFER_LIST
 	arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
-#else
-	arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
-#endif
 
 	/*
 	 * Initialize Interconnect for this cluster during cold boot.
@@ -382,8 +375,8 @@
 	struct transfer_list_entry *te __unused;
 
 #if TRANSFER_LIST && !RESET_TO_BL31
-	ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE,
-				       PLAT_ARM_FW_HANDOFF_SIZE);
+	ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE,
+				   PLAT_ARM_FW_HANDOFF_SIZE);
 	if (ns_tl == NULL) {
 		ERROR("Non-secure transfer list initialisation failed!\n");
 		panic();
@@ -406,11 +399,17 @@
 	te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
 			       transfer_list_entry_data(te));
 	assert(te != NULL);
-#endif /* TRANSFER_LIST && !RESET_TO_BL31 */
 
-	/* Initialize the GIC driver, cpu and distributor interfaces */
-	plat_arm_gic_driver_init();
-	plat_arm_gic_init();
+	te = transfer_list_find(secure_tl, TL_TAG_TPM_EVLOG);
+	if (te != NULL) {
+		te = transfer_list_add(ns_tl, TL_TAG_TPM_EVLOG, te->data_size,
+				  transfer_list_entry_data(te));
+		if (te == NULL) {
+			ERROR("Failed to load event log in Non-Secure transfer list\n");
+			panic();
+		}
+	}
+#endif /* TRANSFER_LIST && !RESET_TO_BL31 */
 
 #if RESET_TO_BL31
 	/*

diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index c8f6b41..53fe806 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk

@@ -79,6 +79,15 @@
 $(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
 $(eval $(call add_define,ARM_BL31_IN_DRAM))
 
+# Macro to enable ACS SMC handler
+PLAT_ARM_ACS_SMC_HANDLER	:=	0
+ifeq (${ENABLE_ACS_SMC}, 1)
+PLAT_ARM_ACS_SMC_HANDLER	:=	1
+endif
+
+# Build macro necessary for branching to ACS tests
+$(eval $(call add_define,PLAT_ARM_ACS_SMC_HANDLER))
+
 # As per CCA security model, all root firmware must execute from on-chip secure
 # memory. This means we must not run BL31 from TZC-protected DRAM.
 ifeq (${ARM_BL31_IN_DRAM},1)
@@ -224,14 +233,9 @@
 PLAT_BL_COMMON_SOURCES 	+=	lib/xlat_tables/xlat_tables_common.c	      \
 				lib/xlat_tables/${ARCH}/xlat_tables.c
 else
-ifeq (${XLAT_MPU_LIB_V1}, 1)
-include lib/xlat_mpu/xlat_mpu.mk
-PLAT_BL_COMMON_SOURCES	+=	${XLAT_MPU_LIB_V1_SRCS}
-else
 include lib/xlat_tables_v2/xlat_tables.mk
 PLAT_BL_COMMON_SOURCES	+=      ${XLAT_TABLES_LIB_SRCS}
 endif
-endif
 
 ARM_IO_SOURCES		+=	plat/arm/common/arm_io_storage.c		\
 				plat/arm/common/fconf/arm_fconf_io.c
@@ -310,7 +314,13 @@
 				plat/arm/common/arm_topology.c			\
 				plat/common/plat_psci_common.c
 
+ifeq (${PLAT_ARM_ACS_SMC_HANDLER},1)
+BL31_SOURCES		+=	plat/arm/common/plat_acs_smc_handler.c		\
+				${VENDOR_EL3_SRCS}
+endif
+
 ifeq (${TRANSFER_LIST}, 1)
+	include lib/transfer_list/transfer_list.mk
 	TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c
 endif
 
@@ -360,7 +370,7 @@
 endif
 
 # Pointer Authentication sources
-ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3))
+ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3 5))
 PLAT_BL_COMMON_SOURCES	+=	plat/arm/common/aarch64/arm_pauth.c
 endif
 
@@ -392,8 +402,9 @@
 ifneq (${TRUSTED_BOARD_BOOT},0)
 
     # Include common TBB sources
-    AUTH_SOURCES 	:= 	drivers/auth/auth_mod.c	\
-				drivers/auth/img_parser_mod.c
+    AUTH_MK := drivers/auth/auth.mk
+    $(info Including ${AUTH_MK})
+    include ${AUTH_MK}
 
     # Include the selected chain of trust sources.
     ifeq (${COT},tbbr)
@@ -460,6 +471,9 @@
     ifeq (${MEASURED_BOOT},1)
          BL1_SOURCES		+= 	${EVENT_LOG_SOURCES}
          BL2_SOURCES		+= 	${EVENT_LOG_SOURCES}
+         ifeq (${SPD_tspd},1)
+             BL32_SOURCES		+= 	${EVENT_LOG_SOURCES}
+         endif
     endif
 
     ifeq (${DRTM_SUPPORT},1)
@@ -467,12 +481,22 @@
     endif
 endif
 
-ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),)
-    CRYPTO_SOURCES	:=	drivers/auth/crypto_mod.c 	\
-				lib/fconf/fconf_tbbr_getter.c
+ifneq ($(filter 1,${MEASURED_BOOT} ${DRTM_SUPPORT}),)
+ifeq (${TRUSTED_BOARD_BOOT},0)
+    CRYPTO_SOURCES	:=	drivers/auth/crypto_mod.c
     BL1_SOURCES		+=	${CRYPTO_SOURCES}
     BL2_SOURCES		+=	${CRYPTO_SOURCES}
+endif
+endif
+
+ifeq (${DRTM_SUPPORT},1)
     BL31_SOURCES	+=	drivers/auth/crypto_mod.c
+endif
+
+ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),)
+    FCONF_TBB_SOURCES	:=	lib/fconf/fconf_tbbr_getter.c
+    BL1_SOURCES		+=	${FCONF_TBB_SOURCES}
+    BL2_SOURCES		+=	${FCONF_TBB_SOURCES}
 
     # We expect to locate the *.mk files under the directories specified below
     CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk

diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index 3e6c9f2..e8d15f7 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c

@@ -148,7 +148,7 @@
 	/* Assert system power domain is available on the platform */
 	assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
 
-	plat_arm_gic_save();
+	gic_save();
 
 	/*
 	 * Unregister console now so that it is not registered for a second
@@ -177,7 +177,7 @@
 	/* Assert system power domain is available on the platform */
 	assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
 
-	plat_arm_gic_resume();
+	gic_resume();
 
 	plat_arm_security_setup();
 	arm_configure_sys_timer();

diff --git a/plat/arm/common/arm_transfer_list.c b/plat/arm/common/arm_transfer_list.c
index 6847591..5a480b6 100644
--- a/plat/arm/common/arm_transfer_list.c
+++ b/plat/arm/common/arm_transfer_list.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -71,9 +71,8 @@
 					struct transfer_list_header *tl)
 {
 	uint32_t next_exe_img_id;
-	entry_point_info_t *ep;
+	entry_point_info_t *ep __unused;
 	struct transfer_list_entry *te;
-
 	assert(next_param_node != NULL);
 
 	while ((next_exe_img_id = next_param_node->next_handoff_image_id) !=
@@ -83,14 +82,16 @@
 				next_exe_img_id)];
 		assert(next_param_node != NULL);
 
-		te = transfer_list_add(tl, TL_TAG_EXEC_EP_INFO64,
+		te = transfer_list_add(tl, TL_TAG_EXEC_EP_INFO,
 				       sizeof(entry_point_info_t),
 				       &next_param_node->ep_info);
 		assert(te != NULL);
 
 		ep = transfer_list_entry_data(te);
+		assert(ep != NULL);
 
-		if ((next_exe_img_id == BL32_IMAGE_ID) && SPMC_AT_EL3) {
+#if SPMC_AT_EL3
+		if (next_exe_img_id == BL32_IMAGE_ID) {
 			/*
 			 * Populate the BL32 image base, size and max limit in
 			 * the entry point information, since there is no
@@ -106,6 +107,7 @@
 				next_param_node->image_info.image_base +
 				next_param_node->image_info.image_max_size;
 		}
+#endif /* SPMC_AT_EL3 */
 
 		next_exe_img_id = next_param_node->next_handoff_image_id;
 	}

diff --git a/plat/arm/common/plat_acs_smc_handler.c b/plat/arm/common/plat_acs_smc_handler.c
new file mode 100644
index 0000000..6f96874
--- /dev/null
+++ b/plat/arm/common/plat_acs_smc_handler.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <plat/arm/common/plat_acs_smc_handler.h>
+
+/*
+ * Placeholder function for handling ACS SMC calls.
+ * return 0  till the handling is done.
+ */
+uintptr_t plat_arm_acs_smc_handler(unsigned int smc_fid, uint64_t services,
+		 uint64_t arg0, uint64_t arg1, uint64_t arg2, void *handle)
+{
+	WARN("Unimplemented ACS Call: 0x%x\n", smc_fid);
+	SMC_RET1(handle, SMC_UNK);
+}

diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 4cd514b..6b15b73 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,6 +16,9 @@
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 
+struct transfer_list_header *secure_tl;
+struct transfer_list_header *ns_tl __unused;
+
 static entry_point_info_t bl33_image_ep_info;
 
 /* Weak definitions may be overridden in specific ARM standard platform */
@@ -28,13 +31,25 @@
 					BL32_END - BL32_BASE,		\
 					MT_MEMORY | MT_RW | MT_SECURE)
 
+#define MAP_EL3_FW_HANDOFF                            \
+	MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
+			PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
+
+#define MAP_FW_NS_HANDOFF                                             \
+	MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
+			MT_MEMORY | MT_RW | MT_NS)
+
 /*
  * Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
  * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
  */
 #if !RESET_TO_SP_MIN
+#if TRANSFER_LIST
+CASSERT(BL32_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl32_base_overflows);
+#else
 CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
 #endif
+#endif
 
 /*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for the
@@ -61,12 +76,25 @@
 /*******************************************************************************
  * Utility function to perform early platform setup.
  ******************************************************************************/
-void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
-			uintptr_t hw_config, void *plat_params_from_bl2)
+void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			u_register_t arg2, u_register_t arg3)
 {
+	struct transfer_list_entry *te __unused;
+
 	/* Initialize the console to provide early debug support */
 	arm_console_boot_init();
 
+#if TRANSFER_LIST
+	secure_tl = (struct transfer_list_header *)arg3;
+
+	te = transfer_list_find(secure_tl, TL_TAG_EXEC_EP_INFO32);
+	assert(te != NULL);
+
+	bl33_image_ep_info =
+		*(struct entry_point_info *)transfer_list_entry_data(te);
+	return;
+#endif /* TRANSFER_LIST */
+
 #if RESET_TO_SP_MIN
 	/* Populate entry point information for BL33 */
 	SET_PARAM_HEAD(&bl33_image_ep_info,
@@ -81,7 +109,7 @@
 	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
 	/*
 	 * According to the file ``Documentation/arm/Booting`` of the Linux
 	 * kernel tree, Linux expects:
@@ -99,7 +127,7 @@
 	/*
 	 * Check params passed from BL2 should not be NULL,
 	 */
-	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+	bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
 	assert(params_from_bl2 != NULL);
 	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
 	assert(params_from_bl2->h.version >= VERSION_2);
@@ -132,7 +160,7 @@
 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
-	arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+	arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/*
 	 * Initialize Interconnect for this cluster during cold boot.
@@ -176,9 +204,35 @@
  ******************************************************************************/
 void sp_min_platform_setup(void)
 {
+	struct transfer_list_entry *te __unused;
+
 	/* Initialize the GIC driver, cpu and distributor interfaces */
-	plat_arm_gic_driver_init();
-	plat_arm_gic_init();
+	unsigned int core_pos = plat_my_core_pos();
+
+	gic_init(core_pos);
+	gic_pcpu_init(core_pos);
+	gic_cpuif_enable(core_pos);
+
+#if TRANSFER_LIST
+	ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE,
+				       PLAT_ARM_FW_HANDOFF_SIZE);
+	if (ns_tl == NULL) {
+		ERROR("Non-secure transfer list initialisation failed!\n");
+		panic();
+	}
+
+	te = transfer_list_find(secure_tl, TL_TAG_FDT);
+	if (te != NULL) {
+		te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
+				  (void *)transfer_list_entry_data(te));
+		if (te == NULL) {
+			ERROR("Failed to relocate device tree into non-secure memory.\n");
+			panic();
+		}
+	}
+
+	transfer_list_set_handoff_args(ns_tl, &bl33_image_ep_info);
+#endif
 
 	/*
 	 * Do initial security configuration to allow DRAM/device access
@@ -223,6 +277,10 @@
 #if USE_COHERENT_MEM
 		ARM_MAP_BL_COHERENT_RAM,
 #endif
+#if TRANSFER_LIST
+		MAP_EL3_FW_HANDOFF,
+		MAP_FW_NS_HANDOFF,
+#endif
 		{0}
 	};
 

diff --git a/plat/arm/common/tsp/arm_tsp.mk b/plat/arm/common/tsp/arm_tsp.mk
index 4ad77c6..d7592df 100644
--- a/plat/arm/common/tsp/arm_tsp.mk
+++ b/plat/arm/common/tsp/arm_tsp.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,3 +8,10 @@
 BL32_SOURCES		+=	plat/arm/common/arm_topology.c			\
 				plat/arm/common/tsp/arm_tsp_setup.c		\
 				plat/common/aarch64/platform_mp_stack.S
+
+ifeq (${TRANSFER_LIST},1)
+BL32_SOURCES	+=	$(TRANSFER_LIST_SOURCES)
+ifeq (${MEASURED_BOOT},1)
+BL32_SOURCES	+=	$(EVENT_LOG_SOURCES)
+endif
+endif

diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index df3488b..d018dee 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,11 @@
 #include <common/debug.h>
 #include <drivers/arm/pl011.h>
 #include <drivers/console.h>
+#if TRANSFER_LIST && MEASURED_BOOT
+#include <drivers/measured_boot/event_log/event_log.h>
+#endif
 #include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
 
 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak tsp_early_platform_setup
@@ -25,13 +29,32 @@
 					BL32_END - BL32_BASE,		\
 					MT_MEMORY | MT_RW | MT_SECURE)
 
+#define MAP_FW_HANDOFF		MAP_REGION_FLAT(			\
+					PLAT_ARM_EL3_FW_HANDOFF_BASE,	\
+					PLAT_ARM_FW_HANDOFF_SIZE,	\
+					MT_MEMORY | MT_RO | MT_SECURE)
+
+struct transfer_list_header *secure_tl __unused;
+
 /*******************************************************************************
  * Initialize the UART
  ******************************************************************************/
 static console_t arm_tsp_runtime_console;
 
-void arm_tsp_early_platform_setup(void)
+void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3)
 {
+#if TRANSFER_LIST
+	secure_tl = (struct transfer_list_header *)arg3;
+	assert(secure_tl != NULL);
+
+	if (transfer_list_check_header(secure_tl) == TL_OPS_NON) {
+		ERROR("Invalid transfer list received");
+		transfer_list_dump(secure_tl);
+		panic();
+	}
+#endif
+
 	/*
 	 * Initialize a different console than already in use to display
 	 * messages from TSP
@@ -40,16 +63,18 @@
 					PLAT_ARM_TSP_UART_CLK_IN_HZ,
 					ARM_CONSOLE_BAUDRATE,
 					&arm_tsp_runtime_console);
-	if (rc == 0)
+	if (rc == 0) {
 		panic();
+	}
 
 	console_set_scope(&arm_tsp_runtime_console,
 			  CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
 }
 
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3)
 {
-	arm_tsp_early_platform_setup();
+	arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3);
 }
 
 /*******************************************************************************
@@ -57,7 +82,26 @@
  ******************************************************************************/
 void tsp_platform_setup(void)
 {
-	plat_arm_gic_driver_init();
+	struct transfer_list_entry *te __unused;
+
+	/*
+	 * On GICv2 the driver must be initialised before calling the plat_ic_*
+	 * functions as they need the data structures. Higher versions don't.
+	 */
+#if USE_GIC_DRIVER == 2
+	gic_init(plat_my_core_pos());
+#endif
+
+#if TRANSFER_LIST && MEASURED_BOOT
+	te = transfer_list_find(secure_tl, TL_TAG_TPM_EVLOG);
+	assert(te != NULL);
+
+	/*
+	 * Note the actual log is offset 4-bytes from the start of entry data, the
+	 * first bytes are reserved.
+	 */
+	event_log_dump(transfer_list_entry_data(te) + U(4), te->data_size - U(4));
+#endif
 }
 
 /*******************************************************************************
@@ -74,6 +118,9 @@
 	const mmap_region_t bl_regions[] = {
 		MAP_BL_TSP_TOTAL,
 		ARM_MAP_BL_RO,
+#if TRANSFER_LIST
+		MAP_FW_HANDOFF,
+#endif
 		{0}
 	};
 

diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c
index 1e055c5..995ef78 100644
--- a/plat/arm/css/common/css_bl2_setup.c
+++ b/plat/arm/css/common/css_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -56,7 +56,7 @@
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 			u_register_t arg2, u_register_t arg3)
 {
-	arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+	arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
 
 	/* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */
 	scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR);

diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index f8bc542..80da3d9 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,7 @@
 #include <bl31/interrupt_mgmt.h>
 #include <common/debug.h>
 #include <drivers/arm/css/css_scp.h>
-#include <drivers/arm/css/dsu.h>
+#include <drivers/arm/dsu.h>
 #include <lib/cassert.h>
 #include <plat/arm/common/plat_arm.h>
 
@@ -114,12 +114,6 @@
  ******************************************************************************/
 void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
 {
-	/* Program the gic per-cpu distributor or re-distributor interface */
-	plat_arm_gic_pcpu_init();
-
-	/* Enable the gic cpu interface */
-	plat_arm_gic_cpuif_enable();
-
 	/* Setup the CPU power down request interrupt for secondary core(s) */
 	css_setup_cpu_pwr_down_intr();
 }
@@ -132,9 +126,6 @@
  ******************************************************************************/
 static void css_power_down_common(const psci_power_state_t *target_state)
 {
-	/* Prevent interrupts from spuriously waking up this cpu */
-	plat_arm_gic_cpuif_disable();
-
 	/* Cluster is to be turned off, so disable coherency */
 	if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
 #if PRESERVE_DSU_PMU_REGS
@@ -152,8 +143,6 @@
 {
 	assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
 	css_power_down_common(target_state);
-	/* ask the GIC not to wake us up */
-	plat_arm_gic_redistif_off();
 	css_scp_off(target_state);
 }
 
@@ -179,7 +168,7 @@
 		arm_system_pwr_domain_save();
 
 		/* Power off the Redistributor after having saved its context */
-		plat_arm_gic_redistif_off();
+		gic_pcpu_off(plat_my_core_pos());
 	}
 
 	css_scp_suspend(target_state);
@@ -209,9 +198,6 @@
 		arm_system_pwr_domain_resume();
 
 	css_pwr_domain_on_finisher_common(target_state);
-
-	/* Enable the gic cpu interface */
-	plat_arm_gic_cpuif_enable();
 }
 
 /*******************************************************************************
@@ -352,6 +338,8 @@
 int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags,
 		void *handle, void *cookie)
 {
+	unsigned int core_pos = plat_my_core_pos();
+
 	assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR);
 
 	/* Deactivate warm reboot SGI */
@@ -361,8 +349,8 @@
 	 * Disable GIC CPU interface to prevent pending interrupt from waking
 	 * up the AP from WFI.
 	 */
-	plat_arm_gic_cpuif_disable();
-	plat_arm_gic_redistif_off();
+	gic_cpuif_disable(core_pos);
+	gic_pcpu_off(core_pos);
 
 	psci_pwrdown_cpu_start(PLAT_MAX_PWR_LVL);
 

diff --git a/plat/brcm/board/common/board_common.mk b/plat/brcm/board/common/board_common.mk
index 24a27ed..ef11e39 100644
--- a/plat/brcm/board/common/board_common.mk
+++ b/plat/brcm/board/common/board_common.mk

@@ -225,10 +225,11 @@
 KEY_ALG := rsa_1_5
 
 # Include common TBB sources
-AUTH_SOURCES	+= 	drivers/auth/auth_mod.c \
-			drivers/auth/crypto_mod.c \
-			drivers/auth/img_parser_mod.c \
-			drivers/auth/tbbr/tbbr_cot_common.c \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES	+= 	drivers/auth/tbbr/tbbr_cot_common.c \
 			drivers/auth/tbbr/tbbr_cot_bl2.c
 
 BL2_SOURCES	+=	${AUTH_SOURCES}

diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index ba47b30..4423863 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,18 +45,6 @@
 {
 }
 
-/*
- * Helper function for platform_get_pos() when platform compatibility is
- * disabled. This is to enable SPDs using the older platform API to continue
- * to work.
- */
-unsigned int platform_core_pos_helper(unsigned long mpidr)
-{
-	int idx = plat_core_pos_by_mpidr(mpidr);
-	assert(idx >= 0);
-	return idx;
-}
-
 #if SDEI_SUPPORT
 /*
  * Function that handles spurious SDEI interrupts while events are masked.

diff --git a/plat/arm/common/arm_gicv2.c b/plat/common/plat_gicv2_base.c
similarity index 97%
rename from plat/arm/common/arm_gicv2.c
rename to plat/common/plat_gicv2_base.c
index 80a845f..7fe41c2 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/plat/common/plat_gicv2_base.c

@@ -1,14 +1,13 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <platform_def.h>
-
 #include <drivers/arm/gicv2.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
 /******************************************************************************
  * The following functions are defined as weak to allow a platform to override

diff --git a/plat/arm/common/arm_gicv3.c b/plat/common/plat_gicv3_base.c
similarity index 97%
rename from plat/arm/common/arm_gicv3.c
rename to plat/common/plat_gicv3_base.c
index 5becbcd..df05b89 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/common/plat_gicv3_base.c

@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <platform_def.h>
 
 #include <common/debug.h>
 #include <common/interrupt_props.h>
@@ -13,6 +12,7 @@
 #include <lib/utils.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
+#include <platform_def.h>
 
 /******************************************************************************
  * The following functions are defined as weak to allow a platform to override
@@ -79,7 +79,7 @@
 	return plat_arm_calc_core_pos(mpidr);
 }
 
-static const gicv3_driver_data_t arm_gic_data __unused = {
+gicv3_driver_data_t arm_gic_data __unused = {
 	.gicd_base = PLAT_ARM_GICD_BASE,
 	.gicr_base = 0U,
 	.interrupt_props = arm_interrupt_props,

diff --git a/plat/common/plat_gicv5.c b/plat/common/plat_gicv5.c
new file mode 100644
index 0000000..e445886
--- /dev/null
+++ b/plat/common/plat_gicv5.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl31/interrupt_mgmt.h>
+#include <drivers/arm/gicv5.h>
+
+uint32_t plat_ic_get_pending_interrupt_type(void)
+{
+	return gicv5_get_pending_interrupt_type();
+}
+
+bool plat_ic_has_interrupt_type(unsigned int type)
+{
+	return gicv5_has_interrupt_type(type);
+}

diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index b67d3ff..0b919e5 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -127,10 +127,11 @@
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
 
-AUTH_SOURCES		:=	drivers/auth/auth_mod.c			\
-				drivers/auth/crypto_mod.c		\
-				drivers/auth/img_parser_mod.c		\
-				drivers/auth/tbbr/tbbr_cot_common.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES		+=	drivers/auth/tbbr/tbbr_cot_common.c
 
 BL1_SOURCES		+=	${AUTH_SOURCES}				\
 				plat/common/tbbr/plat_tbbr.c		\

diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index c278d8e..a4be841 100644
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -120,10 +120,11 @@
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
 
-AUTH_SOURCES		:=	drivers/auth/auth_mod.c			\
-				drivers/auth/crypto_mod.c		\
-				drivers/auth/img_parser_mod.c		\
-				drivers/auth/tbbr/tbbr_cot_common.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES		+=	drivers/auth/tbbr/tbbr_cot_common.c
 
 BL1_SOURCES		+=	${AUTH_SOURCES}				\
 				plat/common/tbbr/plat_tbbr.c		\

diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index a7e8fe8..7d201c2 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -56,10 +56,11 @@
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
 
-AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-			drivers/auth/crypto_mod.c		\
-			drivers/auth/img_parser_mod.c		\
-			drivers/auth/tbbr/tbbr_cot_common.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot_common.c
 
 BL2_SOURCES		+=	${AUTH_SOURCES}					\
 				plat/common/tbbr/plat_tbbr.c			\

diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c
index 159be00..7566403 100644
--- a/plat/imx/imx8m/imx8m_measured_boot.c
+++ b/plat/imx/imx8m/imx8m_measured_boot.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
  * Copyright (c) 2022, Linaro.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -78,7 +78,7 @@
 	/* Ensure that the Event Log is visible in Non-secure memory */
 	flush_dcache_range(ns_log_addr, event_log_cur_size);
 
-	dump_event_log((uint8_t *)event_log, event_log_cur_size);
+	event_log_dump((uint8_t *)event_log, event_log_cur_size);
 }
 
 int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,

diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index e54256c..d2e812d 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -112,10 +112,11 @@
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
 
-AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-			drivers/auth/crypto_mod.c		\
-			drivers/auth/img_parser_mod.c		\
-			drivers/auth/tbbr/tbbr_cot_common.c     \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot_common.c     \
 			drivers/auth/tbbr/tbbr_cot_bl2.c
 
 BL2_SOURCES	+=	${AUTH_SOURCES}					\

diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index a95eb36..5e2d9e4 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c

@@ -268,23 +268,6 @@
 		/* set the PGC bit */
 		mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
 
-		/*
-		 * leave the G1, G2, H1 power domain on until VPUMIX power off,
-		 * otherwise system will hang due to VPUMIX ACK
-		 */
-		if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
-			return;
-		}
-
-		if (domain_id == VPUMIX) {
-			mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
-				 VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
-
-			while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
-					VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
-				;
-		}
-
 		/* power down the domain */
 		mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
 

diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 98b99d1..7d42391 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk

@@ -109,10 +109,11 @@
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
 
-AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-			drivers/auth/crypto_mod.c		\
-			drivers/auth/img_parser_mod.c		\
-			drivers/auth/tbbr/tbbr_cot_common.c     \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot_common.c     \
 			drivers/auth/tbbr/tbbr_cot_bl2.c
 
 BL2_SOURCES		+=	${AUTH_SOURCES}					\
@@ -149,6 +150,7 @@
 ERRATA_A53_835769	:=	1
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
+ERRATA_A53_1530924	:=	1
 
 IMX_DRAM_RETENTION	?=	1
 $(eval $(call assert_boolean,IMX_DRAM_RETENTION))

diff --git a/plat/imx/imx8ulp/imx8ulp_psci.c b/plat/imx/imx8ulp/imx8ulp_psci.c
index 59af8be..e67d0b5 100644
--- a/plat/imx/imx8ulp/imx8ulp_psci.c
+++ b/plat/imx/imx8ulp/imx8ulp_psci.c

@@ -289,7 +289,9 @@
 		/* LDO1 should be power off in PD mode */
 		} else if (mode == PD_PWR_MODE) {
 			/* overwrite the buck3 voltage setting in active mode */
-			upower_pmic_i2c_read(0x22, &volt);
+			if (upower_pmic_i2c_read(0x22, &volt) != 0) {
+				panic();
+			}
 			pd_pmic_reg_cfgs[3].i2c_data = volt;
 			memcpy(&pwr_sys_cfg->ps_apd_pmic_reg_data_cfg, &pd_pmic_reg_cfgs,
 				 sizeof(ps_apd_pmic_reg_data_cfgs_t));

diff --git a/plat/imx/imx93/trdc_config.h b/plat/imx/imx93/trdc_config.h
index c623a19..478bbcd 100644
--- a/plat/imx/imx93/trdc_config.h
+++ b/plat/imx/imx93/trdc_config.h

@@ -40,6 +40,7 @@
 	{ 1, 2, 1, MBC_BLK_ALL, 2, true  }, /* MBC1 CM33 system TCM for M33 DID2 */
 
 	{ 0, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS1 for A55 DID3 */
+	{ 0, 3, 0, 79, 0, true }, /* MBC0 AIPS1 BLK_CTRL_S_AONMIX  for A55 DID3 */
 	{ 0, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC0 Sentinel_SOC_In for A55 DID3 */
 	{ 0, 3, 2, MBC_BLK_ALL, 0, false }, /* MBC0 GPIO1 for A55 DID3 */
 	{ 1, 3, 0, MBC_BLK_ALL, 1, false }, /* MBC1 CM33 code TCM for A55 DID3 */

diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 4c10e7b..dabe865 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,6 +67,11 @@
 	mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
 	console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
 		PLAT_BAUDRATE, &console);
+
+	/* Enable TF-A BL31 logs when running from non-secure world also. */
+	console_set_scope(&console,
+		(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
+
 	/*
 	 * Check params passed from BL31 should not be NULL,
 	 */
@@ -175,6 +180,16 @@
 	mmio_write_64(PLAT_CPU_RELEASE_ADDR,
 		(uint64_t)plat_secondary_cpus_bl31_entry);
 
+#if SIP_SVC_V3
+	/*
+	 * Re-initialize the mailbox to include V3 specific routines.
+	 * In V3, this re-initialize is required because prior to BL31, U-Boot
+	 * SPL has its own mailbox settings and this initialization will
+	 * override to those settings as required by the V3 framework.
+	 */
+	mailbox_init();
+#endif
+
 	mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
 }
 

diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 20701a4..66e0ea5 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c

@@ -177,6 +177,17 @@
 	gicv3_distif_init();
 	gicv3_rdistif_init(plat_my_core_pos());
 	gicv3_cpuif_enable(plat_my_core_pos());
+
+#if SIP_SVC_V3
+	/*
+	 * Re-initialize the mailbox to include V3 specific routines.
+	 * In V3, this re-initialize is required because prior to BL31, U-Boot
+	 * SPL has its own mailbox settings and this initialization will
+	 * override to those settings as required by the V3 framework.
+	 */
+	mailbox_init();
+#endif
+
 	mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
 }
 
@@ -206,9 +217,11 @@
 	NOTICE("SOCFPGA: CPU ID = %x\n", cpuid);
 	INFO("SOCFPGA: Invalidate Data cache\n");
 	invalidate_dcache_all();
-
 	/* Invalidate for NS EL2 and EL1 */
 	invalidate_cache_low_el();
+
+	NOTICE("SOCFPGA: Setting CLUSTERECTRL_EL1\n");
+	setup_clusterectlr_el1();
 }
 
 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
@@ -292,6 +305,22 @@
 	mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
 }
 
+void setup_clusterectlr_el1(void)
+{
+	uint64_t value = 0;
+
+	/* Read CLUSTERECTLR_EL1 */
+	asm volatile("mrs %0, S3_0_C15_C3_4" : "=r"(value));
+
+	/* Disable broadcasting atomics */
+	value |= 0x80; /* set bit 7 */
+	/* Disable sending data with clean evicts */
+	value &= 0xFFFFBFFF; /* Mask out bit 14 */
+
+	/* Write CLUSTERECTLR_EL1 */
+	asm volatile("msr S3_0_C15_C3_4, %0" :: "r"(value));
+}
+
 void bl31_plat_runtime_setup(void)
 {
 	/* Dummy override function. */

diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 8c86ab1..f4b53e8 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h

@@ -160,6 +160,11 @@
 #define SOCFPGA_ECC_QSPI_ECC_STARTACC					0x7C
 #define SOCFPGA_ECC_QSPI_ECC_WDCTRL					0x80
 
+/* IOSSM mailbox address */
+#define IOSSM_CMD_PARAM							0x18400438
+#define IOSSM_CMD_TRIG_OP						0x1840043C
+#define IOSSM_CMD_RESP_STATUS						0x1840045C
+
 #define DMA0_STREAM_CTRL_REG						0x10D1217C
 #define DMA1_STREAM_CTRL_REG						0x10D12180
 #define SDM_STREAM_CTRL_REG						0x10D12184

diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
index 0d60324..acf7528 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_ddr.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c

@@ -297,7 +297,7 @@
 	bool full_mem_init = false;
 	phys_size_t hw_ddr_size;
 	phys_size_t config_ddr_size;
-	struct io96b_info io96b_ctrl;
+	struct io96b_info io96b_ctrl = {0};
 	enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR(
 						BOOT_SCRATCH_COLD_3)));
 	bool is_dualport = hoff_ptr->ddr_config & BIT(0);

diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index e2efeb1..6325d35 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -207,6 +207,9 @@
 #define MAX_IO_DEVICES				4
 #define MAX_IO_BLOCK_DEVICES			2
 
+/* Define this, to support the SiPSVC V3 implementation. */
+#define SIP_SVC_V3				1
+
 #ifndef __ASSEMBLER__
 struct socfpga_bl31_params {
 	param_header_t h;

diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index 6bb70e0..21d9b66 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,6 +76,10 @@
 #define FCS_MAX_DATA_SIZE					0x20000000	/* 512 MB */
 #define FCS_MIN_DATA_SIZE					0x8	/* 8 Bytes */
 
+#define FCS_AES_DATA_SIZE_CHECK(x)				(((x >= FCS_AES_MIN_DATA_SIZE) && \
+								  (x <= FCS_AES_MAX_DATA_SIZE)) ? \
+								  true : false)
+
 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE			7U
 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE			19U
 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE			23U
@@ -88,12 +93,22 @@
 #define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE		52U
 #define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE			29U
 
-#define FCS_CRYPTO_ECB_BUFFER_SIZE			12U
-#define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE			28U
-#define FCS_CRYPTO_BLOCK_MODE_MASK			0x07
-#define FCS_CRYPTO_ECB_MODE			0x00
-#define FCS_CRYPTO_CBC_MODE			0x01
-#define FCS_CRYPTO_CTR_MODE			0x02
+#define FCS_CRYPTO_ECB_BUFFER_SIZE				12U
+#define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE				28U
+#define FCS_CRYPTO_BLOCK_MODE_MASK				0x07
+#define FCS_CRYPTO_ECB_MODE					0x00
+#define FCS_CRYPTO_CBC_MODE					0x01
+#define FCS_CRYPTO_CTR_MODE					0x02
+#define FCS_CRYPTO_GCM_MODE					0x03
+#define FCS_CRYPTO_GCM_GHASH_MODE				0x04
+
+#define FCS_HKDF_REQUEST_DATA_SIZE				512U
+#define FCS_HKDF_KEY_OBJ_MAX_SIZE				352U
+#define FCS_HKDF_KEY_DATA_SIZE					168U
+#define FCS_HKDF_STEP0_1_KEY_OBJ_SIZE_BITS			384U
+#define FCS_HKDF_STEP2_KEY_OBJ_SIZE_BITS			256U
+#define FCS_HKDF_INPUT_BLOCK_SIZE				80U
+#define FCS_HKDF_SHA2_384_KEY_DATA_SIZE				48U
 
 /* FCS Payload Structure */
 typedef struct fcs_rng_payload_t {
@@ -183,10 +198,12 @@
 				uint32_t *mbox_error);
 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
 				uint32_t size, uint32_t *send_id);
-uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
+uint32_t intel_fcs_send_cert(uint32_t smc_fid, uint32_t trans_id,
+				uint64_t addr, uint64_t size,
 				uint32_t *send_id);
 uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
-uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
+uint32_t intel_fcs_cntr_set_preauth(uint32_t smc_fid, uint32_t trans_id,
+				uint8_t counter_type,
 				int32_t counter_value,
 				uint32_t test_bit,
 				uint32_t *mbox_error);
@@ -198,14 +215,18 @@
 				uint32_t dst_addr, uint32_t dst_size,
 				uint32_t *send_id);
 
-int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
+int intel_fcs_encryption_ext(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint32_t dst_addr, uint32_t *dst_size,
-				uint32_t *mbox_error);
-int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id,
+				uint32_t *mbox_error, uint32_t smmu_src_addr,
+				uint32_t smmu_dst_addr);
+int intel_fcs_decryption_ext(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t sesion_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint32_t dst_addr, uint32_t *dst_size,
-				uint32_t *mbox_error);
+				uint32_t *mbox_error, uint64_t owner_id,
+				uint32_t smmu_src_addr, uint32_t smmu_dst_addr);
 
 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
@@ -218,9 +239,10 @@
 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
 				uint32_t *mbox_error);
 
-int intel_fcs_create_cert_on_reload(uint32_t cert_request,
-				uint32_t *mbox_error);
-int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
+int intel_fcs_create_cert_on_reload(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t cert_request, uint32_t *mbox_error);
+int intel_fcs_get_attestation_cert(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t cert_request, uint64_t dst_addr,
 				uint32_t *dst_size, uint32_t *mbox_error);
 
 int intel_fcs_open_crypto_service_session(uint32_t *session_id,
@@ -242,10 +264,12 @@
 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint32_t param_size,
 				uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_get_digest_update_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_get_digest_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
-				uint8_t is_finalised, uint32_t *mbox_error);
+				uint8_t is_finalised, uint32_t *mbox_error,
+				uint32_t smmu_src_addr);
 int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
@@ -255,11 +279,12 @@
 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint32_t param_size,
 				uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_mac_verify_update_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_mac_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t data_size, uint8_t is_finalised,
-				uint32_t *mbox_error);
+				uint32_t *mbox_error, uint64_t smmu_src_addr);
 int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
@@ -269,7 +294,8 @@
 int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint32_t param_size,
 				uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sign_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error);
@@ -277,7 +303,8 @@
 int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint32_t param_size,
 				uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error);
@@ -286,11 +313,12 @@
 				uint32_t context_id, uint32_t key_id,
 				uint32_t param_size, uint64_t param_data,
 				uint32_t *mbox_error);
-int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint32_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t *dst_size, uint8_t is_finalised,
-				uint32_t *mbox_error);
+int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint32_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t *dst_size,
+				uint8_t is_finalised, uint32_t *mbox_error,
+				uint64_t smmu_src_addr);
 int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id,
 				uint32_t context_id, uint32_t src_addr,
 				uint32_t src_size, uint64_t dst_addr,
@@ -301,11 +329,12 @@
 				uint32_t context_id, uint32_t key_id,
 				uint32_t param_size, uint64_t param_data,
 				uint32_t *mbox_error);
-int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint32_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t *dst_size, uint32_t data_size,
-				uint8_t is_finalised, uint32_t *mbox_error);
+int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint32_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t *dst_size,
+				uint32_t data_size, uint8_t is_finalised,
+				uint32_t *mbox_error, uint64_t smmu_src_addr);
 int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id,
 				uint32_t context_id, uint32_t src_addr,
 				uint32_t src_size, uint64_t dst_addr,
@@ -316,14 +345,16 @@
 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint32_t param_size,
 				uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error);
 
 int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint32_t param_size,
 				uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdh_request_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error);
@@ -331,10 +362,16 @@
 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id,
 				uint32_t key_id, uint64_t param_addr,
 				uint32_t param_size, uint32_t *mbox_error);
-int intel_fcs_aes_crypt_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint64_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t dst_size, uint8_t is_finalised,
-				uint32_t *send_id);
+int intel_fcs_aes_crypt_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint64_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t dst_size,
+				uint32_t padding_size, uint8_t is_finalised,
+				uint32_t *send_id, uint64_t smmu_src_addr,
+				uint64_t smmu_dst_addr);
 
+int intel_fcs_hkdf_request(uint32_t smc_fid, uint32_t trans_id,
+			uint32_t session_id, uint32_t step_type,
+			uint32_t mac_mode, uint32_t src_addr,
+			uint32_t key_uid, uint32_t op_key_size);
 #endif /* SOCFPGA_FCS_H */

diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index e27af21..4da318b 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,20 +23,22 @@
 #define MBOX_TEST_BIT					BIT(31)
 
 /* Mailbox Shared Memory Register Map */
-#define MBOX_CIN					0x00
-#define MBOX_ROUT					0x04
-#define MBOX_URG					0x08
-#define MBOX_INT					0x0C
-#define MBOX_COUT					0x20
-#define MBOX_RIN					0x24
-#define MBOX_STATUS					0x2C
-#define MBOX_CMD_BUFFER					0x40
-#define MBOX_RESP_BUFFER				0xC0
+#define MBOX_CIN					0x00 /* Command valid offset, to SDM */
+#define MBOX_ROUT					0x04 /* Response output offset, to SDM */
+#define MBOX_URG					0x08 /* Urgent command, to SDM */
+#define MBOX_INT					0x0C /* Interrupt enables, to SDM */
+/* 0x10 - 0x1F, Reserved */
 
-/* Mailbox SDM doorbell */
-#define MBOX_DOORBELL_TO_SDM				0x400
-#define MBOX_DOORBELL_FROM_SDM				0x480
+#define MBOX_COUT					0x20 /* Command free offset, from SDM */
+#define MBOX_RIN					0x24 /* Response valid offset, from SDM */
+#define MBOX_STATUS					0x2C /* Mailbox status from SDM to client */
+/* 0x30 - 0x3F, Reserved */
 
+#define MBOX_CMD_BUFFER					0x40 /* Circular buffer, cmds to SDM */
+#define MBOX_RESP_BUFFER				0xC0 /* Circular buffer, resp from SDM */
+
+#define MBOX_DOORBELL_TO_SDM				0x400 /* Doorbell from HPS to SDM */
+#define MBOX_DOORBELL_FROM_SDM				0x480 /* Doorbell from SDM to HPS */
 
 /* Mailbox commands */
 
@@ -61,12 +63,15 @@
 #define MBOX_HWMON_READVOLT				0x18
 #define MBOX_HWMON_READTEMP				0x19
 
-
 /* QSPI Commands */
 #define MBOX_CMD_QSPI_OPEN				0x32
 #define MBOX_CMD_QSPI_CLOSE				0x33
 #define MBOX_CMD_QSPI_SET_CS				0x34
+#define MBOX_CMD_QSPI_ERASE				0x38
+#define MBOX_CMD_QSPI_WRITE				0x39
+#define MBOX_CMD_QSPI_READ				0x3A
 #define MBOX_CMD_QSPI_DIRECT				0x3B
+#define MBOX_CMD_QSPI_GET_DEV_INFO			0x74
 
 /* SEU Commands */
 #define MBOX_CMD_SEU_ERR_READ				0x3C
@@ -94,12 +99,14 @@
 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY		0x87
 #define MBOX_FCS_ECDSA_GET_PUBKEY			0x88
 #define MBOX_FCS_ECDH_REQUEST				0x89
+#define MBOX_FCS_HKDF_REQUEST				0x8B
 #define MBOX_FCS_OPEN_CS_SESSION			0xA0
 #define MBOX_FCS_CLOSE_CS_SESSION			0xA1
 #define MBOX_FCS_IMPORT_CS_KEY				0xA5
 #define MBOX_FCS_EXPORT_CS_KEY				0xA6
 #define MBOX_FCS_REMOVE_CS_KEY				0xA7
 #define MBOX_FCS_GET_CS_KEY_INFO			0xA8
+#define MBOX_FCS_CREATE_CS_KEY				0xA9
 
 /* PSG SIGMA Commands */
 #define MBOX_PSG_SIGMA_TEARDOWN				0xD5
@@ -111,7 +118,9 @@
 #define MBOX_GET_MEASUREMENT				0x183
 
 /* Miscellaneous commands */
+#define MBOX_CMD_MCTP_MSG				0x194
 #define MBOX_GET_ROM_PATCH_SHA384			0x1B0
+#define MBOX_CMD_GET_DEVICEID				0x500
 
 /* Mailbox Definitions */
 
@@ -120,6 +129,18 @@
 #define CMD_CASUAL					0
 #define CMD_URGENT					1
 
+/* Mailbox command flags and related macros */
+#define MBOX_CMD_FLAG_DIRECT				BIT(0)
+#define MBOX_CMD_FLAG_INDIRECT				BIT(1)
+#define MBOX_CMD_FLAG_CASUAL				BIT(2)
+#define MBOX_CMD_FLAG_URGENT				BIT(3)
+
+#define MBOX_CMD_FLAG_CASUAL_INDIRECT			(MBOX_CMD_FLAG_CASUAL | \
+							 MBOX_CMD_FLAG_INDIRECT)
+
+#define IS_CMD_SET(cmd, _type)				((((cmd) & MBOX_CMD_FLAG_##_type) != 0) ? \
+								1 : 0)
+
 #define MBOX_WORD_BYTE					4U
 #define MBOX_RESP_BUFFER_SIZE				16
 #define MBOX_CMD_BUFFER_SIZE				32
@@ -171,22 +192,25 @@
 								+ MBOX_WORD_BYTE * (ptr))
 
 /* Mailbox interrupt flags and masks */
-#define MBOX_INT_FLAG_COE				0x1
-#define MBOX_INT_FLAG_RIE				0x2
-#define MBOX_INT_FLAG_UAE				0x100
-#define MBOX_COE_BIT(INTERRUPT)				((INTERRUPT) & 0x3)
-#define MBOX_UAE_BIT(INTERRUPT)				(((INTERRUPT) & (1<<8)))
+#define MBOX_INT_FLAG_COE				BIT(0) /* COUT update interrupt enable */
+#define MBOX_INT_FLAG_RIE				BIT(1) /* RIN update interrupt enable */
+#define MBOX_INT_FLAG_UAE				BIT(8) /* Urgent ACK interrupt enable */
+
+#define MBOX_COE_BIT(INTERRUPT)				((INTERRUPT) & MBOX_INT_FLAG_COE)
+#define MBOX_RIE_BIT(INTERRUPT)				((INTERRUPT) & MBOX_INT_FLAG_RIE)
+#define MBOX_UAE_BIT(INTERRUPT)				((INTERRUPT) & MBOX_INT_FLAG_UAE)
 
 /* Mailbox response and status */
 #define MBOX_RESP_ERR(BUFFER)				((BUFFER) & 0x000007ff)
 #define MBOX_RESP_LEN(BUFFER)				(((BUFFER) & 0x007ff000) >> 12)
 #define MBOX_RESP_CLIENT_ID(BUFFER)			(((BUFFER) & 0xf0000000) >> 28)
 #define MBOX_RESP_JOB_ID(BUFFER)			(((BUFFER) & 0x0f000000) >> 24)
+#define MBOX_RESP_TRANSACTION_ID(BUFFER)		(((BUFFER) & 0xff000000) >> 24)
 #define MBOX_STATUS_UA_MASK				(1<<8)
 
 /* Mailbox command and response */
 #define MBOX_CLIENT_ID_CMD(CLIENT_ID)			((CLIENT_ID) << 28)
-#define MBOX_JOB_ID_CMD(JOB_ID)				(JOB_ID<<24)
+#define MBOX_JOB_ID_CMD(JOB_ID)				(JOB_ID << 24)
 #define MBOX_CMD_LEN_CMD(CMD_LEN)			((CMD_LEN) << 12)
 #define MBOX_INDIRECT(val)				((val) << 11)
 #define MBOX_CMD_MASK(header)				((header) & 0x7ff)
@@ -204,6 +228,17 @@
 #define CONFIG_STATUS_FW_VER_OFFSET			1
 #define CONFIG_STATUS_FW_VER_MASK			0x00FFFFFF
 
+/* QSPI mailbox command macros */
+#define MBOX_QSPI_SET_CS_OFFSET				(28)
+#define MBOX_QSPI_SET_CS_MODE_OFFSET			(27)
+#define MBOX_QSPI_SET_CS_CA_OFFSET			(26)
+#define MBOX_QSPI_ERASE_SIZE_GRAN			(0x400)
+
+#define MBOX_4K_ALIGNED_MASK				(0xFFF)
+#define MBOX_IS_4K_ALIGNED(x)				((x) & MBOX_4K_ALIGNED_MASK)
+#define MBOX_IS_WORD_ALIGNED(x)				(!((x) & 0x3))
+#define MBOX_QSPI_RW_MAX_WORDS				(0x1000)
+
 /* Data structure */
 
 typedef struct mailbox_payload {
@@ -264,4 +299,107 @@
 
 int mailbox_send_fpga_config_comp(void);
 
+#if SIP_SVC_V3
+#define MBOX_CLIENT_ID_SHIFT				(28)
+#define MBOX_JOB_ID_SHIFT				(24)
+#define MBOX_CMD_LEN_SHIFT				(12)
+#define MBOX_INDIRECT_SHIFT				(11)
+
+#define MBOX_FRAME_CMD_HEADER(client_id, job_id, args_len, indirect, cmd)\
+				((client_id << MBOX_CLIENT_ID_SHIFT) |	 \
+				(job_id << MBOX_JOB_ID_SHIFT) |		 \
+				(args_len << MBOX_CMD_LEN_SHIFT) |	 \
+				(indirect << MBOX_INDIRECT_SHIFT) |	 \
+				cmd)
+
+#define FLAG_SDM_RESPONSE_IS_VALID			BIT(0)
+#define FLAG_SDM_RESPONSE_IS_USED			BIT(1)
+#define FLAG_SDM_RESPONSE_IS_IN_PROGRESS		BIT(2)
+#define FLAG_SDM_RESPONSE_IS_POLL_ON_INTR		BIT(3)
+
+/*
+ * TODO: Re-visit this queue size based on the system load.
+ * 4 bits for client ID and 4 bits for job ID, total 8 bits and we can have up to
+ * 256 transactions. We can tune this based on our system load at any given time
+ */
+#define MBOX_SVC_CMD_QUEUE_SIZE				(32)
+#define MBOX_SVC_RESP_QUEUE_SIZE			(32)
+#define MBOX_SVC_MAX_JOB_ID				(16)
+#define MBOX_SVC_CMD_ARG_SIZE				(2)
+#define MBOX_SVC_CMD_IS_USED				BIT(0)
+#define MBOX_SVC_CMD_CB_ARGS_SIZE			(4)
+#define MBOX_SVC_MAX_CLIENTS				(16)
+#define MBOX_SVC_MAX_RESP_DATA_SIZE			(32)
+#define MBOX_SVC_SMC_RET_MAX_SIZE			(8)
+
+/* Client ID(4bits) + Job ID(4bits) = Transcation ID(TID - 8bits, 256 combinations) */
+#define MBOX_MAX_TIDS					(256)
+/* Each transcation ID bitmap holds 64bits */
+#define MBOX_TID_BITMAP_SIZE				(sizeof(uint64_t) * 8)
+/* Number of transcation ID bitmaps required to hold 256 combinations */
+#define MBOX_MAX_TIDS_BITMAP				(MBOX_MAX_TIDS / MBOX_TID_BITMAP_SIZE)
+
+/* SDM Response State (SRS) enums */
+typedef enum sdm_resp_state {
+	SRS_WAIT_FOR_RESP = 0x00U,
+	SRS_WAIT_FOR_HEADER,
+	SRS_WAIT_FOR_ARGUMENTS,
+	SRS_SYNC_ERROR
+} sdm_resp_state_t;
+
+/* SDM response data structure */
+typedef struct sdm_response {
+	bool is_poll_intr;
+	uint8_t client_id;
+	uint8_t job_id;
+	uint16_t resp_len;
+	uint16_t err_code;
+	uint32_t flags;
+	uint32_t header;
+	uint16_t rcvd_resp_len;
+	uint32_t resp_data[MBOX_SVC_MAX_RESP_DATA_SIZE];
+} sdm_response_t;
+
+/* SDM client callback template */
+typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
+					uint64_t *ret_args);
+
+/* SDM command data structure */
+typedef struct sdm_command {
+	uint8_t client_id;
+	uint8_t job_id;
+	uint32_t flags;
+	sdm_command_callback cb;
+	uint32_t *cb_args;
+	uint8_t cb_args_len;
+} sdm_command_t;
+
+/* Get the transcation ID from client ID and job ID. */
+#define MBOX_GET_TRANS_ID(cid, jib)			(((cid) << 4) | (jib))
+
+/* Mailbox service data structure */
+typedef struct mailbox_service {
+	sdm_resp_state_t resp_state;
+	sdm_resp_state_t next_resp_state;
+	uint32_t flags;
+	int curr_di;
+	uint64_t received_bitmap[MBOX_MAX_TIDS_BITMAP];
+	uint64_t interrupt_bitmap[MBOX_MAX_TIDS_BITMAP];
+	sdm_command_t cmd_queue[MBOX_SVC_CMD_QUEUE_SIZE];
+	sdm_response_t resp_queue[MBOX_SVC_RESP_QUEUE_SIZE];
+} mailbox_service_t;
+
+int mailbox_send_cmd_async_v3(uint8_t client_id, uint8_t job_id, uint32_t cmd,
+			      uint32_t *args, uint32_t args_len, uint8_t cmd_flag,
+			      sdm_command_callback cb, uint32_t *cb_args,
+			      uint32_t cb_args_len);
+
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint64_t *ret_args,
+			     uint32_t *ret_args_size);
+
+int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
+				     uint64_t *bitmap);
+
+#endif		/* #if SIP_SVC_V3 */
+
 #endif /* SOCFPGA_MBOX_H */

diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index fbe18c3..782b2b5 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h

@@ -65,4 +65,6 @@
 
 void plat_secondary_cpus_bl31_entry(void);
 
+void setup_clusterectlr_el1(void);
+
 #endif /* SOCFPGA_PRIVATE_H */

diff --git a/plat/intel/soc/common/include/socfpga_ros.h b/plat/intel/soc/common/include/socfpga_ros.h
index 10cabd3..62a9fe8 100644
--- a/plat/intel/soc/common/include/socfpga_ros.h
+++ b/plat/intel/soc/common/include/socfpga_ros.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2024, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -40,8 +41,8 @@
 #define SPT_MIN_PARTITIONS		(9U)
 
 #define FACTORY_IMAGE			"FACTORY_IMAGE"
-#define FACTORY_SSBL			"FACTORY_IM.SSBL"
-#define SSBL_SUFFIX			".SSBL"
+#define FACTORY_SSBL			"SSBL.FACTORY_IM"
+#define SSBL_PREFIX			"SSBL."
 
 typedef struct {
 	const uint32_t magic_number;
@@ -55,7 +56,7 @@
 		const uint32_t length;
 		const uint32_t flags;
 	} partition[SPT_MAX_PARTITIONS];
-} __packed spt_table_t;
+} __packed __aligned(4) spt_table_t;
 
 uint32_t ros_qspi_get_ssbl_offset(unsigned long *offset);
 

diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index fc667cc..9e06397 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h

@@ -26,6 +26,10 @@
 #define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN				0x400
 #define INTEL_SIP_SMC_CMD_V2_RANGE_END					0x4FF
 
+/* SiP V3 command code range */
+#define INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN				0x00C8
+#define INTEL_SIP_SMC_CMD_V3_RANGE_END					0x01F4
+
 /* SiP V2 protocol header */
 #define INTEL_SIP_SMC_HEADER_JOB_ID_MASK				0xF
 #define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET				0U
@@ -149,6 +153,9 @@
 /* ATF build version */
 #define INTEL_SIP_SMC_ATF_BUILD_VER					0xC200009B
 
+/* IO96B ECC Error Injection */
+#define INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR				0xC200009C
+
 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK					0xF
 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK				0xF
 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET				4U
@@ -159,6 +166,8 @@
 #define SYSMGR_ECC_DBE_COLD_RST_MASK					(SYSMGR_ECC_OCRAM_MASK |\
 									SYSMGR_ECC_DDR0_MASK |\
 									SYSMGR_ECC_DDR1_MASK)
+#define IOSSM_ECC_ERR_INJ_DELAY_USECS					(40U)
+#define IOSSM_CMD_STATUS_RESP_READY					BIT(0)
 
 /* Non-mailbox SMC Call */
 #define INTEL_SIP_SMC_SVC_VERSION					0xC2000200
@@ -189,11 +198,11 @@
 /*
  * Increase if there is any backward compatibility impact
  */
-#define SIP_SVC_VERSION_MAJOR						2
+#define SIP_SVC_VERSION_MAJOR						3
 /*
  * Increase if there is new SMC function ID being added
  */
-#define SIP_SVC_VERSION_MINOR						2
+#define SIP_SVC_VERSION_MINOR						1
 
 
 /* Structure Definitions */
@@ -243,4 +252,119 @@
 			 void *handle,
 			 u_register_t flags);
 
+
+#if SIP_SVC_V3
+#define SMC_RET_ARGS_ONE							(1)
+#define SMC_RET_ARGS_TWO							(2)
+#define SMC_RET_ARGS_THREE							(3)
+#define SMC_RET_ARGS_FOUR							(4)
+#define SMC_RET_ARGS_FIVE							(5)
+#define SMC_RET_ARGS_SIX							(6)
+#define SMC_RET_ARGS_SEVEN							(7)
+#define SMC_RET_ARGS_EIGHT							(8)
+#define SMC_RET_ARGS_NINE							(9)
+#define SMC_RET_ARGS_TEN							(10)
+
+#define MBOX_GEN_CMD_MAX_WORDS							(0x1000)
+
+/*
+ * SiP SVC Version3 SMC Functions IDs
+ */
+
+/* Generic response POLL commands */
+#define ALTERA_SIP_SMC_ASYNC_RESP_POLL						(0x420000C8)
+#define ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR					(0x420000C9)
+
+/* QSPI related commands */
+#define ALTERA_SIP_SMC_ASYNC_QSPI_OPEN						(0x420000CC)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE						(0x420000CD)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS					(0x420000CE)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_ERASE						(0x420000CF)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_WRITE						(0x420000D0)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_READ						(0x420000D1)
+#define ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY				(0x420000D2)
+#define ALTERA_SIP_SMC_ASYNC_GET_IDCODE						(0x420000D3)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO					(0x420000D4)
+
+#define ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP					(0x420000E8)
+#define ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT					(0x420000E9)
+
+/* RSU related commands */
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT					(0x420000EA)
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS					(0x420000EB)
+#define ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY						(0x420000EC)
+
+/* V3 Generic mailbox command. */
+#define ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD					(0x420000EE)
+
+/* FCS crypto service VAB/SDOS commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER					(0x4200012C)
+#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT				(0x4200012D)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION					(0x4200012E)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT					(0x4200012F)
+#define ALTERA_SIP_SMC_ASYNC_FCS_SERVICE_REQUEST				(0x42000130)
+#define ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE				(0x42000131)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA				(0x42000132)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH				(0x42000133)
+#define ALTERA_SIP_SMC_ASYNC_FCS_PSGSIGMA_TEARDOWN				(0x42000134)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID					(0x42000135)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ATTESTATION_SUBKEY				(0x42000136)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ATTESTATION_MEASUREMENTS			(0x42000137)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT				(0x42000138)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD				(0x42000139)
+
+/* FCS crypto service session management commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION				(0x4200013A)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION				(0x4200013B)
+
+/* FCS crypto service key management commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY					(0x4200013C)
+#define ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY					(0x4200013D)
+#define ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY					(0x4200013E)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO				(0x4200013F)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY					(0x42000167)
+
+/* FCS crypto service primitive commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT					(0x42000140)
+#define ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE				(0x42000141)
+#define ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE				(0x42000142)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT				(0x42000143)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE				(0x42000144)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE				(0x42000145)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_SMMU_UPDATE				(0x42000146)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_SMMU_FINALIZE			(0x42000147)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT				(0x42000148)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE				(0x42000149)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE				(0x4200014A)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_SMMU_UPDATE				(0x4200014B)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_SMMU_FINALIZE			(0x4200014C)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT				(0x4200014D)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE			(0x4200014E)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT			(0x4200014F)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE			(0x42000150)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE			(0x42000151)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE		(0x42000152)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE		(0x42000153)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT			(0x42000154)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE			(0x42000155)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT		(0x42000156)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE		(0x42000157)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE		(0x42000158)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE		(0x42000159)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE	(0x4200015A)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT				(0x42000160)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE			(0x42000161)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT				(0x42000162)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE				(0x42000163)
+#define ALTERA_SIP_SMC_ASYNC_FCS_SDM_REMAPPER_CONFIG				(0x42000164)
+#define ALTERA_SIP_SMC_ASYNC_MCTP_MSG						(0x42000165)
+#define ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST					(0x42000166)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY					(0x42000167)
+
+#define GET_CLIENT_ID(x)							(((x) & 0xF0) >> 4)
+#define GET_JOB_ID(x)								((x) & 0x0F)
+#define GET_ADDR64(high, low)							(((uint64_t)(high) \
+										   << 32) | (low))
+#endif	/* SIP_SVC_V3 */
+
 #endif /* SOCFPGA_SIP_SVC_H */

diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index 91df934..507a9e9 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c

@@ -1,13 +1,15 @@
 /*
  * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch_helpers.h>
+#include <common/debug.h>
 #include <lib/mmio.h>
 
+#include "socfpga_plat_def.h"
 #include "socfpga_fcs.h"
 #include "socfpga_mailbox.h"
 #include "socfpga_sip_svc.h"
@@ -23,6 +25,267 @@
 static fcs_crypto_service_data fcs_ecdsa_get_pubkey_param;
 static fcs_crypto_service_data fcs_ecdh_request_param;
 
+uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0x%x, status_word %d\n",
+		__func__, resp->err_code, resp->resp_data[0]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->resp_data[0];
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0x%x\n", __func__, resp->err_code);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0x%x, nbytes_ret %d\n",
+		__func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+
+	INFO("MBOX: %s: mbox_err 0x%x, hkdf_status 0x%x\n", __func__,
+		resp->err_code, resp->resp_data[0]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->resp_data[0];
+
+	return ret_args_len;
+}
+
+uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0x%x\n", __func__, resp->err_code);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mbox_err  0x%x, nbytes_ret %d\n", __func__,
+		resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d, verify_result 0x%x\n",
+		__func__, resp->err_code,
+		resp->rcvd_resp_len * MBOX_WORD_BYTE,
+		resp->resp_data[3]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+	ret_args[ret_args_len++] = resp->resp_data[3];
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: [0] 0%x, [1] 0x%x, [2] 0x%x, len_words %d\n",
+			__func__, resp->resp_data[0], resp->resp_data[1],
+			resp->resp_data[2], resp->rcvd_resp_len);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: [0] 0%x, [1] 0x%x, [2] 0x%x, [3] 0x%x\n",
+			__func__, resp->resp_data[0], resp->resp_data[1],
+			resp->resp_data[2], resp->resp_data[3]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+
+	INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d\n", __func__,
+		resp->err_code, resp->resp_data[3]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->resp_data[3];
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d\n", __func__,
+		resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0x%x, nbytes_ret %d\n",
+		__func__, resp->err_code, resp->resp_data[3]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	/* Encrypted/Decrypted data size written to the destination buffer */
+	ret_args[ret_args_len++] = resp->resp_data[3];
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %u\n",
+			__func__, resp->err_code,
+			resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret 0x%x\n",
+			__func__, resp->err_code, resp->rcvd_resp_len);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: [0] 0%x, [1] 0x%x, [2] 0x%x, len_words %d\n",
+			__func__, resp->resp_data[0], resp->resp_data[1],
+			resp->resp_data[2], resp->rcvd_resp_len);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
 bool is_size_4_bytes_aligned(uint32_t size)
 {
 	if ((size % MBOX_WORD_BYTE) != 0U) {
@@ -41,6 +304,17 @@
 	}
 }
 
+/* As of now used on only Agilex5 platform. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+static bool is_16_bytes_aligned(uint32_t data)
+{
+	if ((data % (MBOX_WORD_BYTE * 4U)) != 0U)
+		return false;
+	else
+		return true;
+}
+#endif
+
 static bool is_32_bytes_aligned(uint32_t data)
 {
 	if ((data % (8U * MBOX_WORD_BYTE)) != 0U) {
@@ -155,7 +429,8 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
+uint32_t intel_fcs_send_cert(uint32_t smc_fid, uint32_t trans_id,
+			     uint64_t addr, uint64_t size,
 					uint32_t *send_id)
 {
 	int status;
@@ -168,7 +443,17 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	status = mailbox_send_cmd_async(send_id, MBOX_CMD_VAB_SRC_CERT,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE) ?
+		mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_CMD_VAB_SRC_CERT,
+					(uint32_t *) addr,
+					size / MBOX_WORD_BYTE,
+					MBOX_CMD_FLAG_CASUAL,
+					fcs_send_cert_cb,
+					NULL,
+					0U) :
+		mailbox_send_cmd_async(send_id, MBOX_CMD_VAB_SRC_CERT,
 				(uint32_t *)addr, size / MBOX_WORD_BYTE,
 				CMD_DIRECT);
 
@@ -195,7 +480,8 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, int32_t counter_value,
+uint32_t intel_fcs_cntr_set_preauth(uint32_t smc_fid, uint32_t trans_id,
+				    uint8_t counter_type, int32_t counter_value,
 					uint32_t test_bit, uint32_t *mbox_error)
 {
 	int status;
@@ -230,7 +516,18 @@
 	};
 
 	payload_size = sizeof(payload) / MBOX_WORD_BYTE;
-	status =  mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_CNTR_SET_PREAUTH,
+
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						  GET_JOB_ID(trans_id),
+						  MBOX_FCS_CNTR_SET_PREAUTH,
+						  (uint32_t *) &payload,
+						  payload_size,
+						  MBOX_CMD_FLAG_CASUAL,
+						  fcs_cntr_set_preauth_cb,
+						  NULL,
+						  0U) :
+			mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_CNTR_SET_PREAUTH,
 				  (uint32_t *) &payload, payload_size,
 				  CMD_CASUAL, NULL, NULL);
 
@@ -317,14 +614,18 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
+int intel_fcs_encryption_ext(uint32_t smc_fid, uint32_t trans_id,
+		uint32_t session_id, uint32_t context_id,
 		uint32_t src_addr, uint32_t src_size,
-		uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error)
+		uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error,
+		uint32_t smmu_src_addr, uint32_t smmu_dst_addr)
 {
 	int status;
 	uint32_t payload_size;
 	uint32_t resp_len = FCS_CRYPTION_RESP_WORD_SIZE;
 	uint32_t resp_data[FCS_CRYPTION_RESP_WORD_SIZE] = {0U};
+	uint32_t src_addr_sdm = src_addr;
+	uint32_t dst_addr_sdm = dst_addr;
 
 	if ((dst_size == NULL) || (mbox_error == NULL)) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
@@ -339,19 +640,35 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
+	/* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	src_addr_sdm = smmu_src_addr;
+	dst_addr_sdm = smmu_dst_addr;
+#endif
+
 	fcs_encrypt_ext_payload payload = {
 		session_id,
 		context_id,
 		FCS_CRYPTION_CRYPTO_HEADER,
-		src_addr,
+		src_addr_sdm,
 		src_size,
-		dst_addr,
+		dst_addr_sdm,
 		*dst_size
 	};
 
 	payload_size = sizeof(payload) / MBOX_WORD_BYTE;
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ENCRYPT_REQ,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT) ?
+		mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_FCS_ENCRYPT_REQ,
+					(uint32_t *) &payload,
+					payload_size,
+					MBOX_CMD_FLAG_INDIRECT,
+					fcs_sdos_crypto_request_cb,
+					NULL,
+					0U) :
+		mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ENCRYPT_REQ,
 				(uint32_t *) &payload, payload_size,
 				CMD_CASUAL, resp_data, &resp_len);
 
@@ -371,15 +688,20 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-int intel_fcs_decryption_ext(uint32_t session_id, uint32_t context_id,
+int intel_fcs_decryption_ext(uint32_t smc_fid, uint32_t trans_id,
+		uint32_t session_id, uint32_t context_id,
 		uint32_t src_addr, uint32_t src_size,
-		uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error)
+		uint32_t dst_addr, uint32_t *dst_size,
+		uint32_t *mbox_error, uint64_t owner_id,
+		uint32_t smmu_src_addr, uint32_t smmu_dst_addr)
 {
 	int status;
 	uintptr_t id_offset;
 	uint32_t payload_size;
 	uint32_t resp_len = FCS_CRYPTION_RESP_WORD_SIZE;
 	uint32_t resp_data[FCS_CRYPTION_RESP_WORD_SIZE] = {0U};
+	uint32_t src_addr_sdm = src_addr;
+	uint32_t dst_addr_sdm = dst_addr;
 
 	if ((dst_size == NULL) || (mbox_error == NULL)) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
@@ -394,6 +716,12 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
+	/* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	src_addr_sdm = smmu_src_addr;
+	dst_addr_sdm = smmu_dst_addr;
+#endif
+
 	inv_dcache_range(src_addr, src_size); /* flush cache before mmio read to avoid reading old values */
 	id_offset = src_addr + FCS_OWNER_ID_OFFSET;
 	fcs_decrypt_ext_payload payload = {
@@ -402,15 +730,25 @@
 		FCS_CRYPTION_CRYPTO_HEADER,
 		{mmio_read_32(id_offset),
 		mmio_read_32(id_offset + MBOX_WORD_BYTE)},
-		src_addr,
+		src_addr_sdm,
 		src_size,
-		dst_addr,
+		dst_addr_sdm,
 		*dst_size
 	};
 
 	payload_size = sizeof(payload) / MBOX_WORD_BYTE;
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_DECRYPT_REQ,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT) ?
+		mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_FCS_DECRYPT_REQ,
+					(uint32_t *) &payload,
+					payload_size,
+					MBOX_CMD_FLAG_INDIRECT,
+					fcs_sdos_crypto_request_cb,
+					NULL,
+					0U) :
+		mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_DECRYPT_REQ,
 				(uint32_t *) &payload, payload_size,
 				CMD_CASUAL, resp_data, &resp_len);
 
@@ -567,7 +905,8 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
+int intel_fcs_get_attestation_cert(uint32_t smc_fid, uint32_t trans_id,
+			uint32_t cert_request, uint64_t dst_addr,
 			uint32_t *dst_size, uint32_t *mbox_error)
 {
 	int status;
@@ -586,7 +925,17 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ATTESTATION_CERT,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT) ?
+		mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_GET_ATTESTATION_CERT,
+					(uint32_t *) &cert_request,
+					1U,
+					MBOX_CMD_FLAG_CASUAL,
+					fcs_get_attest_cert_cb,
+					(uint32_t *)dst_addr,
+					2U) :
+		mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ATTESTATION_CERT,
 			(uint32_t *) &cert_request, 1U, CMD_CASUAL,
 			(uint32_t *) dst_addr, &ret_size);
 
@@ -601,8 +950,8 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-int intel_fcs_create_cert_on_reload(uint32_t cert_request,
-			uint32_t *mbox_error)
+int intel_fcs_create_cert_on_reload(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t cert_request, uint32_t *mbox_error)
 {
 	int status;
 
@@ -615,7 +964,17 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CREATE_CERT_ON_RELOAD,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD) ?
+		mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_CREATE_CERT_ON_RELOAD,
+					(uint32_t *) &cert_request,
+					1U,
+					MBOX_CMD_FLAG_CASUAL,
+					fcs_create_cert_reload_cb,
+					NULL,
+					0U) :
+		mailbox_send_cmd(MBOX_JOB_ID, MBOX_CREATE_CERT_ON_RELOAD,
 			(uint32_t *) &cert_request, 1U, CMD_CASUAL,
 			NULL, NULL);
 
@@ -851,11 +1210,12 @@
 				mbox_error);
 }
 
-int intel_fcs_get_digest_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint32_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t *dst_size, uint8_t is_finalised,
-				uint32_t *mbox_error)
+int intel_fcs_get_digest_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint32_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t *dst_size,
+				uint8_t is_finalised, uint32_t *mbox_error,
+				uint32_t smmu_src_addr)
 {
 	int status;
 	uint32_t i;
@@ -928,12 +1288,29 @@
 		i++;
 	}
 	/* Data source address and size */
+
+	/* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	payload[i] = smmu_src_addr;
+#else
 	payload[i] = src_addr;
+#endif
 	i++;
 	payload[i] = src_size;
 	i++;
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_GET_DIGEST_REQ,
+	status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE) ||
+		  (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE)) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						   GET_JOB_ID(trans_id),
+						   MBOX_FCS_GET_DIGEST_REQ,
+						   payload,
+						   i,
+						   MBOX_CMD_FLAG_CASUAL,
+						   fcs_cs_get_digest_cb,
+						   (uint32_t *)dst_addr,
+						   2U) :
+			mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_GET_DIGEST_REQ,
 				payload, i, CMD_CASUAL,
 				(uint32_t *) dst_addr, &resp_len);
 
@@ -1061,11 +1438,12 @@
 				mbox_error);
 }
 
-int intel_fcs_mac_verify_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint32_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t *dst_size, uint32_t data_size,
-				uint8_t is_finalised, uint32_t *mbox_error)
+int intel_fcs_mac_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint32_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t *dst_size,
+				uint32_t data_size, uint8_t is_finalised,
+				uint32_t *mbox_error, uint64_t smmu_src_addr)
 {
 	int status;
 	uint32_t i;
@@ -1149,8 +1527,13 @@
 				<< FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET;
 		i++;
 	}
+
 	/* Data source address and size */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	payload[i] = (uint32_t)smmu_src_addr;
+#else
 	payload[i] = src_addr;
+#endif
 	i++;
 	payload[i] = data_size;
 	i++;
@@ -1171,7 +1554,18 @@
 		i += (src_size - data_size) / MBOX_WORD_BYTE;
 	}
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_MAC_VERIFY_REQ,
+	status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE) ||
+		  (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE)) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						   GET_JOB_ID(trans_id),
+						   MBOX_FCS_MAC_VERIFY_REQ,
+						   payload,
+						   i,
+						   MBOX_CMD_FLAG_CASUAL,
+						   fcs_cs_mac_verify_cb,
+						   (uint32_t *)dst_addr,
+						   2U) :
+			mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_MAC_VERIFY_REQ,
 				payload, i, CMD_CASUAL,
 				(uint32_t *) dst_addr, &resp_len);
 
@@ -1336,7 +1730,8 @@
 				mbox_error);
 }
 
-int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sign_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error)
@@ -1407,7 +1802,17 @@
 
 	i += src_size / MBOX_WORD_BYTE;
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIGN_REQ,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						   GET_JOB_ID(trans_id),
+						   MBOX_FCS_ECDSA_HASH_SIGN_REQ,
+						   payload,
+						   i,
+						   MBOX_CMD_FLAG_CASUAL,
+						   fcs_cs_hash_sign_req_cb,
+						   (uint32_t *)dst_addr,
+						   2U) :
+			mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIGN_REQ,
 			payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
 			&resp_len);
 
@@ -1435,7 +1840,8 @@
 				mbox_error);
 }
 
-int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t smc_fid, uint32_t trans_id,
+					uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error)
@@ -1451,8 +1857,8 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	if (fcs_ecdsa_hash_sig_verify_param.session_id != session_id ||
-	fcs_ecdsa_hash_sig_verify_param.context_id != context_id) {
+	if ((fcs_ecdsa_hash_sig_verify_param.session_id != session_id) ||
+	    (fcs_ecdsa_hash_sig_verify_param.context_id != context_id)) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
@@ -1508,7 +1914,18 @@
 
 	i += (src_size / MBOX_WORD_BYTE);
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE) ?
+		mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
+					payload,
+					i,
+					MBOX_CMD_FLAG_CASUAL,
+					fcs_cs_hash_sig_verify_req_cb,
+					(uint32_t *)dst_addr,
+					2U) :
+
+		mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
 			payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
 			&resp_len);
 
@@ -1537,11 +1954,12 @@
 				mbox_error);
 }
 
-int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint32_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t *dst_size, uint8_t is_finalised,
-				uint32_t *mbox_error)
+int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint32_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t *dst_size,
+				uint8_t is_finalised, uint32_t *mbox_error,
+				uint64_t smmu_src_addr)
 {
 	int status;
 	int i;
@@ -1608,11 +2026,27 @@
 	}
 
 	/* Data source address and size */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	payload[i] = (uint32_t)smmu_src_addr;
+#else
 	payload[i] = src_addr;
+#endif
 	i++;
 	payload[i] = src_size;
 	i++;
-	status = mailbox_send_cmd(MBOX_JOB_ID,
+
+	status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE) ||
+		  (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE)) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						GET_JOB_ID(trans_id),
+						MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ,
+						payload,
+						i,
+						MBOX_CMD_FLAG_CASUAL,
+						fcs_cs_data_sign_req_cb,
+						(uint32_t *)dst_addr,
+						2U) :
+			mailbox_send_cmd(MBOX_JOB_ID,
 			MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ, payload,
 			i, CMD_CASUAL, (uint32_t *) dst_addr,
 			&resp_len);
@@ -1737,11 +2171,12 @@
 				mbox_error);
 }
 
-int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint32_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t *dst_size, uint32_t data_size,
-				uint8_t is_finalised, uint32_t *mbox_error)
+int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint32_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t *dst_size,
+				uint32_t data_size, uint8_t is_finalised,
+				uint32_t *mbox_error, uint64_t smmu_src_addr)
 {
 	int status;
 	uint32_t i;
@@ -1825,7 +2260,12 @@
 	}
 
 	/* Data source address and size */
+	/* On the Agilex5 platform, the SMMU remapped address is used */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	payload[i] = smmu_src_addr;
+#else
 	payload[i] = src_addr;
+#endif
 	i++;
 	payload[i] = data_size;
 	i++;
@@ -1846,7 +2286,18 @@
 		i += (src_size - data_size) / MBOX_WORD_BYTE;
 	}
 
-	status = mailbox_send_cmd(MBOX_JOB_ID,
+	status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE) ||
+		  (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE)) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						GET_JOB_ID(trans_id),
+						MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY,
+						payload,
+						i,
+						MBOX_CMD_FLAG_CASUAL,
+						fcs_cs_data_sig_verify_req_cb,
+						(uint32_t *)dst_addr,
+						2U) :
+			mailbox_send_cmd(MBOX_JOB_ID,
 			MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY, payload, i,
 			CMD_CASUAL, (uint32_t *) dst_addr, &resp_len);
 
@@ -2010,7 +2461,8 @@
 				mbox_error);
 }
 
-int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error)
 {
@@ -2054,7 +2506,18 @@
 			INTEL_SIP_SMC_FCS_ECC_ALGO_MASK;
 	i++;
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_GET_PUBKEY,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						GET_JOB_ID(trans_id),
+						MBOX_FCS_ECDSA_GET_PUBKEY,
+						payload,
+						i,
+						MBOX_CMD_FLAG_CASUAL,
+						fcs_cs_get_public_key_cb,
+						(uint32_t *)dst_addr,
+						2U) :
+			mailbox_send_cmd(MBOX_JOB_ID,
+					 MBOX_FCS_ECDSA_GET_PUBKEY,
 			payload, i, CMD_CASUAL,
 			(uint32_t *) dst_addr, &ret_size);
 
@@ -2082,7 +2545,8 @@
 				mbox_error);
 }
 
-int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdh_request_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
 				uint32_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t *dst_size,
 				uint32_t *mbox_error)
@@ -2098,7 +2562,6 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-
 	if (fcs_ecdh_request_param.session_id != session_id ||
 		fcs_ecdh_request_param.context_id != context_id) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
@@ -2110,10 +2573,9 @@
 	}
 
 	dst_size_check = *dst_size;
-	if ((dst_size_check > FCS_MAX_DATA_SIZE ||
-		dst_size_check < FCS_MIN_DATA_SIZE) ||
-		(src_size > FCS_MAX_DATA_SIZE ||
-		src_size < FCS_MIN_DATA_SIZE)) {
+
+	if ((dst_size_check > FCS_MAX_DATA_SIZE || dst_size_check < FCS_MIN_DATA_SIZE) ||
+	    (src_size > FCS_MAX_DATA_SIZE || src_size < FCS_MIN_DATA_SIZE)) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
@@ -2150,7 +2612,17 @@
 		(void *) pubkey, src_size / MBOX_WORD_BYTE);
 	i += src_size / MBOX_WORD_BYTE;
 
-	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDH_REQUEST,
+	status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						  GET_JOB_ID(trans_id),
+						  MBOX_FCS_ECDH_REQUEST,
+						  payload,
+						  i,
+						  MBOX_CMD_FLAG_CASUAL,
+						  fcs_cs_ecdh_request_cb,
+						  (uint32_t *)dst_addr,
+						  2U) :
+			mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDH_REQUEST,
 			payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
 			&resp_len);
 
@@ -2189,13 +2661,19 @@
 	}
 
 	/*
-	 * Check if not ECB, CBC and CTR mode, addr ptr is NULL.
-	 * Return "Reject" status
+	 * Check if not ECB, CBC and CTR, GCM and GCM-GHASH mode (only for Agilex5),
+	 * addr ptr is NULL. Return "Reject" status
 	 */
 	if ((param_addr_ptr == NULL) ||
-		(((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_ECB_MODE) &&
-		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CBC_MODE) &&
-		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CTR_MODE))) {
+	    (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_ECB_MODE) &&
+	    ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CBC_MODE) &&
+	    ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CTR_MODE)
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	    &&
+	    ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_GCM_MODE) &&
+	    ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_GCM_GHASH_MODE)
+#endif
+	    )){
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
@@ -2204,7 +2682,9 @@
 	 * Check CBC/CTR here and limit to size 28 bytes
 	 */
 	if ((((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CBC_MODE) ||
-		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CTR_MODE)) &&
+		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CTR_MODE) ||
+		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_GCM_MODE) ||
+		((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_GCM_GHASH_MODE)) &&
 		(param_size > FCS_CRYPTO_CBC_CTR_BUFFER_SIZE)) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
@@ -2235,41 +2715,70 @@
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
-int intel_fcs_aes_crypt_update_finalize(uint32_t session_id,
-				uint32_t context_id, uint64_t src_addr,
-				uint32_t src_size, uint64_t dst_addr,
-				uint32_t dst_size, uint8_t is_finalised,
-				uint32_t *send_id)
+int intel_fcs_aes_crypt_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+				uint32_t session_id, uint32_t context_id,
+				uint64_t src_addr, uint32_t src_size,
+				uint64_t dst_addr, uint32_t dst_size,
+				uint32_t padding_size, uint8_t is_finalised,
+				uint32_t *send_id, uint64_t smmu_src_addr,
+				uint64_t smmu_dst_addr)
 {
 	int status;
 	int i;
 	uint32_t flag;
 	uint32_t crypto_header;
 	uint32_t fcs_aes_crypt_payload[FCS_AES_CMD_MAX_WORD_SIZE];
+	uint32_t src_addr_sdm = (uint32_t)src_addr;
+	uint32_t dst_addr_sdm = (uint32_t)dst_addr;
+	bool is_src_size_aligned;
+	bool is_dst_size_aligned;
+	bool is_src_size_valid;
+	bool is_dst_size_valid;
 
 	if (fcs_aes_init_payload.session_id != session_id ||
 		fcs_aes_init_payload.context_id != context_id) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
+	/* Default source and destination size align check, 32 bytes alignment. */
+	is_src_size_aligned = is_32_bytes_aligned(src_size);
+	is_dst_size_aligned = is_32_bytes_aligned(dst_size);
+	is_src_size_valid = FCS_AES_DATA_SIZE_CHECK(src_size);
+	is_dst_size_valid = FCS_AES_DATA_SIZE_CHECK(dst_size);
+
+	/*
+	 * Get the requested block mode.
+	 * On the Agilex5 platform with GCM and GCM-GHASH modes, the source and destination size
+	 * should be in multiples of 16 bytes. For other platforms and other modes, it should be
+	 * in multiples of 32 bytes.
+	 */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	uint32_t block_mode = fcs_aes_init_payload.crypto_param[0] & FCS_CRYPTO_BLOCK_MODE_MASK;
+
+	if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+	    (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+		is_src_size_aligned = is_16_bytes_aligned(src_size);
+		is_dst_size_aligned = is_16_bytes_aligned(dst_size);
+		/* The size validity here is, should be 0 or multiples of 16 bytes. */
+		is_src_size_valid = is_16_bytes_aligned(src_size);
+		is_dst_size_valid = is_16_bytes_aligned(dst_size);
+	}
+#endif
+
 	if ((!is_8_bytes_aligned(src_addr)) ||
-		(!is_32_bytes_aligned(src_size)) ||
+		(!is_src_size_aligned) ||
 		(!is_address_in_ddr_range(src_addr, src_size))) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
 	if ((!is_8_bytes_aligned(dst_addr)) ||
-		(!is_32_bytes_aligned(dst_size)) ||
+		(!is_dst_size_aligned) ||
 		(!is_address_in_ddr_range(dst_addr, dst_size))) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	if ((dst_size > FCS_AES_MAX_DATA_SIZE ||
-		dst_size < FCS_AES_MIN_DATA_SIZE) ||
-		(src_size > FCS_AES_MAX_DATA_SIZE ||
-		src_size < FCS_AES_MIN_DATA_SIZE)) {
+	if (!is_src_size_valid || !is_dst_size_valid)
 		return INTEL_SIP_SMC_STATUS_REJECTED;
-	}
 
 	/* Prepare crypto header*/
 	flag = 0;
@@ -2297,7 +2806,7 @@
 	i++;
 
 	if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
-		FCS_CS_FIELD_FLAG_INIT) {
+	    (FCS_CS_FIELD_FLAG_INIT)) {
 		fcs_aes_crypt_payload[i] = fcs_aes_init_payload.key_id;
 		i++;
 
@@ -2314,25 +2823,125 @@
 		i += fcs_aes_init_payload.param_size / MBOX_WORD_BYTE;
 	}
 
-	fcs_aes_crypt_payload[i] = (uint32_t) src_addr;
+	/* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	src_addr_sdm = (uint32_t)smmu_src_addr;
+	dst_addr_sdm = (uint32_t)smmu_dst_addr;
+#endif
+
+	fcs_aes_crypt_payload[i] = src_addr_sdm;
 	i++;
 	fcs_aes_crypt_payload[i] = src_size;
 	i++;
-	fcs_aes_crypt_payload[i] = (uint32_t) dst_addr;
+	fcs_aes_crypt_payload[i] = dst_addr_sdm;
 	i++;
 	fcs_aes_crypt_payload[i] = dst_size;
 	i++;
 
-	status = mailbox_send_cmd_async(send_id, MBOX_FCS_AES_CRYPT_REQ,
-					fcs_aes_crypt_payload, i,
-					CMD_INDIRECT);
+	/* Padding data size, only on Agilex5 with GCM and GCM-GHASH modes. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+	    (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+		fcs_aes_crypt_payload[i] = padding_size;
+		i++;
+	}
+#endif
+
+	status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE) ||
+		  (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE)) ?
+			mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+						   GET_JOB_ID(trans_id),
+						   MBOX_FCS_AES_CRYPT_REQ,
+						   fcs_aes_crypt_payload,
+						   i,
+						   MBOX_CMD_FLAG_INDIRECT,
+						   fcs_cs_aes_cb,
+						   NULL,
+						   0U) :
+			mailbox_send_cmd_async(send_id, MBOX_FCS_AES_CRYPT_REQ,
+					fcs_aes_crypt_payload, i, CMD_INDIRECT);
+
 
 	if (is_finalised != 0U) {
 		memset((void *)&fcs_aes_init_payload, 0,
 			sizeof(fcs_aes_init_payload));
 	}
 
-	if (status < 0U) {
+	if (status < 0) {
+		return INTEL_SIP_SMC_STATUS_ERROR;
+	}
+
+	return INTEL_SIP_SMC_STATUS_OK;
+}
+
+int intel_fcs_hkdf_request(uint32_t smc_fid, uint32_t trans_id,
+			   uint32_t session_id, uint32_t step_type,
+			   uint32_t mac_mode, uint32_t src_addr,
+			   uint32_t key_uid, uint32_t op_key_size)
+{
+	int status;
+	uint32_t i = 0;
+	uintptr_t inputdata;
+	uint32_t payload[FCS_HKDF_REQUEST_DATA_SIZE] = {0U};
+
+	if (!is_address_in_ddr_range(src_addr, FCS_HKDF_REQUEST_DATA_SIZE)) {
+		ERROR("MBOX: %s: source addr not in the DDR range\n", __func__);
+		return INTEL_SIP_SMC_STATUS_REJECTED;
+	}
+
+	/* Prepare command payload */
+
+	/* Session ID */
+	payload[i] = session_id;
+	i++;
+
+	/* Reserved, 8 bytes */
+	payload[i] = 0;
+	i++;
+
+	payload[i] = 0;
+	i++;
+
+	/* HKDF step type */
+	payload[i] = step_type;
+	i++;
+
+	/* MAC mode/PRF */
+	payload[i] = mac_mode;
+	i++;
+
+	/* Complete input data, 1st input data len + its data + 2nd input data len + its data. */
+	inputdata = src_addr;
+	memcpy_s((uint8_t *)&payload[i], FCS_HKDF_KEY_DATA_SIZE / sizeof(uint32_t),
+		(uint8_t *)inputdata, FCS_HKDF_KEY_DATA_SIZE / sizeof(uint32_t));
+
+	i += FCS_HKDF_KEY_DATA_SIZE / sizeof(uint32_t);
+
+	/* Key UID */
+	payload[i] = key_uid;
+	i++;
+
+	/* Pointer to size of output key object */
+	inputdata = inputdata + FCS_HKDF_KEY_DATA_SIZE;
+
+	/* Output Key object */
+	memcpy_s(&payload[i], op_key_size / sizeof(uint32_t), (void *)inputdata,
+		op_key_size / sizeof(uint32_t));
+
+	i += op_key_size / sizeof(uint32_t);
+
+	status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+					GET_JOB_ID(trans_id),
+					MBOX_FCS_HKDF_REQUEST,
+					payload,
+					i,
+					MBOX_CMD_FLAG_CASUAL,
+					fcs_hkdf_request_cb,
+					NULL,
+					0U);
+
+	if (status < 0) {
+		ERROR("MBOX: %s: status %d\n", __func__, status);
 		return INTEL_SIP_SMC_STATUS_ERROR;
 	}
 

diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 69f0008..bf1b7fb 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c

@@ -1,11 +1,12 @@
 /*
  * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <lib/mmio.h>
+#include <lib/spinlock.h>
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <platform_def.h>
@@ -15,6 +16,34 @@
 #include "socfpga_sip_svc.h"
 #include "socfpga_system_manager.h"
 
+#if SIP_SVC_V3
+/* Function prototypes */
+void mailbox_init_v3(void);
+static int mailbox_response_handler_fsm(void);
+static inline void mailbox_free_cmd_desc(sdm_command_t *cmd_desc);
+static sdm_response_t *mailbox_get_resp_desc(uint8_t client_id, uint8_t job_id,
+					     uint8_t *index);
+static sdm_command_t *mailbox_get_cmd_desc(uint8_t client_id, uint8_t job_id);
+static inline void mailbox_free_resp_desc(uint8_t index);
+static sdm_command_t *mailbox_get_free_cmd_desc(void);
+static sdm_response_t *mailbox_get_resp_desc_cid(uint8_t client_id,
+						 uint8_t *index);
+static int mailbox_read_response_v3(uint8_t client_id, uint8_t *job_id,
+				    uint32_t *header, uint32_t *resp,
+				    uint32_t *resp_len,
+				    uint8_t ignore_client_id);
+static int mailbox_poll_response_v3(uint8_t client_id, uint8_t job_id,
+				    uint32_t *resp, unsigned int *resp_len,
+				    uint32_t urgent);
+
+static spinlock_t mbox_db_lock;		/* Mailbox service data base lock */
+static spinlock_t mbox_write_lock;	/* Hardware mailbox FIFO write lock */
+static spinlock_t mbox_read_lock;	/* Hardware mailbox FIFO read lock */
+
+static mailbox_service_t mbox_svc;	/* Mailbox service data base */
+static uint8_t async_v1_job_id;
+#endif /* #if SIP_SVC_V3 */
+
 static mailbox_payload_t mailbox_resp_payload;
 static mailbox_container_t mailbox_resp_ctr = {0, 0, &mailbox_resp_payload};
 
@@ -34,13 +63,13 @@
 
 static int wait_for_mailbox_cmdbuf_empty(uint32_t cin)
 {
-	unsigned int timeout = 200U;
+	unsigned int timeout = 20000U;
 
 	do {
 		if (is_mailbox_cmdbuf_empty(cin)) {
 			break;
 		}
-		mdelay(10U);
+		udelay(50U);
 	} while (--timeout != 0U);
 
 	if (timeout == 0U) {
@@ -54,7 +83,9 @@
 				    uint32_t data,
 				    bool *is_doorbell_triggered)
 {
-	unsigned int timeout = 100U;
+	unsigned int timeout = 20000U;
+
+	VERBOSE("MBOX: 0x%x\n", data);
 
 	do {
 		if (is_mailbox_cmdbuf_full(*cin)) {
@@ -63,7 +94,7 @@
 					      MBOX_DOORBELL_TO_SDM, 1U);
 				*is_doorbell_triggered = true;
 			}
-			mdelay(10U);
+			udelay(50U);
 		} else {
 			mmio_write_32(MBOX_ENTRY_TO_ADDR(CMD, (*cin)++), data);
 			*cin %= MBOX_CMD_BUFFER_SIZE;
@@ -84,6 +115,11 @@
 	return MBOX_RET_OK;
 }
 
+/*
+ * Function description: Write the command header, and its payload one by one
+ * into the mailbox command buffer. Along with this, check for mailbox buffer
+ * full condition and trigger doorbell to SDM if the command buffer is full.
+ */
 static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
 					unsigned int len)
 {
@@ -92,15 +128,21 @@
 	int ret;
 	bool is_doorbell_triggered = false;
 
+#if SIP_SVC_V3
+	spin_lock(&mbox_write_lock);
+#endif
+
 	cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN);
 	sdm_read_offset = mmio_read_32(MBOX_OFFSET + MBOX_COUT);
 
+	/* Write the command header here */
 	ret = write_mailbox_cmd_buffer(&cmd_free_offset, sdm_read_offset,
 				       header_cmd, &is_doorbell_triggered);
 	if (ret != 0) {
 		goto restart_mailbox;
 	}
 
+	/* Write the payload here w.r.to args and its len - one by one. */
 	for (i = 0U; i < len; i++) {
 		is_doorbell_triggered = false;
 		ret = write_mailbox_cmd_buffer(&cmd_free_offset,
@@ -113,6 +155,9 @@
 
 	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
 
+#if SIP_SVC_V3
+	spin_unlock(&mbox_write_lock);
+#endif
 	return MBOX_RET_OK;
 
 restart_mailbox:
@@ -129,12 +174,21 @@
 		}
 	}
 
+#if SIP_SVC_V3
+	spin_unlock(&mbox_write_lock);
+#endif
 	return MBOX_TIMEOUT;
 }
 
 int mailbox_read_response(unsigned int *job_id, uint32_t *response,
 				unsigned int *resp_len)
 {
+#if SIP_SVC_V3
+	return mailbox_read_response_v3(MBOX_ATF_CLIENT_ID,
+					(uint8_t *)job_id, NULL,
+					response, resp_len,
+					0);
+#else
 	uint32_t rin;
 	uint32_t rout;
 	uint32_t resp_data;
@@ -174,13 +228,23 @@
 
 		return MBOX_RET_OK;
 	}
+
 	return MBOX_NO_RESPONSE;
+#endif
 }
 
 int mailbox_read_response_async(unsigned int *job_id, uint32_t *header,
 				uint32_t *response, unsigned int *resp_len,
 				uint8_t ignore_client_id)
 {
+#if SIP_SVC_V3
+	/* Just to avoid the build warning */
+	(void)mailbox_resp_ctr;
+	return mailbox_read_response_v3(MBOX_ATF_CLIENT_ID,
+					(uint8_t *)job_id, header,
+					response, resp_len,
+					ignore_client_id);
+#else
 	uint32_t rin;
 	uint32_t rout;
 	uint32_t resp_data;
@@ -220,7 +284,6 @@
 					return MBOX_WRONG_ID;
 				}
 			}
-
 			*job_id = MBOX_RESP_JOB_ID(resp_data);
 			ret_resp_len = MBOX_RESP_LEN(resp_data);
 			mailbox_resp_ctr.payload->header = resp_data;
@@ -272,11 +335,16 @@
 
 	*resp_len = 0;
 	return (mailbox_resp_ctr.flag & MBOX_PAYLOAD_FLAG_BUSY) ? MBOX_BUSY : MBOX_NO_RESPONSE;
+#endif
 }
 
 int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response,
-				unsigned int *resp_len)
+			  unsigned int *resp_len)
 {
+#if SIP_SVC_V3
+	return mailbox_poll_response_v3(MBOX_ATF_CLIENT_ID, (uint8_t)job_id,
+					response, resp_len, urgent);
+#else
 	unsigned int timeout = 40U;
 	unsigned int sdm_loop = 255U;
 	unsigned int ret_resp_len;
@@ -285,7 +353,6 @@
 	uint32_t resp_data;
 
 	while (sdm_loop != 0U) {
-
 		do {
 			if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)
 				== 1U) {
@@ -310,7 +377,7 @@
 			}
 
 			mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
-			INFO("Error: Mailbox did not get UA");
+			ERROR("MBOX: Mailbox did not get UA");
 			return MBOX_RET_ERROR;
 		}
 
@@ -324,13 +391,21 @@
 			rout %= MBOX_RESP_BUFFER_SIZE;
 			mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
 
-			if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID
-				|| MBOX_RESP_JOB_ID(resp_data) != job_id) {
+			if ((MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID) ||
+			    (MBOX_RESP_JOB_ID(resp_data) != job_id)) {
 				continue;
 			}
 
+			/* Get the return response len from the response header. */
 			ret_resp_len = MBOX_RESP_LEN(resp_data);
 
+			/* Print the response header. */
+			VERBOSE("MBOX: RespHdr: cid %d, jid %d, len %d, err_code 0x%x\n",
+				MBOX_RESP_CLIENT_ID(resp_data),
+				MBOX_RESP_JOB_ID(resp_data),
+				MBOX_RESP_LEN(resp_data),
+				MBOX_RESP_ERR(resp_data));
+
 			if (iterate_resp(ret_resp_len, response, resp_len)
 				!= MBOX_RET_OK) {
 				return MBOX_TIMEOUT;
@@ -349,6 +424,7 @@
 
 	INFO("Timed out waiting for SDM\n");
 	return MBOX_TIMEOUT;
+#endif
 }
 
 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
@@ -366,8 +442,7 @@
 
 		if ((resp_buf != NULL) && (resp_len != NULL)
 			&& (*resp_len != 0U)) {
-			*(resp_buf + total_resp_len)
-					= resp_data;
+			*(resp_buf + total_resp_len) = resp_data;
 			*resp_len = *resp_len - 1;
 			total_resp_len++;
 		}
@@ -417,6 +492,9 @@
 		return status;
 	}
 
+#if SIP_SVC_V3
+	async_v1_job_id = (uint8_t)*job_id;
+#endif
 	*job_id = (*job_id + 1U) % MBOX_MAX_IND_JOB_ID;
 
 	return MBOX_RET_OK;
@@ -433,9 +511,7 @@
 					MBOX_STATUS_UA_MASK;
 		mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd);
 		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
-	}
-
-	else {
+	} else {
 		status = fill_mailbox_circular_buffer(
 			MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
 			MBOX_JOB_ID_CMD(job_id) |
@@ -460,12 +536,12 @@
 
 void mailbox_set_int(uint32_t interrupt)
 {
-
-	mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) |
+	mmio_write_32(MBOX_OFFSET+MBOX_INT,
+			MBOX_COE_BIT(interrupt) |
+			MBOX_RIE_BIT(interrupt) |
 			MBOX_UAE_BIT(interrupt));
 }
 
-
 void mailbox_set_qspi_open(void)
 {
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
@@ -606,6 +682,7 @@
 
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
 			MBOX_INT_FLAG_UAE);
+
 	mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
 	mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
 
@@ -616,8 +693,16 @@
 		return status;
 	}
 
+#if SIP_SVC_V3
+	/* Initialize the mailbox version3 implementation, and in V3 we
+	 * are interested in only RIE interrupt
+	 */
+	mailbox_init_v3();
+	mailbox_set_int(MBOX_INT_FLAG_RIE);
+#else
 	mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
 			MBOX_INT_FLAG_UAE);
+#endif
 
 	return MBOX_RET_OK;
 }
@@ -730,3 +815,693 @@
 	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SAFE_INJECT_SEU_ERR, arg, len,
 			CMD_CASUAL, NULL, NULL);
 }
+
+#if SIP_SVC_V3
+static int mailbox_fill_cmd_desc(uint8_t client_id, uint8_t job_id,
+				 uint32_t *resp_buff)
+{
+	sdm_command_t *cmd_desc = NULL;
+
+	/* Get a free command descriptor */
+	cmd_desc = mailbox_get_free_cmd_desc();
+	if (cmd_desc == NULL) {
+		return MBOX_BUFFER_FULL;
+	}
+
+	/* Record all the given values for the command. */
+	cmd_desc->client_id = client_id;
+	cmd_desc->job_id = job_id;
+	cmd_desc->cb = NULL;
+	cmd_desc->cb_args = resp_buff;
+	cmd_desc->cb_args_len = 0U;
+
+	return MBOX_RET_OK;
+}
+
+/* Returns the command descriptor based on the client and job ID. */
+static sdm_command_t *mailbox_get_cmd_desc(uint8_t client_id, uint8_t job_id)
+{
+	spin_lock(&mbox_db_lock);
+	for (uint32_t count = 0; count < MBOX_SVC_CMD_QUEUE_SIZE; count++) {
+		if ((mbox_svc.cmd_queue[count].client_id == client_id) &&
+		    (mbox_svc.cmd_queue[count].job_id == job_id) &&
+		    (mbox_svc.cmd_queue[count].flags & MBOX_SVC_CMD_IS_USED)) {
+			spin_unlock(&mbox_db_lock);
+			return &(mbox_svc.cmd_queue[count]);
+		}
+	}
+
+	spin_unlock(&mbox_db_lock);
+	VERBOSE("MBOX: Command descriptor not found for cid %d, jid %d\n",
+		client_id, job_id);
+
+	return NULL;
+}
+
+/* Returns the response descriptor based on only client ID. */
+static sdm_response_t *mailbox_get_resp_desc_cid(uint8_t client_id, uint8_t *index)
+{
+	spin_lock(&mbox_db_lock);
+
+	for (uint32_t count = 0; count < MBOX_SVC_RESP_QUEUE_SIZE; count++) {
+		if ((mbox_svc.resp_queue[count].client_id == client_id) &&
+		    (mbox_svc.resp_queue[count].flags & FLAG_SDM_RESPONSE_IS_VALID)) {
+			*index = count;
+			/*
+			 * Once we get the valid response descriptor, get the
+			 * job ID and mark up the bitmaps.
+			 */
+			uint8_t job_id = mbox_svc.resp_queue[count].job_id;
+			uint8_t transaction_id = MBOX_GET_TRANS_ID(client_id, job_id);
+
+			mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+				~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+			mbox_svc.interrupt_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+				~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+			spin_unlock(&mbox_db_lock);
+			return &(mbox_svc.resp_queue[count]);
+		}
+	}
+
+	spin_unlock(&mbox_db_lock);
+	VERBOSE("MBOX: Response descriptor not found for cid %d\n", client_id);
+
+	return NULL;
+}
+
+/* Returns the response descriptor based on the client and job ID. */
+static sdm_response_t *mailbox_get_resp_desc(uint8_t client_id, uint8_t job_id, uint8_t *index)
+{
+	spin_lock(&mbox_db_lock);
+	/*
+	 * Let's first check whether we have a response bitmap set for the given
+	 * client ID and job ID.
+	 */
+	uint8_t transaction_id = MBOX_GET_TRANS_ID(client_id, job_id);
+
+	if ((mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &
+		(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE))) == 0) {
+		spin_unlock(&mbox_db_lock);
+		VERBOSE("MBOX: Response bitmap not set for cid %d, jid %d, bitmap 0x%16lx\n",
+			client_id, job_id, mbox_svc.received_bitmap[transaction_id / 64]);
+		return NULL;
+	}
+
+	for (uint32_t count = 0; count < MBOX_SVC_RESP_QUEUE_SIZE; count++) {
+		if (mbox_svc.resp_queue[count].flags & FLAG_SDM_RESPONSE_IS_VALID) {
+			if ((mbox_svc.resp_queue[count].client_id == client_id) &&
+			    (mbox_svc.resp_queue[count].job_id == job_id)) {
+				*index = count;
+				mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+					~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+				mbox_svc.interrupt_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+					~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+				spin_unlock(&mbox_db_lock);
+				return &(mbox_svc.resp_queue[count]);
+			}
+		}
+	}
+
+	spin_unlock(&mbox_db_lock);
+	VERBOSE("MBOX: Response descriptor not found for cid %d, jid %d\n",
+		client_id, job_id);
+
+	return NULL;
+}
+
+static int32_t mailbox_get_free_resp_desc(void)
+{
+	spin_lock(&mbox_db_lock);
+	static uint32_t free_index = MBOX_SVC_RESP_QUEUE_SIZE - 1;
+	uint32_t count = 0U, try = 0U;
+
+	for (try = 0; try < MBOX_SVC_RESP_QUEUE_SIZE; try++) {
+		free_index = (free_index + 1) % MBOX_SVC_RESP_QUEUE_SIZE;
+		if ((mbox_svc.resp_queue[free_index].flags &
+			FLAG_SDM_RESPONSE_IS_USED) != 0U) {
+			count = free_index;
+			spin_unlock(&mbox_db_lock);
+			return count;
+		}
+	}
+
+	/* No free descriptors are available */
+	spin_unlock(&mbox_db_lock);
+	VERBOSE("MBOX: No free response descriptors are available\n");
+
+	return MBOX_BUFFER_FULL;
+}
+
+static sdm_command_t *mailbox_get_free_cmd_desc(void)
+{
+	spin_lock(&mbox_db_lock);
+	static uint32_t free_index;
+
+	/* Rollover the command queue free index */
+	if (free_index == (MBOX_SVC_CMD_QUEUE_SIZE - 1)) {
+		free_index = 0U;
+	}
+
+	for (; free_index < MBOX_SVC_CMD_QUEUE_SIZE; free_index++) {
+		if ((mbox_svc.cmd_queue[free_index].flags &
+			MBOX_SVC_CMD_IS_USED) != 0U) {
+			mbox_svc.cmd_queue[free_index].flags |= MBOX_SVC_CMD_IS_USED;
+			spin_unlock(&mbox_db_lock);
+			return &(mbox_svc.cmd_queue[free_index]);
+		}
+	}
+
+	/* No free command descriptors are available */
+	spin_unlock(&mbox_db_lock);
+	VERBOSE("MBOX: No free command descriptors available\n");
+
+	return NULL;
+}
+
+static inline void mailbox_free_cmd_desc(sdm_command_t *cmd_desc)
+{
+	if (cmd_desc == NULL) {
+		return;
+	}
+
+	spin_lock(&mbox_db_lock);
+	memset((void *)cmd_desc, 0, sizeof(sdm_command_t));
+	spin_unlock(&mbox_db_lock);
+}
+
+static inline void mailbox_free_resp_desc(uint8_t index)
+{
+	if (index >= MBOX_SVC_RESP_QUEUE_SIZE) {
+		return;
+	}
+
+	spin_lock(&mbox_db_lock);
+	memset((void *)&mbox_svc.resp_queue[index], 0, sizeof(sdm_response_t));
+	spin_unlock(&mbox_db_lock);
+}
+
+/*
+ * This function serves the V1 _sync_read and _async_read functionality, and it
+ * is introduced as part of V3 framework to keep backward compatible with V1
+ * clients.
+ */
+static int mailbox_read_response_v3(uint8_t client_id, uint8_t *job_id,
+				    uint32_t *header, uint32_t *resp,
+				    uint32_t *resp_len,
+				    uint8_t ignore_client_id)
+{
+	uint8_t di = 0U;
+	int status = MBOX_RET_OK;
+	sdm_response_t *resp_desc = NULL;
+	sdm_command_t *cmd_desc = NULL;
+
+	/*
+	 * In the V1, the client ID is always MBOX_ATF_CLIENT_ID and in this
+	 * routine we will collect the response which only belongs to this
+	 * client ID. So safe to ignore this input.
+	 */
+	(void)ignore_client_id;
+
+	/* Clear the SDM doorbell interrupt */
+	if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U)
+		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+
+	/* Fill the command descriptor index and get the same */
+	status = mailbox_fill_cmd_desc(client_id, async_v1_job_id, resp);
+	if (status != MBOX_RET_OK) {
+		return status;
+	}
+
+	cmd_desc = mailbox_get_cmd_desc(client_id, async_v1_job_id);
+
+	/* Get the response from SDM, just go through one cycle */
+	status = mailbox_response_handler_fsm();
+	if (status != MBOX_RET_OK) {
+		mailbox_free_cmd_desc(cmd_desc);
+		*resp_len = 0U;
+		return status;
+	}
+
+	/* Check the local response queue with the given client ID */
+	resp_desc = mailbox_get_resp_desc_cid(client_id, &di);
+	if (resp_desc == NULL) {
+		mailbox_free_cmd_desc(cmd_desc);
+		*resp_len = 0U;
+		return MBOX_NO_RESPONSE;
+	}
+
+	/* Update the received mailbox response length, job ID and header */
+	*job_id = resp_desc->job_id;
+	*resp_len = resp_desc->rcvd_resp_len;
+	if (header != NULL) {
+		*header = resp_desc->header;
+	}
+
+	/* Check the mailbox response error code */
+	if (MBOX_RESP_ERR(resp_desc->header) > 0U) {
+		INFO("MBOX: Error in async response: %x\n", resp_desc->header);
+		status = -MBOX_RESP_ERR(resp_desc->header);
+	}
+
+	/* Free up the response and command descriptors */
+	mailbox_free_resp_desc(di);
+	mailbox_free_cmd_desc(cmd_desc);
+
+	return status;
+}
+
+int mailbox_send_cmd_async_v3(uint8_t client_id, uint8_t job_id, uint32_t cmd,
+			      uint32_t *args, uint32_t args_len, uint8_t cmd_flag,
+			      sdm_command_callback cb, uint32_t *cb_args,
+			      uint32_t cb_args_len)
+{
+	int status = 0;
+	sdm_command_t *cmd_desc = NULL;
+
+	VERBOSE("MBOX: cid: %d, jid: %d, cmd: %d, cmd_flag: %d\n",
+		client_id, job_id, cmd, cmd_flag);
+
+	if (IS_CMD_SET(cmd_flag, URGENT)) {
+		mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd);
+		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
+	} else {
+		/* Get a free command descriptor */
+		cmd_desc = mailbox_get_free_cmd_desc();
+		if (cmd_desc == NULL) {
+			return MBOX_BUFFER_FULL;
+		}
+
+		/* Record all the given values for the command. */
+		cmd_desc->client_id = client_id;
+		cmd_desc->job_id = job_id;
+		cmd_desc->cb = cb;
+		cmd_desc->cb_args = cb_args;
+		cmd_desc->cb_args_len = cb_args_len;
+
+		/* Push the command to mailbox FIFO */
+		status = fill_mailbox_circular_buffer(
+					MBOX_FRAME_CMD_HEADER(client_id, job_id,
+					args_len, IS_CMD_SET(cmd_flag, INDIRECT), cmd),
+					args,
+					args_len);
+
+		if (status != MBOX_RET_OK) {
+			INFO("MBOX: Failed to push the command to mailbox FIFO\n");
+			/* Free the command descriptor. */
+			mailbox_free_cmd_desc(cmd_desc);
+		}
+	}
+
+	INFO("MBOX: %s: status: %d\n", __func__, status);
+
+	return status;
+}
+
+static int mailbox_poll_response_v3(uint8_t client_id, uint8_t job_id,
+				    uint32_t *resp, unsigned int *resp_len,
+				    uint32_t urgent)
+{
+	unsigned int timeout = 40U;
+	unsigned int sdm_loop = 255U;
+	bool is_cmd_desc_fill = false;
+	uint8_t di = 0U;
+	sdm_response_t *resp_desc = NULL;
+	sdm_command_t *cmd_desc = NULL;
+
+	while (sdm_loop != 0U) {
+		do {
+			if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)
+				== 1U) {
+				break;
+			}
+			mdelay(10U);
+		} while (--timeout != 0U);
+
+		if (timeout == 0U) {
+			INFO("%s: Timed out waiting for SDM intr\n", __func__);
+			break;
+		}
+
+		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+
+		if ((urgent & 1U) != 0U) {
+			mdelay(5U);
+			if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
+				MBOX_STATUS_UA_MASK) ^
+				(urgent & MBOX_STATUS_UA_MASK)) {
+				mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
+				return MBOX_RET_OK;
+			}
+
+			mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
+			ERROR("MBOX: Mailbox did not get UA");
+			return MBOX_RET_ERROR;
+		}
+
+		/* Fill the command descriptor index and get the same. */
+		if (!is_cmd_desc_fill) {
+			if (mailbox_fill_cmd_desc(client_id, job_id, resp) !=
+				MBOX_RET_OK) {
+				return MBOX_BUFFER_FULL;
+			}
+
+			cmd_desc = mailbox_get_cmd_desc(client_id, job_id);
+			is_cmd_desc_fill = true;
+		}
+
+		/* Since it is sync call, will try to read till it time out */
+		(void)mailbox_response_handler_fsm();
+
+		/* Check the response queue with the given client ID and job ID */
+		resp_desc = mailbox_get_resp_desc(client_id, job_id, &di);
+		if (resp_desc != NULL) {
+			VERBOSE("%s: Resp received for cid %d, jid %d\n",
+				__func__, resp_desc->client_id, resp_desc->job_id);
+
+			uint16_t header = resp_desc->header;
+
+			/* Update the return response length */
+			if (resp_len != NULL) {
+				*resp_len = resp_desc->rcvd_resp_len;
+			}
+
+			/* Free the response and command descriptor */
+			mailbox_free_resp_desc(di);
+			mailbox_free_cmd_desc(cmd_desc);
+
+			if (MBOX_RESP_ERR(header) > 0U) {
+				INFO("%s: SDM err code: 0x%x\n", __func__,
+					MBOX_RESP_ERR(header));
+				return -MBOX_RESP_ERR(header);
+			}
+
+			VERBOSE("%s: MBOX_RET_OK\n", __func__);
+			return MBOX_RET_OK;
+		}
+		sdm_loop--;
+	}
+
+	INFO("%s: Timed out waiting for SDM\n", __func__);
+	return MBOX_TIMEOUT;
+}
+
+/* SDM response parser handler state machine. */
+static void mailbox_response_parser(void)
+{
+	int di = -1;		/* Descriptor index */
+	uint32_t rin;
+	uint32_t rout;
+
+	switch (mbox_svc.next_resp_state) {
+	case SRS_WAIT_FOR_RESP:
+	{
+		mbox_svc.resp_state = SRS_WAIT_FOR_RESP;
+
+		rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+		rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+		if (rin != rout) {
+			mbox_svc.next_resp_state = SRS_WAIT_FOR_HEADER;
+		}
+
+		break;
+	}
+
+	case SRS_WAIT_FOR_HEADER:
+	{
+		mbox_svc.resp_state = SRS_WAIT_FOR_HEADER;
+		uint32_t resp_hdr;
+		uint8_t trans_id = 0U;
+
+		rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+		rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+		if (rin != rout) {
+			/* Read the header and dequeue from the queue. */
+			resp_hdr = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
+			rout %= MBOX_RESP_BUFFER_SIZE;
+			mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+
+			/* Allocate a new response descriptor */
+			di = mailbox_get_free_resp_desc();
+			if (di != -1) {
+				mbox_svc.curr_di = di;
+				mbox_svc.resp_queue[di].header = resp_hdr;
+				mbox_svc.resp_queue[di].client_id = MBOX_RESP_CLIENT_ID(resp_hdr);
+				mbox_svc.resp_queue[di].job_id = MBOX_RESP_JOB_ID(resp_hdr);
+				mbox_svc.resp_queue[di].resp_len = MBOX_RESP_LEN(resp_hdr);
+				mbox_svc.resp_queue[di].flags |= (FLAG_SDM_RESPONSE_IS_USED |
+								  FLAG_SDM_RESPONSE_IS_IN_PROGRESS);
+				mbox_svc.resp_queue[di].err_code = MBOX_RESP_ERR(resp_hdr);
+				trans_id = MBOX_RESP_TRANSACTION_ID(resp_hdr);
+
+				VERBOSE("MBOX: Resp Hdr: cid %d, jid %d, len %d, err_code 0x%x\n",
+					mbox_svc.resp_queue[di].client_id,
+					mbox_svc.resp_queue[di].job_id,
+					mbox_svc.resp_queue[di].resp_len,
+					mbox_svc.resp_queue[di].err_code);
+
+				/* Check if the response is an argument response */
+				if (mbox_svc.resp_queue[di].resp_len > 0) {
+					mbox_svc.next_resp_state = SRS_WAIT_FOR_ARGUMENTS;
+				} else {
+					VERBOSE("MBOX: Received complete response with no args\n");
+					/* Non argument response, done */
+					mbox_svc.resp_queue[mbox_svc.curr_di].flags |=
+									FLAG_SDM_RESPONSE_IS_VALID;
+
+					/* Go back to waiting for new response */
+					mbox_svc.next_resp_state = SRS_WAIT_FOR_RESP;
+					mbox_svc.curr_di = -1;
+
+					/* Mark the transaction ID as received */
+					spin_lock(&mbox_db_lock);
+					mbox_svc.received_bitmap[trans_id / MBOX_TID_BITMAP_SIZE] |=
+							(1ULL << (trans_id % MBOX_TID_BITMAP_SIZE));
+					spin_unlock(&mbox_db_lock);
+				}
+			} else {
+				mbox_svc.next_resp_state = SRS_SYNC_ERROR;
+			}
+		}
+		break;
+	}
+
+	case SRS_WAIT_FOR_ARGUMENTS:
+	{
+		mbox_svc.resp_state = SRS_WAIT_FOR_ARGUMENTS;
+		uint16_t mbox_resp_len = mbox_svc.resp_queue[mbox_svc.curr_di].resp_len;
+		uint32_t *read_buff = NULL;
+		uint16_t read_len = 0U;
+		uint16_t read_max_len = 0U;
+		uint32_t timeout = 0U;
+
+		/* Determine where to copy the buffer. */
+		sdm_command_t *cmd_desc = mailbox_get_cmd_desc(
+						mbox_svc.resp_queue[mbox_svc.curr_di].client_id,
+						mbox_svc.resp_queue[mbox_svc.curr_di].job_id);
+		if (cmd_desc != NULL && cmd_desc->cb_args != NULL) {
+			read_buff = cmd_desc->cb_args;
+			read_max_len = mbox_resp_len;
+		} else {
+			read_buff = (uint32_t *)mbox_svc.resp_queue[mbox_svc.curr_di].resp_data;
+			read_max_len = MBOX_SVC_MAX_RESP_DATA_SIZE;
+		}
+
+		rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+		rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+
+		while ((read_len < mbox_resp_len) && (rin != rout) && (read_len < read_max_len)) {
+			timeout = 10000U;
+
+			/* Copy the response data to the buffer */
+			read_buff[read_len++] = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
+
+			VERBOSE("MBOX: 0x%x\n", read_buff[read_len - 1]);
+
+			/* Update the read out buffer index */
+			rout %= MBOX_RESP_BUFFER_SIZE;
+			mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+
+			/*
+			 * The response buffer is of 16 words size, this loop checks
+			 * if the response buffer is empty and if empty trigger an
+			 * interrupt to SDM and wait for the response buffer to fill
+			 */
+			do {
+				if (read_len == mbox_resp_len)
+					break;
+
+				rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+				if (rout == rin) {
+					mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
+					udelay(100);
+				} else {
+					break;
+				}
+				timeout--;
+			} while ((read_len < mbox_resp_len) && (timeout != 0U));
+
+			if (timeout == 0U) {
+				INFO("MBOX: Timeout waiting for response data\n");
+				mbox_svc.next_resp_state = SRS_SYNC_ERROR;
+				break;
+			}
+		}
+
+		/* Check if we have received all the arguments */
+		mbox_svc.resp_queue[mbox_svc.curr_di].rcvd_resp_len = read_len;
+		if (mbox_resp_len == read_len) {
+			uint8_t transaction_id =
+					((mbox_svc.resp_queue[mbox_svc.curr_di].client_id << 4) |
+					 (mbox_svc.resp_queue[mbox_svc.curr_di].job_id));
+			VERBOSE("MBOX: Received all the response data len %d, transaction_id %d\n",
+				read_len, transaction_id);
+
+			spin_lock(&mbox_db_lock);
+			mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] |=
+						(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+			spin_unlock(&mbox_db_lock);
+
+			mbox_svc.resp_queue[mbox_svc.curr_di].flags |= FLAG_SDM_RESPONSE_IS_VALID;
+			mbox_svc.next_resp_state = SRS_WAIT_FOR_RESP;
+			mbox_svc.curr_di = -1;
+		} else {
+			mbox_svc.next_resp_state = SRS_SYNC_ERROR;
+			VERBOSE("MBOX: Received partial response data len %d, max len %d\n",
+				read_len, read_max_len);
+		}
+		break;
+	}
+
+	case SRS_SYNC_ERROR:
+	{
+		mbox_svc.resp_state = SRS_SYNC_ERROR;
+		INFO("MBOX: Error in response handling\n");
+		break;
+	}
+
+	default:
+		break;
+	} /* switch */
+}
+
+static int mailbox_response_handler_fsm(void)
+{
+	int status = MBOX_RET_OK;
+
+	spin_lock(&mbox_read_lock);
+	/* Mailbox peripheral response parser */
+	do {
+		/* Iterate till the state machine transition ends */
+		mailbox_response_parser();
+
+		/* Note down if there is any error in the response parsing */
+		if (mbox_svc.next_resp_state == SRS_SYNC_ERROR) {
+			status = MBOX_RET_ERROR;
+		}
+
+	} while (mbox_svc.resp_state != mbox_svc.next_resp_state);
+	spin_unlock(&mbox_read_lock);
+
+	return status;
+}
+
+int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
+				     uint64_t *bitmap)
+{
+	uint32_t i = 0U;
+	int status = MBOX_RET_OK;
+
+	/* Clear the SDM doorbell interrupt immediately */
+	if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U) {
+		mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+	}
+
+	/* Check mailbox FIFO for any pending responses available to read. */
+	status = mailbox_response_handler_fsm();
+	if (status != MBOX_RET_OK) {
+		return status;
+	}
+
+	/*
+	 * Once we read the complete mailbox FIFO, let's mark up the bitmap for
+	 * available responses with respect to each transcation IDs.
+	 */
+	status = MBOX_NO_RESPONSE;
+	spin_lock(&mbox_db_lock);
+	for (i = 0; i < MBOX_MAX_TIDS_BITMAP; i++) {
+		bitmap[i] = mbox_svc.interrupt_bitmap[i] ^ mbox_svc.received_bitmap[i];
+		if (bitmap[i] != 0 && status == MBOX_NO_RESPONSE) {
+			status = MBOX_RET_OK;
+		}
+
+		mbox_svc.interrupt_bitmap[i] = mbox_svc.received_bitmap[i];
+	}
+	spin_unlock(&mbox_db_lock);
+
+	return status;
+}
+
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id,
+			     uint64_t *ret_args, uint32_t *ret_args_len)
+{
+	sdm_command_t *cmd_desc = NULL;
+	sdm_response_t *resp_desc = NULL;
+	uint8_t di = 0U;
+	int status = MBOX_RET_OK;
+
+	/*
+	 * Let's first check the local response queue with the given
+	 * client ID and job ID
+	 */
+	resp_desc = mailbox_get_resp_desc(client_id, job_id, &di);
+	if (resp_desc == NULL) {
+		/* Not available in the local queue, let's read mailbox FIFO */
+		status = mailbox_response_handler_fsm();
+		if (status != MBOX_RET_OK) {
+			return status;
+		}
+
+		resp_desc = mailbox_get_resp_desc(client_id, job_id, &di);
+	}
+	cmd_desc = mailbox_get_cmd_desc(client_id, job_id);
+
+	if (cmd_desc != NULL && resp_desc != NULL) {
+		VERBOSE("MBOX: Resp found for cid %d, jid %d\n", client_id, job_id);
+
+		/* Command callback function */
+		*ret_args_len = cmd_desc->cb(resp_desc, cmd_desc, ret_args);
+
+		/* Free the command and response descriptors. */
+		mailbox_free_cmd_desc(cmd_desc);
+		mailbox_free_resp_desc(di);
+
+		return MBOX_RET_OK;
+	}
+
+	INFO("MBOX: No resp found for cid: %d, jid: %d\n", client_id, job_id);
+
+	return MBOX_NO_RESPONSE;
+}
+
+void mailbox_init_v3(void)
+{
+	uint32_t count;
+
+	memset((void *)&mbox_svc, 0, sizeof(mbox_svc));
+
+	mbox_svc.next_resp_state = SRS_WAIT_FOR_RESP;
+	mbox_svc.resp_state = SRS_WAIT_FOR_RESP;
+
+	/* Free all entries from the response queue. */
+	for (count = 0; count < MBOX_SVC_RESP_QUEUE_SIZE; count++) {
+		mbox_svc.resp_queue[count].flags = 0;
+	}
+
+	/* Free all entries from the command queue. */
+	for (count = 0; count < MBOX_SVC_CMD_QUEUE_SIZE; count++) {
+		mbox_svc.cmd_queue[count].flags = 0;
+	}
+
+	mbox_svc.curr_di = -1;
+}
+#endif /* #if SIP_SVC_V3 */

diff --git a/plat/intel/soc/common/socfpga_ros.c b/plat/intel/soc/common/socfpga_ros.c
index ea37384..62e689c 100644
--- a/plat/intel/soc/common/socfpga_ros.c
+++ b/plat/intel/soc/common/socfpga_ros.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2024, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,6 +21,8 @@
 
 #include <socfpga_ros.h>
 
+#define WORD_SIZE	(sizeof(uint32_t))
+
 static void swap_bits(char *const data, uint32_t len)
 {
 	uint32_t x, y;
@@ -99,7 +102,8 @@
 		return ROS_IMAGE_PARTNUM_OVFL;
 	}
 
-	memcpy_s(&spt_data, SPT_SIZE, spt_ptr, SPT_SIZE);
+	memcpy_s(&spt_data, (sizeof(spt_table_t) / WORD_SIZE),
+		 spt_ptr, (SPT_SIZE / WORD_SIZE));
 	spt_data.checksum = 0U;
 	swap_bits((char *)&spt_data, SPT_SIZE);
 
@@ -153,6 +157,7 @@
 	}
 
 	uint32_t ret, img_index;
+	size_t len;
 	char ssbl_name[SPT_PARTITION_NAME_LENGTH];
 	static spt_table_t spt;
 
@@ -168,11 +173,12 @@
 
 	if (strncmp(spt.partition[img_index].name, FACTORY_IMAGE,
 		SPT_PARTITION_NAME_LENGTH) == 0U) {
-		strlcpy(ssbl_name, FACTORY_SSBL, SPT_PARTITION_NAME_LENGTH);
+		strcpy_secure(ssbl_name, SPT_PARTITION_NAME_LENGTH, FACTORY_SSBL);
 	} else {
-		strlcpy(ssbl_name, spt.partition[img_index].name,
-			SPT_PARTITION_NAME_LENGTH);
-		strlcat(ssbl_name, SSBL_SUFFIX, SPT_PARTITION_NAME_LENGTH);
+		strcpy_secure(ssbl_name, SPT_PARTITION_NAME_LENGTH, SSBL_PREFIX);
+		len = strnlen_secure(ssbl_name, SPT_PARTITION_NAME_LENGTH);
+		strcpy_secure(ssbl_name + len, SPT_PARTITION_NAME_LENGTH - len,
+			 spt.partition[img_index].name);
 	}
 
 	for (uint32_t index = 0U; index < spt.partitions; index++) {

diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f7b41fa..ff19e23 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c

@@ -9,6 +9,7 @@
 #include <assert.h>
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 #include <tools_share/uuid.h>
 
@@ -799,6 +800,1124 @@
 	}
 	return INTEL_SIP_SMC_STATUS_OK;
 }
+
+static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command)
+{
+	volatile uint64_t atf_ddr_buffer;
+	volatile uint64_t val;
+
+	mmio_write_32(IOSSM_CMD_PARAM, *syndrome);
+	mmio_write_32(IOSSM_CMD_TRIG_OP, command);
+	udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS);
+	atf_ddr_buffer = 0xCAFEBABEFEEDFACE;	/* Write data */
+	memcpy_s((void *)&val, sizeof(val),
+		 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer));
+
+	/* Clear response_ready BIT0 of status_register before sending next command. */
+	mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY);
+}
+#endif
+
+#if SIP_SVC_V3
+uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	/* Returns 3 SMC arguments for SMC_RET3 */
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+
+	return ret_args_len;
+}
+
+uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	/* Returns 3 SMC arguments for SMC_RET3 */
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->resp_data[0];
+
+	return ret_args_len;
+}
+
+uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n",
+		__func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+	return ret_args_len;
+}
+
+uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n",
+		__func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]);
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	ret_args[ret_args_len++] = resp->resp_data[0];
+	ret_args[ret_args_len++] = resp->resp_data[1];
+
+	return ret_args_len;
+}
+
+uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	uint32_t retry_counter = ~0U;
+	uint32_t failure_source = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	/* Get the failure source and current image retry counter value from the response. */
+	failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK;
+	retry_counter = resp->resp_data[8];
+
+	if ((retry_counter != ~0U) && (failure_source == 0U))
+		resp->resp_data[5] |= RSU_VERSION_ACMF;
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	/* Current CMF */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]);
+	/* Last Failing CMF Address */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]);
+	/* Config State */
+	ret_args[ret_args_len++] = resp->resp_data[4];
+	/* Version */
+	ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]);
+	/* Failure Source */
+	ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16);
+	/* Error location */
+	ret_args[ret_args_len++] = resp->resp_data[6];
+	/* Error details */
+	ret_args[ret_args_len++] = resp->resp_data[7];
+	/* Current image retry counter */
+	ret_args[ret_args_len++] = resp->resp_data[8];
+
+	return ret_args_len;
+}
+
+uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	/* Sub Partition Table (SPT) 0 address */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]);
+	/* Sub Partition Table (SPT) 1 address */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]);
+
+	return ret_args_len;
+}
+
+static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len)
+{
+
+	switch (ret_args_len) {
+	case SMC_RET_ARGS_ONE:
+		VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]);
+		SMC_RET1(handle, ret_args[0]);
+		break;
+
+	case SMC_RET_ARGS_TWO:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]);
+		SMC_RET2(handle, ret_args[0], ret_args[1]);
+		break;
+
+	case SMC_RET_ARGS_THREE:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n",
+			__func__, ret_args[0],	ret_args[1], ret_args[2]);
+		SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
+		break;
+
+	case SMC_RET_ARGS_FOUR:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
+		SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
+		break;
+
+	case SMC_RET_ARGS_FIVE:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
+		SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
+		break;
+
+	case SMC_RET_ARGS_SIX:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5]);
+		SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5]);
+		break;
+
+	case SMC_RET_ARGS_SEVEN:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+			"x6 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5], ret_args[6]);
+		SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5], ret_args[6]);
+		break;
+
+	case SMC_RET_ARGS_EIGHT:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+			"x6 0x%lx, x7 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5], ret_args[6], ret_args[7]);
+		SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5], ret_args[6], ret_args[7]);
+		break;
+
+	case SMC_RET_ARGS_NINE:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+			"x6 0x%lx, x7 0x%lx, x8 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5], ret_args[6], ret_args[7], ret_args[8]);
+		SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+			 0, 0, 0, 0, 0, 0, 0, 0, 0);
+		break;
+
+	case SMC_RET_ARGS_TEN:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+			"x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3],
+			ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+			ret_args[9], ret_args[10]);
+		SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			  ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9],
+			  0, 0, 0, 0, 0, 0, 0, 0);
+		break;
+
+	default:
+		VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ",
+			__func__, ret_args_len);
+		SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
+		break;
+	}
+}
+
+static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd)
+{
+	/* Check if the command is allowed to be executed in generic mbox format */
+	bool is_cmd_allowed = false;
+
+	switch (cmd) {
+	case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+	case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION:
+		/* These commands are not supported in the generic mailbox format. */
+		break;
+
+	default:
+		is_cmd_allowed = true;
+		break;
+	} /* switch */
+
+	return is_cmd_allowed;
+}
+
+/*
+ * This function is responsible for handling all SiP SVC V3 calls from the
+ * non-secure world.
+ */
+static uintptr_t sip_smc_handler_v3(uint32_t smc_fid,
+				    u_register_t x1,
+				    u_register_t x2,
+				    u_register_t x3,
+				    u_register_t x4,
+				    void *cookie,
+				    void *handle,
+				    u_register_t flags)
+{
+	int status = 0;
+	uint32_t mbox_error = 0U;
+	u_register_t x5, x6, x7, x8, x9, x10, x11;
+
+	/* Get all the SMC call arguments */
+	x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+	x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+	x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
+	x8 = SMC_GET_GP(handle, CTX_GPREG_X8);
+	x9 = SMC_GET_GP(handle, CTX_GPREG_X9);
+	x10 = SMC_GET_GP(handle, CTX_GPREG_X10);
+	x11 = SMC_GET_GP(handle, CTX_GPREG_X11);
+
+	INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n",
+		smc_fid, x1, x2, x3, x4, x5);
+	INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n",
+		x6, x7, x8, x9, x10, x11);
+
+	switch (smc_fid) {
+	case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
+	{
+		uint64_t ret_args[16] = {0};
+		uint32_t ret_args_len = 0;
+
+		status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
+						  GET_JOB_ID(x1),
+						  ret_args,
+						  &ret_args_len);
+		/* Always reserve [0] index for command status. */
+		ret_args[0] = status;
+
+		/* Return SMC call based on the number of return arguments */
+		return smc_ret(handle, ret_args, ret_args_len);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR:
+	{
+		/* TBD: Here now we don't need these CID and JID?? */
+		uint8_t client_id = 0U;
+		uint8_t job_id = 0U;
+		uint64_t trans_id_bitmap[4] = {0U};
+
+		status = mailbox_response_poll_on_intr_v3(&client_id,
+							  &job_id,
+							  trans_id_bitmap);
+
+		SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1],
+			 trans_id_bitmap[2], trans_id_bitmap[3]);
+		break;
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_GET_DEVICEID,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)x2,
+						   2);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_GET_IDCODE:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_GET_IDCODE,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret3,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_OPEN,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0U);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_CLOSE,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0U);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS:
+	{
+		uint32_t cmd_data = 0U;
+		uint32_t chip_sel = (uint32_t)x2;
+		uint32_t comb_addr_mode = (uint32_t)x3;
+		uint32_t ext_dec_mode = (uint32_t)x4;
+
+		cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) |
+			   (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) |
+			   (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET);
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_SET_CS,
+						   &cmd_data,
+						   1U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0U);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE:
+	{
+		uint32_t qspi_addr = (uint32_t)x2;
+		uint32_t qspi_nwords = (uint32_t)x3;
+
+		/* QSPI address offset to start erase, must be 4K aligned */
+		if (MBOX_IS_4K_ALIGNED(qspi_addr)) {
+			ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		/* Number of words to erase, multiples of 0x400 or 4K */
+		if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) {
+			ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		uint32_t cmd_data[2] = {qspi_addr, qspi_nwords};
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_ERASE,
+						   cmd_data,
+						   sizeof(cmd_data) / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0U);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE:
+	{
+		uint32_t *qspi_payload = (uint32_t *)x2;
+		uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE);
+		uint32_t qspi_addr = qspi_payload[0];
+		uint32_t qspi_nwords = qspi_payload[1];
+
+		if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) {
+			ERROR("MBOX: 0x%x: Given address is not WORD aligned\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) {
+			ERROR("MBOX: 0x%x: Number of words exceeds max limit\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_WRITE,
+						   qspi_payload,
+						   qspi_total_nwords,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0U);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_READ:
+	{
+		uint32_t qspi_addr = (uint32_t)x2;
+		uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE);
+
+		if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) {
+			ERROR("MBOX: 0x%x: Number of words exceeds max limit\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		uint32_t cmd_data[2] = {qspi_addr, qspi_nwords};
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_READ,
+						   cmd_data,
+						   sizeof(cmd_data) / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)x3,
+						   2);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO:
+	{
+		uint32_t *dst_addr = (uint32_t *)x2;
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_QSPI_GET_DEV_INFO,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)dst_addr,
+						   2);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT:
+	case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP:
+	{
+		uint32_t channel = (uint32_t)x2;
+		uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ?
+					MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP);
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   mbox_cmd,
+						   &channel,
+						   1U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret3,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_GET_SUBPARTITION_TABLE,
+						   NULL,
+						   0,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_rsu_spt,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_RSU_STATUS,
+						   NULL,
+						   0,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_rsu_status,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY:
+	{
+		uint32_t notify_code = (uint32_t)x2;
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_HPS_STAGE_NOTIFY,
+						   &notify_code,
+						   1U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD:
+	{
+		/* Filter the required commands here. */
+		if (!is_gen_mbox_cmd_allowed(smc_fid)) {
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		/* Collect all the args passed in, and send the mailbox command. */
+		uint32_t mbox_cmd = (uint32_t)x2;
+		uint32_t *cmd_payload_addr = NULL;
+		uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE;
+		uint32_t *resp_payload_addr = NULL;
+		uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE;
+
+		if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) ||
+		    (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) {
+			ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		/* Make sure we have valid command payload length and buffer */
+		if (cmd_payload_len != 0U) {
+			cmd_payload_addr = (uint32_t *)x3;
+			if (cmd_payload_addr == NULL) {
+				ERROR("MBOX: 0x%x: Command payload address is NULL\n",
+					smc_fid);
+				status = INTEL_SIP_SMC_STATUS_REJECTED;
+				SMC_RET1(handle, status);
+			}
+		}
+
+		/* Make sure we have valid response payload length and buffer */
+		if (resp_payload_len != 0U) {
+			resp_payload_addr = (uint32_t *)x5;
+			if (resp_payload_addr == NULL) {
+				ERROR("MBOX: 0x%x: Response payload address is NULL\n",
+					smc_fid);
+				status = INTEL_SIP_SMC_STATUS_REJECTED;
+				SMC_RET1(handle, status);
+			}
+		}
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   mbox_cmd,
+						   (uint32_t *)cmd_payload_addr,
+						   cmd_payload_len,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)resp_payload_addr,
+						   resp_payload_len);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+	{
+		uint32_t session_id = (uint32_t)x2;
+		uint32_t context_id = (uint32_t)x3;
+		uint64_t ret_random_addr = (uint64_t)x4;
+		uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
+		uint32_t crypto_header = 0U;
+
+		if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) ||
+		    (random_len == 0U) ||
+		    (!is_size_4_bytes_aligned(random_len))) {
+			ERROR("MBOX: 0x%x is rejected\n", smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) <<
+				  FCS_CS_FIELD_FLAG_OFFSET);
+		fcs_rng_payload payload = {session_id, context_id,
+					   crypto_header, random_len};
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_RANDOM_GEN,
+						   (uint32_t *)&payload,
+						   sizeof(payload) / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)ret_random_addr,
+						   2);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_GET_PROVISION,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)x2,
+						   2);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH:
+	{
+		status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3,
+					x4, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_GET_CHIPID,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_get_chipid_cb,
+						   NULL,
+						   0);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT:
+	{
+		status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3,
+					(uint32_t *) &x4, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD:
+	{
+		status = intel_fcs_create_cert_on_reload(smc_fid, x1,
+					x2, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+	{
+		if (x4 == FCS_MODE_ENCRYPT) {
+			status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3,
+					x5, x6, x7, (uint32_t *) &x8,
+					&mbox_error, x10, x11);
+		} else if (x4 == FCS_MODE_DECRYPT) {
+			status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3,
+					x5, x6, x7, (uint32_t *) &x8,
+					&mbox_error, x9, x10, x11);
+		} else {
+			ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+		}
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE:
+	{
+		status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_OPEN_CS_SESSION,
+						   NULL,
+						   0U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret3,
+						   NULL,
+						   0);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+	{
+		uint32_t session_id = (uint32_t)x2;
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_CLOSE_CS_SESSION,
+						   &session_id,
+						   1U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+	{
+		uint64_t key_addr = x2;
+		uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
+
+		if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) ||
+		    (!is_address_in_ddr_range(key_addr, key_len_words * 4))) {
+			ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_IMPORT_CS_KEY,
+						   (uint32_t *)key_addr,
+						   key_len_words,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret3,
+						   NULL,
+						   0);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+	{
+		uint64_t key_addr = x2;
+		uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
+
+		if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) {
+			ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_CREATE_CS_KEY,
+						   (uint32_t *)key_addr,
+						   key_len_words,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret3,
+						   NULL,
+						   0);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+	{
+		uint32_t session_id = (uint32_t)x2;
+		uint32_t key_uid = (uint32_t)x3;
+		uint64_t ret_key_addr = (uint64_t)x4;
+		uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
+
+		if (!is_address_in_ddr_range(ret_key_addr, key_len)) {
+			ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
+					      RESERVED_AS_ZERO, key_uid};
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_EXPORT_CS_KEY,
+						   (uint32_t *)&payload,
+						   sizeof(payload) / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)ret_key_addr,
+						   2);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+	{
+		uint32_t session_id = (uint32_t)x2;
+		uint32_t key_uid = (uint32_t)x3;
+
+		fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
+					      RESERVED_AS_ZERO, key_uid};
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_REMOVE_CS_KEY,
+						   (uint32_t *)&payload,
+						   sizeof(payload) / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret3,
+						   NULL,
+						   0);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+	{
+		uint32_t session_id = (uint32_t)x2;
+		uint32_t key_uid = (uint32_t)x3;
+		uint64_t ret_key_addr = (uint64_t)x4;
+		uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
+
+		if (!is_address_in_ddr_range(ret_key_addr, key_len)) {
+			ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
+					      RESERVED_AS_ZERO, key_uid};
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_FCS_GET_CS_KEY_INFO,
+						   (uint32_t *)&payload,
+						   sizeof(payload) / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)ret_key_addr,
+						   2);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT:
+	{
+		status = intel_fcs_aes_crypt_init(x2, x3, x4, x5,
+					x6, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE:
+	{
+		uint32_t job_id = 0U;
+		bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ?
+				true : false;
+
+		status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2,
+					x3, x4, x5, x6, x7, x8, is_final,
+					&job_id, x9, x10);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+	{
+		status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+	{
+		bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ?
+				true : false;
+
+		status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2,
+					x3, x4, x5, x6, (uint32_t *) &x7,
+					is_final, &mbox_error, x8);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+	{
+		status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+	{
+		bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ?
+				true : false;
+
+		status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2,
+					x3, x4, x5, x6, (uint32_t *) &x7, x8,
+					is_final, &mbox_error, x9);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+	{
+		status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+	{
+		status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3,
+					x4, x5, x6, (uint32_t *) &x7,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+	{
+		status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+	{
+		bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE)
+				? true : false;
+
+		status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
+					x1, x2, x3, x4, x5, x6, (uint32_t *) &x7,
+					is_final, &mbox_error, x8);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+	{
+		status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5,
+					x6, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+	{
+		status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1,
+					x2, x3, x4, x5, x6, (uint32_t *) &x7,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+	{
+		status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4,
+					x5, x6, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+	{
+		bool is_final = (smc_fid ==
+				ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ?
+				true : false;
+
+		status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
+					smc_fid, x1, x2, x3, x4, x5, x6,
+					(uint32_t *) &x7, x8, is_final,
+					&mbox_error, x9);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+	{
+		status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+	{
+		status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3,
+					x4, (uint32_t *) &x5, &mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+	{
+		status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+	{
+		uint32_t dest_size = (uint32_t)x7;
+
+		NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n",
+			__func__, __LINE__, (uint32_t)x7, dest_size);
+
+		status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3,
+					x4, x5, x6, (uint32_t *) &dest_size,
+					&mbox_error);
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_MCTP_MSG:
+	{
+		uint32_t *src_addr = (uint32_t *)x2;
+		uint32_t src_size = (uint32_t)x3;
+		uint32_t *dst_addr = (uint32_t *)x4;
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_CMD_MCTP_MSG,
+						   src_addr,
+						   src_size / MBOX_WORD_BYTE,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   dst_addr,
+						   2);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+	{
+		status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6,
+					x7);
+		SMC_RET1(handle, status);
+	}
+
+	default:
+		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
+					   cookie, handle, flags);
+	} /* switch (smc_fid) */
+}
 #endif
 
 /*
@@ -995,11 +2114,11 @@
 		x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
 
 		if (x3 == FCS_MODE_DECRYPT) {
-			status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
-					(uint32_t *) &x7, &mbox_error);
+			status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
+					(uint32_t *) &x7, &mbox_error, 0, 0, 0);
 		} else if (x3 == FCS_MODE_ENCRYPT) {
-			status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
-					(uint32_t *) &x7, &mbox_error);
+			status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
+					(uint32_t *) &x7, &mbox_error, 0, 0);
 		} else {
 			status = INTEL_SIP_SMC_STATUS_REJECTED;
 		}
@@ -1017,7 +2136,7 @@
 		SMC_RET1(handle, status);
 
 	case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
-		status = intel_fcs_send_cert(x1, x2, &send_id);
+		status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id);
 		SMC_RET1(handle, status);
 
 	case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
@@ -1025,7 +2144,7 @@
 		SMC_RET1(handle, status);
 
 	case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
-		status = intel_fcs_cntr_set_preauth(x1, x2, x3,
+		status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3,
 							&mbox_error);
 		SMC_RET2(handle, status, mbox_error);
 
@@ -1060,12 +2179,12 @@
 		SMC_RET4(handle, status, mbox_error, x3, x4);
 
 	case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
-		status = intel_fcs_get_attestation_cert(x1, x2,
+		status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2,
 					(uint32_t *) &x3, &mbox_error);
 		SMC_RET4(handle, status, mbox_error, x2, x3);
 
 	case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
-		status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
+		status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error);
 		SMC_RET2(handle, status, mbox_error);
 
 	case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
@@ -1104,17 +2223,17 @@
 	case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
-					x4, x5, (uint32_t *) &x6, false,
-					&mbox_error);
+		status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, (uint32_t *) &x6, false,
+					&mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
-					x4, x5, (uint32_t *) &x6, true,
-					&mbox_error);
+		status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, (uint32_t *) &x6, true,
+					&mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
@@ -1143,18 +2262,18 @@
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
 		x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-		status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
-					x4, x5, (uint32_t *) &x6, x7,
-					false, &mbox_error);
+		status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, (uint32_t *) &x6, x7, false,
+					&mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
 		x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
-		status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
-					x4, x5, (uint32_t *) &x6, x7,
-					true, &mbox_error);
+		status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, (uint32_t *) &x6, x7, true,
+					&mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
@@ -1184,17 +2303,17 @@
 	case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
-					x3, x4, x5, (uint32_t *) &x6, false,
-					&mbox_error);
+		status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
+					0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
+					false, &mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
-					x3, x4, x5, (uint32_t *) &x6, true,
-					&mbox_error);
+		status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
+					0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
+					true, &mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
@@ -1222,8 +2341,9 @@
 	case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
-					 x4, x5, (uint32_t *) &x6, &mbox_error);
+		status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, (uint32_t *) &x6,
+					&mbox_error);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
@@ -1235,8 +2355,9 @@
 	case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
-					 x4, x5, (uint32_t *) &x6, &mbox_error);
+		status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1,
+					x2, x3, x4, x5, (uint32_t *) &x6,
+					&mbox_error);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
@@ -1250,8 +2371,9 @@
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
 		x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
 		status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
-					x1, x2, x3, x4, x5, (uint32_t *) &x6,
-					x7, false, &mbox_error);
+					smc_fid, 0, x1, x2, x3, x4, x5,
+					(uint32_t *) &x6, x7, false,
+					&mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
@@ -1277,8 +2399,9 @@
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
 		x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
 		status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
-					x1, x2, x3, x4, x5, (uint32_t *) &x6,
-					x7, true, &mbox_error);
+					smc_fid, 0, x1, x2, x3, x4, x5,
+					(uint32_t *) &x6, x7, true,
+					&mbox_error, 0);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
@@ -1288,8 +2411,9 @@
 		SMC_RET2(handle, status, mbox_error);
 
 	case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
-		status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
-					(uint32_t *) &x4, &mbox_error);
+		status = intel_fcs_ecdsa_get_pubkey_finalize(
+				INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0,
+				x1, x2, x3, (uint32_t *) &x4, &mbox_error);
 		SMC_RET4(handle, status, mbox_error, x3, x4);
 
 	case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
@@ -1301,7 +2425,7 @@
 	case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
+		status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3,
 					 x4, x5, (uint32_t *) &x6, &mbox_error);
 		SMC_RET4(handle, status, mbox_error, x5, x6);
 
@@ -1314,15 +2438,15 @@
 	case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
-					x5, x6, false, &send_id);
+		status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, x6, 0, false, &send_id, 0, 0);
 		SMC_RET1(handle, status);
 
 	case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
 		x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 		x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
-		status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
-					x5, x6, true, &send_id);
+		status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
+					x3, x4, x5, x6, 0, true, &send_id, 0, 0);
 		SMC_RET1(handle, status);
 
 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
@@ -1358,6 +2482,12 @@
 		SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
 			 VERSION_MINOR, VERSION_PATCH);
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR:
+		intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2);
+		SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
+#endif
+
 	default:
 		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
 			cookie, handle, flags);
@@ -1379,7 +2509,16 @@
 	    cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
 		return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
 			cookie, handle, flags);
-	} else {
+	}
+#if SIP_SVC_V3
+	else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) &&
+		(cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) {
+		uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4,
+						   cookie, handle, flags);
+		return ret;
+	}
+#endif
+	else {
 		return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
 			cookie, handle, flags);
 	}

diff --git a/plat/intel/soc/n5x/bl31_plat_setup.c b/plat/intel/soc/n5x/bl31_plat_setup.c
index cb5ced6..65de036 100644
--- a/plat/intel/soc/n5x/bl31_plat_setup.c
+++ b/plat/intel/soc/n5x/bl31_plat_setup.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -115,6 +116,16 @@
 	mmio_write_64(PLAT_CPU_RELEASE_ADDR,
 		(uint64_t)plat_secondary_cpus_bl31_entry);
 
+#if SIP_SVC_V3
+	/*
+	 * Re-initialize the mailbox to include V3 specific routines.
+	 * In V3, this re-initialize is required because prior to BL31, U-Boot
+	 * SPL has its own mailbox settings and this initialization will
+	 * override to those settings as required by the V3 framework.
+	 */
+	mailbox_init();
+#endif
+
 	mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
 }
 

diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index d0aa972..5c25e43 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c

@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
  * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -122,6 +123,16 @@
 	mmio_write_64(PLAT_CPU_RELEASE_ADDR,
 		(uint64_t)plat_secondary_cpus_bl31_entry);
 
+#if SIP_SVC_V3
+	/*
+	 * Re-initialize the mailbox to include V3 specific routines.
+	 * In V3, this re-initialize is required because prior to BL31, U-Boot
+	 * SPL has its own mailbox settings and this initialization will
+	 * override to those settings as required by the V3 framework.
+	 */
+	mailbox_init();
+#endif
+
 	mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
 }
 

diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index bdad8b5..81b3551 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk

@@ -125,7 +125,7 @@
 				$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c	\
 				$(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c	\
 				$(MARVELL_DRV_BASE)/ddr_phy_access.c	\
-				drivers/rambus/trng_ip_76.c
+				$(MARVELL_DRV_BASE)/trng.c
 
 ifeq (${MSS_SUPPORT}, 1)
 MARVELL_DRV		+=	$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c

diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index c4c5c0e..55d316f 100644
--- a/plat/marvell/armada/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c

@@ -9,7 +9,7 @@
 #include <common/runtime_svc.h>
 #include <drivers/marvell/cache_llc.h>
 #include <drivers/marvell/mochi/ap_setup.h>
-#include <drivers/rambus/trng_ip_76.h>
+#include <drivers/marvell/trng.h>
 #include <lib/smccc.h>
 
 #include <marvell_plat_priv.h>
@@ -164,12 +164,12 @@
 		ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read);
 		SMC_RET2(handle, ret, read);
 	case MV_SIP_RNG_64:
-		if ((x1 % 2 + 1) > sizeof(read)/4) {
-			ERROR("%s: Maximum %ld random bytes per SMC call\n",
-			      __func__, sizeof(read));
+		if (x1 > 1) {
 			SMC_RET1(handle, SMC_UNK);
 		}
-		ret = eip76_rng_get_random((uint8_t *)&read, 4 * (x1 % 2 + 1));
+
+		ret = mv_trng_get_random32((uint32_t *)&read,
+					   ((uint8_t)x1 + 1));
 		SMC_RET2(handle, ret, read);
 	default:
 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);

diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk
index 75cc80a..d2a8fd3 100644
--- a/plat/mediatek/build_helpers/options.mk
+++ b/plat/mediatek/build_helpers/options.mk

@@ -1,27 +1,32 @@
 #
-# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2025, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 # call add_defined_option to evaluate MTK defined value
-$(eval $(call add_defined_option,MTK_SIP_KERNEL_BOOT_ENABLE))
-$(eval $(call add_defined_option,PLAT_EXTRA_RODATA_INCLUDES))
-$(eval $(call add_defined_option,MTK_EXTRA_LINKERFILE))
-$(eval $(call add_defined_option,MTK_BL31_AS_BL2))
-$(eval $(call add_defined_option,MTK_BL33_IS_64BIT))
-$(eval $(call add_defined_option,PLAT_XLAT_TABLES_DYNAMIC))
-$(eval $(call add_defined_option,MTK_ADAPTED))
-$(eval $(call add_defined_option,MTK_PUBEVENT_ENABLE))
-$(eval $(call add_defined_option,MTK_SOC))
-$(eval $(call add_defined_option,UART_CLOCK))
-$(eval $(call add_defined_option,UART_BAUDRATE))
-$(eval $(call add_defined_option,CONFIG_MTK_MCUSYS))
-$(eval $(call add_defined_option,CONFIG_MTK_PM_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_SMP_EN))
-$(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN))
-$(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH))
-$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH))
-$(eval $(call add_defined_option,CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND))
-$(eval $(call add_defined_option,CONFIG_MTK_MTCMOS))
+DEFINED_OPTIONS := \
+	CONFIG_MTK_CPU_PM_ARCH \
+	CONFIG_MTK_CPU_PM_SUPPORT \
+	CONFIG_MTK_CPU_SUSPEND_EN \
+	CONFIG_MTK_DISABLE_CACHE_AS_RAM \
+	CONFIG_MTK_MCUSYS \
+	CONFIG_MTK_MTCMOS \
+	CONFIG_MTK_PM_ARCH \
+	CONFIG_MTK_PM_SUPPORT \
+	CONFIG_MTK_SMMU_SID \
+	CONFIG_MTK_SMP_EN \
+	CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND \
+	MTK_ADAPTED \
+	MTK_BL31_AS_BL2 \
+	MTK_BL33_IS_64BIT \
+	MTK_EXTRA_LINKERFILE \
+	MTK_PUBEVENT_ENABLE \
+	MTK_SIP_KERNEL_BOOT_ENABLE \
+	MTK_SOC \
+	PLAT_EXTRA_RODATA_INCLUDES \
+	PLAT_XLAT_TABLES_DYNAMIC \
+	UART_BAUDRATE \
+	UART_CLOCK
+
+$(foreach opt, $(DEFINED_OPTIONS),$(eval $(call add_defined_option,$(opt))))

diff --git a/plat/mediatek/common/cache_ops.c b/plat/mediatek/common/cache_ops.c
new file mode 100644
index 0000000..df43667
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+
+#include <cache_ops.h>
+#include <mcucfg.h>
+
+#define L3_SHARE_EN	9
+#define L3_SHARE_PRE_EN	8
+
+void disable_cache_as_ram(void)
+{
+	unsigned long v;
+
+	mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_EN);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_PRE_EN);
+	dsb();
+}

diff --git a/plat/mediatek/common/cache_ops.h b/plat/mediatek/common/cache_ops.h
new file mode 100644
index 0000000..aeec6be
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.h

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CACHES_OPS_H_
+#define _CACHES_OPS_H_
+
+void disable_cache_as_ram(void);
+
+#endif /* _CACHES_OPS_H_ */

diff --git a/plat/mediatek/mt8196/include/plat_macros.S b/plat/mediatek/common/include/plat_macros.S
similarity index 93%
rename from plat/mediatek/mt8196/include/plat_macros.S
rename to plat/mediatek/common/include/plat_macros.S
index c646edd..b26be39 100644
--- a/plat/mediatek/mt8196/include/plat_macros.S
+++ b/plat/mediatek/common/include/plat_macros.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Mediatek Inc. All rights reserved.
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

diff --git a/plat/mediatek/mt8196/include/plat_private.h b/plat/mediatek/common/include/plat_private.h
similarity index 88%
rename from plat/mediatek/mt8196/include/plat_private.h
rename to plat/mediatek/common/include/plat_private.h
index 1ed1973..9a0a6ae 100644
--- a/plat/mediatek/mt8196/include/plat_private.h
+++ b/plat/mediatek/common/include/plat_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Mediatek Inc. All rights reserved.
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

diff --git a/plat/mediatek/common/mtk_bl31_lib.c b/plat/mediatek/common/mtk_bl31_lib.c
new file mode 100644
index 0000000..3428471
--- /dev/null
+++ b/plat/mediatek/common/mtk_bl31_lib.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+int mtk_bl31_map_to_sip_error(enum mtk_bl31_status status)
+{
+	switch (status) {
+	case MTK_BL31_STATUS_SUCCESS:
+		return MTK_SIP_E_SUCCESS;
+	case MTK_BL31_STATUS_INVALID_PARAM:
+		return MTK_SIP_E_INVALID_PARAM;
+	case MTK_BL31_STATUS_NOT_SUPPORTED:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	case MTK_BL31_STATUS_INVALID_RANGE:
+		return MTK_SIP_E_INVALID_RANGE;
+	case MTK_BL31_STATUS_PERMISSION_DENY:
+		return MTK_SIP_E_PERMISSION_DENY;
+	case MTK_BL31_STATUS_LOCK_FAIL:
+		return MTK_SIP_E_LOCK_FAIL;
+	default:
+		ERROR("%s: unknown status: %d\n", __func__, status);
+	}
+
+	return MTK_SIP_E_NOT_SUPPORTED;
+}
+
+int mtk_bl31_mmap_add_dynamic_region(unsigned long long base_pa, size_t size,
+				     enum mtk_bl31_memory_type type)
+{
+	unsigned int attr;
+
+	switch (type) {
+	case MTK_BL31_DEV_RW_SEC:
+		attr = MT_DEVICE | MT_RW | MT_SECURE;
+		break;
+	default:
+		attr = 0;
+		ERROR("%s: unknown memory type %d\n", __func__, type);
+		break;
+	}
+
+	return mmap_add_dynamic_region(base_pa, base_pa, size, attr);
+}
+
+int mtk_bl31_mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
+{
+	return mmap_remove_dynamic_region(base_va, size);
+}

diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 0d264b9..a6d1e73 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c

@@ -24,6 +24,9 @@
 #endif
 
 /* MTK headers */
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+#include <cache_ops.h>
+#endif
 #if MTK_SIP_KERNEL_BOOT_ENABLE
 #include <cold_boot.h>
 #endif
@@ -101,6 +104,9 @@
 				u_register_t hw_config, u_register_t plat_params_from_bl2)
 
 {
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+	disable_cache_as_ram();
+#endif
 #if COREBOOT
 	static console_t console;
 

diff --git a/plat/mediatek/common/rules.mk b/plat/mediatek/common/rules.mk
index 6acc731..66ea8b7 100644
--- a/plat/mediatek/common/rules.mk
+++ b/plat/mediatek/common/rules.mk

@@ -8,7 +8,8 @@
 
 MODULE := mtk_common
 
-LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_setup.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_lib.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_bl31_setup.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_smc_handlers.c
 LOCAL_SRCS-$(MTK_SIP_KERNEL_BOOT_ENABLE) += ${LOCAL_DIR}/cold_boot.c
 

diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
index 632af52..70168d1 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c

@@ -22,7 +22,15 @@
 	uint32_t count = 0;
 
 	while ((mmio_read_32(reg) & mask) != expect) {
-		if (count > retry_times) {
+		/*
+		 * If retry_times == HW_SEM_NO_WAIT, it is just for checking if the hardware
+		 * semaphore can be locked or not. The purpose is for SMMU to check NPU power
+		 * status. Hence, just returning -EBUSY is okay. There is no need to show any
+		 * ERROR message here.
+		 */
+		if (retry_times == HW_SEM_NO_WAIT) {
+			return -EBUSY;
+		} else if (count > retry_times) {
 			ERROR("%s: timed out, reg = %x, mask = %x, expect = %x\n",
 			       __func__, reg, mask, expect);
 			return -EBUSY;
@@ -116,14 +124,14 @@
 {
 	return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
 					APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
-					APU_HW_SEM_SYS_APMCU, HW_SEM_GET, 0, 0);
+					APU_HW_SEM_SYS_APMCU, HW_SEM_GET, HW_SEM_NO_WAIT, 0);
 }
 
 int rv_iommu_hw_sem_unlock(void)
 {
 	return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
 					APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
-					APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, 0, 0);
+					APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, HW_SEM_NO_WAIT, 0);
 }
 
 int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,

diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
index b5a48e2..17f5500 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h

@@ -27,6 +27,7 @@
 		    uint8_t bypass);
 
 #define HW_SEM_TIMEOUT	(300) /* 300 us */
+#define HW_SEM_NO_WAIT	(0)   /* no wait */
 
 /* APU MBOX */
 #define MBOX_WKUP_CFG		(0x80)

diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
index a0d21c6..6edf9c6 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c

@@ -6,14 +6,11 @@
 
 #define ENABLE_SMPU_PROTECT	(1)
 
-#if ENABLE_SMPU_PROTECT
-#include "emi.h"
-#endif
-
 #include <common/debug.h>
 #include <lib/mmio.h>
 
 #include <apusys_security_ctrl_plat.h>
+#include <mtk_bl31_interface.h>
 
 #define APUSYS_SEC_FW_EMI_REGION	(23)
 
@@ -71,9 +68,10 @@
 int apusys_plat_setup_sec_mem(void)
 {
 #if ENABLE_SMPU_PROTECT
-	return sip_emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
-		(APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >> EMI_MPU_ALIGN_BITS,
-		APUSYS_SEC_FW_EMI_REGION);
+	return emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
+				      (APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >>
+				      EMI_MPU_ALIGN_BITS,
+				      APUSYS_SEC_FW_EMI_REGION);
 #else
 	INFO("%s: Bypass SMPU protection setup.\n", __func__);
 	return 0;

diff --git a/plat/mediatek/drivers/apusys/mt8196/rules.mk b/plat/mediatek/drivers/apusys/mt8196/rules.mk
index aeb6d3d..67243da 100644
--- a/plat/mediatek/drivers/apusys/mt8196/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8196/rules.mk

@@ -8,10 +8,6 @@
 
 MODULE := apusys_${MTK_SOC}
 
-ifeq (${CONFIG_MTK_APUSYS_EMI_SUPPORT}, y)
-PLAT_INCLUDES += -I${MTK_PLAT}/drivers/emi/common
-endif
-
 LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_ammu.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_devapc.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c

diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 24cc79c..f487c11 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk

@@ -13,7 +13,6 @@
 PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
 
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_CE_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_EMI_SUPPORT))
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_LOGTOP_SUPPORT))
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT))
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT))

diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
index 4d99df1..e1ead97 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h

@@ -71,6 +71,7 @@
 		PER_CPU_PWR_DATA(ctrl, 0, 7); \
 		break; \
 	default: \
+		PER_CPU_PWR_DATA(ctrl, 0, 0); \
 		assert(0); \
 		break; \
 	} })

diff --git a/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c b/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
index 563e6b5..a1c903e 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
+++ b/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c

@@ -7,12 +7,11 @@
 #include <stdint.h>
 #include <stdio.h>
 
-#include <drivers/cirq.h>
-
 #include <platform_def.h>
 
 #include <lib/pm/mtk_pm.h>
 #include <lpm_v2/mt_lp_rm.h>
+#include <mt_cirq.h>
 #include "mt_cpu_pm.h"
 #include "mt_lp_irqremain.h"
 

diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c
new file mode 100644
index 0000000..eb4436c
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/pm/mtk_pm.h>
+#include <mtk_bl31_interface.h>
+
+static void *cpu_qos_handle_cluster_on_event_cb(const void *arg)
+{
+	return cpu_qos_handle_cluster_on_event(arg);
+}
+
+MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(cpu_qos_handle_cluster_on_event_cb);

diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c
new file mode 100644
index 0000000..f3540bd
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+void cpu_qos_change_dcc(uint32_t on, uint32_t is_auto)
+{
+}
+
+void *cpu_qos_handle_cluster_on_event(const void *arg)
+{
+	return (void *)arg;
+}

diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk b/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk
new file mode 100644
index 0000000..fa12496
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := cpu_qos_$(MTK_SOC)
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/mtk_cpuqos.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/mtk_cpuqos_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/cpu_qos/rules.mk b/plat/mediatek/drivers/cpu_qos/rules.mk
new file mode 100644
index 0000000..c67a136
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/rules.mk

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+SUB_RULES := $(LOCAL_DIR)/$(MTK_SOC)
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES)))

diff --git a/plat/mediatek/drivers/emi/common/emi.h b/plat/mediatek/drivers/emi/common/emi.h
deleted file mode 100644
index eb2a0d3..0000000
--- a/plat/mediatek/drivers/emi/common/emi.h
+++ /dev/null

@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2025, Mediatek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef EMI_H
-#define EMI_H
-
-#include <stdint.h>
-
-#define EMI_MPU_ALIGN_BITS	12
-
-uint64_t sip_emi_mpu_set_protection(u_register_t start, u_register_t end, u_register_t region);
-
-#endif /* EMI_H */

diff --git a/plat/mediatek/drivers/emi/emi_ctrl.c b/plat/mediatek/drivers/emi/emi_ctrl.c
new file mode 100644
index 0000000..00ac7df
--- /dev/null
+++ b/plat/mediatek/drivers/emi/emi_ctrl.c

@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+#define NO_PROTECTION	0
+#define SEC_RW		1
+#define SEC_RW_NSEC_R	2
+#define SEC_RW_NSEC_W	3
+#define SEC_R_NSEC_R	4
+#define FORBIDDEN	5
+#define SEC_R_NSEC_RW	6
+
+#define EMIMPU_SET	0
+#define EMIMPU_CLEAR	1
+#define EMIMPU_READ	2
+#define EMIMPU_SLVERR	3
+#define EMIDBG_DUMP	4
+#define EMIDBG_MSG	5
+#define AID_TABLE_SET	6
+#define EMIMPU_CLEAR_MD	7
+#define KP_SET		8
+#define KP_CLEAR	9
+
+#define EMIMPU_READ_SA			0
+#define EMIMPU_READ_EA			1
+#define EMIMPU_READ_APC			2
+#define EMIMPU_READ_ENABLE		3
+#define EMIMPU_READ_AID			4
+#define EMIMPU_CHECK_NS_CPU		5
+#define EMIMPU_CHECK_REGION_INFO	6
+#define EMIMPU_PAGE_BASE_REGION		7
+#define SLBMPU_CLEAR			8
+#define EMIMPU_CHECK_HP_MOD		9
+#define EMI_CLE				10
+#define SLC_PARITY_SELECT		11
+#define SLC_PARITY_CLEAR		12
+
+static uint64_t emi_mpu_read_by_type(unsigned int reg_type, unsigned int region,
+				     unsigned int aid_shift, struct smccc_res *smccc_ret)
+{
+	switch (reg_type) {
+	case EMIMPU_READ_SA:
+		return emi_mpu_read_addr(region, 0x0);
+	case EMIMPU_READ_EA:
+		return emi_mpu_read_addr(region, 0x8);
+	case EMIMPU_READ_ENABLE:
+		return emi_mpu_read_enable(region);
+	case EMIMPU_READ_AID:
+		return emi_mpu_read_aid(region, aid_shift);
+	case EMIMPU_CHECK_REGION_INFO:
+		return emi_mpu_check_region_info(region, &smccc_ret->a1, &smccc_ret->a2);
+	case EMIMPU_CHECK_NS_CPU:
+		return emi_mpu_check_ns_cpu();
+	case EMIMPU_PAGE_BASE_REGION:
+		return emi_mpu_page_base_region();
+	case EMIMPU_CHECK_HP_MOD:
+		return emi_mpu_smc_hp_mod_check();
+	default:
+		return 0;
+	}
+}
+
+static u_register_t sip_emidbg_control(u_register_t op_id,
+				       u_register_t x2,
+				       u_register_t x3,
+				       u_register_t x4,
+				       void *handle,
+				       struct smccc_res *smccc_ret)
+{
+	enum mtk_bl31_status ret;
+
+	switch (op_id) {
+	case EMIDBG_DUMP:
+		return MTK_SIP_E_SUCCESS;
+	case EMIDBG_MSG:
+		return MTK_SIP_E_SUCCESS;
+#ifdef MTK_EMI_MPU_DEBUG
+	case EMIMPU_READ:
+		ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3,
+					   (unsigned int)x4, smccc_ret);
+		break;
+#endif
+	case EMIMPU_CLEAR_MD:
+		ret = emi_clear_md_violation();
+		break;
+	case KP_CLEAR:
+		ret = emi_kp_clear_violation((unsigned int)x2);
+		break;
+#ifdef CONFIG_MTK_SLB_MPU_CLEAR
+	case SLBMPU_CLEAR:
+		ret = slb_clear_violation((unsigned int)x2);
+		break;
+#endif
+#ifdef CONFIG_MTK_EMI_CLEAR
+	case EMI_CLEAR:
+		ret = emi_clear_violation((unsigned int)x2, (unsigned int)x3);
+		break;
+#endif
+#ifdef CONFIG_MTK_SLC_PARITY
+	case SLC_PARITY_SELECT:
+		ret = slc_parity_select((unsigned int)x2, (unsigned int)x3);
+		break;
+	case SLC_PARITY_CLEAR:
+		ret = slc_parity_clear((unsigned int)x2);
+		break;
+#endif
+	default:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_EMIDBG_CONTROL, sip_emidbg_control);
+
+static u_register_t sip_emimpu_control(u_register_t op_id,
+				       u_register_t x2,
+				       u_register_t x3,
+				       u_register_t x4,
+				       void *handle,
+				       struct smccc_res *smccc_ret)
+{
+	enum mtk_bl31_status ret;
+
+	switch (op_id) {
+	case EMIMPU_SET:
+		ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4);
+		break;
+	case AID_TABLE_SET:
+		ret = emi_mpu_set_aid((unsigned int)x2, (unsigned int)x3);
+		break;
+	case EMIMPU_READ:
+		ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3,
+					   (unsigned int)x4, smccc_ret);
+		break;
+	case KP_SET:
+		ret = emi_kp_set_protection((size_t)x2, (size_t)x3, (unsigned int)x4);
+		break;
+	case KP_CLEAR:
+		ret = emi_kp_clear_violation((unsigned int)x2);
+		break;
+	default:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_BL_EMIMPU_CONTROL, sip_emimpu_control);
+
+static u_register_t sip_tee_emimpu_control(u_register_t op_id,
+					   u_register_t x2,
+					   u_register_t x3,
+					   u_register_t x4,
+					   void *handle,
+					   struct smccc_res *smccc_ret)
+{
+	enum mtk_bl31_status ret;
+
+	switch (op_id) {
+	case EMIMPU_SET:
+		ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4);
+		break;
+	case EMIMPU_CLEAR:
+		ret = emi_clear_protection((unsigned int)x2);
+		break;
+	default:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_TEE_EMI_MPU_CONTROL, sip_tee_emimpu_control);
+
+int emi_mpu_init(void)
+{
+	INFO("[%s] emi mpu initialization\n", __func__);
+
+	emi_protection_init();
+
+	return 0;
+}
+MTK_PLAT_SETUP_0_INIT(emi_mpu_init);

diff --git a/plat/mediatek/drivers/emi/emi_stub.c b/plat/mediatek/drivers/emi/emi_stub.c
index 3682bf7..abe559a 100644
--- a/plat/mediatek/drivers/emi/emi_stub.c
+++ b/plat/mediatek/drivers/emi/emi_stub.c

@@ -3,13 +3,95 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#include <common/debug.h>
 
-#include "common/emi.h"
-#include <mtk_sip_svc.h>
+#include <mtk_bl31_interface.h>
 
-uint64_t sip_emi_mpu_set_protection(u_register_t start, u_register_t end,
-				    u_register_t region)
+uint64_t emi_mpu_read_addr(unsigned int region, unsigned int offset)
 {
-	return MTK_SIP_E_NOT_SUPPORTED;
+	return 0;
+}
+
+uint64_t emi_mpu_read_enable(unsigned int region)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_read_aid(unsigned int region, unsigned int aid_shift)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_check_ns_cpu(void)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_kp_set_protection(size_t start, size_t end, unsigned int region)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_kp_clear_violation(unsigned int emiid)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_protection(unsigned int region)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_md_violation(void)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+uint64_t emi_mpu_check_region_info(unsigned int region, uint64_t *sa, uint64_t *ea)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_page_base_region(void)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_smc_hp_mod_check(void)
+{
+	return 0;
+}
+
+enum mtk_bl31_status slb_clear_violation(unsigned int id)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_violation(unsigned int id, unsigned int type)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status slc_parity_clear(unsigned int id)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_mpu_set_aid(unsigned int region, unsigned int num)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+void emi_protection_init(void)
+{
+}
+
+enum mtk_bl31_status emi_mpu_set_protection(uint32_t start, uint32_t end,
+					    unsigned int region)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
 }

diff --git a/plat/mediatek/drivers/emi/rules.mk b/plat/mediatek/drivers/emi/rules.mk
index 9f462bb..ffe1817 100644
--- a/plat/mediatek/drivers/emi/rules.mk
+++ b/plat/mediatek/drivers/emi/rules.mk

@@ -8,8 +8,9 @@
 
 MODULE := emi
 
+LOCAL_SRCS-y := $(LOCAL_DIR)/emi_ctrl.c
 ifeq ($(MTKLIB_PATH),)
-LOCAL_SRCS-y := $(LOCAL_DIR)/emi_stub.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/emi_stub.c
 endif
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/gicv3/mt_gic_v3.c b/plat/mediatek/drivers/gicv3/mt_gic_v3.c
index 659ca9c..e9bbbe1 100644
--- a/plat/mediatek/drivers/gicv3/mt_gic_v3.c
+++ b/plat/mediatek/drivers/gicv3/mt_gic_v3.c

@@ -23,7 +23,7 @@
 
 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
-static gicv3_redist_ctx_t rdist_ctx;
+static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
 static gicv3_dist_ctx_t dist_ctx;
 
 /* Configure Secure IRQs */
@@ -112,7 +112,7 @@
 	 * before the Distributor context.
 	 */
 	for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
-		gicv3_rdistif_save(cpu, &rdist_ctx);
+		gicv3_rdistif_save(cpu, &rdist_ctx[cpu]);
 }
 
 void mt_gic_rdistif_restore(void)
@@ -126,7 +126,7 @@
 	 * the SYSTEM SUSPEND call.
 	 */
 	for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
-		gicv3_rdistif_init_restore(cpu, &rdist_ctx);
+		gicv3_rdistif_init_restore(cpu, &rdist_ctx[cpu]);
 }
 
 void mt_gic_redistif_on(void)

diff --git a/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c
new file mode 100644
index 0000000..50fd2e7
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_iommu_priv.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+/* mm iommu */
+#define SMI_L0_ID		(0)
+#define SMI_L1_ID		(1)
+#define SMI_L2_ID		(2)
+#define SMI_L4_ID		(3)
+#define SMI_L7_ID		(4)
+#define SMI_L9_ID		(5)
+#define SMI_L11_ID		(6)
+#define SMI_L13_ID		(7)
+#define SMI_L14_ID		(8)
+#define SMI_L16_ID		(9)
+#define SMI_L17_ID		(10)
+#define SMI_L19_ID		(11)
+#define SMI_L20_ID		(12)
+
+/* infra iommu */
+#define PERICFG_AO_IOMMU_0	(0x90)
+#define PERICFG_AO_IOMMU_1	(0x94)
+#define MMU_DEV_PCIE_0		(0)
+#define IFR_CFG_GROUP_NUM	(1)
+
+static struct mtk_smi_larb_config mt8189_larb_cfg[] = {
+	[SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 8, 0),
+	[SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 8, 0),
+	[SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 11, 0),
+	[SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 12, 0),
+	[SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 18, 0),
+	[SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 29, 0),
+	[SMI_L11_ID] = LARB_CFG_ENTRY(SMI_LARB_11_BASE, 29, 0),
+	[SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 15, 0),
+	[SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 10, 0),
+	[SMI_L16_ID] = LARB_CFG_ENTRY(SMI_LARB_16_BASE, 17, 0),
+	[SMI_L17_ID] = LARB_CFG_ENTRY(SMI_LARB_17_BASE, 17, 0),
+	[SMI_L19_ID] = LARB_CFG_ENTRY(SMI_LARB_19_BASE, 4, 0),
+	[SMI_L20_ID] = LARB_CFG_ENTRY(SMI_LARB_20_BASE, 6, 0),
+};
+
+static uint32_t mt8189_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = {
+	PERICFG_AO_BASE,
+};
+static uint32_t mt8189_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = {
+	PERICFG_AO_IOMMU_1,
+};
+static struct mtk_ifr_mst_config mt8189_ifr_mst_cfg[] = {
+	[MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 0),
+};
+
+struct mtk_smi_larb_config *g_larb_cfg = &mt8189_larb_cfg[0];
+const unsigned int g_larb_num = ARRAY_SIZE(mt8189_larb_cfg);
+
+static struct mtk_secure_iommu_config mt8189_secure_iommu_config[] = {
+	SEC_IOMMU_CFG_ENTRY(MM_IOMMU_BASE),
+};
+
+struct mtk_secure_iommu_config *g_sec_iommu_cfg = &mt8189_secure_iommu_config[0];
+const unsigned int g_sec_iommu_num = ARRAY_SIZE(mt8189_secure_iommu_config);
+
+struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8189_ifr_mst_cfg[0];
+const unsigned int g_ifr_mst_num = ARRAY_SIZE(mt8189_ifr_mst_cfg);
+
+uint32_t *g_ifr_mst_cfg_base = &mt8189_ifr_mst_cfg_base[0];
+uint32_t *g_ifr_mst_cfg_offs = &mt8189_ifr_mst_cfg_offs[0];
+
+/**
+ * Protect infra iommu enable setting registers as secure access.
+ * This is removed in MT8189, just return here.
+ */
+void mtk_infra_iommu_enable_protect(void)
+{
+}

diff --git a/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h
new file mode 100644
index 0000000..935036f
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IOMMU_PLAT_H
+#define IOMMU_PLAT_H
+
+/* mm iommu */
+#define ATF_MTK_SMI_LARB_CFG_SUPPORT
+
+/* mm iommu, sec bank dump */
+#define ATF_MTK_IOMMU_CFG_SUPPORT
+
+/* infra iommu */
+#define ATF_MTK_INFRA_MASTER_CFG_SUPPORT
+
+#endif /* IOMMU_PLAT_H */

diff --git a/plat/mediatek/drivers/mminfra/mminfra_common.h b/plat/mediatek/drivers/mminfra/mminfra_common.h
new file mode 100644
index 0000000..93820c7
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mminfra_common.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMINFRA_COMMON_H
+#define MMINFRA_COMMON_H
+
+#define mminfra_info(fmt, args...)	INFO("[mminfra] %s: "fmt"\n", __func__, ##args)
+#define mminfra_err(fmt, args...)	ERROR("[mminfra] %s: "fmt"\n", __func__, ##args)
+
+#endif

diff --git a/plat/mediatek/drivers/mminfra/mminfra_stub.c b/plat/mediatek/drivers/mminfra/mminfra_stub.c
deleted file mode 100644
index dc37280..0000000
--- a/plat/mediatek/drivers/mminfra/mminfra_stub.c
+++ /dev/null

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2025, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <drivers/mminfra_public.h>
-
-int mminfra_get_if_in_use(void)
-{
-	return 0;
-}
-
-int mminfra_put(void)
-{
-	return 0;
-}

diff --git a/plat/mediatek/drivers/mminfra/mt8196/mminfra.c b/plat/mediatek/drivers/mminfra/mt8196/mminfra.c
new file mode 100644
index 0000000..1086c75
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mt8196/mminfra.c

@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <drivers/mminfra_public.h>
+#include <mminfra.h>
+#include <mtk_mmap_pool.h>
+
+static const mmap_region_t mminfra_plat_mmap[] MTK_MMAP_SECTION = {
+	MAP_REGION_FLAT(MMINFRA_HW_VOTER_BASE, PAGE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+	{0}
+};
+DECLARE_MTK_MMAP_REGIONS(mminfra_plat_mmap);
+
+static struct mtk_mminfra_pwr_ctrl mminfra_pwr_ctrl = {
+	.hw_voter = {
+		.base = MMINFRA_HW_VOTER_BASE,
+		.set_ofs = 0x104,
+		.clr_ofs = 0x108,
+		.en_ofs = 0x100,
+		.en_shift = 0x1,
+		.done_bits = VLP_AO_RSVD6,
+	},
+	.hw_sema = {
+		.base = SPM_BASE,
+		.offset = SPM_SEMAPHORE_M1,
+		.offset_all = {
+			SPM_SEMAPHORE_M0,
+			SPM_SEMAPHORE_M1,
+			SPM_SEMAPHORE_M2,
+			SPM_SEMAPHORE_M3,
+			SPM_SEMAPHORE_M4,
+			SPM_SEMAPHORE_M5,
+			SPM_SEMAPHORE_M6,
+			SPM_SEMAPHORE_M7,
+		},
+		.set_val = SPM_SEMA_MMINFRA,
+	},
+	.active = true,
+	.ref_cnt = 0,
+};
+
+static int spm_semaphore_get(uint32_t base, uint32_t set_val)
+{
+	int  cnt = SEMA_RETRY_CNT;
+	uint32_t val;
+
+	val = mmio_read_32(base);
+	if ((val & set_val) == set_val) {
+		mminfra_err("hw_sem was already got, base:0x%x=0x%x, set_val:0x%x\n",
+			    base, val, set_val);
+		return -1;
+	}
+
+	while (cnt > 0) {
+		mmio_write_32(base, set_val);
+		udelay(10);
+		if ((mmio_read_32(base) & set_val) == set_val)
+			return 0;
+		cnt--;
+	}
+
+	mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val);
+	return -1;
+}
+
+static int spm_semaphore_release(uint32_t base, uint32_t set_val)
+{
+	int cnt = SEMA_RETRY_CNT;
+	uint32_t val;
+
+	val = mmio_read_32(base);
+	if ((val & set_val) != set_val) {
+		mminfra_err("hw_sem was already released, base:0x%x=0x%x, set_val:0x%x\n",
+			    base, val, set_val);
+		return -1;
+	}
+	do {
+		mmio_write_32(base, set_val);
+		udelay(10);
+		if (cnt-- < 0) {
+			if ((mmio_read_32(base) & set_val) != set_val)
+				return 0;
+			mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val);
+			return -1;
+		}
+	} while ((mmio_read_32(base) & set_val) == set_val);
+
+	return 0;
+}
+
+static int mminfra_hw_sema_ctrl(struct mminfra_hw_sema *hw_sema, bool is_get)
+{
+	int i, ret;
+
+	if (!hw_sema)
+		return 0;
+
+	if (is_get)
+		ret = spm_semaphore_get(hw_sema->base + hw_sema->offset, hw_sema->set_val);
+	else
+		ret = spm_semaphore_release(hw_sema->base + hw_sema->offset, hw_sema->set_val);
+
+	if (ret)
+		for (i = 0; i < SPM_SEMA_MMINFRA_NR; i++)
+			mminfra_err("0x%x=0x%x\n", hw_sema->base + hw_sema->offset_all[i],
+				    mmio_read_32(hw_sema->base + hw_sema->offset_all[i]));
+
+	return ret;
+}
+
+static bool is_mminfra_ready(struct mminfra_hw_voter *hw_voter)
+{
+	if (!hw_voter)
+		return false;
+
+	return !!(mmio_read_32(hw_voter->done_bits) & MMINFRA_DONE);
+}
+
+static int mminfra_hwv_power_ctrl(struct mminfra_hw_voter *hw_voter, bool is_on)
+{
+	uint32_t vote_ofs, vote_mask, vote_ack;
+	uint32_t val = 0, cnt;
+
+	vote_mask = BIT(hw_voter->en_shift);
+	vote_ofs = is_on ? hw_voter->set_ofs : hw_voter->clr_ofs;
+	vote_ack = is_on ? vote_mask : 0x0;
+
+	/* Vote on off */
+	cnt = 0;
+	do {
+		mmio_write_32(hw_voter->base + vote_ofs, vote_mask);
+		udelay(MTK_POLL_HWV_VOTE_US);
+		val = mmio_read_32(hw_voter->base + hw_voter->en_ofs);
+		if ((val & vote_mask) == vote_ack)
+			break;
+
+		if (cnt > MTK_POLL_HWV_VOTE_CNT) {
+			mminfra_err("vote mminfra timeout, is_on:%d, 0x%x=0x%x\n",
+				    is_on, hw_voter->base + hw_voter->en_ofs, val);
+			return -1;
+		}
+		cnt++;
+	} while (1);
+
+	if (!is_on)
+		return 0;
+
+	/* Confirm done bits */
+	cnt = 0;
+	while (cnt < MTK_POLL_DONE_RETRY) {
+		if (is_mminfra_ready(hw_voter))
+			return 0;
+		udelay(MTK_POLL_DONE_DELAY_US);
+		cnt++;
+	}
+
+	mminfra_err("polling mminfra done timeout, 0x%x=0x%x\n",
+		    hw_voter->done_bits, val);
+	return -1;
+}
+
+int mminfra_get_if_in_use(void)
+{
+	int ret, is_on = MMINFRA_RET_POWER_OFF;
+
+	if (!mminfra_pwr_ctrl.active) {
+		mminfra_err("not ready\n");
+		return MMINFRA_RET_POWER_OFF;
+	}
+
+	spin_lock(&mminfra_pwr_ctrl.lock);
+	if (mminfra_pwr_ctrl.ref_cnt > 0) {
+		mminfra_pwr_ctrl.ref_cnt++;
+		is_on = MMINFRA_RET_POWER_ON;
+		spin_unlock(&mminfra_pwr_ctrl.lock);
+		return is_on;
+	}
+
+	ret = mminfra_hw_sema_ctrl(&mminfra_pwr_ctrl.hw_sema, true);
+	if (ret)
+		goto err;
+
+	/* Check if mminfra is in use */
+	if (is_mminfra_ready(&mminfra_pwr_ctrl.hw_voter)) {
+		ret = mminfra_hwv_power_ctrl(&mminfra_pwr_ctrl.hw_voter, true);
+		if (ret) {
+			mminfra_err("vote for mminfra fail, ret=%d\n", ret);
+			goto err;
+		}
+		mminfra_pwr_ctrl.ref_cnt++;
+		is_on = MMINFRA_RET_POWER_ON;
+	} else {
+		is_on = MMINFRA_RET_POWER_OFF;
+	}
+
+	ret = mminfra_hw_sema_ctrl(&mminfra_pwr_ctrl.hw_sema, false);
+	if (ret)
+		goto err;
+	ret = is_on; /* Return power is on or off. */
+err:
+	spin_unlock(&mminfra_pwr_ctrl.lock);
+	return ret;
+}
+
+int mminfra_put(void)
+{
+	if (!mminfra_pwr_ctrl.active) {
+		mminfra_err("not ready\n");
+		return 0;
+	}
+
+	spin_lock(&mminfra_pwr_ctrl.lock);
+	mminfra_pwr_ctrl.ref_cnt--;
+	if (mminfra_pwr_ctrl.ref_cnt > 0)
+		goto out;
+
+	mminfra_hwv_power_ctrl(&mminfra_pwr_ctrl.hw_voter, false);
+out:
+	spin_unlock(&mminfra_pwr_ctrl.lock);
+	return 0;
+}

diff --git a/plat/mediatek/drivers/mminfra/mt8196/mminfra.h b/plat/mediatek/drivers/mminfra/mt8196/mminfra.h
new file mode 100644
index 0000000..fcee08c
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mt8196/mminfra.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMINFRA_H
+#define MMINFRA_H
+
+#include <lib/spinlock.h>
+
+#include "../mminfra_common.h"
+#include <platform_def.h>
+
+#define VLP_AO_RSVD6			(MTK_VLP_TRACER_MON_BASE + 0x918)
+#define MMINFRA_DONE			(1U << 0)
+
+#define SPM_SEMA_MMINFRA                (1U << 5)
+#define SPM_SEMA_MMINFRA_NR             (8)
+
+#define SEMA_RETRY_CNT			(500)
+
+#define SPM_SEMAPHORE_M0		(0x69C)
+#define SPM_SEMAPHORE_M1		(0x6A0)
+#define SPM_SEMAPHORE_M2		(0x6A4)
+#define SPM_SEMAPHORE_M3		(0x6A8)
+#define SPM_SEMAPHORE_M4		(0x6AC)
+#define SPM_SEMAPHORE_M5		(0x6B0)
+#define SPM_SEMAPHORE_M6		(0x6B4)
+#define SPM_SEMAPHORE_M7		(0x6B8)
+
+#define MMINFRA_HW_VOTER_BASE		(0x31A80000)
+#define MTK_POLL_HWV_VOTE_US		(2)
+#define MTK_POLL_HWV_VOTE_CNT		(2500)
+#define MTK_POLL_DONE_DELAY_US		(1)
+#define MTK_POLL_DONE_RETRY		(3000)
+
+struct mminfra_hw_sema {
+	uint32_t base;
+	uint32_t offset;
+	uint32_t offset_all[SPM_SEMA_MMINFRA_NR];
+	uint32_t set_val;
+};
+
+struct mminfra_hw_voter {
+	uint32_t base;
+	uint32_t set_ofs;
+	uint32_t clr_ofs;
+	uint32_t en_ofs;
+	uint32_t en_shift;
+	uint32_t done_bits;
+};
+
+struct mtk_mminfra_pwr_ctrl {
+	spinlock_t lock;
+	struct mminfra_hw_voter hw_voter;
+	struct mminfra_hw_sema hw_sema;
+	uint32_t ref_cnt;
+	bool active;
+};
+
+#endif

diff --git a/plat/mediatek/drivers/mminfra/rules.mk b/plat/mediatek/drivers/mminfra/rules.mk
index f3a6822..cd5d607 100644
--- a/plat/mediatek/drivers/mminfra/rules.mk
+++ b/plat/mediatek/drivers/mminfra/rules.mk

@@ -8,10 +8,9 @@
 
 MODULE := mminfra
 
-PLAT_INCLUDES += -I${MTK_PLAT}/include/drivers/
+PLAT_INCLUDES += -I$(MTK_PLAT)/include/drivers/
+PLAT_INCLUDES += -I$(MTK_PLAT)/drivers/mminfra/$(MTK_SOC)
 
-ifeq ($(MTKLIB_PATH),)
-LOCAL_SRCS-y := ${LOCAL_DIR}/mminfra_stub.c
-endif
+LOCAL_SRCS-y := $(LOCAL_DIR)/$(MTK_SOC)/mminfra.c
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
new file mode 100644
index 0000000..6c0eb9c
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/pmic/pmic_psc.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#include "registers.h"
+
+static const struct pmic_psc_reg mt6359p_psc_regs[] = {
+	PMIC_PSC_REG(RG_PWRHOLD, MT6359P_PPCCTL0, 0),
+	PMIC_PSC_REG(RG_CRST, MT6359P_PPCCTL1, 0),
+	PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6359P_STRUP_CON12, 9),
+	PMIC_PSC_REG(RG_SMART_RST_MODE, MT6359P_STRUP_CON12, 10),
+};
+
+static const struct pmic_psc_config mt6359p_psc_config = {
+	.read_field = pwrap_read_field,
+	.write_field = pwrap_write_field,
+	.regs = mt6359p_psc_regs,
+	.reg_size = ARRAY_SIZE(mt6359p_psc_regs),
+};
+
+static int mt6359p_psc_init(void)
+{
+	return pmic_psc_register(&mt6359p_psc_config);
+}
+
+MTK_PLAT_SETUP_0_INIT(mt6359p_psc_init);

diff --git a/plat/mediatek/drivers/pmic/mt6359p/registers.h b/plat/mediatek/drivers/pmic/mt6359p/registers.h
new file mode 100644
index 0000000..f1b2a6d
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/registers.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+/* PMIC Registers for PSC */
+#define MT6359P_PPCCTL0		0xa08
+#define MT6359P_PPCCTL1		0xa0a
+#define MT6359P_STRUP_CON12	0xa12
+
+#endif /* REGISTER_H */

diff --git a/plat/mediatek/drivers/pmic/mt6359p/rules.mk b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
new file mode 100644
index 0000000..39908f8
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/rules.mk

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mt6359p
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/${PMIC_CHIP}_psc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
new file mode 100644
index 0000000..aa90b86
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <drivers/pmic/mt6319_lowpower_reg.h>
+#include <drivers/pmic/mt6359p_set_lowpower.h>
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define PMIC_SLVID_BUCK_SET_LP(_chip, _slvid, _name, _user, _en, _mode, _cfg) \
+{ \
+	struct spmi_device *sdev = lowpower_sdev[_slvid]; \
+	if (sdev) {\
+		pmic_spmi_update_bits(sdev, \
+				      _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+				      1 << _user, \
+				      _cfg ? 1 << _user : 0); \
+		pmic_spmi_update_bits(sdev, \
+				      _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+				      1 << _user, \
+				      _mode ? 1 << _user : 0); \
+		pmic_spmi_update_bits(sdev, \
+				      _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+				      1 << _user, \
+				      _en ? 1 << _user : 0); \
+	} \
+}
+
+struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
+
+static const uint8_t lowpower_slvid_arr[] = {
+	SPMI_SLAVE_7,
+};
+
+static int pmic_spmi_update_bits(struct spmi_device *sdev, uint16_t reg,
+				 uint8_t mask, uint8_t val)
+{
+	uint8_t orig = 0;
+	int ret = 0;
+
+	ret = spmi_ext_register_readl(sdev, reg, &orig, 1);
+	if (ret < 0)
+		return ret;
+	orig &= ~mask;
+	orig |= val & mask;
+	ret = spmi_ext_register_writel(sdev, reg, &orig, 1);
+	return ret;
+}
+
+static int pmic_lowpower_init(void)
+{
+	uint8_t i, slvid;
+
+	for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
+		slvid = lowpower_slvid_arr[i];
+		lowpower_sdev[slvid] = get_spmi_device(SPMI_MASTER_P_1, slvid);
+		if (!lowpower_sdev[slvid])
+			return -ENODEV;
+	}
+
+	PMIC_SLVID_BUCK_SET_LP(MT6319, SPMI_SLAVE_7, VBUCK3, HW0, true, OP_MODE_LP, HW_LP);
+
+	PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW0, true, OP_MODE_LP, HW_OFF);
+	PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS1, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS1, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS2, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS2, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VRF12, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VRF12, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA12, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA12, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA09, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA09, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VAUX18, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VAUX18, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VXO22, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VXO22, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VUSB, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VUSB, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VUFS, HW0, true, OP_MODE_LP, HW_LP);
+
+	return 0;
+}
+
+MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);

diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
new file mode 100644
index 0000000..dbb5852
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "../mt6359p/registers.h"
+#include <drivers/pmic/pmic_shutdown_cfg.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define MT6319_RG_SEQ_OFF		0x2d
+#define MT6319_TOP_RST_MISC_CLR		0x128
+#define MT6319_TOP_DIG_WPK_H		0x3a9
+#define MT6319_TOP_DIG_WPK_H_MASK	0xFF
+#define MT6319_TOP_DIG_WPK_H_SHIFT	0
+#define MT6319_TOP_DIG_WPK		0x3a8
+#define MT6319_TOP_DIG_WPK_MASK		0xFF
+#define MT6319_TOP_DIG_WPK_SHIFT	0
+
+
+int pmic_shutdown_cfg(void)
+{
+/*
+ * In mt8189, the pmic_shutdown_cfg() api does not need to read and write the
+ * pmic register to determine the return value and in order not to modify the
+ * common code to affect other ICs, the pmic_shutdown_cfg() will directly
+ * return 1.
+ */
+	return 1;
+}
+
+static void shutdown_slave_dev(struct spmi_device *dev)
+{
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0x63,
+				       MT6319_TOP_DIG_WPK_H_MASK,
+				       MT6319_TOP_DIG_WPK_H_SHIFT);
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0x15,
+				       MT6319_TOP_DIG_WPK_MASK,
+				       MT6319_TOP_DIG_WPK_SHIFT);
+
+	/* Disable WDTRSTB_EN */
+	spmi_ext_register_writel_field(dev, MT6319_TOP_RST_MISC_CLR, 1, 0x1, 0);
+	/* Normal sequence power off when PAD_EN falling */
+	spmi_ext_register_writel_field(dev, MT6319_RG_SEQ_OFF, 1, 0x1, 0);
+
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0,
+				       MT6319_TOP_DIG_WPK_H_MASK,
+				       MT6319_TOP_DIG_WPK_H_SHIFT);
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0,
+				       MT6319_TOP_DIG_WPK_MASK,
+				       MT6319_TOP_DIG_WPK_SHIFT);
+
+}
+
+int spmi_shutdown(void)
+{
+	struct spmi_device *mt6319_sdev;
+
+	mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_7);
+	if (!mt6319_sdev)
+		return -ENODEV;
+	shutdown_slave_dev(mt6319_sdev);
+
+	if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+	    mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189H) {
+		mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
+		if (!mt6319_sdev)
+			return -ENODEV;
+		shutdown_slave_dev(mt6319_sdev);
+	}
+
+	/* clear main pmic power hold */
+	pwrap_write_field(MT6359P_PPCCTL0, 0, 0x1, 0);
+
+	return 0;
+}

diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
new file mode 100644
index 0000000..0310389
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <drivers/pmic/pmic_swap_api.h>
+
+/* No need to check second pmic mt6369 */
+bool is_second_pmic_pp_swap(void)
+{
+	return false;
+}

diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk
index 0280df8..13ce658 100644
--- a/plat/mediatek/drivers/pmic/rules.mk
+++ b/plat/mediatek/drivers/pmic/rules.mk

@@ -8,15 +8,15 @@
 
 MODULE := pmic
 
-ifneq (${PMIC_CHIP}, mt6363)
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
-PLAT_INCLUDES += -I${LOCAL_DIR}/
-else
-LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_common_swap_api.c
+ifeq (${CONFIG_MTK_PMIC_SHUTDOWN_V2}, y)
+LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_common_swap_api.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_psc.c
 LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_lowpower_init.c
 LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_swap_api.c
 LOCAL_SRCS-${CONFIG_MTK_PMIC_SHUTDOWN_CFG} += ${LOCAL_DIR}/${MTK_SOC}/pmic_shutdown_cfg.c
+else
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
+PLAT_INCLUDES += -I${LOCAL_DIR}/
 endif
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
new file mode 100644
index 0000000..9647326
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <pmic_wrap_init_common.h>
+
+#define PWRAP_DEBUG				0
+
+/* PMIC_WRAP registers */
+struct mt8189_pmic_wrap_regs {
+	uint32_t init_done;
+	uint32_t reserved[511];
+	struct {
+		uint32_t cmd;
+		uint32_t wdata;
+		uint32_t reserved1[3];
+		uint32_t rdata;
+		uint32_t reserved2[3];
+		uint32_t vldclr;
+		uint32_t sta;
+		uint32_t reserved3[5];
+	} wacs[4];
+};
+
+static struct mt8189_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+#define PMIF_SPI_SWINF_NO			2
+
+#endif /* PMIC_WRAP_INIT_H */

diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
index 4ba1f5c..3a30435 100644
--- a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h

@@ -12,10 +12,14 @@
 #include "platform_def.h"
 
 /* external API */
+int32_t pmic_wrap_test(void);
 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
 
-#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
+#define GET_SWINF_INIT_DONE(x)	((x>>15) & 0x00000001)
+#define GET_WACS_FSM(x)		((x >> 1) & 0x7)
 
 /* macro for SWINF_FSM */
 #define SWINF_FSM_IDLE		(0x00)
@@ -43,6 +47,11 @@
 	E_PWR_INIT_SIDLY_FAIL		= 11,
 	E_PWR_RESET_TIMEOUT		= 12,
 	E_PWR_TIMEOUT			= 13,
+	E_PWR_INVALID_SWINF		= 14,
+	E_PWR_INVALID_CMD		= 15,
+	E_PWR_INVALID_PMIFID		= 16,
+	E_PWR_INVALID_SLVID		= 17,
+	E_PWR_INVALID_BYTECNT		= 18,
 	E_PWR_INIT_RESET_SPI		= 20,
 	E_PWR_INIT_SIDLY		= 21,
 	E_PWR_INIT_REG_CLOCK		= 22,

diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
new file mode 100644
index 0000000..4e9c321
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c

@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+
+#include <mtk_mmap_pool.h>
+#include "pmic_wrap_init.h"
+#include "pmic_wrap_v3.h"
+
+static spinlock_t wrp_lock;
+
+static uint32_t pwrap_check_idle(uintptr_t wacs_register, uintptr_t wacs_vldclr_register,
+				 uint32_t timeout_us)
+{
+	uint32_t reg_rdata = 0U, retry;
+
+	retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+	while (retry != 0) {
+		udelay(PWRAP_POLL_STEP_US);
+		reg_rdata = mmio_read_32(wacs_register);
+		/* if last read command timeout,clear vldclr bit
+		 * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+		 * write:FSM_REQ-->idle
+		 */
+		switch (GET_WACS_FSM(reg_rdata)) {
+		case SWINF_FSM_WFVLDCLR:
+			mmio_write_32(wacs_vldclr_register, 0x1);
+			INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+			break;
+		case SWINF_FSM_WFDLE:
+			INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+			break;
+		case SWINF_FSM_REQ:
+			INFO("WACS_FSM = SWINF_FSM_REQ\n");
+			break;
+		case SWINF_FSM_IDLE:
+			goto done;
+		default:
+			break;
+		}
+		retry--;
+	}
+
+done:
+	if (retry == 0) {
+		/* timeout */
+		return E_PWR_WAIT_IDLE_TIMEOUT;
+	}
+
+	return 0U;
+}
+
+static uint32_t pwrap_check_vldclr(uintptr_t wacs_register, uint32_t timeout_us)
+{
+	uint32_t reg_rdata = 0U, retry;
+
+	retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+	while (retry != 0) {
+		udelay(PWRAP_POLL_STEP_US);
+		reg_rdata = mmio_read_32(wacs_register);
+		if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_WFVLDCLR) {
+			break;
+		}
+		retry--;
+	}
+
+	if (retry == 0) {
+		/* timeout */
+		return E_PWR_WAIT_IDLE_TIMEOUT;
+	}
+
+	return 0U;
+}
+
+static int32_t pwrap_swinf_acc(uint32_t swinf_no, uint32_t cmd, uint32_t write,
+			       uint32_t pmifid, uint32_t slvid, uint32_t addr,
+			       uint32_t bytecnt, uint32_t wdata, uint32_t *rdata)
+{
+	uint32_t reg_rdata = 0x0;
+	int32_t ret = 0x0;
+
+	/* Check argument validation */
+	if ((swinf_no & ~(0x3)) != 0)
+		return -E_PWR_INVALID_SWINF;
+	if ((cmd & ~(0x3)) != 0)
+		return -E_PWR_INVALID_CMD;
+	if ((write & ~(0x1)) != 0)
+		return -E_PWR_INVALID_RW;
+	if ((pmifid & ~(0x1)) != 0)
+		return -E_PWR_INVALID_PMIFID;
+	if ((slvid & ~(0xf)) != 0)
+		return -E_PWR_INVALID_SLVID;
+	if ((addr & ~(0xffff)) != 0)
+		return -E_PWR_INVALID_ADDR;
+	if ((bytecnt & ~(0x1)) != 0)
+		return -E_PWR_INVALID_BYTECNT;
+	if ((wdata & ~(0xffff)) != 0)
+		return -E_PWR_INVALID_WDAT;
+
+	spin_lock(&wrp_lock);
+	/* Check whether INIT_DONE is set */
+	if (pmifid == 0)
+		reg_rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta));
+
+	if (GET_SWINF_INIT_DONE(reg_rdata) != 0x1) {
+		ERROR("[PWRAP] init not finish\n");
+		ret = -E_PWR_NOT_INIT_DONE;
+		goto end;
+	}
+
+	/* Wait for Software Interface FSM state to be IDLE */
+	ret = pwrap_check_idle((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta),
+			(uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), TIMEOUT_WAIT_IDLE);
+	if (ret != 0) {
+		ERROR("[PWRAP] fsm_idle fail\n");
+		goto end;
+	}
+
+	/* Set the write data */
+	if (write == 1) {
+		if (pmifid == 0)
+			mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].wdata), wdata);
+	}
+
+	/* Send the command */
+	if (pmifid == 0)
+		mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].cmd),
+			  (cmd << 30) | (write << 29) | (slvid << 24) | (bytecnt << 16) | addr);
+
+	if (write == 0) {
+		if (rdata == NULL) {
+			ERROR("[PWRAP] rdata null\n");
+			ret = -E_PWR_INVALID_ARG;
+			goto end;
+		}
+
+		/* Wait for Software Interface FSM to be WFVLDCLR */
+		/* read the data and clear the valid flag         */
+		ret = pwrap_check_vldclr((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), TIMEOUT_READ);
+		if (ret != 0) {
+			ERROR("[PWRAP] fsm_vldclr fail\n");
+			goto end;
+		}
+
+		if (pmifid == 0) {
+			*rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].rdata));
+			mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), 0x1);
+		}
+	}
+
+end:
+	spin_unlock(&wrp_lock);
+	if (ret < 0)
+		ERROR("%s fail, ret=%d\n", __func__, ret);
+	return ret;
+}
+
+/* external API for pmic_wrap user */
+
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+	return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 0, PMIF_SPI_PMIFID,
+		DEFAULT_SLVID, adr, DEFAULT_BYTECNT, 0x0, rdata);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+	return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 1, PMIF_SPI_PMIFID,
+		DEFAULT_SLVID, adr, DEFAULT_BYTECNT, wdata, 0x0);
+}
+
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift)
+{
+	uint32_t rdata;
+	int32_t ret;
+
+	if (!val)
+		return -E_PWR_INVALID_ARG;
+	ret = pwrap_read(reg, &rdata);
+	if (ret == 0x0)
+		*val = (rdata >> shift) & mask;
+
+	return ret;
+}
+
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift)
+{
+	uint32_t data;
+	int32_t ret;
+
+	ret = pwrap_read(reg, &data);
+	if (ret != 0)
+		return ret;
+
+	data = data & ~(mask << shift);
+	data |= (val << shift);
+	ret = pwrap_write(reg, data);
+
+	return ret;
+}
+
+#if PWRAP_DEBUG
+static int32_t pwrap_read_test(void)
+{
+	uint32_t rdata = 0;
+	int32_t ret;
+
+	ret = pwrap_read(DEW_READ_TEST, &rdata);
+	if (rdata != DEFAULT_VALUE_READ_TEST) {
+		ERROR("[PWRAP] Read fail,rdata=0x%x,exp=0x5aa5,ret=0x%x\n", rdata, ret);
+		return -E_PWR_READ_TEST_FAIL;
+	}
+	INFO("[PWRAP] Read Test pass,ret=%x\n", ret);
+	return 0;
+}
+
+static int32_t pwrap_write_test(void)
+{
+	uint32_t rdata = 0;
+	int32_t ret;
+	int32_t ret1;
+
+	ret = pwrap_write(DEW_WRITE_TEST, PWRAP_WRITE_TEST_VALUE);
+	ret1 = pwrap_read(DEW_WRITE_TEST, &rdata);
+	if ((rdata != PWRAP_WRITE_TEST_VALUE) || (ret != 0) || (ret1 != 0)) {
+		ERROR("[PWRAP] Write fail,rdata=0x%x,exp=0xa55a,ret=0x%x,ret1=0x%x\n",
+			rdata, ret, ret1);
+		return -E_PWR_WRITE_TEST_FAIL;
+	}
+	INFO("[PWRAP] Write Test pass\n");
+	return 0;
+}
+
+int32_t pmic_wrap_test(void)
+{
+	int32_t ret;
+
+	INFO("[PWRAP] Read/Write Test start\n");
+
+	ret = pwrap_read_test();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = pwrap_write_test();
+	if (ret != 0) {
+		return ret;
+	}
+	INFO("[PWRAP] Read/Write Test done\n");
+
+	return 0;
+}
+#endif

diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
new file mode 100644
index 0000000..075c2d5
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_V3_H
+#define PMIC_WRAP_V3_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+
+#define PMIF_REG_RANGE			(0x774)
+#define PMICSPI_MST_REG_RANGE		(0x80)
+#define DEFAULT_CMD			0
+#define DEFAULT_SLVID			0
+#define DEFAULT_BYTECNT			0
+#define PMIF_SPI_PMIFID			0
+/* #define PWRAP_DEBUG 1 */
+
+#if PWRAP_DEBUG
+#define PWRAP_LOG(fmts, args...) do {\
+		console_init(gteearg.atf_log_port, UART_CLOCK, UART_BAUDRATE);\
+		INFO("[%s:%d] -" fmts, __func__, __LINE__, ##args);\
+		console_uninit();\
+	} while (0)
+#endif
+
+/**********************************************************/
+#define DEFAULT_VALUE_READ_TEST		(0x5aa5)
+#define PWRAP_WRITE_TEST_VALUE		(0xa55a)
+#define PWRAP_POLL_STEP_US		(10)
+
+/* timeout setting */
+enum {
+	TIMEOUT_RESET		= 50,	/* us */
+	TIMEOUT_READ		= 50,	/* us */
+	TIMEOUT_WAIT_IDLE	= 50	/* us */
+};
+
+#endif /* PMIC_WRAP_V3_H */

diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk
index 9ba44a6..662c7e4 100644
--- a/plat/mediatek/drivers/pmic_wrap/rules.mk
+++ b/plat/mediatek/drivers/pmic_wrap/rules.mk

@@ -10,6 +10,8 @@
 
 ifeq (${USE_PMIC_WRAP_INIT_V2}, 1)
 LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c
+else ifeq (${USE_PMIC_WRAP_INIT_V3}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v3.c
 else
 LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c
 endif

diff --git a/plat/mediatek/drivers/slbc/mt8196/rules.mk b/plat/mediatek/drivers/slbc/mt8196/rules.mk
new file mode 100644
index 0000000..eabddfa
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/mt8196/rules.mk

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := slbc_$(MTK_SOC)
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/slbc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/slbc/mt8196/slbc.c b/plat/mediatek/drivers/slbc/mt8196/slbc.c
new file mode 100644
index 0000000..5f7b1e1
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/mt8196/slbc.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+#define MODULE_TAG "[SLBC]"
+
+enum {
+	MTK_SLBC_KERNEL_OP_CPU_DCC = 0,
+};
+
+static u_register_t slbc_kernel_handler(u_register_t x1, u_register_t x2,
+					u_register_t x3, u_register_t x4,
+					void *handle,
+					struct smccc_res *smccc_ret)
+{
+	uint32_t request_ops = (uint32_t)x1;
+	u_register_t ret = 0;
+
+	switch (request_ops) {
+	case MTK_SLBC_KERNEL_OP_CPU_DCC:
+		cpu_qos_change_dcc(x2, x3);
+		break;
+	default:
+		ERROR("%s: %s, unknown request_ops = %x\n", MODULE_TAG, __func__, request_ops);
+		ret = EIO;
+		break;
+	}
+
+	VERBOSE("%s: %s, request_ops = %x, ret = %lu\n", MODULE_TAG, __func__, request_ops, ret);
+	return ret;
+}
+
+/* Register SiP SMC service */
+DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_SLBC_CONTROL, slbc_kernel_handler);

diff --git a/plat/mediatek/drivers/slbc/rules.mk b/plat/mediatek/drivers/slbc/rules.mk
new file mode 100644
index 0000000..93fd1b8
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/rules.mk

@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := slbc
+
+LOCAL_SOC_DIR := $(LOCAL_DIR)/$(MTK_SOC)
+PLATFORM_DIR_EXIST := $(shell test -f $(LOCAL_SOC_DIR)/rules.mk && echo yes)
+
+ifeq ($(PLATFORM_DIR_EXIST), yes)
+SUB_RULES-y := $(LOCAL_SOC_DIR)
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
+endif

diff --git a/plat/mediatek/drivers/smmu/smmu.c b/plat/mediatek/drivers/smmu/smmu.c
index 4d31071..a3d83ec 100644
--- a/plat/mediatek/drivers/smmu/smmu.c
+++ b/plat/mediatek/drivers/smmu/smmu.c

@@ -255,9 +255,6 @@
 		break;
 	}
 
-	if (ret)
-		ERROR(TAG "%s, smmu_%u cmd:%u fail:%u\n", __func__, smmu_id, cmd_id, ret);
-
 	return ret;
 }
 /* Register MTK SMMU service */

diff --git a/plat/mediatek/drivers/smmu_sid/rules.mk b/plat/mediatek/drivers/smmu_sid/rules.mk
new file mode 100644
index 0000000..9c6dfc8
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/rules.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := smmu_sid
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/smmu_sid.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/smmu_sid_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/smmu_sid/smmu_sid.c b/plat/mediatek/drivers/smmu_sid/smmu_sid.c
new file mode 100644
index 0000000..2d852b6
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/smmu_sid.c

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_bl31_interface.h>
+
+static int mtk_smmu_sid_init(void)
+{
+	return smmu_sid_init();
+}
+
+MTK_PLAT_SETUP_0_INIT(mtk_smmu_sid_init);

diff --git a/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c b/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c
new file mode 100644
index 0000000..2ed162c
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+int smmu_sid_init(void)
+{
+	return 0;
+}

diff --git a/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
new file mode 100644
index 0000000..417f779
--- /dev/null
+++ b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c

@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <drivers/spmi/pmif_common.h>
+#include <drivers/spmi/pmif_v1/pmif.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi/spmi_sw.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_mmap_pool.h>
+
+#define SPMI_GROUP_ID	0xB
+#define SPMI_DEBUG	0
+
+static uint16_t mt6xxx_regs[] = {
+	[PMIF_INIT_DONE] =			0x0000,
+	[PMIF_INF_EN] =				0x0024,
+	[PMIF_ARB_EN] =				0x0150,
+	[PMIF_IRQ_EVENT_EN_0] =			0x0420,
+	[PMIF_IRQ_FLAG_0] =			0x0428,
+	[PMIF_IRQ_CLR_0] =			0x042C,
+	[PMIF_IRQ_EVENT_EN_2] =			0x0440,
+	[PMIF_IRQ_FLAG_2] =			0x0448,
+	[PMIF_IRQ_CLR_2] =			0x044C,
+	[PMIF_WDT_CTRL] =			0x0470,
+	[PMIF_WDT_EVENT_EN_1] =			0x047C,
+	[PMIF_WDT_FLAG_1] =			0x0480,
+	[PMIF_SWINF_2_ACC] =			0x0880,
+	[PMIF_SWINF_2_WDATA_31_0] =		0x0884,
+	[PMIF_SWINF_2_WDATA_63_32] =		0x0888,
+	[PMIF_SWINF_2_RDATA_31_0] =		0x0894,
+	[PMIF_SWINF_2_RDATA_63_32] =		0x0898,
+	[PMIF_SWINF_2_VLD_CLR] =		0x08A4,
+	[PMIF_SWINF_2_STA] =			0x08A8,
+	[PMIF_SWINF_3_ACC] =			0x08C0,
+	[PMIF_SWINF_3_WDATA_31_0] =		0x08C4,
+	[PMIF_SWINF_3_WDATA_63_32] =		0x08C8,
+	[PMIF_SWINF_3_RDATA_31_0] =		0x08D4,
+	[PMIF_SWINF_3_RDATA_63_32] =		0x08D8,
+	[PMIF_SWINF_3_VLD_CLR] =		0x08E4,
+	[PMIF_SWINF_3_STA] =			0x08E8,
+	/* hw mpu */
+	[PMIF_PMIC_ALL_RGN_EN_1] =		0x09B0,
+	[PMIF_PMIC_ALL_RGN_EN_2] =		0x0D30,
+	[PMIF_PMIC_ALL_RGN_0_START] =		0x09B4,
+	[PMIF_PMIC_ALL_RGN_0_END] =		0x09B8,
+	[PMIF_PMIC_ALL_RGN_1_START] =		0x09BC,
+	[PMIF_PMIC_ALL_RGN_1_END] =		0x09C0,
+	[PMIF_PMIC_ALL_RGN_2_START] =		0x09C4,
+	[PMIF_PMIC_ALL_RGN_2_END] =		0x09C8,
+	[PMIF_PMIC_ALL_RGN_3_START] =		0x09CC,
+	[PMIF_PMIC_ALL_RGN_3_END] =		0x09D0,
+	[PMIF_PMIC_ALL_RGN_31_START] =		0x0D34,
+	[PMIF_PMIC_ALL_RGN_31_END] =		0x0D38,
+	[PMIF_PMIC_ALL_INVLD_SLVID] =		0x0AAC,
+	[PMIF_PMIC_ALL_RGN_0_PER0] =		0x0AB0,
+	[PMIF_PMIC_ALL_RGN_0_PER1] =		0x0AB4,
+	[PMIF_PMIC_ALL_RGN_1_PER0] =		0x0AB8,
+	[PMIF_PMIC_ALL_RGN_2_PER0] =		0x0AC0,
+	[PMIF_PMIC_ALL_RGN_3_PER0] =		0x0AC8,
+	[PMIF_PMIC_ALL_RGN_31_PER0] =		0x0E34,
+	[PMIF_PMIC_ALL_RGN_31_PER1] =		0x0E38,
+	[PMIF_PMIC_ALL_RGN_OTHERS_PER0] =	0x0BA8,
+	[PMIF_PMIC_ALL_RGN_OTHERS_PER1] =	0x0BAC,
+};
+
+static uint16_t mt6xxx_spmi_regs[] = {
+	[SPMI_OP_ST_CTRL] =		0x0000,
+	[SPMI_GRP_ID_EN] =		0x0004,
+	[SPMI_OP_ST_STA] =		0x0008,
+	[SPMI_MST_SAMPL] =		0x000c,
+	[SPMI_MST_REQ_EN] =		0x0010,
+	[SPMI_RCS_CTRL] =		0x0014,
+	[SPMI_SLV_3_0_EINT] =		0x0020,
+	[SPMI_SLV_7_4_EINT] =		0x0024,
+	[SPMI_SLV_B_8_EINT] =		0x0028,
+	[SPMI_SLV_F_C_EINT] =		0x002c,
+	[SPMI_REC_CTRL] =		0x0040,
+	[SPMI_REC0] =			0x0044,
+	[SPMI_REC1] =			0x0048,
+	[SPMI_REC2] =			0x004c,
+	[SPMI_REC3] =			0x0050,
+	[SPMI_REC4] =			0x0054,
+	[SPMI_REC_CMD_DEC] =		0x005c,
+	[SPMI_DEC_DBG] =		0x00f8,
+	[SPMI_MST_DBG] =		0x00fc,
+};
+
+struct pmif pmif_spmi_arb[] = {
+	{
+		.regs = mt6xxx_regs,
+		.spmimst_regs = mt6xxx_spmi_regs,
+		.mstid = SPMI_MASTER_0,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+	},
+	{
+		.regs = mt6xxx_regs,
+		.spmimst_regs = mt6xxx_spmi_regs,
+		.mstid = SPMI_MASTER_1,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+	},
+	{
+		.base = (unsigned int *)PMIF_SPMI_P_BASE,
+		.regs = mt6xxx_regs,
+		.spmimst_base = (unsigned int *)SPMI_MST_P_BASE,
+		.spmimst_regs = mt6xxx_spmi_regs,
+		.mstid = SPMI_MASTER_P_1,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+	},
+};
+
+static struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_7, /* MT6319 */
+		.grpiden = 0x800,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+		.mstid = SPMI_MASTER_P_1,/* spmi-p */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0B,
+		.swcid_val = 0x15,
+		.wpk_key_addr = 0x3A8,
+		.wpk_key_val = 0x6315,
+		.tma_key_addr = 0x39F,
+		.tma_key_val = 0x9CEA,
+		.pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+	},
+	{
+		.slvid = SPMI_SLAVE_8, /* MT6319 */
+		.grpiden = 0x800,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+		.mstid = SPMI_MASTER_P_1,/* spmi-p */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0B,
+		.swcid_val = 0x15,
+		.wpk_key_addr = 0x3A8,
+		.wpk_key_val = 0x6315,
+		.tma_key_addr = 0x39F,
+		.tma_key_val = 0x9CEA,
+		.pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+	},
+};
+
+int platform_pmif_spmi_init(void)
+{
+/*
+ * The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
+ * MT8189G variant uses a single PMIC IC (MT6319), whereas the MT8189H
+ * variant uses two PMIC ICs. To ensure driver compatibility, we utilize
+ * the CPU ID and segment ID to accurately determine the required number
+ * of SPMIF instances.
+ */
+	if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+	    mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189G)
+		spmi_device_register(spmi_dev, 1);
+	else
+		spmi_device_register(spmi_dev, ARRAY_SIZE(spmi_dev));
+
+	return 0;
+}
+MTK_ARCH_INIT(platform_pmif_spmi_init);

diff --git a/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c b/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c
new file mode 100644
index 0000000..2db07bf
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/pmic/pmic_set_lowpower.h>
+#if defined(CONFIG_MTK_MTCMOS)
+#include <mtcmos.h>
+#endif
+#include <mtk_bl31_interface.h>
+
+static void ufs_vsx_lpm(bool lpm, uint64_t ufs_version)
+{
+	if (lpm) {
+		/* MT6363 VS2 voter LOW byte BIT6 vote reduce VS2 voltage */
+		PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_CLR);
+
+		/* VS2 buck can enter LPM */
+		PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP);
+	} else {
+		/* MT6363 VS2 voter LOW byte BIT6 vote raise VS2 voltage */
+		PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_SET);
+
+		/* VS2 buck can not enter LPM */
+		PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_ONLV);
+	}
+}
+
+void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version)
+{
+	if (vcc_on)
+		ufs_vsx_lpm(false, ufs_version);
+	else
+		ufs_vsx_lpm(true, ufs_version);
+}
+
+int ufs_spm_mtcmos_power(bool on)
+{
+#if defined(CONFIG_MTK_MTCMOS)
+	return spm_mtcmos_ctrl_ufs0(on ? STA_POWER_ON : STA_POWER_DOWN);
+#else
+	return 0;
+#endif
+}
+
+int ufs_phy_spm_mtcmos_power(bool on)
+{
+#if defined(CONFIG_MTK_MTCMOS)
+	return spm_mtcmos_ctrl_ufs0_phy(on ? STA_POWER_ON : STA_POWER_DOWN);
+#else
+	return 0;
+#endif
+}

diff --git a/plat/mediatek/drivers/ufs/rules.mk b/plat/mediatek/drivers/ufs/rules.mk
new file mode 100644
index 0000000..13d3f53
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/rules.mk

@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := ufs
+
+PLAT_INCLUDES += -I$(LOCAL_DIR)
+PLAT_INCLUDES += -I$(MTK_PLAT)/include/drivers/
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/ufs_ctrl.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/$(MTK_SOC)/ufs_ctrl_soc.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/ufs_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/ufs/ufs_ctrl.c b/plat/mediatek/drivers/ufs/ufs_ctrl.c
new file mode 100644
index 0000000..14d0616
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/ufs_ctrl.c

@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+/* MTK header */
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lpm_v2/mt_lp_api.h>
+#include <lpm_v2/mt_lp_rq.h>
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+/* UFS generic control flags */
+#define UFS_MTK_SIP_VA09_PWR_CTRL		BIT(0)
+#define UFS_MTK_SIP_DEVICE_RESET		BIT(1)
+#define UFS_MTK_SIP_CRYPTO_CTRL			BIT(2)
+#define UFS_MTK_SIP_REF_CLK_NOTIFICATION	BIT(3)
+#define UFS_MTK_SIP_SRAM_PWR_CTRL		BIT(5)
+#define UFS_MTK_SIP_GET_VCC_INFO		BIT(6)
+#define UFS_MTK_SIP_DEVICE_PWR_CTRL		BIT(7)
+#define UFS_MTK_SIP_MPHY_CTRL			BIT(8)
+#define UFS_MTK_SIP_MTCMOS_CTRL			BIT(9)
+
+enum {
+	VCC_NONE = 0,
+	VCC_1,
+	VCC_2,
+};
+
+static void ufs_get_vcc_info(struct smccc_res *smccc_ret)
+{
+	if (smccc_ret == NULL)
+		return;
+
+	if (is_second_pmic_pp_swap())
+		smccc_ret->a1 = VCC_2;
+	else
+		smccc_ret->a1 = VCC_1;
+}
+
+/* SPM resource control */
+#define RSC_MEM			(MT_LP_RQ_DRAM | MT_LP_RQ_EMI)
+#define RSC_PMIC		MT_LP_RQ_PMIC
+
+static int ufs_rsc_ctrl(unsigned int rsc, bool hold)
+{
+	static struct mt_lp_resource_user ufs_res_user;
+	int ret = -1;
+
+	if (!ufs_res_user.uid) {
+		ret = mt_lp_resource_user_register("UFS", &ufs_res_user);
+
+		if (ret) {
+			WARN("%s: register lp resource failed\n", __func__);
+			return ret;
+		}
+	}
+
+	if (hold)
+		ret = ufs_res_user.request(&ufs_res_user, rsc);
+	else
+		ret = ufs_res_user.release(&ufs_res_user);
+
+	VERBOSE("%s: rsc=%d, hold=%d\n", __func__, rsc, hold);
+
+	if (ret)
+		WARN("%s: RSC_%d %s failed\n", __func__, rsc, hold ? "request" : "release");
+
+	return ret;
+}
+
+int ufs_rsc_ctrl_mem(bool hold)
+{
+	return ufs_rsc_ctrl(RSC_MEM, hold);
+}
+
+int ufs_rcs_ctrl_pmic(bool hold)
+{
+	return ufs_rsc_ctrl(RSC_PMIC, hold);
+}
+
+/* UFS clock status */
+static uint32_t ufs_clk_sta = UFS_REF_CLK_ON;
+
+bool ufs_is_clk_status_off(void)
+{
+	return ufs_clk_sta == UFS_REF_CLK_OFF;
+}
+
+void ufs_set_clk_status(bool on)
+{
+	if (on)
+		ufs_clk_sta = UFS_REF_CLK_ON;
+	else
+		ufs_clk_sta = UFS_REF_CLK_OFF;
+}
+
+static u_register_t ufs_knl_ctrl(u_register_t x1,
+				 u_register_t x2,
+				 u_register_t x3,
+				 u_register_t x4,
+				 void *handle,
+				 struct smccc_res *smccc_ret)
+{
+	uint64_t ret = 0;
+
+	switch (x1) {
+	case UFS_MTK_SIP_VA09_PWR_CTRL:
+		ufs_mphy_va09_cg_ctrl(!!x2);
+		break;
+	case UFS_MTK_SIP_DEVICE_RESET:
+		ufs_device_reset_ctrl(!!x2);
+		break;
+	case UFS_MTK_SIP_CRYPTO_CTRL:
+		ufs_crypto_hie_init();
+		break;
+	case UFS_MTK_SIP_REF_CLK_NOTIFICATION:
+		ufs_ref_clk_status(x2, x3);
+		break;
+	case UFS_MTK_SIP_SRAM_PWR_CTRL:
+		ufs_sram_pwr_ctrl(x2);
+		break;
+	case UFS_MTK_SIP_GET_VCC_INFO:
+		ufs_get_vcc_info(smccc_ret);
+		break;
+	case UFS_MTK_SIP_DEVICE_PWR_CTRL:
+		ufs_device_pwr_ctrl(x2, x3);
+		break;
+	case UFS_MTK_SIP_MPHY_CTRL:
+		ufs_mphy_ctrl(x2);
+		break;
+	case UFS_MTK_SIP_MTCMOS_CTRL:
+#if defined(CONFIG_MTK_MTCMOS)
+		ufs_mtcmos_ctrl(!!x2);
+#endif
+		break;
+	default:
+		ret = -1;
+		WARN("[UFS] invalid argument 0x%lx from kernel\n", x1);
+		break;
+	}
+
+	return ret;
+}
+
+static u_register_t ufs_bl_ctrl(u_register_t x1,
+				u_register_t x2,
+				u_register_t x3,
+				u_register_t x4,
+				void *handle,
+				struct smccc_res *smccc_ret)
+{
+	uint64_t ret = 0;
+
+	switch (x1) {
+	case UFS_MTK_SIP_DEVICE_RESET:
+		ufs_device_reset_ctrl(x2);
+		break;
+	default:
+		ret = -1;
+		WARN("[UFS] invalid argument 0x%lx from bootloader\n", x1);
+		break;
+	}
+
+	return ret;
+}
+
+DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_UFS_CONTROL, ufs_knl_ctrl);
+DECLARE_SMC_HANDLER(MTK_SIP_BL_UFS_CONTROL, ufs_bl_ctrl);

diff --git a/plat/mediatek/drivers/ufs/ufs_stub.c b/plat/mediatek/drivers/ufs/ufs_stub.c
new file mode 100644
index 0000000..c03f27e
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/ufs_stub.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+void ufs_mphy_va09_cg_ctrl(bool enable) {}
+void ufs_device_reset_ctrl(bool rst_n) {}
+void ufs_crypto_hie_init(void) {}
+void ufs_ref_clk_status(uint32_t on, enum ufs_notify_change_status stage) {}
+void ufs_sram_pwr_ctrl(bool on) {}
+void ufs_device_pwr_ctrl(bool vcc_on, uint64_t ufs_version) {}
+void ufs_mphy_ctrl(enum ufs_mtk_mphy_op op) {}
+void ufs_mtcmos_ctrl(bool on) {}

diff --git a/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
new file mode 100644
index 0000000..71a2d2b
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h

@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6319_LOWPOWER_REG_H
+#define MT6319_LOWPOWER_REG_H
+
+#define MT6319_RG_LDO_VDIG18_SW_OP_EN_ADDR		0x0196
+#define MT6319_RG_LDO_VDIG18_HW_OP_EN_ADDR		0x0196
+#define MT6319_RG_VDIG18_PWROFF_OP_EN_ADDR		0x0197
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_SW_OP_EN_ADDR		0x1490
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_SW_OP_EN_ADDR		0x1510
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_MODE_ADD		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_SW_OP_EN_ADDR		0x1590
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_SW_OP_EN_ADDR		0x1610
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_MODE_ADDR		0x1729
+
+#endif /* MT6319_LOWPOWER_REG_H */

diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
new file mode 100644
index 0000000..7e14f00
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h

@@ -0,0 +1,1593 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_LOWPOWER_REG_H
+#define MT6359P_LOWPOWER_REG_H
+
+#define MT6359P_RG_BUCK_VPU_VOSEL_SLEEP_ADDR			0x148e
+#define MT6359P_RG_BUCK_VPU_HW0_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW1_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW2_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW3_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW4_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW5_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW6_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW7_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW8_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW9_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW10_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW11_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW12_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW13_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW14_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_SW_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW0_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW1_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW2_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW3_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW4_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW5_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW6_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW7_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW8_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW9_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW10_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW11_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW12_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW13_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW14_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_SHIFT			10
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_SHIFT			11
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_SHIFT			12
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_SHIFT			13
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_SHIFT			14
+#define MT6359P_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR			0x150e
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_SW_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VGPU11_VOSEL_SLEEP_ADDR			0x158e
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_SW_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VGPU12_VOSEL_SLEEP_ADDR			0x160e
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_SW_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR			0x168e
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_SW_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VPROC1_VOSEL_SLEEP_ADDR			0x170e
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_SW_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VPROC2_VOSEL_SLEEP_ADDR			0x178e
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_SW_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VS1_VOSEL_SLEEP_ADDR			0x180e
+#define MT6359P_RG_BUCK_VS1_HW0_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW1_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW2_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW3_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW4_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW5_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW6_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW7_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW8_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW9_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW10_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW11_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW12_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW13_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW14_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_SW_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW0_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW1_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW2_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW3_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW4_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW5_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW6_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW7_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW8_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW9_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW10_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW11_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW12_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW13_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW14_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_SHIFT			10
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_SHIFT			11
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_SHIFT			12
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_SHIFT			13
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_SHIFT			14
+#define MT6359P_RG_BUCK_VS2_VOSEL_SLEEP_ADDR			0x188e
+#define MT6359P_RG_BUCK_VS2_HW0_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW1_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW2_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW3_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW4_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW5_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW6_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW7_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW8_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW9_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW10_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW11_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW12_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW13_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW14_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_SW_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW0_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW1_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW2_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW3_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW4_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW5_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW6_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW7_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW8_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW9_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW10_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW11_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW12_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW13_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW14_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_SHIFT			10
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_SHIFT			11
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_SHIFT			12
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_SHIFT			13
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_SHIFT			14
+#define MT6359P_RG_LDO_VFE28_OP_MODE_ADDR			0x1b8a
+#define MT6359P_RG_LDO_VFE28_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VFE28_HW0_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW1_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW2_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW3_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW4_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW5_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW6_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW7_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW8_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW9_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW10_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW11_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW12_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW13_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW14_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_SW_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW0_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW1_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW2_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW3_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW4_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW5_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW6_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW7_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW8_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW9_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW10_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW11_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW12_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW13_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW14_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_SW_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VXO22_OP_MODE_ADDR			0x1b9c
+#define MT6359P_RG_LDO_VXO22_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VXO22_HW0_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW1_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW2_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW3_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW4_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW5_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW6_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW7_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW8_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW9_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW10_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW11_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW12_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW13_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW14_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_SW_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW0_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW1_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW2_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW3_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW4_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW5_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW6_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW7_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW8_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW9_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW10_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW11_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW12_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW13_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW14_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_SW_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VRF18_OP_MODE_ADDR			0x1bae
+#define MT6359P_RG_LDO_VRF18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VRF18_HW0_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW1_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW2_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW3_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW4_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW5_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW6_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW7_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW8_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW9_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW10_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW11_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW12_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW13_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW14_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_SW_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW0_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW1_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW2_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW3_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW4_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW5_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW6_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW7_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW8_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW9_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW10_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW11_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW12_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW13_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW14_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_SW_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF12_OP_MODE_ADDR			0x1bc0
+#define MT6359P_RG_LDO_VRF12_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VRF12_HW0_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW1_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW2_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW3_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW4_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW5_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW6_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW7_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW8_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW9_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW10_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW11_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW12_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW13_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW14_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_SW_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW0_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW1_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW2_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW3_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW4_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW5_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW6_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW7_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW8_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW9_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW10_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW11_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW12_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW13_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW14_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_SW_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_ADDR			0x1bd2
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_ADDR			0x1be4
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_ADDR			0x1c0a
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN13_OP_MODE_ADDR			0x1c1e
+#define MT6359P_RG_LDO_VCN13_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN13_HW0_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW1_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW2_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW3_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW4_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW5_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW6_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW7_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW8_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW9_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW10_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW11_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW12_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW13_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW14_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_SW_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW0_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW1_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW2_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW3_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW4_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW5_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW6_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW7_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW8_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW9_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW10_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW11_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW12_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW13_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW14_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_SW_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN18_OP_MODE_ADDR			0x1c30
+#define MT6359P_RG_LDO_VCN18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN18_HW0_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW1_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW2_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW3_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW4_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW5_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW6_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW7_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW8_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW9_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW10_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW11_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW12_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW13_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW14_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_SW_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW0_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW1_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW2_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW3_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW4_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW5_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW6_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW7_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW8_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW9_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW10_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW11_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW12_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW13_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW14_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_SW_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VA09_OP_MODE_ADDR			0x1c42
+#define MT6359P_RG_LDO_VA09_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VA09_HW0_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW1_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW2_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW3_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW4_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW5_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW6_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW7_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW8_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW9_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW10_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW11_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW12_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW13_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW14_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_SW_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW0_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW1_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW2_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW3_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW4_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW5_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW6_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW7_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW8_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW9_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW10_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW11_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW12_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW13_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW14_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_SW_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_ADDR			0x1c54
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VA12_OP_MODE_ADDR			0x1c66
+#define MT6359P_RG_LDO_VA12_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VA12_HW0_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW1_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW2_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW3_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW4_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW5_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW6_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW7_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW8_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW9_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW10_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW11_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW12_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW13_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW14_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_SW_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW0_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW1_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW2_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW3_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW4_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW5_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW6_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW7_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW8_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW9_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW10_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW11_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW12_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW13_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW14_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_SW_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_ADDR			0x1c8a
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_SW_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_SW_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_ADDR			0x1c9c
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_SW_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_SW_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VIO18_OP_MODE_ADDR			0x1cae
+#define MT6359P_RG_LDO_VIO18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VIO18_HW0_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW1_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW2_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW3_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW4_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW5_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW6_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW7_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW8_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW9_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW10_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW11_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW12_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW13_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW14_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_SW_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW0_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW1_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW2_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW3_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW4_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW5_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW6_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW7_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW8_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW9_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW10_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW11_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW12_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW13_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW14_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_SW_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VEMC_OP_MODE_ADDR			0x1cc0
+#define MT6359P_RG_LDO_VEMC_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VEMC_HW0_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW1_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW2_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW3_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW4_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW5_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW6_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW7_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW8_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW9_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW10_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW11_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW12_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW13_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW14_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_SW_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW0_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW1_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW2_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW3_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW4_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW5_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW6_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW7_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW8_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW9_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW10_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW11_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW12_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW13_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW14_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_SW_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_ADDR			0x1cd2
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_SW_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_SW_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_ADDR			0x1ce4
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_SW_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_SW_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VUSB_OP_MODE_ADDR			0x1d0a
+#define MT6359P_RG_LDO_VUSB_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VUSB_HW0_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW1_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW2_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW3_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW4_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW5_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW6_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW7_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW8_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW9_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW10_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW11_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW12_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW13_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW14_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_SW_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW0_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW1_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW2_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW3_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW4_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW5_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW6_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW7_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW8_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW9_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW10_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW11_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW12_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW13_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW14_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_SW_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_ADDR			0x1d1e
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_SW_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_SW_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_ADDR			0x1d30
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_SW_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_SW_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_ADDR			0x1d42
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_SW_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_SW_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VIBR_OP_MODE_ADDR			0x1d54
+#define MT6359P_RG_LDO_VIBR_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VIBR_HW0_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW1_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW2_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW3_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW4_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW5_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW6_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW7_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW8_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW9_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW10_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW11_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW12_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW13_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW14_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_SW_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW0_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW1_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW2_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW3_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW4_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW5_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW6_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW7_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW8_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW9_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW10_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW11_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW12_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW13_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW14_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_SW_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIO28_OP_MODE_ADDR			0x1d66
+#define MT6359P_RG_LDO_VIO28_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VIO28_HW0_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW1_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW2_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW3_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW4_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW5_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW6_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW7_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW8_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW9_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW10_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW11_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW12_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW13_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW14_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_SW_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW0_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW1_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW2_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW3_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW4_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW5_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW6_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW7_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW8_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW9_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW10_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW11_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW12_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW13_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW14_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_SW_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VM18_OP_MODE_ADDR			0x1d8a
+#define MT6359P_RG_LDO_VM18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VM18_HW0_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW1_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW2_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW3_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW4_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW5_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW6_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW7_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW8_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW9_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW10_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW11_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW12_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW13_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW14_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_SW_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW0_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW1_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW2_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW3_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW4_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW5_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW6_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW7_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW8_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW9_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW10_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW11_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW12_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW13_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW14_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_SW_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VUFS_OP_MODE_ADDR			0x1d9c
+#define MT6359P_RG_LDO_VUFS_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VUFS_HW0_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW1_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW2_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW3_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW4_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW5_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW6_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW7_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW8_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW9_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW10_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW11_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW12_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW13_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW14_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_SW_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW0_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW1_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW2_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW3_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW4_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW5_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW6_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW7_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW8_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW9_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW10_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW11_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW12_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW13_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW14_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_SW_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_ADDR			0x1e8a
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_SHIFT		10
+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_ADDR		0x1e8e
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_ADDR			0x1eaa
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_SHIFT		10
+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_ADDR		0x1eae
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_ADDR		0x1f0a
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_SHIFT		10
+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR		0x1f0e
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR	0x1f28
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_ADDR			0x1f30
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR		0x1f34
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_CFG_ADDR			0x1f42
+
+#endif /* MT6359P_LOWPOWER_REG_H */

diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
new file mode 100644
index 0000000..60b49bf
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_SET_LOWPOWER_H
+#define MT6359P_SET_LOWPOWER_H
+
+#include <stdint.h>
+
+#include "mt6359p_lowpower_reg.h"
+#include <pmic_wrap_init_common.h>
+
+#define OP_MODE_MU	(0)
+#define OP_MODE_LP	(1)
+
+#define HW_OFF		(0)
+#define HW_ON		(0)
+#define HW_LP		(1)
+
+enum {
+	HW0 = 0,
+	HW1,
+	HW2,
+	HW3,
+	HW4,
+	HW5,
+	HW6,
+	HW7,
+	HW8,
+	HW9,
+	HW10,
+	HW11,
+	HW12,
+	HW13,
+	HW14,
+};
+
+#define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+	pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+			      1 << _user, \
+			      (_cfg & 0x1) ? 1 << _user : 0); \
+	pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+			      1 << _user, \
+			      _mode ? 1 << _user : 0); \
+	pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+			      1 << _user, \
+			      _en ? 1 << _user : 0); \
+}
+
+#define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+	if (_user <= HW2) { \
+		pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_OP_MODE_ADDR, \
+			1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT), \
+			_mode ? 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT) : 0); \
+	} \
+	pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
+			      1 << _user, \
+			      (_cfg & 0x1) ? 1 << _user : 0); \
+	pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
+			      1 << _user, \
+			      _en ? 1 << _user : 0); \
+}
+
+static inline int pmic_wrap_update_bits(uint32_t reg, uint32_t mask, uint32_t val)
+{
+	uint32_t orig = 0;
+	int ret = 0;
+
+	ret = pwrap_read(reg, &orig);
+	if (ret < 0)
+		return ret;
+
+	orig &= ~mask;
+	orig |= val & mask;
+
+	ret = pwrap_write(reg, orig);
+	return ret;
+}
+
+#endif /* MT6359P_MT6359P_SET_LOWPOWER_H */

diff --git a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
index f79612d..4f0517f 100644
--- a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
+++ b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h

@@ -12,6 +12,7 @@
 #include <drivers/spmi_api.h>
 
 #include "mt6316_lowpower_reg.h"
+#include "mt6319_lowpower_reg.h"
 #include "mt6363_lowpower_reg.h"
 #include "mt6373_lowpower_reg.h"
 

diff --git a/plat/mediatek/include/mtk_bl31_interface.h b/plat/mediatek/include/mtk_bl31_interface.h
new file mode 100644
index 0000000..208276c
--- /dev/null
+++ b/plat/mediatek/include/mtk_bl31_interface.h

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_BL31_INTERFACE_H__
+#define __MTK_BL31_INTERFACE_H__
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+enum mtk_bl31_status {
+	MTK_BL31_STATUS_SUCCESS = 0,
+	MTK_BL31_STATUS_INVALID_PARAM = -1,
+	MTK_BL31_STATUS_NOT_SUPPORTED = -2,
+	MTK_BL31_STATUS_INVALID_RANGE = -3,
+	MTK_BL31_STATUS_PERMISSION_DENY = -4,
+	MTK_BL31_STATUS_LOCK_FAIL = -5,
+};
+
+int mtk_bl31_map_to_sip_error(enum mtk_bl31_status status);
+
+enum mtk_bl31_memory_type {
+	MTK_BL31_DEV_RW_SEC = 0,
+};
+
+int mtk_bl31_mmap_add_dynamic_region(unsigned long long base_pa, size_t size,
+				     enum mtk_bl31_memory_type attr);
+int mtk_bl31_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
+
+/* UFS definitions */
+enum ufs_mtk_mphy_op {
+	UFS_MPHY_BACKUP = 0,
+	UFS_MPHY_RESTORE,
+};
+
+enum ufs_notify_change_status {
+	PRE_CHANGE,
+	POST_CHANGE,
+};
+
+/* UFS interfaces */
+void ufs_mphy_va09_cg_ctrl(bool enable);
+void ufs_device_reset_ctrl(bool rst_n);
+void ufs_crypto_hie_init(void);
+void ufs_ref_clk_status(uint32_t on, enum ufs_notify_change_status stage);
+void ufs_sram_pwr_ctrl(bool on);
+void ufs_device_pwr_ctrl(bool vcc_on, uint64_t ufs_version);
+void ufs_mphy_ctrl(enum ufs_mtk_mphy_op op);
+void ufs_mtcmos_ctrl(bool on);
+
+/* UFS functions implemented in the public ATF repo */
+int ufs_rsc_ctrl_mem(bool hold);
+int ufs_rsc_ctrl_pmic(bool hold);
+void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version);
+int ufs_spm_mtcmos_power(bool on);
+int ufs_phy_spm_mtcmos_power(bool on);
+bool ufs_is_clk_status_off(void);
+void ufs_set_clk_status(bool on);
+
+/* EMI interfaces */
+uint64_t emi_mpu_read_addr(unsigned int region, unsigned int offset);
+uint64_t emi_mpu_read_enable(unsigned int region);
+uint64_t emi_mpu_read_aid(unsigned int region, unsigned int aid_shift);
+uint64_t emi_mpu_check_ns_cpu(void);
+enum mtk_bl31_status emi_mpu_set_protection(uint32_t start, uint32_t end,
+					    unsigned int region);
+enum mtk_bl31_status emi_kp_set_protection(size_t start, size_t end, unsigned int region);
+enum mtk_bl31_status emi_kp_clear_violation(unsigned int emiid);
+enum mtk_bl31_status emi_clear_protection(unsigned int region);
+enum mtk_bl31_status emi_clear_md_violation(void);
+uint64_t emi_mpu_check_region_info(unsigned int region, uint64_t *sa, uint64_t *ea);
+uint64_t emi_mpu_page_base_region(void);
+uint64_t emi_mpu_smc_hp_mod_check(void);
+enum mtk_bl31_status slb_clear_violation(unsigned int id);
+enum mtk_bl31_status emi_clear_violation(unsigned int id, unsigned int type);
+enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port);
+enum mtk_bl31_status slc_parity_clear(unsigned int id);
+enum mtk_bl31_status emi_mpu_set_aid(unsigned int region, unsigned int num);
+void emi_protection_init(void);
+
+/* CPU QoS interfaces */
+void cpu_qos_change_dcc(uint32_t on, uint32_t is_auto);
+void *cpu_qos_handle_cluster_on_event(const void *arg);
+
+/* SMMU sid interfaces */
+int smmu_sid_init(void);
+
+#endif /* __MTK_BL31_INTERFACE_H__ */

diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index 4d5a100..a41c205 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk

@@ -21,7 +21,7 @@
 
 PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c		\
-				plat/arm/common/arm_gicv2.c			\
+				plat/common/plat_gicv2_base.c			\
 				plat/common/plat_gicv2.c			\
 				plat/common/aarch64/crash_console_helpers.S
 

diff --git a/plat/mediatek/mt8186/include/plat_macros.S b/plat/mediatek/mt8186/include/plat_macros.S
deleted file mode 100644
index 39727ea..0000000
--- a/plat/mediatek/mt8186/include/plat_macros.S
+++ /dev/null

@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <platform_def.h>
-
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
-	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
-		" Offset:\t\t\tvalue\n"
-newline:
-	.asciz "\n"
-spacer:
-	.asciz ":\t\t0x"
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
-	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
-	/* ---------------------------------------------
-	 * The below macro prints out relevant GIC
-	 * registers whenever an unhandled exception
-	 * is taken in BL31.
-	 * Clobbers: x0 - x10, x26, x27, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_crash_print_regs
-	/* TODO: leave implementation to GIC owner */
-	.endm
-
-#endif /* PLAT_MACROS_S */

diff --git a/plat/mediatek/mt8186/include/plat_private.h b/plat/mediatek/mt8186/include/plat_private.h
deleted file mode 100644
index 7ef2b85..0000000
--- a/plat/mediatek/mt8186/include/plat_private.h
+++ /dev/null

@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_PRIVATE_H
-#define PLAT_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void plat_configure_mmu_el3(uintptr_t total_base,
-			    uintptr_t total_size,
-			    uintptr_t ro_start,
-			    uintptr_t ro_limit);
-
-#endif /* PLAT_PRIVATE_H */

diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 9c03340..3ac4b29 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2024, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2025, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -11,6 +11,7 @@
 TRNG_SUPPORT := 1
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/include                     \
                  -I${MTK_PLAT}/drivers/cirq/                      \
                  -I${MTK_PLAT}/drivers/gic600/                    \
                  -I${MTK_PLAT}/drivers/gpio/                      \

diff --git a/plat/mediatek/mt8188/include/plat_macros.S b/plat/mediatek/mt8188/include/plat_macros.S
deleted file mode 100644
index a6e05a9..0000000
--- a/plat/mediatek/mt8188/include/plat_macros.S
+++ /dev/null

@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <platform_def.h>
-
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
-	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
-		" Offset:\t\t\tvalue\n"
-newline:
-	.asciz "\n"
-spacer:
-	.asciz ":\t\t0x"
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
-	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
-	/* ---------------------------------------------
-	 * The below macro prints out relevant GIC
-	 * registers whenever an unhandled exception
-	 * is taken in BL31.
-	 * Clobbers: x0 - x10, x26, x27, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_crash_print_regs
-	/* TODO: leave implementation to GIC owner */
-	.endm
-
-#endif /* PLAT_MACROS_S */

diff --git a/plat/mediatek/mt8188/include/plat_private.h b/plat/mediatek/mt8188/include/plat_private.h
deleted file mode 100644
index 4d4ac85..0000000
--- a/plat/mediatek/mt8188/include/plat_private.h
+++ /dev/null

@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_PRIVATE_H
-#define PLAT_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void plat_configure_mmu_el3(uintptr_t total_base,
-			    uintptr_t total_size,
-			    uintptr_t ro_start,
-			    uintptr_t ro_limit);
-
-#endif /* PLAT_PRIVATE_H */

diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
index 82ef7e8..3f7d187 100644
--- a/plat/mediatek/mt8188/plat_config.mk
+++ b/plat/mediatek/mt8188/plat_config.mk

@@ -27,7 +27,6 @@
 ERRATA_A78_1941498 := 1
 ERRATA_A78_1951500 := 1
 ERRATA_A78_1821534 := 1
-ERRATA_A78_2132060 := 1
 ERRATA_A78_2242635 := 1
 ERRATA_A78_2376745 := 1
 ERRATA_A78_2395406 := 1

diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
index b776447..c57a6f5 100644
--- a/plat/mediatek/mt8188/platform.mk
+++ b/plat/mediatek/mt8188/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2022-2024, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2025, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -13,6 +13,7 @@
 include lib/xlat_tables_v2/xlat_tables.mk
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common \
+		 -I${MTK_PLAT}/common/include \
 		 -I${MTK_PLAT}/include \
 		 -I${MTK_PLAT}/include/${ARCH_VERSION} \
 		 -I${MTK_PLAT} \

diff --git a/plat/mediatek/mt8189/drivers/gpio/mtgpio.c b/plat/mediatek/mt8189/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..e81d132
--- /dev/null
+++ b/plat/mediatek/mt8189/drivers/gpio/mtgpio.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <mtgpio.h>
+#include <platform_def.h>
+
+typedef enum {
+	REG_0 = 0,
+	REG_1,
+	REG_2,
+	REG_3,
+	REG_4,
+	REG_5,
+	REG_6,
+	REG_7,
+	REG_8
+} RegEnum;
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+	uintptr_t reg_addr = 0U;
+	struct mt_pin_info gpio_info;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
+
+	switch (gpio_info.base & 0xF) {
+	case REG_0:
+		reg_addr = IOCFG_LM_BASE;
+		break;
+	case REG_1:
+		reg_addr = IOCFG_RB0_BASE;
+		break;
+	case REG_2:
+		reg_addr = IOCFG_RB1_BASE;
+		break;
+	case REG_3:
+		reg_addr = IOCFG_BM0_BASE;
+		break;
+	case REG_4:
+		reg_addr = IOCFG_BM1_BASE;
+		break;
+	case REG_5:
+		reg_addr = IOCFG_BM2_BASE;
+		break;
+	case REG_6:
+		reg_addr = IOCFG_LT0_BASE;
+		break;
+	case REG_7:
+		reg_addr = IOCFG_LT1_BASE;
+		break;
+	case REG_8:
+		reg_addr = IOCFG_RT_BASE;
+		break;
+	default:
+		break;
+	}
+
+	return reg_addr;
+}

diff --git a/plat/mediatek/mt8189/drivers/gpio/mtgpio.h b/plat/mediatek/mt8189/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..cf461e1
--- /dev/null
+++ b/plat/mediatek/mt8189/drivers/gpio/mtgpio.h

@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+	GPIO_UNSUPPORTED = -1,
+	GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6,
+	GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14,
+	GPIO15, GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22,
+	GPIO23, GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30,
+	GPIO31, GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38,
+	GPIO39, GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46,
+	GPIO47, GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54,
+	GPIO55, GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62,
+	GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70,
+	GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78,
+	GPIO79, GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86,
+	GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94,
+	GPIO95, GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102,
+	GPIO103, GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110,
+	GPIO111, GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118,
+	GPIO119, GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126,
+	GPIO127, GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134,
+	GPIO135, GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142,
+	GPIO143, GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150,
+	GPIO151, GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158,
+	GPIO159, GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166,
+	GPIO167, GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174,
+	GPIO175, GPIO176, GPIO177, GPIO178, GPIO179, GPIO180, GPIO181, GPIO182,
+	MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+	PIN(0, 0, 5, 0x21, 0xa0),
+	PIN(1, 0, 3, 0x12, 0x90),
+	PIN(2, 0, 4, 0x12, 0x90),
+	PIN(3, 0, 5, 0x12, 0x90),
+	PIN(4, 0, 6, 0x12, 0x90),
+	PIN(5, 0, 7, 0x12, 0x90),
+	PIN(6, 0, 6, 0x21, 0xa0),
+	PIN(7, 0, 7, 0x21, 0xa0),
+	PIN(8, 0, 8, 0x21, 0xa0),
+	PIN(9, 0, 9, 0x21, 0xa0),
+	PIN(10, 0, 10, 0x21, 0xa0),
+	PIN(11, 0, 11, 0x21, 0xa0),
+	PIN(12, 0, 5, 0x14, 0xb0),
+	PIN(13, 0, 6, 0x14, 0xb0),
+	PIN(14, 0, 0, 0x25, 0xa0),
+	PIN(15, 0, 1, 0x25, 0xa0),
+	PIN(16, 0, 7, 0x14, 0xb0),
+	PIN(17, 0, 8, 0x14, 0xb0),
+	PIN(18, 0, 0, 0x21, 0xa0),
+	PIN(19, 0, 2, 0x21, 0xa0),
+	PIN(20, 0, 1, 0x21, 0xa0),
+	PIN(21, 0, 3, 0x21, 0xa0),
+	PIN(22, 0, 0, 0x28, 0x90),
+	PIN(23, 0, 1, 0x28, 0x90),
+	PIN(24, 0, 2, 0x28, 0x90),
+	PIN(25, 0, 2, 0x10, 0x90),
+	PIN(26, 0, 1, 0x10, 0x90),
+	PIN(27, 0, 1, 0x14, 0xb0),
+	PIN(28, 0, 2, 0x14, 0xb0),
+	PIN(29, 0, 0, 0x10, 0x90),
+	PIN(30, 0, 0, 0x14, 0xb0),
+	PIN(31, 0, 13, 0x25, 0xa0),
+	PIN(32, 0, 30, 0x13, 0x90),
+	PIN(33, 0, 15, 0x25, 0xa0),
+	PIN(34, 0, 14, 0x25, 0xa0),
+	PIN(35, 0, 17, 0x25, 0xa0),
+	PIN(36, 0, 16, 0x25, 0xa0),
+	PIN(37, 0, 19, 0x25, 0xa0),
+	PIN(38, 0, 18, 0x25, 0xa0),
+	PIN(39, 0, 5, 0x25, 0xa0),
+	PIN(40, 0, 2, 0x25, 0xa0),
+	PIN(41, 0, 3, 0x25, 0xa0),
+	PIN(42, 0, 4, 0x25, 0xa0),
+	PIN(43, 0, 6, 0x25, 0xa0),
+	PIN(44, 1, 0, 0x21, 0x90),
+	PIN(45, 1, 1, 0x21, 0x90),
+	PIN(46, 1, 2, 0x21, 0x90),
+	PIN(47, 1, 3, 0x21, 0x90),
+	PIN(48, 0, 5, 0x10, 0x90),
+	PIN(49, 0, 4, 0x10, 0x90),
+	PIN(50, 0, 3, 0x10, 0x90),
+	PIN(51, 0, 8, 0x12, 0x90),
+	PIN(52, 0, 10, 0x12, 0x90),
+	PIN(53, 0, 9, 0x12, 0x90),
+	PIN(54, 0, 11, 0x12, 0x90),
+	PIN(55, 0, 6, 0x10, 0x90),
+	PIN(56, 0, 7, 0x10, 0x90),
+	PIN(57, 0, 13, 0x14, 0xb0),
+	PIN(58, 0, 17, 0x14, 0xb0),
+	PIN(59, 0, 14, 0x14, 0xb0),
+	PIN(60, 0, 18, 0x14, 0xb0),
+	PIN(61, 0, 15, 0x14, 0xb0),
+	PIN(62, 0, 19, 0x14, 0xb0),
+	PIN(63, 0, 16, 0x14, 0xb0),
+	PIN(64, 0, 20, 0x14, 0xb0),
+	PIN(65, 0, 4, 0x28, 0x90),
+	PIN(66, 0, 6, 0x28, 0x90),
+	PIN(67, 0, 5, 0x28, 0x90),
+	PIN(68, 0, 7, 0x28, 0x90),
+	PIN(69, 0, 22, 0x14, 0xb0),
+	PIN(70, 0, 21, 0x14, 0xb0),
+	PIN(71, 0, 24, 0x14, 0xb0),
+	PIN(72, 0, 23, 0x14, 0xb0),
+	PIN(73, 0, 26, 0x14, 0xb0),
+	PIN(74, 0, 25, 0x14, 0xb0),
+	PIN(75, 0, 7, 0x25, 0xa0),
+	PIN(76, 0, 27, 0x14, 0xb0),
+	PIN(77, 0, 13, 0x12, 0x90),
+	PIN(78, 0, 12, 0x12, 0x90),
+	PIN(79, 0, 15, 0x12, 0x90),
+	PIN(80, 0, 14, 0x12, 0x90),
+	PIN(81, 0, 29, 0x14, 0xb0),
+	PIN(82, 0, 28, 0x14, 0xb0),
+	PIN(83, 0, 30, 0x14, 0xb0),
+	PIN(84, 0, 22, 0x21, 0xa0),
+	PIN(85, 0, 23, 0x21, 0xa0),
+	PIN(86, 0, 24, 0x21, 0xa0),
+	PIN(87, 0, 25, 0x21, 0xa0),
+	PIN(88, 0, 11, 0x26, 0xb0),
+	PIN(89, 0, 10, 0x26, 0xb0),
+	PIN(90, 0, 13, 0x26, 0xb0),
+	PIN(91, 0, 12, 0x26, 0xb0),
+	PIN(92, 0, 7, 0x26, 0xb0),
+	PIN(93, 0, 8, 0x26, 0xb0),
+	PIN(94, 0, 14, 0x26, 0xb0),
+	PIN(95, 0, 6, 0x26, 0xb0),
+	PIN(96, 0, 9, 0x26, 0xb0),
+	PIN(97, 0, 0, 0x26, 0xb0),
+	PIN(98, 0, 5, 0x26, 0xb0),
+	PIN(99, 0, 3, 0x26, 0xb0),
+	PIN(100, 0, 4, 0x26, 0xb0),
+	PIN(101, 0, 1, 0x26, 0xb0),
+	PIN(102, 0, 2, 0x26, 0xb0),
+	PIN(103, 0, 15, 0x21, 0xa0),
+	PIN(104, 0, 12, 0x21, 0xa0),
+	PIN(105, 0, 14, 0x21, 0xa0),
+	PIN(106, 0, 13, 0x21, 0xa0),
+	PIN(107, 0, 19, 0x21, 0xa0),
+	PIN(108, 0, 16, 0x21, 0xa0),
+	PIN(109, 0, 18, 0x21, 0xa0),
+	PIN(110, 0, 17, 0x21, 0xa0),
+	PIN(111, 0, 4, 0x21, 0xa0),
+	PIN(112, 0, 0, 0x12, 0x90),
+	PIN(113, 0, 1, 0x12, 0x90),
+	PIN(114, 0, 2, 0x12, 0x90),
+	PIN(115, 0, 9, 0x14, 0xb0),
+	PIN(116, 0, 12, 0x14, 0xb0),
+	PIN(117, 0, 10, 0x14, 0xb0),
+	PIN(118, 0, 11, 0x14, 0xb0),
+	PIN(119, 0, 26, 0x13, 0x90),
+	PIN(120, 0, 25, 0x13, 0x90),
+	PIN(121, 0, 24, 0x13, 0x90),
+	PIN(122, 0, 23, 0x13, 0x90),
+	PIN(123, 0, 19, 0x13, 0x90),
+	PIN(124, 0, 18, 0x13, 0x90),
+	PIN(125, 0, 17, 0x13, 0x90),
+	PIN(126, 0, 16, 0x13, 0x90),
+	PIN(127, 0, 22, 0x13, 0x90),
+	PIN(128, 0, 15, 0x13, 0x90),
+	PIN(129, 0, 20, 0x13, 0x90),
+	PIN(130, 0, 27, 0x13, 0x90),
+	PIN(131, 0, 13, 0x13, 0x90),
+	PIN(132, 0, 14, 0x13, 0x90),
+	PIN(133, 0, 28, 0x13, 0x90),
+	PIN(134, 0, 21, 0x13, 0x90),
+	PIN(135, 0, 11, 0x13, 0x90),
+	PIN(136, 0, 12, 0x13, 0x90),
+	PIN(137, 0, 3, 0x14, 0xb0),
+	PIN(138, 0, 4, 0x14, 0xb0),
+	PIN(139, 0, 3, 0x13, 0x90),
+	PIN(140, 0, 4, 0x13, 0x90),
+	PIN(141, 0, 0, 0x13, 0x90),
+	PIN(142, 0, 1, 0x13, 0x90),
+	PIN(143, 0, 2, 0x13, 0x90),
+	PIN(144, 0, 5, 0x13, 0x90),
+	PIN(145, 0, 6, 0x13, 0x90),
+	PIN(146, 0, 7, 0x13, 0x90),
+	PIN(147, 0, 8, 0x13, 0x90),
+	PIN(148, 0, 9, 0x13, 0x90),
+	PIN(149, 0, 10, 0x13, 0x90),
+	PIN(150, 0, 8, 0x25, 0xa0),
+	PIN(151, 0, 29, 0x13, 0x90),
+	PIN(152, 0, 9, 0x25, 0xa0),
+	PIN(153, 0, 10, 0x25, 0xa0),
+	PIN(154, 0, 11, 0x25, 0xa0),
+	PIN(155, 0, 12, 0x25, 0xa0),
+	PIN(156, 1, 6, 0x26, 0xa0),
+	PIN(157, 1, 5, 0x26, 0xa0),
+	PIN(158, 1, 4, 0x26, 0xa0),
+	PIN(159, 1, 2, 0x17, 0x50),
+	PIN(160, 1, 8, 0x26, 0xa0),
+	PIN(161, 1, 1, 0x26, 0xa0),
+	PIN(162, 1, 0, 0x26, 0xa0),
+	PIN(163, 1, 1, 0x17, 0x50),
+	PIN(164, 1, 3, 0x26, 0xa0),
+	PIN(165, 1, 2, 0x26, 0xa0),
+	PIN(166, 1, 0, 0x17, 0x50),
+	PIN(167, 1, 7, 0x26, 0xa0),
+	PIN(168, 1, 1, 0x25, 0x90),
+	PIN(169, 1, 0, 0x25, 0x90),
+	PIN(170, 1, 2, 0x25, 0x90),
+	PIN(171, 1, 3, 0x25, 0x90),
+	PIN(172, 1, 4, 0x25, 0x90),
+	PIN(173, 1, 5, 0x25, 0x90),
+	PIN(174, 1, 1, 0x28, 0x80),
+	PIN(175, 1, 0, 0x28, 0x80),
+	PIN(176, 1, 2, 0x28, 0x80),
+	PIN(177, 1, 3, 0x28, 0x80),
+	PIN(178, 1, 4, 0x28, 0x80),
+	PIN(179, 1, 5, 0x28, 0x80),
+	PIN(180, 0, 15, 0x26, 0xb0),
+	PIN(181, 0, 16, 0x26, 0xb0),
+	PIN(182, 0, 3, 0x28, 0x90),
+};
+
+#endif /* MT_GPIO_H */

diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
new file mode 100644
index 0000000..54bf5ba
--- /dev/null
+++ b/plat/mediatek/mt8189/include/platform_def.h

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch_def.h>
+
+#define PLAT_PRIMARY_CPU	(0x0)
+
+#define MT_GIC_BASE		(0x0C000000)
+#define MCUCFG_BASE		(0x0C530000)
+#define MCUCFG_REG_SIZE		(0x10000)
+#define IO_PHYS			(0x10000000)
+
+/* Aggregate of all devices for MMU mapping */
+#define MTK_DEV_RNG0_BASE	(MT_GIC_BASE)
+#define MTK_DEV_RNG0_SIZE	(0x600000)
+#define MTK_DEV_RNG1_BASE	(IO_PHYS)
+#define MTK_DEV_RNG1_SIZE	(0x10000000)
+
+#define TOPCKGEN_BASE		(IO_PHYS)
+
+/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define IOCFG_LM_BASE		(IO_PHYS + 0x01B50000)
+#define IOCFG_RB0_BASE		(IO_PHYS + 0x01C50000)
+#define IOCFG_RB1_BASE		(IO_PHYS + 0x01C60000)
+#define IOCFG_BM0_BASE		(IO_PHYS + 0x01D20000)
+#define IOCFG_BM1_BASE		(IO_PHYS + 0x01D30000)
+#define IOCFG_BM2_BASE		(IO_PHYS + 0x01D40000)
+#define IOCFG_LT0_BASE		(IO_PHYS + 0x01E20000)
+#define IOCFG_LT1_BASE		(IO_PHYS + 0x01E30000)
+#define IOCFG_RT_BASE		(IO_PHYS + 0x01F20000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE	(IO_PHYS + 0x01002000)
+#define UART_BAUDRATE	(115200)
+
+/*******************************************************************************
+ * Infra IOMMU related constants
+ ******************************************************************************/
+#define PERICFG_AO_BASE		(IO_PHYS + 0x01036000)
+#define PERICFG_AO_REG_SIZE	(0x1000)
+
+/*******************************************************************************
+ * CIRQ related constants
+ ******************************************************************************/
+#define SYS_CIRQ_BASE		(IO_PHYS + 204000)
+#define MD_WDT_IRQ_BIT_ID	(519)
+#define CIRQ_REG_NUM		(19)
+#define CIRQ_SPI_START		(128)
+#define CIRQ_IRQ_NUM		(598)
+
+/*******************************************************************************
+ * MM IOMMU & SMI related constants
+ ******************************************************************************/
+#define SMI_LARB_0_BASE		(IO_PHYS + 0x0401c000)
+#define SMI_LARB_1_BASE		(IO_PHYS + 0x0401d000)
+#define SMI_LARB_2_BASE		(IO_PHYS + 0x0f002000)
+#define SMI_LARB_4_BASE		(IO_PHYS + 0x0602e000)
+#define SMI_LARB_7_BASE		(IO_PHYS + 0x07010000)
+#define SMI_LARB_9_BASE		(IO_PHYS + 0x0502e000)
+#define SMI_LARB_11_BASE	(IO_PHYS + 0x0582e000)
+#define SMI_LARB_13_BASE	(IO_PHYS + 0x0a001000)
+#define SMI_LARB_14_BASE	(IO_PHYS + 0x0a002000)
+#define SMI_LARB_16_BASE	(IO_PHYS + 0x0a00f000)
+#define SMI_LARB_17_BASE	(IO_PHYS + 0x0a010000)
+#define SMI_LARB_19_BASE	(IO_PHYS + 0x0b10f000)
+#define SMI_LARB_20_BASE	(IO_PHYS + 0x0b00f000)
+#define SMI_LARB_REG_RNG_SIZE	(0x1000)
+
+#define MM_IOMMU_BASE		(IO_PHYS + 0x0e802000 + 0x4000)
+#define APU_IOMMU_BASE		(IO_PHYS + 0x09010000)
+
+#define IOMMU_REG_RNG_SIZE	(0x5000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_HZ	(13000000)
+#define SYS_COUNTER_FREQ_IN_MHZ	(13)
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLATFORM_STACK_SIZE		(0x800)
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+#define SOC_CHIP_ID			U(0x8189)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZRAM_BASE			(0x54600000)
+#define TZRAM_SIZE			(0x00200000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE			(TZRAM_BASE + 0x1000)
+#define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE		(MT_GIC_BASE)
+#define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID		300
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_XLAT_TABLES			(16)
+#define MAX_MMAP_REGIONS		(16)
+
+/*******************************************************************************
+ * SYSTIMER related definitions
+ ******************************************************************************/
+#define SYSTIMER_BASE		(IO_PHYS + 0x0CC10000)
+
+/*******************************************************************************
+ * SPMI related definitions
+ ******************************************************************************/
+#define SPMI_MST_P_BASE			(IO_PHYS + 0x0CC00000)
+#define PMIF_SPMI_P_BASE		(IO_PHYS + 0x0CC06000)
+#define SPMI_MST_P_SIZE			(0x1000)
+
+/*******************************************************************************
+ * PWRAP related definitions
+ ******************************************************************************/
+#define PMICSPI_MST_BASE		(IO_PHYS + 0x0c013000)
+#define PMICSPI_MST_SIZE		(0x1000)
+#define PMIC_WRAP_BASE			(IO_PHYS + 0x0CC04000)
+#define PMIF_SPI_BASE			(0x1CC04000)
+#define PWRAP_REG_BASE			(0x1C013000)
+#define PWRAP_WRAP_EN			(PWRAP_REG_BASE + 0x14)
+
+/*******************************************************************************
+ * PMIC regsister related definitions
+ ******************************************************************************/
+#define PMIC_REG_BASE			(0x0000)
+#define PWRAP_SIZE			(0x1000)
+#define DEW_READ_TEST			(PMIC_REG_BASE + 0x040e)
+#define DEW_WRITE_TEST			(PMIC_REG_BASE + 0x0410)
+
+/*******************************************************************************
+ * Differentiate between 3G and 2.6G-related definitions
+ ******************************************************************************/
+#define EFUSEC_BASE			(IO_PHYS + 0x01F10000)
+#define CHIP_ID_REG			(EFUSEC_BASE + 0x7A0)
+#define CPU_SEG_ID_REG			(EFUSEC_BASE + 0x7E0)
+
+#define MTK_CPU_ID_MT8189		0x81890000
+#define MTK_CPU_SEG_ID_MT8189G		0x20
+#define MTK_CPU_SEG_ID_MT8189H		0x21
+
+#endif /* PLATFORM_DEF_H */

diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
new file mode 100644
index 0000000..6293052
--- /dev/null
+++ b/plat/mediatek/mt8189/plat_config.mk

@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Separate text code and read only data
+SEPARATE_CODE_AND_RODATA := 1
+
+# ARMv8.2 and above need enable HW assist coherence
+HW_ASSISTED_COHERENCY := 1
+
+# No need coherency memory because of HW assistency
+USE_COHERENT_MEM := 0
+
+# GIC600
+GICV3_SUPPORT_GIC600 := 1
+
+#
+# MTK options
+#
+MCUSYS_VERSION := v1
+PLAT_EXTRA_RODATA_INCLUDES := 1
+CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
+
+CONFIG_MTK_PMIC := y
+CONFIG_MTK_PMIC_LOWPOWER := y
+CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
+CONFIG_MTK_SPMI := y
+PMIC_CHIP := mt6359p
+USE_PMIC_WRAP_INIT_V3 := 1
+
+# Configs for A78 and A55
+CTX_INCLUDE_AARCH32_REGS := 0
+ERRATA_A55_1530923 := 1
+ERRATA_A55_1221012 := 1
+ERRATA_A78_1688305 := 1
+ERRATA_A78_1941498 := 1
+ERRATA_A78_1951500 := 1
+ERRATA_A78_1821534 := 1
+ERRATA_A78_2132060 := 1
+ERRATA_A78_2242635 := 1
+ERRATA_A78_2376745 := 1
+ERRATA_A78_2395406 := 1
+
+CONFIG_ARCH_ARM_V8_2 := y

diff --git a/plat/mediatek/mt8189/plat_mmap.c b/plat/mediatek/mt8189/plat_mmap.c
new file mode 100644
index 0000000..199abf7
--- /dev/null
+++ b/plat/mediatek/mt8189/plat_mmap.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+static const mmap_region_t plat_mmap[] = {
+	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	{ 0 }
+};
+DECLARE_MTK_MMAP_REGIONS(plat_mmap);

diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
new file mode 100644
index 0000000..381071a
--- /dev/null
+++ b/plat/mediatek/mt8189/platform.mk

@@ -0,0 +1,65 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+MTK_SOC := ${PLAT}
+
+include plat/mediatek/build_helpers/mtk_build_helpers.mk
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common \
+		 -I${MTK_PLAT}/common/include \
+		 -I${MTK_PLAT}/drivers/gpio/ \
+		 -I${MTK_PLAT}/include \
+		 -I${MTK_PLAT}/include/${ARCH_VERSION} \
+		 -I${MTK_PLAT} \
+		 -I${MTK_PLAT_SOC}/drivers/gpio/ \
+		 -I${MTK_PLAT_SOC}/include \
+		 -Idrivers/arm/gic \
+
+MODULES-y += $(MTK_PLAT)/common
+MODULES-y += $(MTK_PLAT)/helpers
+MODULES-y += $(MTK_PLAT)/lib/mtk_init
+MODULES-y += $(MTK_PLAT)/lib/pm
+MODULES-y += $(MTK_PLAT)/topology
+MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/gic600
+MODULES-y += $(MTK_PLAT)/drivers/iommu
+MODULES-y += $(MTK_PLAT)/drivers/mcusys
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
+MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
+
+PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
+			  drivers/ti/uart/aarch64/16550_console.S \
+			  lib/bl_aux_params/bl_aux_params.c
+
+BL31_SOURCES += drivers/delay_timer/delay_timer.c \
+		drivers/delay_timer/generic_delay_timer.c \
+		drivers/gpio/gpio.c \
+		lib/cpus/aarch64/cortex_a55.S \
+		lib/cpus/aarch64/cortex_a78.S \
+		${GICV3_SOURCES} \
+		${XLAT_TABLES_LIB_SRCS} \
+		plat/common/plat_gicv3.c \
+		plat/common/plat_psci_common.c \
+		plat/common/aarch64/crash_console_helpers.S \
+		${MTK_PLAT}/common/mtk_plat_common.c \
+		${MTK_PLAT}/common/params_setup.c \
+		${MTK_PLAT}/drivers/gpio/mtgpio_common.c \
+		$(MTK_PLAT)/$(MTK_SOC)/drivers/gpio/mtgpio.c \
+		$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
+
+ifeq (${CONFIG_MTK_DISABLE_CACHE_AS_RAM}, 1)
+BL31_SOURCES += ${MTK_PLAT}/common/cache_ops.c
+endif
+
+include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
+
+include lib/coreboot/coreboot.mk

diff --git a/plat/mediatek/mt8192/include/plat_macros.S b/plat/mediatek/mt8192/include/plat_macros.S
deleted file mode 100644
index 7d17e36..0000000
--- a/plat/mediatek/mt8192/include/plat_macros.S
+++ /dev/null

@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <platform_def.h>
-
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
-	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
-		" Offset:\t\t\tvalue\n"
-newline:
-	.asciz "\n"
-spacer:
-	.asciz ":\t\t0x"
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
-	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
-	/* ---------------------------------------------
-	 * The below macro prints out relevant GIC
-	 * registers whenever an unhandled exception
-	 * is taken in BL31.
-	 * Clobbers: x0 - x10, x26, x27, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_crash_print_regs
-	/* To-do: GIC owner */
-	/* To-do: CCI owner */
-	.endm
-
-#endif /* PLAT_MACROS_S */

diff --git a/plat/mediatek/mt8192/include/plat_private.h b/plat/mediatek/mt8192/include/plat_private.h
deleted file mode 100644
index 42ca415..0000000
--- a/plat/mediatek/mt8192/include/plat_private.h
+++ /dev/null

@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_PRIVATE_H
-#define PLAT_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void plat_configure_mmu_el3(uintptr_t total_base,
-			    uintptr_t total_size,
-			    uintptr_t ro_start,
-			    uintptr_t ro_limit);
-
-#endif /* PLAT_PRIVATE_H */

diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 4afd157..45ffd39 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2020-2025, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,6 +8,7 @@
 MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/include                     \
                  -I${MTK_PLAT}/drivers/cirq/                      \
                  -I${MTK_PLAT}/drivers/gic600/                    \
                  -I${MTK_PLAT}/drivers/gpio/                      \

diff --git a/plat/mediatek/mt8195/include/plat_macros.S b/plat/mediatek/mt8195/include/plat_macros.S
deleted file mode 100644
index 39727ea..0000000
--- a/plat/mediatek/mt8195/include/plat_macros.S
+++ /dev/null

@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-#include <platform_def.h>
-
-.section .rodata.gic_reg_name, "aS"
-gicc_regs:
-	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
-gicd_pend_reg:
-	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
-		" Offset:\t\t\tvalue\n"
-newline:
-	.asciz "\n"
-spacer:
-	.asciz ":\t\t0x"
-
-.section .rodata.cci_reg_name, "aS"
-cci_iface_regs:
-	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
-
-	/* ---------------------------------------------
-	 * The below macro prints out relevant GIC
-	 * registers whenever an unhandled exception
-	 * is taken in BL31.
-	 * Clobbers: x0 - x10, x26, x27, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_crash_print_regs
-	/* TODO: leave implementation to GIC owner */
-	.endm
-
-#endif /* PLAT_MACROS_S */

diff --git a/plat/mediatek/mt8195/include/plat_private.h b/plat/mediatek/mt8195/include/plat_private.h
deleted file mode 100644
index 7ef2b85..0000000
--- a/plat/mediatek/mt8195/include/plat_private.h
+++ /dev/null

@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_PRIVATE_H
-#define PLAT_PRIVATE_H
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-void plat_configure_mmu_el3(uintptr_t total_base,
-			    uintptr_t total_size,
-			    uintptr_t ro_start,
-			    uintptr_t ro_limit);
-
-#endif /* PLAT_PRIVATE_H */

diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
index 2debeff..faa0ba5 100644
--- a/plat/mediatek/mt8195/plat_sip_calls.c
+++ b/plat/mediatek/mt8195/plat_sip_calls.c

@@ -31,7 +31,7 @@
 	case MTK_SIP_TEE_MPU_PERM_SET_AARCH64:
 	case MTK_SIP_TEE_MPU_PERM_SET_AARCH32:
 		ret = emi_mpu_sip_handler(x1, x2, x3);
-		SMC_RET2(handle, ret, ret_val);
+		SMC_RET1(handle, ret);
 		break;
 	case MTK_SIP_DP_CONTROL_AARCH32:
 	case MTK_SIP_DP_CONTROL_AARCH64:

diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 48dafa3..e7a5a1a 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2025, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,6 +8,7 @@
 MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
+                 -I${MTK_PLAT}/common/include                     \
                  -I${MTK_PLAT}/drivers/cirq/                      \
                  -I${MTK_PLAT}/drivers/dp/                        \
                  -I${MTK_PLAT}/drivers/gic600/                    \
@@ -99,7 +100,6 @@
 ERRATA_A78_1941498 := 1
 ERRATA_A78_1951500 := 1
 ERRATA_A78_1821534 := 1
-ERRATA_A78_2132060 := 1
 ERRATA_A78_2242635 := 1
 
 # indicate the reset vector address can be programmed

diff --git a/plat/mediatek/mt8196/include/platform_def.h b/plat/mediatek/mt8196/include/platform_def.h
index 363c8cc..fb5212a 100644
--- a/plat/mediatek/mt8196/include/platform_def.h
+++ b/plat/mediatek/mt8196/include/platform_def.h

@@ -230,6 +230,7 @@
 #define SUB_EMI_APB_BASE		(IO_PHYS + 0x00529000)
 #define SUB_INFRA_EMI_DEBUG_CFG_BASE	(IO_PHYS + 0x00525000)
 #define SUB_INFRACFG_AO_MEM_BASE	(IO_PHYS + 0x00504000)
+#define EMI_MPU_ALIGN_BITS		12
 
 /*******************************************************************************
  * System counter frequency related constants
@@ -341,4 +342,10 @@
 #define SSPM_CFGREG_BASE	(IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET)
 #define SSPM_CFGREG_SIZE	(0x1000)
 
+/*******************************************************************************
+ * MMinfra related constants
+ ******************************************************************************/
+#define MTK_VLP_TRACER_MON_BASE		(IO_PHYS + 0x0c000000)
+#define MTK_VLP_TRACER_MON_REG_SIZE	(0x1000)
+
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index 84a25e9..a7f17e1 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk

@@ -27,7 +27,6 @@
 
 CONFIG_ARCH_ARM_V9 := y
 CONFIG_MTK_APUSYS_CE_SUPPORT := y
-CONFIG_MTK_APUSYS_EMI_SUPPORT := y
 CONFIG_MTK_APUSYS_LOGTOP_SUPPORT := y
 CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT := y
 CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT := y
@@ -50,6 +49,7 @@
 CPU_PWR_TOPOLOGY := group_4_3_1
 CPU_PM_CORE_ARCH64_ONLY := y
 CPU_PM_DOMAIN_CORE_ONLY := n
+CPU_PM_IRQ_REMAIN_ENABLE := y
 CPU_PM_SUSPEND_NOTIFY := y
 CONFIG_MTK_SPM_SUPPORT := y
 CONFIG_MTK_SPM_COMMON_SUPPORT := y
@@ -59,7 +59,9 @@
 CONFIG_MTK_PMIC := y
 CONFIG_MTK_PMIC_LOWPOWER := y
 CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
 CONFIG_MTK_PMIC_SPT_SUPPORT := n
+CONFIG_MTK_SMMU_SID := y
 CONFIG_MTK_SPMI := y
 PMIC_CHIP := mt6363
 

diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk
index 36048fe..e98ec4b 100644
--- a/plat/mediatek/mt8196/platform.mk
+++ b/plat/mediatek/mt8196/platform.mk

@@ -27,6 +27,7 @@
 include lib/xlat_tables_v2/xlat_tables.mk
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common \
+		 -I${MTK_PLAT}/common/include \
 		 -I${MTK_PLAT}/drivers/cpu_pm/topology/inc \
                  -I${MTK_PLAT}/drivers/gpio/ \
 		 -I${MTK_PLAT}/include \
@@ -44,19 +45,23 @@
 MODULES-y += $(MTK_PLAT)/lib/system_reset
 MODULES-y += $(MTK_PLAT)/drivers/apusys
 MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/cpu_qos
 MODULES-y += $(MTK_PLAT)/drivers/dp
 MODULES-y += $(MTK_PLAT)/drivers/emi
 MODULES-y += $(MTK_PLAT)/drivers/gicv3
 MODULES-y += $(MTK_PLAT)/drivers/mcusys
 MODULES-y += $(MTK_PLAT)/drivers/mminfra
+MODULES-y += $(MTK_PLAT)/drivers/slbc
 MODULES-y += $(MTK_PLAT)/drivers/smmu
 MODULES-y += $(MTK_PLAT)/drivers/spm
 MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-y += $(MTK_PLAT)/drivers/ufs
 MODULES-y += $(MTK_PLAT)/drivers/vcp
 MODULES-y += $(MTK_PLAT)/helpers
 MODULES-y += $(MTK_PLAT)/topology
 MODULES-$(CONFIG_MTK_CPU_PM_SUPPORT) += $(MTK_PLAT)/drivers/cpu_pm
 MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SMMU_SID) += $(MTK_PLAT)/drivers/smmu_sid
 MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
 
 MODULES-$(CONFIG_MTK_MTCMOS) += $(MTK_PLAT)/drivers/mtcmos

diff --git a/plat/mediatek/topology/armv9/topology.c b/plat/mediatek/topology/armv9/topology.c
deleted file mode 100644
index d6ecc83..0000000
--- a/plat/mediatek/topology/armv9/topology.c
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2024, Mediatek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <lib/psci/psci.h>
-#include <platform_def.h>
-
-#pragma weak plat_get_power_domain_tree_desc
-
-static const unsigned char mtk_power_domain_tree_desc[] = {
-	/* Number of root nodes */
-	PLATFORM_SYSTEM_COUNT,
-	/* Number of children for the root node */
-	PLATFORM_CLUSTER_COUNT,
-	/* Number of children for the first cluster node */
-	PLATFORM_CLUSTER0_CORE_COUNT
-};
-
-/*******************************************************************************
- * This function returns the default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return mtk_power_domain_tree_desc;
-}

diff --git a/plat/nuvoton/npcm845x/platform.mk b/plat/nuvoton/npcm845x/platform.mk
index d73756c..df1809d 100644
--- a/plat/nuvoton/npcm845x/platform.mk
+++ b/plat/nuvoton/npcm845x/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
 #
 # Copyright (c) 2017-2023 Nuvoton Ltd.
 #
@@ -201,7 +201,7 @@
 PLAT_BL_COMMON_SOURCES	:=	drivers/delay_timer/delay_timer.c \
 		drivers/delay_timer/generic_delay_timer.c \
 		plat/common/plat_gicv2.c \
-		plat/arm/common/arm_gicv2.c \
+		plat/common/plat_gicv2_base.c \
 		plat/nuvoton/common/plat_nuvoton_gic.c \
 		${NPCM850_GIC_SOURCES} \
 		plat/nuvoton/npcm845x/npcm845x_common.c \
@@ -330,10 +330,11 @@
 
 ifneq (${TRUSTED_BOARD_BOOT},0)
 # Include common TBB sources
-AUTH_SOURCES	:=	drivers/auth/auth_mod.c \
-		drivers/auth/crypto_mod.c \
-		drivers/auth/img_parser_mod.c \
-		lib/fconf/fconf_tbbr_getter.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES	+=	lib/fconf/fconf_tbbr_getter.c
 
 # Include the selected chain of trust sources.
 ifeq (${COT},tbbr)

diff --git a/plat/nxp/common/tbbr/tbbr.mk b/plat/nxp/common/tbbr/tbbr.mk
index 0233398..f07d7af 100644
--- a/plat/nxp/common/tbbr/tbbr.mk
+++ b/plat/nxp/common/tbbr/tbbr.mk

@@ -146,9 +146,11 @@
 PLAT_INCLUDES		+=	-Iinclude/common/tbbr
 
 # Generic files for authentication framework
-TBBR_SOURCES		+=	drivers/auth/auth_mod.c		\
-				drivers/auth/crypto_mod.c	\
-				drivers/auth/img_parser_mod.c	\
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+TBBR_SOURCES		+=	${AUTH_SOURCES}			\
 				plat/common/tbbr/plat_tbbr.c	\
 				${PLAT_TBBR_SOURCES}
 

diff --git a/plat/nxp/s32/s32g274ardb2/include/platform_def.h b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
index cb16658..227c8e6 100644
--- a/plat/nxp/s32/s32g274ardb2/include/platform_def.h
+++ b/plat/nxp/s32/s32g274ardb2/include/platform_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -44,24 +44,34 @@
 #define BL33_BASE			UL(0x34500000)
 #define BL33_LIMIT			UL(0x345FF000)
 
+/* IO buffer used to copy images from storage */
+#define IO_BUFFER_BASE			BL33_LIMIT
+#define IO_BUFFER_SIZE			U(0x13000)
+
 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 36)
 /* We'll be doing a 1:1 mapping anyway */
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 36)
 
-#define MAX_MMAP_REGIONS		U(18)
-#define MAX_XLAT_TABLES			U(32)
+#define MAX_MMAP_REGIONS		U(21)
+#define MAX_XLAT_TABLES			U(33)
 
 /* Console settings */
 #define UART_BASE			UL(0x401C8000)
 #define UART_BAUDRATE			U(115200)
 #define UART_CLOCK_HZ			U(125000000)
 
+/* uSDHC */
+#define S32G_USDHC_BASE			UL(0x402F0000)
+
 #define S32G_FIP_BASE			UL(0x34100000)
 #define S32G_FIP_SIZE			UL(0x100000)
 
 #define MAX_IO_HANDLES			U(2)
 #define MAX_IO_DEVICES			U(2)
 
+/* uSDHC as block device */
+#define MAX_IO_BLOCK_DEVICES		U(1)
+
 /* GIC settings */
 #define S32G_GIC_BASE			UL(0x50800000)
 #define PLAT_GICD_BASE			S32G_GIC_BASE

diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
index 0929f9d..810b7bb 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,10 @@
 
 #include <common/debug.h>
 #include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
+#include <imx_usdhc.h>
 #include <lib/mmio.h>
+#include <lib/utils.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 #include <plat_console.h>
@@ -70,6 +73,29 @@
 	mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
 }
 
+static void init_s32g_usdhc(void)
+{
+	static struct mmc_device_info sd_device_info = {
+		.mmc_dev_type = MMC_IS_SD_HC,
+		.ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4,
+	};
+	imx_usdhc_params_t params;
+
+	zeromem(&params, sizeof(imx_usdhc_params_t));
+
+	params.reg_base = S32G_USDHC_BASE;
+	params.clk_rate = 25000000;
+	params.bus_width = MMC_BUS_WIDTH_4;
+	params.flags = MMC_FLAG_SD_CMD6;
+
+	imx_usdhc_init(&params, &sd_device_info);
+}
+
+static void plat_s32_mmc_setup(void)
+{
+	init_s32g_usdhc();
+}
+
 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
 				  u_register_t arg2, u_register_t arg3)
 {
@@ -103,9 +129,18 @@
 		panic();
 	}
 
+	generic_delay_timer_init();
+
+	/* Configure the generic timer frequency to ensure proper operation
+	 * of the architectural timer in BL2.
+	 */
+	write_cntfrq_el0(plat_get_syscnt_freq2());
+
 	linflex_config_pinctrl();
 	console_s32g2_register();
 
+	plat_s32_mmc_setup();
+
 	plat_s32g2_io_setup();
 }
 

diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index 7121900..924808b 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -113,16 +113,17 @@
 /* void platform_mem_init(void); */
 func platform_mem_init
 	mov	x10, x30
-	mov	x0, #BL31_BASE
-	mov	x1, #(BL31_LIMIT & 0xFFFFU)
-	movk	x1, #(BL31_LIMIT >> 16), lsl #16
+	mov_imm	x0, BL31_BASE
+	mov_imm	x1, BL31_LIMIT
 	sub	x1, x1, x0
 	bl	zeromem
-	mov	x0, #BL33_BASE
-	mov	x1, #(BL33_LIMIT & 0xFFFFU)
-	movk	x1, #(BL33_LIMIT >> 16), lsl #16
+	mov_imm	x0, BL33_BASE
+	mov_imm	x1, BL33_LIMIT
 	sub	x1, x1, x0
 	bl	zeromem
+	mov_imm	x0, IO_BUFFER_BASE
+	mov_imm	x1, IO_BUFFER_SIZE
+	bl	zeromem
 	mov	x30, x10
 	ret
 endfunc platform_mem_init

diff --git a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
index db6bcc5..c4efe01 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c

@@ -1,14 +1,19 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
 
+#include <drivers/io/io_block.h>
 #include <drivers/io/io_driver.h>
 #include <drivers/io/io_fip.h>
 #include <drivers/io/io_memmap.h>
+#include <drivers/mmc.h>
+#include <drivers/partition/partition.h>
+#include <lib/utils.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 #include <tools_share/firmware_image_package.h>
 
@@ -20,24 +25,23 @@
 	int (*check)(const uintptr_t spec);
 };
 
-static int open_memmap(const uintptr_t spec);
-static int open_fip(const uintptr_t spec);
-
 static uintptr_t fip_dev_handle;
 
-static uintptr_t memmap_dev_handle;
+static io_block_spec_t fip_mmc_spec;
 
-static int open_memmap(const uintptr_t spec)
+static uintptr_t mmc_dev_handle;
+
+static int open_mmc(const uintptr_t spec)
 {
-	uintptr_t temp_handle = 0U;
+	uintptr_t temp_handle;
 	int result;
 
-	result = io_dev_init(memmap_dev_handle, (uintptr_t)0);
+	result = io_dev_init(mmc_dev_handle, (uintptr_t)0U);
 	if (result != 0) {
 		return result;
 	}
 
-	result = io_open(memmap_dev_handle, spec, &temp_handle);
+	result = io_open(mmc_dev_handle, spec, &temp_handle);
 	if (result == 0) {
 		(void)io_close(temp_handle);
 	}
@@ -66,16 +70,43 @@
 
 void plat_s32g2_io_setup(void)
 {
-	static const io_dev_connector_t *memmap_dev_con;
+	static const io_block_dev_spec_t mmc_dev_spec = {
+		/* It's used as temp buffer in block driver. */
+		.buffer		= {
+			.offset = IO_BUFFER_BASE,
+			.length = IO_BUFFER_SIZE,
+		},
+		.ops		= {
+			.read	= mmc_read_blocks,
+			.write	= mmc_write_blocks,
+		},
+		.block_size	= MMC_BLOCK_SIZE,
+	};
 	static const io_dev_connector_t *fip_dev_con;
+	static const io_dev_connector_t *mmc_dev_con;
 
+	partition_entry_t fip_part;
+	uintptr_t io_buf_base;
 	int result __unused;
+	size_t io_buf_size;
+	int ret;
 
-	result = register_io_dev_memmap(&memmap_dev_con);
+	io_buf_base = mmc_dev_spec.buffer.offset;
+	io_buf_size = mmc_dev_spec.buffer.length;
+
+	ret = mmap_add_dynamic_region(io_buf_base, io_buf_base,
+				      io_buf_size,
+				      MT_MEMORY | MT_RW | MT_SECURE);
+	if (ret != 0) {
+		ERROR("Failed to map the IO buffer\n");
+		panic();
+	}
+
+	result = register_io_dev_block(&mmc_dev_con);
 	assert(result == 0);
 
-	result = io_dev_open(memmap_dev_con, (uintptr_t)0,
-			     &memmap_dev_handle);
+	result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+			     &mmc_dev_handle);
 	assert(result == 0);
 
 	result = register_io_dev_fip(&fip_dev_con);
@@ -84,14 +115,24 @@
 	result = io_dev_open(fip_dev_con, (uintptr_t)0,
 			     &fip_dev_handle);
 	assert(result == 0);
+
+	ret = gpt_partition_init();
+	if (ret != 0) {
+		ERROR("Could not load MBR partition table\n");
+		panic();
+	}
+
+	fip_part = get_partition_entry_list()->list[FIP_PART];
+	fip_mmc_spec.offset = fip_part.start;
+	fip_mmc_spec.length = fip_part.length;
 }
 
 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
 			  uintptr_t *image_spec)
 {
-	static const io_block_spec_t fip_block_spec = {
-		.offset = S32G_FIP_BASE,
-		.length = S32G_FIP_SIZE,
+	static const io_block_spec_t mbr_spec = {
+		.offset = 0,
+		.length = PLAT_PARTITION_BLOCK_SIZE,
 	};
 
 	static const io_uuid_spec_t bl31_uuid_spec = {
@@ -102,11 +143,11 @@
 		.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
 	};
 
-	static const struct plat_io_policy policies[BL33_IMAGE_ID + 1] = {
+	static const struct plat_io_policy policies[GPT_IMAGE_ID + 1] = {
 		[FIP_IMAGE_ID] = {
-			.dev_handle = &memmap_dev_handle,
-			.image_spec = (uintptr_t)&fip_block_spec,
-			.check = open_memmap,
+			.dev_handle = &mmc_dev_handle,
+			.image_spec = (uintptr_t)&fip_mmc_spec,
+			.check = open_mmc,
 		},
 		[BL31_IMAGE_ID] = {
 			.dev_handle = &fip_dev_handle,
@@ -118,6 +159,11 @@
 			.image_spec = (uintptr_t)&bl33_uuid_spec,
 			.check = open_fip,
 		},
+		[GPT_IMAGE_ID] = {
+			.dev_handle = &mmc_dev_handle,
+			.image_spec = (uintptr_t)&mbr_spec,
+			.check = open_mmc,
+		},
 	};
 	const struct plat_io_policy *policy;
 	int result;

diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index 4ec7cd0..25e9ebd 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -20,7 +20,8 @@
 S32_ERRATA_LIST += ERRATA_S32_051700
 
 PLAT_INCLUDES = \
-	-I${PLAT_S32G274ARDB2}/include
+	-I${PLAT_S32G274ARDB2}/include \
+	-Idrivers/imx/usdhc \
 
 PROGRAMMABLE_RESET_ADDRESS := 1
 
@@ -41,12 +42,19 @@
 PLAT_XLAT_TABLES_DYNAMIC := 1
 $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
 
+NXP_ESDHC_LE := 1
+$(eval $(call add_define,NXP_ESDHC_LE))
+
 # Selecting Drivers for SoC
 $(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
 $(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM))
 
 include ${PLAT_DRIVERS_PATH}/drivers.mk
 
+# Selecting the raw partition where the FIP image is stored
+FIP_PART ?= 0
+$(eval $(call add_define,FIP_PART))
+
 BL_COMMON_SOURCES += \
 	${PLAT_S32G274ARDB2}/plat_console.c \
 	${PLAT_S32G274ARDB2}/plat_helpers.S \
@@ -60,11 +68,21 @@
 	${PLAT_S32G274ARDB2}/plat_io_storage.c \
 	${PLAT_S32G274ARDB2}/s32cc_ncore.c \
 	common/desc_image_load.c \
+	common/tf_crc32.c \
+	drivers/delay_timer/delay_timer.c \
+	drivers/delay_timer/generic_delay_timer.c \
+	drivers/imx/usdhc/imx_usdhc.c \
+	drivers/io/io_block.c \
 	drivers/io/io_fip.c \
 	drivers/io/io_memmap.c \
 	drivers/io/io_storage.c \
+	drivers/mmc/mmc.c \
+	drivers/partition/gpt.c \
+	drivers/partition/partition.c \
 	lib/cpus/aarch64/cortex_a53.S \
 
+BL2_CPPFLAGS += -march=armv8-a+crc
+
 BL31_SOURCES += \
 	${GICV3_SOURCES} \
 	${PLAT_S32G274ARDB2}/plat_bl31_setup.c \

diff --git a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
index 4664438..eb903c5 100644
--- a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
+++ b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,7 @@
 
 #include <common/bl_common.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
 
 #include <s32cc-bl-common.h>
 
@@ -38,3 +39,8 @@
 
 	return 0;
 }
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return COUNTER_FREQUENCY;
+}

diff --git a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
index 0001352..c005bad 100644
--- a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
+++ b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,8 +45,3 @@
 
 	return (int)core_id;
 }
-
-unsigned int plat_get_syscnt_freq2(void)
-{
-	return COUNTER_FREQUENCY;
-}

diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
index 226b22b..12fbac4 100644
--- a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk

@@ -12,8 +12,8 @@
 NXP_COINED_BB	:=	no
 
  # DDR Compilation Configs
-NUM_OF_DDRC	:=	1
-DDRC_NUM_DIMM	:=	1
+NUM_OF_DDRC	:=	2
+DDRC_NUM_DIMM	:=	2
 DDRC_NUM_CS	:=	2
 DDR_ECC_EN	:=	yes
  #enable address decoding feature

diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index da981e5..751511c 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk

@@ -148,7 +148,7 @@
 endif
 
 # Pointer Authentication sources
-ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3))
+ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3 5))
 PLAT_BL_COMMON_SOURCES	+=	plat/arm/common/aarch64/arm_pauth.c
 endif
 

diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 71f9cf7..3452fde 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,7 +19,9 @@
 #include <common/fdt_fixup.h>
 #include <common/fdt_wrappers.h>
 #include <lib/optee_utils.h>
+#if TRANSFER_LIST
 #include <lib/transfer_list.h>
+#endif
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
@@ -50,7 +52,7 @@
 
 /* Data structure which holds the extents of the trusted SRAM for BL2 */
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-static struct transfer_list_header *bl2_tl;
+static struct transfer_list_header __maybe_unused *bl2_tl;
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 			       u_register_t arg2, u_register_t arg3)
@@ -344,11 +346,11 @@
 
 		INFO("Handoff to BL32\n");
 		bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
-		if (TRANSFER_LIST &&
-			transfer_list_set_handoff_args(bl2_tl,
-				&bl_mem_params->ep_info))
+#if TRANSFER_LIST
+		if (transfer_list_set_handoff_args(bl2_tl,
+						   &bl_mem_params->ep_info))
 			break;
-
+#endif
 		INFO("Using default arguments\n");
 #if defined(SPMC_OPTEE)
 		/*

diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index 1c5e0ea..51fee64 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,9 @@
 #include <common/bl_common.h>
 #include <drivers/arm/pl061_gpio.h>
 #include <lib/gpt_rme/gpt_rme.h>
+#if TRANSFER_LIST
 #include <lib/transfer_list.h>
+#endif
 #include <plat/common/platform.h>
 #if ENABLE_RME
 #ifdef PLAT_qemu
@@ -79,7 +81,7 @@
 #if ENABLE_RME
 static entry_point_info_t rmm_image_ep_info;
 #endif
-static struct transfer_list_header *bl31_tl;
+static struct transfer_list_header __maybe_unused *bl31_tl;
 
 /*******************************************************************************
  * Perform any BL3-1 early platform setup.  Here is an opportunity to copy
@@ -92,8 +94,8 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	bool is64 = false;
-	uint64_t hval;
+	bool __maybe_unused is64 = false;
+	uint64_t __maybe_unused hval;
 
 	/* Initialize the console to provide early debug support */
 	qemu_console_init();
@@ -119,11 +121,11 @@
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
 	while (bl_params) {
-#ifdef __aarch64__
+#if defined(__aarch64__) && TRANSFER_LIST
 		if (bl_params->image_id == BL31_IMAGE_ID &&
 		    GET_RW(bl_params->ep_info->spsr) == MODE_RW_64)
 			is64 = true;
-#endif
+#endif /* defined(__aarch64__) && TRANSFER_LIST */
 		if (bl_params->image_id == BL32_IMAGE_ID)
 			bl32_image_ep_info = *bl_params->ep_info;
 
@@ -145,8 +147,8 @@
 		panic();
 #endif
 
-	if (!TRANSFER_LIST ||
-	    !transfer_list_check_header((void *)arg3))
+#if TRANSFER_LIST
+	if (!transfer_list_check_header((void *)arg3))
 		return;
 
 	if (is64)
@@ -156,6 +158,7 @@
 
 	if (arg1 != hval)
 		return;
+#endif
 
 	bl31_tl = (void *)arg3; /* saved TL address from BL2 */
 }

diff --git a/plat/qemu/common/qemu_spm.c b/plat/qemu/common/qemu_spm.c
index abedbe4..873b97b 100644
--- a/plat/qemu/common/qemu_spm.c
+++ b/plat/qemu/common/qemu_spm.c

@@ -129,7 +129,9 @@
 {
 	uintptr_t ns_buf_base;
 
-	dt_add_ns_buf_node(&ns_buf_base);
+	if (dt_add_ns_buf_node(&ns_buf_base) != 0) {
+		panic();
+	}
 
 	plat_qemu_secure_partition_mmap[0].base_pa = ns_buf_base;
 	plat_qemu_secure_partition_mmap[0].base_va = ns_buf_base;

diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index bd75abc..acd8e0f 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -45,9 +45,11 @@
 
 ifneq (${TRUSTED_BOARD_BOOT},0)
 
-    AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-				drivers/auth/img_parser_mod.c		\
-				drivers/auth/tbbr/tbbr_cot_common.c
+    AUTH_MK := drivers/auth/auth.mk
+    $(info Including ${AUTH_MK})
+    include ${AUTH_MK}
+
+    AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot_common.c
 
     BL1_SOURCES		+=	${AUTH_SOURCES}				\
 				bl1/tbbr/tbbr_img_desc.c		\
@@ -100,12 +102,16 @@
 
 endif
 
+ifeq (${MEASURED_BOOT},1)
+ifeq (${TRUSTED_BOARD_BOOT},0)
+    CRYPTO_SOURCES    :=    drivers/auth/crypto_mod.c
+
+    BL1_SOURCES        +=    ${CRYPTO_SOURCES}
+    BL2_SOURCES        +=    ${CRYPTO_SOURCES}
+endif
+endif
+
 ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),)
-    CRYPTO_SOURCES	:=	drivers/auth/crypto_mod.c
-
-    BL1_SOURCES		+=	${CRYPTO_SOURCES}
-    BL2_SOURCES		+=	${CRYPTO_SOURCES}
-
     # We expect to locate the *.mk files under the directories specified below
     #
     include drivers/auth/mbedtls/mbedtls_crypto.mk

diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
index 54a4156..8f88984 100644
--- a/plat/qemu/qemu/qemu_measured_boot.c
+++ b/plat/qemu/qemu/qemu_measured_boot.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
  * Copyright (c) 2022-2023, Linaro.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -7,6 +7,7 @@
 
 #include <stdint.h>
 
+#include <common/debug.h>
 #include <drivers/measured_boot/event_log/event_log.h>
 #include <drivers/measured_boot/metadata.h>
 #include <plat/common/common_def.h>
@@ -65,7 +66,7 @@
 
 	event_log_cur_size = event_log_get_cur_size((uint8_t *)event_log_base);
 
-	dump_event_log((uint8_t *)event_log_base, event_log_cur_size);
+	event_log_dump((uint8_t *)event_log_base, event_log_cur_size);
 
 #if TRANSFER_LIST
 	if (!plat_handoff_mboot((void *)event_log_base, event_log_cur_size,
@@ -82,13 +83,17 @@
 		ERROR("%s(): Unable to update %s_FW_CONFIG\n",
 		      __func__, "NT");
 		/*
-		 * It is a fatal error because on QEMU secure world software
+		 * It is a non-fatal error because on QEMU secure world software
 		 * assumes that a valid event log exists and will use it to
-		 * record the measurements into the fTPM or sw-tpm.
+		 * record the measurements into the fTPM or sw-tpm, but the boot
+		 * can also happen without TPM on the platform. It's up to
+		 * higher layer in boot sequence to decide if this is fatal or
+		 * not, e.g. by not providing access to TPM encrypted storage.
 		 * Note: In QEMU platform, OP-TEE uses nt_fw_config to get the
 		 * secure Event Log buffer address.
 		 */
-		panic();
+		WARN("Ignoring TPM errors, continuing without\n");
+		return;
 	}
 
 	/* Copy Event Log to Non-secure memory */

diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
index 49b7cf0..61eb755 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S

@@ -59,9 +59,7 @@
 	ret
 endfunc qti_kryo4_gold_cpu_reg_dump
 
-declare_cpu_ops_wa	qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR,	\
+declare_cpu_ops	qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR,	\
 		qti_kryo4_gold_reset_func,		\
-		CPU_NO_EXTRA1_FUNC,		\
-		cortex_a76_disable_wa_cve_2018_3639,	\
 		cortex_a76_core_pwr_dwn,	\
 		qti_kryo4_gold_cluster_pwr_dwn

diff --git a/plat/qti/msm8916/tsp/msm8916_tsp_setup.c b/plat/qti/msm8916/tsp/msm8916_tsp_setup.c
index 218af57..88d3c93 100644
--- a/plat/qti/msm8916/tsp/msm8916_tsp_setup.c
+++ b/plat/qti/msm8916/tsp/msm8916_tsp_setup.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2023, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,7 +11,8 @@
 #include "../msm8916_setup.h"
 #include <platform_def.h>
 
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3)
 {
 	msm8916_early_platform_setup();
 }

diff --git a/plat/qti/sc7280/platform.mk b/plat/qti/sc7280/platform.mk
index 3d7d728..0b5ae52 100644
--- a/plat/qti/sc7280/platform.mk
+++ b/plat/qti/sc7280/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
 # Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
@@ -20,7 +20,6 @@
 ERRATA_A55_1530923 		:=	1
 ERRATA_A78_1941498 		:=	1
 ERRATA_A78_1951500 		:=	1
-ERRATA_A78_2132060 		:=	1
 
 # Disable the PSCI platform compatibility layer
 ENABLE_PLAT_COMPAT		:=	0

diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index 5297177..b60482e 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk

@@ -220,10 +220,11 @@
     include drivers/auth/mbedtls/mbedtls_crypto.mk
     include drivers/auth/mbedtls/mbedtls_x509.mk
 
-    AUTH_SOURCES	:=	drivers/auth/auth_mod.c			\
-				drivers/auth/crypto_mod.c		\
-				drivers/auth/img_parser_mod.c		\
-				drivers/auth/tbbr/tbbr_cot_common.c
+    AUTH_MK := drivers/auth/auth.mk
+    $(info Including ${AUTH_MK})
+    include ${AUTH_MK}
+
+    AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot_common.c
 
     BL1_SOURCES		+=	${AUTH_SOURCES}				\
 				bl1/tbbr/tbbr_img_desc.c		\

diff --git a/plat/rpi/rpi3/rpi3_bl1_mboot.c b/plat/rpi/rpi3/rpi3_bl1_mboot.c
index 4294365..2057962 100644
--- a/plat/rpi/rpi3/rpi3_bl1_mboot.c
+++ b/plat/rpi/rpi3/rpi3_bl1_mboot.c

@@ -131,7 +131,7 @@
 	event_log_record(hash_data, EV_POST_CODE, metadata_ptr);
 
 	/* Dump Event Log for user view */
-	dump_event_log((uint8_t *)event_log, event_log_get_cur_size(event_log));
+	event_log_dump((uint8_t *)event_log, event_log_get_cur_size(event_log));
 
 	return rc;
 }

diff --git a/plat/rpi/rpi3/rpi3_bl2_mboot.c b/plat/rpi/rpi3/rpi3_bl2_mboot.c
index 55c6923..684e697 100644
--- a/plat/rpi/rpi3/rpi3_bl2_mboot.c
+++ b/plat/rpi/rpi3/rpi3_bl2_mboot.c

@@ -106,7 +106,7 @@
 	flush_dcache_range(ns_log_addr, event_log_cur_size);
 
 	/* Dump Event Log for user view */
-	dump_event_log((uint8_t *)event_log_start, event_log_cur_size);
+	event_log_dump((uint8_t *)event_log_start, event_log_cur_size);
 
 #if DISCRETE_TPM
 	/* relinquish control of TPM locality 0 and close interface */

diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 7a5a03c..12f92eb 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -63,9 +63,11 @@
 ifeq (${TRUSTED_BOARD_BOOT},1)
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
-BL2_SOURCES		+=	drivers/auth/auth_mod.c			\
-				drivers/auth/crypto_mod.c		\
-				drivers/auth/img_parser_mod.c		\
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+BL2_SOURCES		+=	${AUTH_SOURCES}				\
 				drivers/auth/tbbr/tbbr_cot_common.c	\
 				drivers/auth/tbbr/tbbr_cot_bl2.c	\
 				plat/common/tbbr/plat_tbbr.c		\

diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 21d95cf..850bd75 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -88,10 +88,11 @@
 
 include drivers/auth/mbedtls/mbedtls_crypto.mk
 include drivers/auth/mbedtls/mbedtls_x509.mk
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
 
-BL2_SOURCES		+=	drivers/auth/auth_mod.c			\
-				drivers/auth/crypto_mod.c		\
-				drivers/auth/img_parser_mod.c		\
+BL2_SOURCES		+=	${AUTH_SOURCES}				\
 				drivers/auth/tbbr/tbbr_cot_common.c	\
 				drivers/auth/tbbr/tbbr_cot_bl2.c	\
 				plat/common/tbbr/plat_tbbr.c		\

diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
index 4bbb259..31583b5 100644
--- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
+++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,7 +15,8 @@
 
 static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
 
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3)
 {
 	uniphier_soc = uniphier_get_soc_id();
 	if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)

diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index dc753a0..56a8814 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
 # Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
@@ -27,7 +27,10 @@
 STM32_HEADER_BL2_BINARY_TYPE	:=	0x10
 
 TF_CFLAGS			+=	-Wsign-compare
+ifeq ($(findstring clang,$(notdir $(CC))),)
+# Only for GCC
 TF_CFLAGS			+=	-Wformat-signedness
+endif
 
 # Number of TF-A copies in the device
 STM32_TF_A_COPIES		:=	2
@@ -177,9 +180,9 @@
 endif
 
 ifeq (${TRUSTED_BOARD_BOOT},1)
-AUTH_SOURCES			:=	drivers/auth/auth_mod.c				\
-					drivers/auth/crypto_mod.c			\
-					drivers/auth/img_parser_mod.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
 
 ifeq (${GENERATE_COT},1)
 TFW_NVCTR_VAL			:=	0

diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 88c1087..bb7e3c5 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk

@@ -71,8 +71,13 @@
 tf-a-%.stm32: tf-a-%.bin ${STM32_DEPS}
 	$(s)echo
 	$(s)echo "Generate $@"
+ifeq ($($(ARCH)-ld-id),llvm-lld)
+	$(eval LOADADDR = 0x$(shell cat $(@:.stm32=.map) | grep '\.data$$' | awk '{print $$1}'))
+	$(eval ENTRY = 0x$(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+else
 	$(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep '^RAM' | awk '{print $$2}'))
 	$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+endif
 	$(q)${STM32IMAGE} -s $< -d $@ \
 		-l $(LOADADDR) -e ${ENTRY} \
 		-v ${STM32_TF_VERSION} \

diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c
index 7223022..6c70b50 100644
--- a/plat/st/common/stm32mp_crypto_lib.c
+++ b/plat/st/common/stm32mp_crypto_lib.c

@@ -661,7 +661,8 @@
 		    crypto_verify_hash,
 		    NULL,
 		    crypto_auth_decrypt,
-		    crypto_convert_pk);
+		    crypto_convert_pk,
+		    NULL);
 
 #else /* No decryption support */
 REGISTER_CRYPTO_LIB("stm32_crypto_lib",
@@ -670,5 +671,6 @@
 		    crypto_verify_hash,
 		    NULL,
 		    NULL,
-		    crypto_convert_pk);
+		    crypto_convert_pk,
+		    NULL);
 #endif

diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index e700823..0e0586b 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk

@@ -17,6 +17,8 @@
 # Default Device tree
 DTB_FILE_NAME		?=	stm32mp157c-ev1.dtb
 
+TF_CFLAGS 		+=	-DSTM32MP1X
+
 STM32MP13		?=	0
 STM32MP15		?=	0
 

diff --git a/plat/st/stm32mp1/stm32mp1.S b/plat/st/stm32mp1/stm32mp1.S
index aee4f0e..a688f4d 100644
--- a/plat/st/stm32mp1/stm32mp1.S
+++ b/plat/st/stm32mp1/stm32mp1.S

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-.section .bl2_image
+.section .bl2_image, "a"
 .incbin BL2_BIN_PATH
 
-.section .dtb_image
+.section .dtb_image, "a"
 .incbin DTB_BIN_PATH

diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
index 1be8219..c9d9873 100644
--- a/plat/st/stm32mp1/stm32mp1.ld.S
+++ b/plat/st/stm32mp1/stm32mp1.ld.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,17 +33,17 @@
     } >HEADER
 
     . = STM32MP_BINARY_BASE;
-    .data . : {
+    .data : {
         . = ALIGN(PAGE_SIZE);
         __DATA_START__ = .;
-        *(.data*)
+        FILL(0);
 
         /*
          * dtb.
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
         __DTB_IMAGE_START__ = .;
         *(.dtb_image*)
         __DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
 #if SEPARATE_CODE_AND_RODATA
-        . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_RO_BASE );
 #else
-        . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_BASE );
 #endif
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)

diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S
index 1866b8b..6c32972 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.S

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-.section .bl2_image
+.section .bl2_image, "a"
 .incbin BL2_BIN_PATH
 
-.section .dtb_image
+.section .dtb_image, "a"
 .incbin DTB_BIN_PATH

diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
index 48bf424..cf71f27 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,17 +33,17 @@
     } >HEADER
 
     . = STM32MP_BINARY_BASE;
-    .data . : {
+    .data : {
         . = ALIGN(PAGE_SIZE);
         __DATA_START__ = .;
-        *(.data*)
+        FILL(0);
 
         /*
          * dtb.
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
         __DTB_IMAGE_START__ = .;
         *(.dtb_image*)
         __DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
 #if SEPARATE_CODE_AND_RODATA
-        . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_RO_BASE );
 #else
-        . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_BASE );
 #endif
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)

diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 621b784..1d49fe7 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c

@@ -34,97 +34,46 @@
 static void print_reset_reason(void)
 {
 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
+	const char *reason_str = "Unidentified";
 
-	if (rstsr == 0U) {
-		WARN("Reset reason unknown\n");
-		return;
+#if !STM32MP21
+	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
+		INFO("CA35 processor core 1 reset\n");
 	}
-
-	INFO("Reset reason (0x%x):\n", rstsr);
+#endif /* !STM32MP21 */
 
 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
 		if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
-			INFO("System exits from Standby for CA35\n");
-			return;
+			reason_str = "System exits from Standby for CA35";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
+			reason_str = "D1 domain exits from DStandby";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) {
+			reason_str = "System reset from VCPU monitor";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
+			reason_str = "CA35 reset by CM33 (C1RST)";
+		} else {
+			reason_str = "Unidentified";
 		}
-
-		if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
-			INFO("D1 domain exits from DStandby\n");
-			return;
+	} else {
+		if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
+			reason_str = "Power-on reset (por_rstn)";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
+			reason_str = "Brownout reset (bor_rstn)";
+		} else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF |
+				     RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) {
+			reason_str = "System reset (SYSRST)";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
+			reason_str = "Clock failure on HSE";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) {
+			reason_str = "IWDG system reset (iwdgX_out_rst)";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
+			reason_str = "Pin reset from NRST";
+		} else {
+			reason_str = "Unidentified";
 		}
 	}
 
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
-		INFO("  Power-on Reset (rst_por)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
-		INFO("  Brownout Reset (rst_bor)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
-		INFO("  System reset (SYSRST) by M33\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
-		INFO("  System reset (SYSRST) by A35\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
-		INFO("  Clock failure on HSE\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
-		INFO("  IWDG1 system reset (rst_iwdg1)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
-		INFO("  IWDG2 system reset (rst_iwdg2)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
-		INFO("  IWDG3 system reset (rst_iwdg3)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
-		INFO("  IWDG4 system reset (rst_iwdg4)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
-		INFO("  IWDG5 system reset (rst_iwdg5)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
-		INFO("  A35 processor core 1 reset\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
-		INFO("  Pad Reset from NRST\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
-		INFO("  Reset due to a failure of VDD_CORE\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
-		INFO("  A35 processor reset\n");
-		return;
-	}
-
-	ERROR("  Unidentified reset reason\n");
+	INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr);
 }
 
 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
@@ -164,11 +113,19 @@
 	 * The protection is enable at each reset by hardware
 	 * and must be disabled by software.
 	 */
+#if STM32MP21
+	mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP);
+
+	while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) {
+		;
+	}
+#else /* STM32MP21 */
 	mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
 
 	while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
 		;
 	}
+#endif /* STM32MP21 */
 
 	/* Reset backup domain on cold boot cases */
 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {

diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index d5e2785..c20435b 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk

@@ -30,11 +30,36 @@
 # Default Device tree
 DTB_FILE_NAME			?=	stm32mp257f-ev1.dtb
 
-STM32MP25			:=	1
+TF_CFLAGS			+=	-DSTM32MP2X
 
-# STM32 image header version v2.2
+STM32MP21			?=	0
+STM32MP23			?=	0
+STM32MP25			?=	0
+
+ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
+STM32MP21			:=	1
+endif
+ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
+STM32MP23			:=	1
+endif
+ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
+STM32MP25			:=	1
+endif
+ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
+$(warning STM32MP21=$(STM32MP21))
+$(warning STM32MP23=$(STM32MP23))
+$(warning STM32MP25=$(STM32MP25))
+$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
+$(error Cannot enable more than one STM32MP2x flag)
+endif
+
+# STM32 image header version v2.2 or v2.3 for STM32MP21
 STM32_HEADER_VERSION_MAJOR	:=	2
+ifeq ($(STM32MP21),1)
+STM32_HEADER_VERSION_MINOR	:=	3
+else
 STM32_HEADER_VERSION_MINOR	:=	2
+endif
 
 # Set load address for serial boot devices
 DWL_BUFFER_BASE 		?=	0x87000000
@@ -89,6 +114,19 @@
 $(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
 endif
 
+# Ultratronik Specific Boards
+ifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly)
+ULTRA_FLY := 1
+$(eval $(call assert_booleans,\
+	$(sort \
+		ULTRA_FLY \
+	)))
+$(eval $(call add_defines,\
+	$(sort \
+		ULTRA_FLY \
+	)))
+endif
+
 # Enable flags for C files
 $(eval $(call assert_booleans,\
 	$(sort \
@@ -97,6 +135,8 @@
 		STM32MP_DDR3_TYPE \
 		STM32MP_DDR4_TYPE \
 		STM32MP_LPDDR4_TYPE \
+		STM32MP21 \
+		STM32MP23 \
 		STM32MP25 \
 		STM32MP_BL33_EL1 \
 )))
@@ -120,6 +160,8 @@
 		STM32MP_DDR3_TYPE \
 		STM32MP_DDR4_TYPE \
 		STM32MP_LPDDR4_TYPE \
+		STM32MP21 \
+		STM32MP23 \
 		STM32MP25 \
 		STM32MP_BL33_EL1 \
 )))

diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 3e60cad..27fc5f9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h

@@ -10,16 +10,31 @@
 #include <common/tbbr/tbbr_img_def.h>
 #ifndef __ASSEMBLER__
 #include <drivers/st/bsec.h>
-#endif
-#include <drivers/st/stm32mp25_rcc.h>
-#ifndef __ASSEMBLER__
 #include <drivers/st/stm32mp2_clk.h>
 #endif
+#if STM32MP21
+#include <drivers/st/stm32mp21_pwr.h>
+#include <drivers/st/stm32mp21_rcc.h>
+#else /* STM32MP21 */
 #include <drivers/st/stm32mp2_pwr.h>
+#include <drivers/st/stm32mp25_rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP21
+#include <dt-bindings/clock/st,stm32mp21-rcc.h>
+#include <dt-bindings/clock/stm32mp21-clksrc.h>
+#include <dt-bindings/reset/st,stm32mp21-rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP23
 #include <dt-bindings/clock/stm32mp25-clks.h>
 #include <dt-bindings/clock/stm32mp25-clksrc.h>
-#include <dt-bindings/gpio/stm32-gpio.h>
 #include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP23 */
+#if STM32MP25
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP25 */
+#include <dt-bindings/gpio/stm32-gpio.h>
 
 #ifndef __ASSEMBLER__
 #include <boot_api.h>
@@ -221,6 +236,22 @@
 /* For UART crash console */
 #define STM32MP_DEBUG_USART_CLK_FRQ		64000000
 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
+#ifdef ULTRA_FLY
+#define STM32MP_DEBUG_USART_BASE		USART1_BASE
+#define DEBUG_UART_TX_GPIO_BANK_ADDRESS		GPIOA_BASE
+#define DEBUG_UART_TX_GPIO_BANK_CLK_REG		RCC_GPIOACFGR
+#define DEBUG_UART_TX_GPIO_BANK_CLK_EN		RCC_GPIOxCFGR_GPIOxEN
+#define DEBUG_UART_TX_GPIO_PORT			3
+#define DEBUG_UART_TX_GPIO_ALTERNATE		6
+#define DEBUG_UART_TX_CLKSRC_REG		RCC_XBAR8CFGR
+#define DEBUG_UART_TX_CLKSRC			XBAR_SRC_HSI
+#define DEBUG_UART_TX_EN_REG			RCC_USART1CFGR
+#define DEBUG_UART_TX_EN			RCC_UARTxCFGR_UARTxEN
+#define DEBUG_UART_RST_REG			RCC_USART1CFGR
+#define DEBUG_UART_RST_BIT			RCC_UARTxCFGR_UARTxRST
+#define DEBUG_UART_PREDIV_CFGR			RCC_PREDIV19CFGR
+#define DEBUG_UART_FINDIV_CFGR			RCC_FINDIV19CFGR
+#else
 #define STM32MP_DEBUG_USART_BASE		USART2_BASE
 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS		GPIOA_BASE
 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG		RCC_GPIOACFGR
@@ -235,6 +266,7 @@
 #define DEBUG_UART_RST_BIT			RCC_UARTxCFGR_UARTxRST
 #define DEBUG_UART_PREDIV_CFGR			RCC_PREDIV8CFGR
 #define DEBUG_UART_FINDIV_CFGR			RCC_FINDIV8CFGR
+#endif
 
 /*******************************************************************************
  * STM32MP2 SDMMC
@@ -369,7 +401,7 @@
 #define DDRPHYC_BASE				U(0x48C00000)
 
 /*******************************************************************************
- * Miscellaneous STM32MP1 peripherals base address
+ * Miscellaneous STM32MP2 peripherals base address
  ******************************************************************************/
 #define BSEC_BASE				U(0x44000000)
 #define DBGMCU_BASE				U(0x4A010000)
@@ -405,7 +437,11 @@
 #define DT_BSEC_COMPAT				"st,stm32mp25-bsec"
 #define DT_DDR_COMPAT				"st,stm32mp2-ddr"
 #define DT_PWR_COMPAT				"st,stm32mp25-pwr"
+#if STM32MP21
+#define DT_RCC_CLK_COMPAT			"st,stm32mp21-rcc"
+#else
 #define DT_RCC_CLK_COMPAT			"st,stm32mp25-rcc"
+#endif
 #define DT_SDMMC2_COMPAT			"st,stm32mp25-sdmmc2"
 #define DT_UART_COMPAT				"st,stm32h7-uart"
 

diff --git a/plat/ti/k3/include/k3_console.h b/plat/ti/common/include/k3_console.h
similarity index 100%
rename from plat/ti/k3/include/k3_console.h
rename to plat/ti/common/include/k3_console.h

diff --git a/plat/ti/k3/include/k3_gicv3.h b/plat/ti/common/include/k3_gicv3.h
similarity index 100%
rename from plat/ti/k3/include/k3_gicv3.h
rename to plat/ti/common/include/k3_gicv3.h

diff --git a/plat/ti/k3/include/plat_macros.S b/plat/ti/common/include/plat_macros.S
similarity index 100%
rename from plat/ti/k3/include/plat_macros.S
rename to plat/ti/common/include/plat_macros.S

diff --git a/plat/ti/common/include/plat_private.h b/plat/ti/common/include/plat_private.h
new file mode 100644
index 0000000..697cc5c
--- /dev/null
+++ b/plat/ti/common/include/plat_private.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLATFORM_PRIVATE_H
+#define PLATFORM_PRIVATE_H
+
+#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <board_def.h>
+
+#define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U))
+#define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr))
+
+#define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \
+	MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr)
+
+extern const mmap_region_t plat_k3_mmap[];
+
+/* Any kind of SOC specific init can be done here */
+int ti_soc_init(void);
+
+#endif /* PLATFORM_PRIVATE_H */

diff --git a/plat/ti/common/include/ti_platform_defs.h b/plat/ti/common/include/ti_platform_defs.h
new file mode 100644
index 0000000..44c2f94
--- /dev/null
+++ b/plat/ti/common/include/ti_platform_defs.h

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TI_PLATFORM_DEF_H
+#define TI_PLATFORM_DEF_H
+
+#include <arch.h>
+#include <plat/common/common_def.h>
+
+#include <board_def.h>
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stack */
+#if IMAGE_BL31
+#define PLATFORM_STACK_SIZE		0x800
+#else
+#define PLATFORM_STACK_SIZE		0x1000
+#endif
+
+#define PLATFORM_SYSTEM_COUNT		1
+#define PLATFORM_CORE_COUNT		(K3_CLUSTER0_CORE_COUNT + \
+					K3_CLUSTER1_CORE_COUNT + \
+					K3_CLUSTER2_CORE_COUNT + \
+					K3_CLUSTER3_CORE_COUNT)
+
+#define PLATFORM_CLUSTER_COUNT		((K3_CLUSTER0_CORE_COUNT != 0) + \
+					(K3_CLUSTER1_CORE_COUNT != 0) + \
+					(K3_CLUSTER2_CORE_COUNT != 0) + \
+					(K3_CLUSTER3_CORE_COUNT != 0))
+
+#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_SYSTEM_COUNT + \
+					PLATFORM_CLUSTER_COUNT + \
+					PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
+#define PLAT_MAX_OFF_STATE		U(2)
+#define PLAT_MAX_RET_STATE		U(1)
+
+/*******************************************************************************
+ * Memory layout constants
+ ******************************************************************************/
+
+/*
+ * This RAM will be used for the bootloader including code, bss, and stacks.
+ * It may need to be increased if BL31 grows in size.
+ *
+ * The link addresses are determined by BL31_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * BL31_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * BL31_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
+ */
+#define BL31_BASE	UL(0x00000000) /* PIE remapped on fly */
+#define BL31_SIZE	UL(0x00020000) /* 128k */
+#define BL31_LIMIT	(BL31_BASE + BL31_SIZE)
+
+/*
+ * Defines the maximum number of translation tables that are allocated by the
+ * translation table library code. To minimize the amount of runtime memory
+ * used, choose the smallest value needed to map the required virtual addresses
+ * for each BL stage.
+ */
+#define MAX_XLAT_TABLES		4
+
+/*
+ * Defines the maximum number of regions that are allocated by the translation
+ * table library code. A region consists of physical base address, virtual base
+ * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
+ * defined in the `mmap_region_t` structure. The platform defines the regions
+ * that should be mapped. Then, the translation table library will create the
+ * corresponding tables and descriptors at runtime. To minimize the amount of
+ * runtime memory used, choose the smallest value needed to register the
+ * required regions for each BL stage.
+ */
+#if USE_COHERENT_MEM
+#define MAX_MMAP_REGIONS	11
+#else
+#define MAX_MMAP_REGIONS	10
+#endif
+
+/*
+ * Defines the total size of the address space in bytes. For example, for a 32
+ * bit address space, this value should be `(1ull << 32)`.
+ */
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/* Platform default console definitions */
+#ifndef K3_USART_BASE
+#define K3_USART_BASE			(0x02800000 + 0x10000 * K3_USART)
+#endif
+
+/* USART has a default size for address space */
+#define K3_USART_SIZE 0x1000
+
+#ifndef K3_USART_CLK_SPEED
+#define K3_USART_CLK_SPEED 48000000
+#endif
+
+/* Crash console defaults */
+#define CRASH_CONSOLE_BASE K3_USART_BASE
+#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
+#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
+
+/* Timer frequency */
+#ifndef SYS_COUNTER_FREQ_IN_TICKS
+#define SYS_COUNTER_FREQ_IN_TICKS 200000000
+#endif
+
+/* Interrupt numbers */
+#define ARM_IRQ_SEC_PHY_TIMER		29
+
+#define ARM_IRQ_SEC_SGI_0		8
+#define ARM_IRQ_SEC_SGI_1		9
+#define ARM_IRQ_SEC_SGI_2		10
+#define ARM_IRQ_SEC_SGI_3		11
+#define ARM_IRQ_SEC_SGI_4		12
+#define ARM_IRQ_SEC_SGI_5		13
+#define ARM_IRQ_SEC_SGI_6		14
+#define ARM_IRQ_SEC_SGI_7		15
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_EDGE)
+
+
+#define K3_GTC_BASE		0x00A90000
+/* We just need 20 byte offset, but simpler to just remap the 64K page in */
+#define K3_GTC_SIZE		0x10000
+#define K3_GTC_CNTCR_OFFSET	0x00
+#define K3_GTC_CNTCR_EN_MASK	0x01
+#define K3_GTC_CNTCR_HDBG_MASK	0x02
+#define K3_GTC_CNTFID0_OFFSET	0x20
+
+#define K3_GIC_BASE	0x01800000
+#define K3_GIC_SIZE	0x200000
+
+#define TI_SCI_HOST_ID			10
+#define TI_SCI_MAX_MESSAGE_SIZE		52
+
+#endif /* TI_PLATFORM_DEF_H */

diff --git a/plat/ti/k3/common/k3_console.c b/plat/ti/common/k3_console.c
similarity index 100%
rename from plat/ti/k3/common/k3_console.c
rename to plat/ti/common/k3_console.c

diff --git a/plat/ti/k3/common/k3_gicv3.c b/plat/ti/common/k3_gicv3.c
similarity index 100%
rename from plat/ti/k3/common/k3_gicv3.c
rename to plat/ti/common/k3_gicv3.c

diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/common/k3_helpers.S
similarity index 100%
rename from plat/ti/k3/common/k3_helpers.S
rename to plat/ti/common/k3_helpers.S

diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/common/plat_common.mk
similarity index 77%
rename from plat/ti/k3/common/plat_common.mk
rename to plat/ti/common/plat_common.mk
index 8db732c..1f1b618 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/common/plat_common.mk

@@ -51,12 +51,11 @@
 
 PLAT_INCLUDES		+=	\
 				-I${PLAT_PATH}/include			\
-				-I${PLAT_PATH}/common/drivers/sec_proxy	\
-				-I${PLAT_PATH}/common/drivers/ti_sci	\
+				-Idrivers/ti/ti_sci			\
 
 K3_CONSOLE_SOURCES	+=	\
 				drivers/ti/uart/aarch64/16550_console.S	\
-				${PLAT_PATH}/common/k3_console.c	\
+				plat/ti/common/k3_console.c		\
 
 # Include GICv3 driver files
 include drivers/arm/gic/v3/gicv3.mk
@@ -64,17 +63,14 @@
 K3_GIC_SOURCES		+=	\
 				${GICV3_SOURCES}			\
 				plat/common/plat_gicv3.c		\
-				${PLAT_PATH}/common/k3_gicv3.c		\
+				plat/ti/common/k3_gicv3.c		\
 
 K3_PSCI_SOURCES		+=	\
 				plat/common/plat_psci_common.c		\
-				${PLAT_PATH}/common/k3_psci.c		\
 
-K3_SEC_PROXY_SOURCES	+=	\
-				${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
 
 K3_TI_SCI_SOURCES	+=	\
-				${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
+				drivers/ti/ti_sci/ti_sci.c		\
 
 PLAT_BL_COMMON_SOURCES	+=	\
 				lib/cpus/aarch64/cortex_a53.S		\
@@ -83,10 +79,7 @@
 				${K3_CONSOLE_SOURCES}			\
 
 BL31_SOURCES		+=	\
-				${PLAT_PATH}/common/k3_bl31_setup.c	\
-				${PLAT_PATH}/common/k3_helpers.S	\
-				${PLAT_PATH}/common/k3_topology.c	\
+				plat/ti/common/ti_bl31_setup.c		\
+				plat/ti/common/k3_helpers.S		\
 				${K3_GIC_SOURCES}			\
-				${K3_PSCI_SOURCES}			\
-				${K3_SEC_PROXY_SOURCES}			\
 				${K3_TI_SCI_SOURCES}			\

diff --git a/plat/ti/common/ti_bl31_setup.c b/plat/ti/common/ti_bl31_setup.c
new file mode 100644
index 0000000..8038452
--- /dev/null
+++ b/plat/ti/common/ti_bl31_setup.c

@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <ti_sci.h>
+
+#include <k3_console.h>
+#include <k3_gicv3.h>
+#include <plat_private.h>
+#include <platform_def.h>
+
+/*
+ * Placeholder variables for maintaining information about the next image(s)
+ */
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+/*******************************************************************************
+ * Gets SPSR for BL33 entry
+ ******************************************************************************/
+static uint32_t k3_get_spsr_for_bl33_entry(void)
+{
+	unsigned long el_status;
+	unsigned int mode;
+	uint32_t spsr;
+
+	/* Figure out what mode we enter the non-secure world in */
+	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
+	el_status &= ID_AA64PFR0_ELX_MASK;
+
+	mode = (el_status) ? MODE_EL2 : MODE_EL1;
+
+	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+	return spsr;
+}
+
+/*******************************************************************************
+ * Perform any BL3-1 early platform setup, such as console init and deciding on
+ * memory layout.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+{
+	/* Initialize the console to provide early debug support */
+	k3_console_setup();
+
+#ifdef BL32_BASE
+	/* Populate entry point information for BL32 */
+	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
+	bl32_image_ep_info.pc = BL32_BASE;
+	bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
+					  DISABLE_ALL_EXCEPTIONS);
+	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+#endif
+
+	/* Populate entry point information for BL33 */
+	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
+	bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
+	bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
+	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+#ifdef K3_HW_CONFIG_BASE
+	/*
+	 * According to the file ``Documentation/arch/arm64/booting.rst`` of the
+	 * Linux kernel tree, Linux expects the physical address of the device
+	 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+	 * must be 0.
+	 */
+	bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
+	bl33_image_ep_info.args.arg1 = 0U;
+	bl33_image_ep_info.args.arg2 = 0U;
+	bl33_image_ep_info.args.arg3 = 0U;
+#endif
+}
+
+void bl31_plat_arch_setup(void)
+{
+	const mmap_region_t bl_regions[] = {
+		MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
+		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
+				MT_CODE | MT_RO | MT_SECURE),
+		MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
+				MT_RO_DATA | MT_RO | MT_SECURE),
+#if USE_COHERENT_MEM
+		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+				MT_DEVICE | MT_RW | MT_SECURE),
+#endif
+		{ /* sentinel */ }
+	};
+
+	setup_page_tables(bl_regions, plat_k3_mmap);
+	enable_mmu_el3(0);
+}
+
+void bl31_platform_setup(void)
+{
+	k3_gic_driver_init(K3_GIC_BASE);
+	k3_gic_init();
+	ti_soc_init();
+}
+
+void platform_mem_init(void)
+{
+	/* Do nothing for now... */
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	uint32_t gtc_freq;
+	uint32_t gtc_ctrl;
+
+	/* Lets try and provide basic diagnostics - cost is low */
+	gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
+	/* Did the bootloader fail to enable timer and OS guys are confused? */
+	if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
+		ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
+	}
+	/*
+	 * If debug will not pause time, we will have issues like
+	 * drivers timing out while debugging, in cases of OS like Linux,
+	 * RCU stall errors, which can be hard to differentiate vs real issues.
+	 */
+	if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
+		WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
+	}
+
+	gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
+	/* Many older bootloaders may have missed programming FID0 register */
+	if (gtc_freq != 0U) {
+		return gtc_freq;
+	}
+
+	/*
+	 * We could have just warned about this, but this can have serious
+	 * hard to debug side effects if we are NOT sure what the actual
+	 * frequency is. Lets make sure people don't miss this.
+	 */
+	ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
+	      SYS_COUNTER_FREQ_IN_TICKS);
+
+	return SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image
+ * for the security state specified. BL3-3 corresponds to the non-secure
+ * image type while BL3-2 corresponds to the secure image type. A NULL
+ * pointer is returned if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	entry_point_info_t *next_image_info;
+
+	assert(sec_state_is_valid(type));
+	next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
+						 &bl32_image_ep_info;
+	/*
+	 * None of the images on the ARM development platforms can have 0x0
+	 * as the entrypoint
+	 */
+	if (next_image_info->pc)
+		return next_image_info;
+
+	NOTICE("Requested nonexistent image\n");
+	return NULL;
+}

diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
deleted file mode 100644
index 4005102..0000000
--- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
+++ /dev/null

@@ -1,82 +0,0 @@
-/*
- * Texas Instruments K3 Secure Proxy Driver
- *   Based on Linux and U-Boot implementation
- *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SEC_PROXY_H
-#define SEC_PROXY_H
-
-#include <stdint.h>
-
-/**
- * enum k3_sec_proxy_chan_id - Secure Proxy thread IDs
- *
- * These the available IDs used in k3_sec_proxy_{send,recv}()
- * There are two schemes we use:
- * * if K3_SEC_PROXY_LITE = 1, we just have two threads to talk
- * * if K3_SEC_PROXY_LITE = 0, we have the full fledged
- *   communication scheme available.
- */
-enum k3_sec_proxy_chan_id {
-#if !K3_SEC_PROXY_LITE
-	SP_NOTIFY = 0,
-	SP_RESPONSE,
-	SP_HIGH_PRIORITY,
-	SP_LOW_PRIORITY,
-	SP_NOTIFY_RESP,
-#else
-	SP_RESPONSE = 8,
-	/*
-	 * Note: TISCI documentation indicates "low priority", but in reality
-	 * with a single thread, there is no low or high priority.. This usage
-	 * is more appropriate for TF-A since we can reduce the churn as a
-	 * result.
-	 */
-	SP_HIGH_PRIORITY,
-#endif /* K3_SEC_PROXY_LITE */
-};
-
-/**
- * struct k3_sec_proxy_msg - Secure proxy message structure
- * @len: Length of data in the Buffer
- * @buf: Buffer pointer
- *
- * This is the structure for data used in k3_sec_proxy_{send,recv}()
- */
-struct k3_sec_proxy_msg {
-	size_t len;
-	uint8_t *buf;
-};
-
-/**
- * k3_sec_proxy_clear_rx_thread() - Clear a receive Secure Proxy thread
- * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
- *
- * Return: 0 if all goes well, else appropriate error message
- */
-int k3_sec_proxy_clear_rx_thread(enum k3_sec_proxy_chan_id id);
-
-/**
- * k3_sec_proxy_send() - Send data over a Secure Proxy thread
- * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
- *
- * Return: 0 if all goes well, else appropriate error message
- */
-int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_msg *msg);
-
-/**
- * k3_sec_proxy_recv() - Receive data from a Secure Proxy thread
- * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
- *
- * Return: 0 if all goes well, else appropriate error message
- */
-int k3_sec_proxy_recv(enum k3_sec_proxy_chan_id id, struct k3_sec_proxy_msg *msg);
-
-#endif /* SEC_PROXY_H */

diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index 63fe020..1b93dc8 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c

@@ -1,30 +1,16 @@
 /*
  * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ * K3 SOC specific bl31_setup
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/bl_common.h>
 #include <common/debug.h>
-#include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-#include <k3_console.h>
-#include <k3_gicv3.h>
 #include <ti_sci.h>
+#include <ti_sci_transport.h>
 
-#define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U))
-#define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr))
-
-#define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \
-	MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr)
+#include <plat_private.h>
 
 /* Table of regions to map using the MMU */
 const mmap_region_t plat_k3_mmap[] = {
@@ -37,98 +23,15 @@
 	{ /* sentinel */ }
 };
 
-/*
- * Placeholder variables for maintaining information about the next image(s)
- */
-static entry_point_info_t bl32_image_ep_info;
-static entry_point_info_t bl33_image_ep_info;
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-static uint32_t k3_get_spsr_for_bl33_entry(void)
-{
-	unsigned long el_status;
-	unsigned int mode;
-	uint32_t spsr;
-
-	/* Figure out what mode we enter the non-secure world in */
-	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
-	el_status &= ID_AA64PFR0_ELX_MASK;
-
-	mode = (el_status) ? MODE_EL2 : MODE_EL1;
-
-	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-	return spsr;
-}
-
-/*******************************************************************************
- * Perform any BL3-1 early platform setup, such as console init and deciding on
- * memory layout.
- ******************************************************************************/
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
-				u_register_t arg2, u_register_t arg3)
-{
-	/* Initialize the console to provide early debug support */
-	k3_console_setup();
-
-#ifdef BL32_BASE
-	/* Populate entry point information for BL32 */
-	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
-	bl32_image_ep_info.pc = BL32_BASE;
-	bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
-					  DISABLE_ALL_EXCEPTIONS);
-	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
-#endif
-
-	/* Populate entry point information for BL33 */
-	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
-	bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
-	bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
-	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-
-#ifdef K3_HW_CONFIG_BASE
-	/*
-	 * According to the file ``Documentation/arm64/booting.txt`` of the
-	 * Linux kernel tree, Linux expects the physical address of the device
-	 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
-	 * must be 0.
-	 */
-	bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
-	bl33_image_ep_info.args.arg1 = 0U;
-	bl33_image_ep_info.args.arg2 = 0U;
-	bl33_image_ep_info.args.arg3 = 0U;
-#endif
-}
-
-void bl31_plat_arch_setup(void)
-{
-	const mmap_region_t bl_regions[] = {
-		MAP_REGION_FLAT(BL31_START,           BL31_SIZE,			          MT_MEMORY  | MT_RW | MT_SECURE),
-		MAP_REGION_FLAT(BL_CODE_BASE,         BL_CODE_END         - BL_CODE_BASE,         MT_CODE    | MT_RO | MT_SECURE),
-		MAP_REGION_FLAT(BL_RO_DATA_BASE,      BL_RO_DATA_END      - BL_RO_DATA_BASE,      MT_RO_DATA | MT_RO | MT_SECURE),
-#if USE_COHERENT_MEM
-		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE  | MT_RW | MT_SECURE),
-#endif
-		{ /* sentinel */ }
-	};
-
-	setup_page_tables(bl_regions, plat_k3_mmap);
-	enable_mmu_el3(0);
-}
-
-void bl31_platform_setup(void)
+int ti_soc_init(void)
 {
 	struct ti_sci_msg_version version;
 	int ret;
 
-	k3_gic_driver_init(K3_GIC_BASE);
-	k3_gic_init();
-
 	ret = ti_sci_get_revision(&version);
 	if (ret) {
 		ERROR("Unable to communicate with the control firmware (%d)\n", ret);
-		return;
+		return ret;
 	}
 
 	INFO("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
@@ -157,70 +60,5 @@
 	} else {
 		NOTICE("Upgrade Firmwares for Power off functionality\n");
 	}
-}
-
-void platform_mem_init(void)
-{
-	/* Do nothing for now... */
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
-	uint32_t gtc_freq;
-	uint32_t gtc_ctrl;
-
-	/* Lets try and provide basic diagnostics - cost is low */
-	gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
-	/* Did the bootloader fail to enable timer and OS guys are confused? */
-	if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
-		ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
-	}
-	/*
-	 * If debug will not pause time, we will have issues like
-	 * drivers timing out while debugging, in cases of OS like Linux,
-	 * RCU stall errors, which can be hard to differentiate vs real issues.
-	 */
-	if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
-		WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
-	}
-
-	gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
-	/* Many older bootloaders may have missed programming FID0 register */
-	if (gtc_freq != 0U) {
-		return gtc_freq;
-	}
-
-	/*
-	 * We could have just warned about this, but this can have serious
-	 * hard to debug side effects if we are NOT sure what the actual
-	 * frequency is. Lets make sure people don't miss this.
-	 */
-	ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
-	      SYS_COUNTER_FREQ_IN_TICKS);
-
-	return SYS_COUNTER_FREQ_IN_TICKS;
-}
-
-/*******************************************************************************
- * Return a pointer to the 'entry_point_info' structure of the next image
- * for the security state specified. BL3-3 corresponds to the non-secure
- * image type while BL3-2 corresponds to the secure image type. A NULL
- * pointer is returned if the image does not exist.
- ******************************************************************************/
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
-	entry_point_info_t *next_image_info;
-
-	assert(sec_state_is_valid(type));
-	next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
-						 &bl32_image_ep_info;
-	/*
-	 * None of the images on the ARM development platforms can have 0x0
-	 * as the entrypoint
-	 */
-	if (next_image_info->pc)
-		return next_image_info;
-
-	NOTICE("Requested nonexistent image\n");
-	return NULL;
+	return 0;
 }

diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index df49f48..c679344 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c

@@ -226,14 +226,6 @@
 		wfi();
 }
 
-static int k3_validate_power_state(unsigned int power_state,
-				   psci_power_state_t *req_state)
-{
-	/* TODO: perform the proper validation */
-
-	return PSCI_E_SUCCESS;
-}
-
 static void k3_pwr_domain_suspend_to_mode(const psci_power_state_t *target_state, uint8_t mode)
 {
 	unsigned int core, proc_id;
@@ -294,7 +286,6 @@
 	.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
 	.system_off = k3_system_off,
 	.system_reset = k3_system_reset,
-	.validate_power_state = k3_validate_power_state,
 };
 
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,

diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index a2cc62d..db5e31d 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h

@@ -7,174 +7,7 @@
 #ifndef PLATFORM_DEF_H
 #define PLATFORM_DEF_H
 
-#include <arch.h>
-#include <plat/common/common_def.h>
-
-#include <board_def.h>
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stack */
-#if IMAGE_BL31
-#define PLATFORM_STACK_SIZE		0x800
-#else
-#define PLATFORM_STACK_SIZE		0x1000
-#endif
-
-#define PLATFORM_SYSTEM_COUNT		1
-#define PLATFORM_CORE_COUNT		(K3_CLUSTER0_CORE_COUNT + \
-					K3_CLUSTER1_CORE_COUNT + \
-					K3_CLUSTER2_CORE_COUNT + \
-					K3_CLUSTER3_CORE_COUNT)
-
-#define PLATFORM_CLUSTER_COUNT		((K3_CLUSTER0_CORE_COUNT != 0) + \
-					(K3_CLUSTER1_CORE_COUNT != 0) + \
-					(K3_CLUSTER2_CORE_COUNT != 0) + \
-					(K3_CLUSTER3_CORE_COUNT != 0))
-
-#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_SYSTEM_COUNT + \
-					PLATFORM_CLUSTER_COUNT + \
-					PLATFORM_CORE_COUNT)
-#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
-#define PLAT_MAX_OFF_STATE		U(2)
-#define PLAT_MAX_RET_STATE		U(1)
-
-/*******************************************************************************
- * Memory layout constants
- ******************************************************************************/
-
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- *
- * The link addresses are determined by BL31_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * BL31_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * BL31_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define BL31_BASE	UL(0x00000000) /* PIE remapped on fly */
-#define BL31_SIZE	UL(0x00020000) /* 128k */
-#define BL31_LIMIT	(BL31_BASE + BL31_SIZE)
-
-/*
- * Defines the maximum number of translation tables that are allocated by the
- * translation table library code. To minimize the amount of runtime memory
- * used, choose the smallest value needed to map the required virtual addresses
- * for each BL stage.
- */
-#define MAX_XLAT_TABLES		4
-
-/*
- * Defines the maximum number of regions that are allocated by the translation
- * table library code. A region consists of physical base address, virtual base
- * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
- * defined in the `mmap_region_t` structure. The platform defines the regions
- * that should be mapped. Then, the translation table library will create the
- * corresponding tables and descriptors at runtime. To minimize the amount of
- * runtime memory used, choose the smallest value needed to register the
- * required regions for each BL stage.
- */
-#if USE_COHERENT_MEM
-#define MAX_MMAP_REGIONS	11
-#else
-#define MAX_MMAP_REGIONS	10
-#endif
-
-/*
- * Defines the total size of the address space in bytes. For example, for a 32
- * bit address space, this value should be `(1ull << 32)`.
- */
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
-
-/*
- * Some data must be aligned on the biggest cache line size in the platform.
- * This is known only to the platform as it might have a combination of
- * integrated and external caches.
- */
-#define CACHE_WRITEBACK_SHIFT		6
-#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
-
-/* Platform default console definitions */
-#ifndef K3_USART_BASE
-#define K3_USART_BASE			(0x02800000 + 0x10000 * K3_USART)
-#endif
-
-/* USART has a default size for address space */
-#define K3_USART_SIZE 0x1000
-
-#ifndef K3_USART_CLK_SPEED
-#define K3_USART_CLK_SPEED 48000000
-#endif
-
-/* Crash console defaults */
-#define CRASH_CONSOLE_BASE K3_USART_BASE
-#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
-#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
-
-/* Timer frequency */
-#ifndef SYS_COUNTER_FREQ_IN_TICKS
-#define SYS_COUNTER_FREQ_IN_TICKS 200000000
-#endif
-
-/* Interrupt numbers */
-#define ARM_IRQ_SEC_PHY_TIMER		29
-
-#define ARM_IRQ_SEC_SGI_0		8
-#define ARM_IRQ_SEC_SGI_1		9
-#define ARM_IRQ_SEC_SGI_2		10
-#define ARM_IRQ_SEC_SGI_3		11
-#define ARM_IRQ_SEC_SGI_4		12
-#define ARM_IRQ_SEC_SGI_5		13
-#define ARM_IRQ_SEC_SGI_6		14
-#define ARM_IRQ_SEC_SGI_7		15
-
-/*
- * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE)
-
-#define PLAT_ARM_G0_IRQ_PROPS(grp) \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE), \
-	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
-			GIC_INTR_CFG_EDGE)
-
-
-#define K3_GTC_BASE		0x00A90000
-/* We just need 20 byte offset, but simpler to just remap the 64K page in */
-#define K3_GTC_SIZE		0x10000
-#define K3_GTC_CNTCR_OFFSET	0x00
-#define K3_GTC_CNTCR_EN_MASK	0x01
-#define K3_GTC_CNTCR_HDBG_MASK	0x02
-#define K3_GTC_CNTFID0_OFFSET	0x20
-
-#define K3_GIC_BASE	0x01800000
-#define K3_GIC_SIZE	0x200000
+#include <ti_platform_defs.h>
 
 #if !K3_SEC_PROXY_LITE
 #define SEC_PROXY_DATA_BASE	0x32C00000
@@ -195,7 +28,4 @@
 #define SEC_PROXY_TIMEOUT_US		1000000
 #define SEC_PROXY_MAX_MESSAGE_SIZE	56
 
-#define TI_SCI_HOST_ID			10
-#define TI_SCI_MAX_MESSAGE_SIZE		52
-
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk
index bce9ef1..347a088 100644
--- a/plat/ti/k3/platform.mk
+++ b/plat/ti/k3/platform.mk

@@ -7,7 +7,7 @@
 PLAT_PATH	:=	plat/ti/k3
 TARGET_BOARD	?=	generic
 
-include ${PLAT_PATH}/common/plat_common.mk
+include plat/ti/common/plat_common.mk
 include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
 
 BL32_BASE ?= 0x9e800000
@@ -19,7 +19,20 @@
 K3_HW_CONFIG_BASE ?= 0x82000000
 $(eval $(call add_define,K3_HW_CONFIG_BASE))
 
-PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include
+PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include	\
+		 -Iplat/ti/common/include			\
 
 # modify BUILD_PLAT to point to board specific build directory
 BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}
+
+K3_PSCI_SOURCES		+=	\
+				${PLAT_PATH}/common/k3_psci.c		\
+
+K3_TI_SCI_TRANSPORT	:=	\
+				drivers/ti/ipc/sec_proxy.c		\
+
+BL31_SOURCES		+=	\
+				${PLAT_PATH}/common/k3_bl31_setup.c	\
+				${PLAT_PATH}/common/k3_topology.c	\
+				${K3_TI_SCI_TRANSPORT}			\
+				${K3_PSCI_SOURCES}			\

diff --git a/plat/ti/k3low/board/am62lx/board.mk b/plat/ti/k3low/board/am62lx/board.mk
new file mode 100644
index 0000000..26e58c6
--- /dev/null
+++ b/plat/ti/k3low/board/am62lx/board.mk

@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2024-2025, Texas Instruments Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# We dont have system level coherency capability
+USE_COHERENT_MEM	:=	0
+
+BL32_BASE ?= 0x80200000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x82000000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x88000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))

diff --git a/plat/ti/k3low/board/am62lx/include/board_def.h b/plat/ti/k3low/board/am62lx/include/board_def.h
new file mode 100644
index 0000000..ea46423
--- /dev/null
+++ b/plat/ti/k3low/board/am62lx/include/board_def.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOARD_DEF_H
+#define BOARD_DEF_H
+
+#include <lib/utils_def.h>
+
+/* The ports must be in order and contiguous */
+#define K3_CLUSTER0_CORE_COUNT		U(2)
+#define K3_CLUSTER1_CORE_COUNT		U(0)
+#define K3_CLUSTER2_CORE_COUNT		U(0)
+#define K3_CLUSTER3_CORE_COUNT		U(0)
+
+#define PLAT_PROC_START_ID		U(32)
+#define PLAT_PROC_DEVICE_START_ID	U(135)
+#define PLAT_CLUSTER_DEVICE_START_ID	U(134)
+#define PLAT_BOARD_DEVICE_ID		U(157)
+
+/* Pre-decided SRAM Addresses for sending and receiving messages */
+#define MAILBOX_TX_START_REGION		UL(0x70814000)
+#define MAILBOX_RX_START_REGION		UL(0x70815000)
+/*
+ * Pre-calculated MAX size of a message
+ * sec_hdr + (type/host/seq + flags) + payload
+ * 4 + 16 + 36
+ */
+#define MAILBOX_MAX_MESSAGE_SIZE	U(56)
+
+#endif /* BOARD_DEF_H */

diff --git a/plat/ti/k3low/common/am62l_bl31_setup.c b/plat/ti/k3low/common/am62l_bl31_setup.c
new file mode 100644
index 0000000..22255f4
--- /dev/null
+++ b/plat/ti/k3low/common/am62l_bl31_setup.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/
+ * K3 SOC specific bl31_setup
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <ti_sci.h>
+#include <ti_sci_transport.h>
+
+#include <plat_private.h>
+
+/* Table of regions to map using the MMU */
+const mmap_region_t plat_k3_mmap[] = {
+	{ /* sentinel */ }
+};
+
+int ti_soc_init(void)
+{
+	/* nothing to do right now */
+	return 0;
+}

diff --git a/plat/ti/k3low/common/am62l_psci.c b/plat/ti/k3low/common/am62l_psci.c
new file mode 100644
index 0000000..b14f0f5
--- /dev/null
+++ b/plat/ti/k3low/common/am62l_psci.c

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/el3_runtime/cpu_data.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+#include <ti_sci.h>
+#include <ti_sci_protocol.h>
+
+#include <k3_gicv3.h>
+#include <platform_def.h>
+
+uintptr_t am62l_sec_entrypoint;
+uintptr_t am62l_sec_entrypoint_glob;
+void  __aligned(16) jump_to_atf_func(void *unused);
+
+static int am62l_pwr_domain_on(u_register_t mpidr)
+{
+	int32_t core, ret;
+	uint8_t proc_id;
+
+	core = plat_core_pos_by_mpidr(mpidr);
+	if (core < 0) {
+		ERROR("Could not get target core id: %d\n", core);
+		return PSCI_E_INTERN_FAIL;
+	}
+
+	proc_id = (uint8_t)(PLAT_PROC_START_ID + (uint32_t)core);
+
+	ret = ti_sci_proc_request(proc_id);
+	if (ret != 0) {
+		ERROR("Request for processor ID 0x%x failed: %d\n",
+				proc_id, ret);
+		return PSCI_E_INTERN_FAIL;
+	}
+
+	ret = ti_sci_proc_set_boot_cfg(proc_id, am62l_sec_entrypoint, 0, 0);
+	if (ret != 0) {
+		ERROR("Request to set core boot address failed: %d\n", ret);
+		return PSCI_E_INTERN_FAIL;
+	}
+
+	/* sanity check these are off before starting a core */
+	ret = ti_sci_proc_set_boot_ctrl(proc_id,
+			0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
+			PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
+			PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
+	if (ret != 0) {
+		ERROR("Request to clear boot config failed: %d\n", ret);
+		return PSCI_E_INTERN_FAIL;
+	}
+
+	/*
+	 * TODO: Add the actual PM operation call
+	 * to turn on the core here
+	 */
+	return PSCI_E_SUCCESS;
+}
+
+static void am62l_pwr_domain_off(const psci_power_state_t *target_state)
+{
+	/* At very least the local core should be powering down */
+	assert(((target_state)->pwr_domain_state[MPIDR_AFFLVL0]) == PLAT_MAX_OFF_STATE);
+
+	/* Prevent interrupts from spuriously waking up this cpu */
+	k3_gic_cpuif_disable();
+
+}
+
+static void am62l_pwr_down_domain(const psci_power_state_t *target_state)
+{
+	/* TODO: Add the actual pm operation call to turn off the core */
+}
+
+void am62l_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+	k3_gic_pcpu_init();
+	k3_gic_cpuif_enable();
+}
+
+static void am62l_system_reset(void)
+{
+	mmio_write_32(WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE + WKUP_CTRL_MMR0_DEVICE_RESET_OFFSET,
+		      0x6);
+
+	/* Wait for reset to complete for 500ms before printing error */
+	mdelay(500);
+
+	/* Ideally we should not reach here */
+	ERROR("%s: Failed to reset device\n", __func__);
+}
+
+static plat_psci_ops_t am62l_plat_psci_ops = {
+	.pwr_domain_on = am62l_pwr_domain_on,
+	.pwr_domain_off = am62l_pwr_domain_off,
+	.pwr_domain_pwr_down = am62l_pwr_down_domain,
+	.pwr_domain_on_finish = am62l_pwr_domain_on_finish,
+	.system_reset = am62l_system_reset,
+};
+
+void  __aligned(16) jump_to_atf_func(void *unused)
+{
+	/*
+	 * MISRA Deviation observed:
+	 * Rule 11.1 (MISRA C:2012) Prohibits conversion performed between a
+	 * pointer to a function and another incompatible type.
+	 * This conversion is required for handling secure boot entry points.
+	 * The conversion is safe as the address is verified before execution.
+	 */
+	void (*bl31_loc_warm_entry)(void) = (void *)am62l_sec_entrypoint_glob;
+
+	bl31_loc_warm_entry();
+}
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+			const plat_psci_ops_t **psci_ops)
+{
+	am62l_sec_entrypoint_glob = sec_entrypoint;
+	/* Note that boot vector reg in sec mmr requires 16B aligned start address */
+	am62l_sec_entrypoint = (uint64_t)(void *)&jump_to_atf_func;
+	VERBOSE("am62l_sec_entrypoint = 0x%lx\n", am62l_sec_entrypoint);
+
+	*psci_ops = &am62l_plat_psci_ops;
+
+	return 0;
+}

diff --git a/plat/ti/k3low/common/am62l_topology.c b/plat/ti/k3low/common/am62l_topology.c
new file mode 100644
index 0000000..15f5118
--- /dev/null
+++ b/plat/ti/k3low/common/am62l_topology.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+
+#include <platform_def.h>
+
+/* The power domain tree descriptor */
+static unsigned char power_domain_tree_desc[] = {
+	PLATFORM_SYSTEM_COUNT,
+	PLATFORM_CLUSTER_COUNT,
+	K3_CLUSTER0_CORE_COUNT,
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
+
+	if (MPIDR_AFFLVL3_VAL(mpidr) > 0 ||
+	    MPIDR_AFFLVL2_VAL(mpidr) > 0) {
+		return -1;
+	}
+
+	return core;
+}

diff --git a/plat/ti/k3low/include/platform_def.h b/plat/ti/k3low/include/platform_def.h
new file mode 100644
index 0000000..37f984c
--- /dev/null
+++ b/plat/ti/k3low/include/platform_def.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <ti_platform_defs.h>
+
+#define TI_MAILBOX_TX_BASE		UL(0x44240000) /* TFA sending IPC messages to TIFS */
+#define TI_MAILBOX_RX_BASE		UL(0x44250000) /* TIFS sending IPC messages to A53 */
+
+#define WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE	(0x43050000UL)
+#define WKUP_CTRL_MMR0_DEVICE_RESET_OFFSET	(0x4000UL)
+
+#endif /* PLATFORM_DEF_H */

diff --git a/plat/ti/k3low/platform.mk b/plat/ti/k3low/platform.mk
new file mode 100644
index 0000000..5bc47ff
--- /dev/null
+++ b/plat/ti/k3low/platform.mk

@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_PATH	:=	plat/ti/k3low
+TARGET_BOARD	?=	am62lx
+
+include plat/ti/common/plat_common.mk
+include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
+
+PLAT_INCLUDES +=	\
+			-I${PLAT_PATH}/board/${TARGET_BOARD}/include	\
+			-I${PLAT_PATH}					\
+			-Iplat/ti/common/include			\
+
+K3_PSCI_SOURCES		+=	\
+				${PLAT_PATH}/common/am62l_psci.c	\
+
+K3_TI_SCI_TRANSPORT	:=	\
+				drivers/ti/ipc/mailbox.c		\
+
+BL31_SOURCES		+=	\
+				drivers/delay_timer/delay_timer.c		\
+				${K3_PSCI_SOURCES}				\
+				${K3_TI_SCI_TRANSPORT}				\
+				${PLAT_PATH}/common/am62l_bl31_setup.c		\
+				${PLAT_PATH}/common/am62l_topology.c		\

diff --git a/plat/xilinx/zynqmp/custom_sip_svc.c b/plat/xilinx/common/custom_sip_svc.c
similarity index 90%
rename from plat/xilinx/zynqmp/custom_sip_svc.c
rename to plat/xilinx/common/custom_sip_svc.c
index c39e4be..2cefb78 100644
--- a/plat/xilinx/zynqmp/custom_sip_svc.c
+++ b/plat/xilinx/common/custom_sip_svc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

diff --git a/plat/xilinx/zynqmp/include/custom_svc.h b/plat/xilinx/common/include/custom_svc.h
similarity index 71%
rename from plat/xilinx/zynqmp/include/custom_svc.h
rename to plat/xilinx/common/include/custom_svc.h
index 242f3eb..2884b69 100644
--- a/plat/xilinx/zynqmp/include/custom_svc.h
+++ b/plat/xilinx/common/include/custom_svc.h

@@ -1,13 +1,13 @@
 /*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef CUSTOM_SVC_H
 #define CUSTOM_SVC_H
 
-#define ZYNQMP_SIP_SVC_CUSTOM   U(0x82002000)
-#define ZYNQMP_SIP_SVC64_CUSTOM U(0xC2002000)
+#define SOC_SIP_SVC_CUSTOM   U(0x82002000)
+#define SOC_SIP_SVC64_CUSTOM U(0xC2002000)
 
 uint64_t custom_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
 			    uint64_t x3, uint64_t x4, void *cookie,

diff --git a/plat/xilinx/common/include/ipi.h b/plat/xilinx/common/include/ipi.h
index d792710..c628496 100644
--- a/plat/xilinx/common/include/ipi.h
+++ b/plat/xilinx/common/include/ipi.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,9 +38,9 @@
 
 /* structure to maintain IPI configuration information */
 struct ipi_config {
-	unsigned int ipi_bit_mask;
-	unsigned int ipi_reg_base;
-	unsigned char secure_only;
+	uint32_t ipi_bit_mask;
+	uint32_t ipi_reg_base;
+	uint8_t secure_only;
 };
 
 /*********************************************************************
@@ -51,7 +52,7 @@
 			   uint32_t total_ipi);
 
 /* Validate IPI mailbox access */
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure);
+int32_t ipi_mb_validate(uint32_t local, uint32_t remote, uint32_t is_secure);
 
 /* Open the IPI mailbox */
 void ipi_mb_open(uint32_t local, uint32_t remote);
@@ -60,7 +61,7 @@
 void ipi_mb_release(uint32_t local, uint32_t remote);
 
 /* Enquire IPI mailbox status */
-int ipi_mb_enquire_status(uint32_t local, uint32_t remote);
+uint32_t ipi_mb_enquire_status(uint32_t local, uint32_t remote);
 
 /* Trigger notification on the IPI mailbox */
 void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking);

diff --git a/plat/xilinx/common/include/pm_api_sys.h b/plat/xilinx/common/include/pm_api_sys.h
index 029bb43..fc55cc3 100644
--- a/plat/xilinx/common/include/pm_api_sys.h
+++ b/plat/xilinx/common/include/pm_api_sys.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,7 +24,7 @@
 
 enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
 				       uint32_t x2, uint32_t x3, uint32_t x4,
-				       uint32_t x5, uint64_t *result);
+				       uint32_t x5, uint32_t *result);
 enum pm_ret_status pm_self_suspend(uint32_t nid,
 				   uint32_t latency,
 				   uint32_t state,
@@ -36,25 +36,15 @@
 				  uint32_t state, uint32_t flag);
 enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address,
 				 uintptr_t address, uint8_t ack, uint32_t flag);
-enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t device_id,
+enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device,
 					uint8_t enable, uint32_t flag);
 enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag,
 			 uint32_t ack);
 void pm_client_set_wakeup_sources(uint32_t node_id);
-enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
-				    uint32_t value, uint32_t flag);
-enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
-				    uint32_t *value, uint32_t flag);
-enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode,
-				   uint32_t flag);
-enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode,
-				   uint32_t flag);
 enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack,
 				      uint32_t flag);
 enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype,
 				      uint32_t flag);
-enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
-				 uint32_t arg3, uint32_t *data, uint32_t flag);
 uint32_t pm_get_shutdown_scope(void);
 enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *ret_payload,
 				    uint32_t flag);
@@ -70,7 +60,8 @@
  * Assigning of argument values into array elements.
  */
 #define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) {	\
-	pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \
+	pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | \
+		((uint32_t)(mid) << 8U) | ((uint32_t)(flag) << 24U)); \
 }
 
 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) {		\

diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h
index 68d1db2..5e53ec6 100644
--- a/plat/xilinx/common/include/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,9 +29,9 @@
 #define RET_PAYLOAD_ARG_CNT	6U
 #define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
 
-#define TZ_VERSION_MAJOR	1
-#define TZ_VERSION_MINOR	0
-#define TZ_VERSION		((TZ_VERSION_MAJOR << 16) | \
+#define TZ_VERSION_MAJOR	1U
+#define TZ_VERSION_MINOR	0U
+#define TZ_VERSION		(((uint32_t)TZ_VERSION_MAJOR << 16U) | \
 				 TZ_VERSION_MINOR)
 
 /**

diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index 9920611..3901555 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,7 +22,6 @@
 #define PM_STATE_SUSPEND_TO_RAM	0xFU
 
 #define MAX_LATENCY		(~0U)
-#define MAX_QOS			100U
 
 /* Processor core device IDs */
 #define APU_DEVID(IDX)	NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \
@@ -202,28 +201,6 @@
 	ABORT_REASON_UNKNOWN,
 };
 
-enum pm_opchar_type {
-	PM_OPCHAR_TYPE_POWER = 1,
-	PM_OPCHAR_TYPE_TEMP,
-	PM_OPCHAR_TYPE_LATENCY,
-};
-
-/*
- * Subsystem IDs
- */
-typedef enum {
-	XPM_SUBSYSID_PMC,
-	XPM_SUBSYSID_PSM,
-	XPM_SUBSYSID_APU,
-	XPM_SUBSYSID_RPU0_LOCK,
-	XPM_SUBSYSID_RPU0_0,
-	XPM_SUBSYSID_RPU0_1,
-	XPM_SUBSYSID_DDR0,
-	XPM_SUBSYSID_ME,
-	XPM_SUBSYSID_PL,
-	XPM_SUBSYSID_MAX,
-} XPm_SubsystemId;
-
 /* TODO: move pm_ret_status from device specific location to common location */
 /**
  * enum pm_ret_status - enum represents the return status codes for a PM
@@ -231,7 +208,7 @@
  * @PM_RET_SUCCESS: success.
  * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated).
  * @PM_RET_ERROR_NOTSUPPORTED: feature not supported  (deprecated).
- * @PM_RET_ERROR_NOFEATURE: feature is not available.
+ * @PM_RET_ERROR_IOCTL_NOT_SUPPORTED: IOCTL is not supported.
  * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication.
  * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled.
  * @PM_RET_ERROR_INTERNAL: internal error.
@@ -246,21 +223,21 @@
  *                           supported.
  */
 enum pm_ret_status {
-	PM_RET_SUCCESS,
-	PM_RET_ERROR_ARGS = 1,
-	PM_RET_ERROR_NOTSUPPORTED = 4,
-	PM_RET_ERROR_NOFEATURE = 19,
-	PM_RET_ERROR_INVALID_CRC = 301,
-	PM_RET_ERROR_NOT_ENABLED = 29,
-	PM_RET_ERROR_INTERNAL = 2000,
-	PM_RET_ERROR_CONFLICT = 2001,
-	PM_RET_ERROR_ACCESS = 2002,
-	PM_RET_ERROR_INVALID_NODE = 2003,
-	PM_RET_ERROR_DOUBLE_REQ = 2004,
-	PM_RET_ERROR_ABORT_SUSPEND = 2005,
-	PM_RET_ERROR_TIMEOUT = 2006,
-	PM_RET_ERROR_NODE_USED = 2007,
-	PM_RET_ERROR_NO_FEATURE = 2008
+	PM_RET_SUCCESS = 0U,
+	PM_RET_ERROR_ARGS = 1U,
+	PM_RET_ERROR_NOTSUPPORTED = 4U,
+	PM_RET_ERROR_IOCTL_NOT_SUPPORTED = 19U,
+	PM_RET_ERROR_NOT_ENABLED = 29U,
+	PM_RET_ERROR_INVALID_CRC = 301U,
+	PM_RET_ERROR_INTERNAL = 2000U,
+	PM_RET_ERROR_CONFLICT = 2001U,
+	PM_RET_ERROR_ACCESS = 2002U,
+	PM_RET_ERROR_INVALID_NODE = 2003U,
+	PM_RET_ERROR_DOUBLE_REQ = 2004U,
+	PM_RET_ERROR_ABORT_SUSPEND = 2005U,
+	PM_RET_ERROR_TIMEOUT = 2006U,
+	PM_RET_ERROR_NODE_USED = 2007U,
+	PM_RET_ERROR_NO_FEATURE = 2008U
 };
 
 /*

diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 3ee55c2..982a410 100644
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h

@@ -23,9 +23,6 @@
 #define NODE_TYPE_MASK_BITS     GENMASK_32(5, 0)
 #define NODE_INDEX_MASK_BITS    GENMASK_32(13, 0)
 #define NODE_CLASS_MASK         (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
-#define NODE_SUBCLASS_MASK      (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
-#define NODE_TYPE_MASK          (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
-#define NODE_INDEX_MASK         (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
 
 #define NODEID(CLASS, SUBCLASS, TYPE, INDEX)	\
 	     ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
@@ -33,11 +30,7 @@
 	     (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
 	     (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
 
-#define NODECLASS(ID)		(((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
-#define NODESUBCLASS(ID)	(((ID) & NODE_SUBCLASS_MASK) >> \
-				NODE_SUBCLASS_SHIFT)
-#define NODETYPE(ID)		(((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
-#define NODEINDEX(ID)		(((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
+#define NODECLASS(ID)           (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
 
 /*********************************************************************
  * Enum definitions

diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index cc4b04d..8dc6da0 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,6 +20,7 @@
 
 #include <ipi.h>
 #include <plat_private.h>
+#include "pm_defs.h"
 
 /*********************************************************************
  * Macros definitions
@@ -66,12 +67,12 @@
  * Return: - 1 if within range, 0 if not.
  *
  */
-static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
+static inline uint32_t is_ipi_mb_within_range(uint32_t local, uint32_t remote)
 {
-	int ret = 1;
+	uint32_t ret = 1U;
 
 	if ((remote >= ipi_total) || (local >= ipi_total)) {
-		ret = 0;
+		ret = 0U;
 	}
 
 	return ret;
@@ -86,11 +87,11 @@
  * Return: 0 success, negative value for errors.
  *
  */
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
+int32_t ipi_mb_validate(uint32_t local, uint32_t remote, uint32_t is_secure)
 {
-	int ret = 0;
+	int32_t ret = 0;
 
-	if (is_ipi_mb_within_range(local, remote) == 0) {
+	if (is_ipi_mb_within_range(local, remote) == 0U) {
 		ret = -EINVAL;
 	} else if (IPI_IS_SECURE(local) && (is_secure == 0U)) {
 		ret = -EPERM;
@@ -139,13 +140,12 @@
  * @local: local IPI ID.
  * @remote: remote IPI ID.
  *
- * Return: 0 idle, positive value for pending sending or receiving,
- *         negative value for errors.
+ * Return: 0 idle and positive value for pending sending or receiving.
  *
  */
-int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
+uint32_t ipi_mb_enquire_status(uint32_t local, uint32_t remote)
 {
-	int ret = 0U;
+	uint32_t ret = (uint32_t)PM_RET_SUCCESS;
 	uint32_t status;
 	uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
 	uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);

diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index 1882669..a2541a3 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -109,7 +109,7 @@
 		bool disable_interrupt;
 
 		disable_interrupt = ((x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) != 0U);
-		ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
+		ret = (int32_t)ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
 		if ((((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) > 0U) && disable_interrupt) {
 			ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
 		}

diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index 679f935..efb9286 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -109,7 +109,7 @@
  */
 enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
 				       uint32_t x2, uint32_t x3, uint32_t x4,
-				       uint32_t x5, uint64_t *result)
+				       uint32_t x5, uint32_t *result)
 {
 	uint32_t payload[PAYLOAD_ARG_CNT] = {0};
 	uint32_t module_id;
@@ -122,7 +122,7 @@
 	}
 
 	PM_PACK_PAYLOAD6(payload, module_id, flag, x0, x1, x2, x3, x4, x5);
-	return pm_ipi_send_sync(primary_proc, payload, (uint32_t *)result, RET_PAYLOAD_ARG_CNT);
+	return pm_ipi_send_sync(primary_proc, payload, result, RET_PAYLOAD_ARG_CNT);
 }
 
 /**
@@ -163,8 +163,7 @@
 
 	/* Send request to the PLM */
 	PM_PACK_PAYLOAD6(payload, LIBPM_MODULE_ID, flag, PM_SELF_SUSPEND,
-			 proc->node_id, latency, state, address,
-			 (address >> 32));
+			 nid, latency, state, address, (address >> 32));
 	ret = pm_ipi_send_sync(proc, payload, NULL, 0);
 
 exit_label:
@@ -280,6 +279,13 @@
 {
 	enum pm_ret_status ret = PM_RET_SUCCESS;
 
+	/*
+	 * Typecasting to void to intentionally retain the variable and avoid
+	 * MISRA violation for unused parameters. This may be used in the
+	 * future if callbacks to a secure target are required.
+	 */
+	(void)flag;
+
 	/* Return if interrupt is not from PMU */
 	if (pm_ipi_irq_status(primary_proc) != 0U) {
 
@@ -403,6 +409,7 @@
 		break;
 	default:
 		ret = PM_RET_ERROR_NO_FEATURE;
+		break;
 	}
 
 	return ret;
@@ -433,33 +440,31 @@
 	case PM_GET_TRUSTZONE_VERSION:
 		ret_payload[0] = PM_API_VERSION_2;
 		ret = PM_RET_SUCCESS;
-		goto exit_label;
+		break;
 	case TF_A_PM_REGISTER_SGI:
 		ret_payload[0] = PM_API_BASE_VERSION;
 		ret = PM_RET_SUCCESS;
-		goto exit_label;
+		break;
 	default:
+		module_id = (api_id & MODULE_ID_MASK) >> 8U;
+
+		/*
+		 * feature check should be done only for LIBPM module
+		 * If module_id is 0, then we consider it LIBPM module as default id
+		 */
+		if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
+			ret = PM_RET_SUCCESS;
+			break;
+		}
+
+		PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
+				 PM_FEATURE_CHECK, api_id);
+		ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
+
 		break;
 	}
 
-	module_id = (api_id & MODULE_ID_MASK) >> 8U;
-
-	/*
-	 * feature check should be done only for LIBPM module
-	 * If module_id is 0, then we consider it LIBPM module as default id
-	 */
-	if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
-		ret = PM_RET_SUCCESS;
-		goto exit_label;
-	}
-
-	PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
-			PM_FEATURE_CHECK, api_id);
-	ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
-
-exit_label:
 	return ret;
-
 }
 
 /**

diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index bf1fd55..38c36e5 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,7 @@
  * power down. Therefore, there is no doubt to use the spin_lock here.
  */
 #if !HW_ASSISTED_COHERENCY
-DEFINE_BAKERY_LOCK(pm_secure_lock);
+static DEFINE_BAKERY_LOCK(pm_secure_lock);
 static inline void pm_ipi_lock_get(void)
 {
 	bakery_lock_get(&pm_secure_lock);
@@ -186,7 +186,12 @@
 		value[i] = mmio_read_32(buffer_base + ((i + 1U) * PAYLOAD_ARG_SIZE));
 	}
 
-	ret = mmio_read_32(buffer_base);
+	/*
+	 * Here mmio_read_32() reads return status stored in IPI payload that
+	 * is received from firmware and it's value will be one the values
+	 * listed in enum pm_ret_status.
+	 */
+	ret = (enum pm_ret_status)mmio_read_32(buffer_base);
 #if IPI_CRC_CHECK
 	crc = mmio_read_32(buffer_base + (PAYLOAD_CRC_POS * PAYLOAD_ARG_SIZE));
 	if (crc != calculate_crc((uint32_t *)buffer_base, IPI_W0_TO_W6_SIZE)) {
@@ -217,8 +222,8 @@
 enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
 {
 	size_t i;
-	size_t local_count = count;
 #if IPI_CRC_CHECK
+	size_t local_count = count;
 	uint32_t crc;
 #endif
 	uintptr_t buffer_base = IPI_BUFFER_REMOTE_BASE +
@@ -226,14 +231,14 @@
 				IPI_BUFFER_REQ_OFFSET;
 	enum pm_ret_status ret = PM_RET_SUCCESS;
 
-	if (local_count > (uint32_t)IPI_BUFFER_MAX_WORDS) {
-		local_count = IPI_BUFFER_MAX_WORDS;
-	}
-
 	for (i = 0; i < count; i++) {
 		value[i] = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
 	}
 #if IPI_CRC_CHECK
+	if (local_count > (uint32_t)IPI_BUFFER_MAX_WORDS) {
+		local_count = IPI_BUFFER_MAX_WORDS;
+	}
+
 	crc = mmio_read_32(buffer_base + (PAYLOAD_CRC_POS * PAYLOAD_ARG_SIZE));
 	if (crc != calculate_crc((uint32_t *)buffer_base, IPI_W0_TO_W6_SIZE)) {
 		NOTICE("ERROR in CRC response payload value:0x%x\n", crc);
@@ -273,7 +278,8 @@
 		goto unlock;
 	}
 
-	ret = ERROR_CODE_MASK & (uint32_t)(pm_ipi_buff_read(proc, value, count));
+	ret = (enum pm_ret_status)(ERROR_CODE_MASK &
+				   (uint32_t)(pm_ipi_buff_read(proc, value, count)));
 
 unlock:
 	pm_ipi_lock_release();
@@ -293,22 +299,20 @@
 
 uint32_t pm_ipi_irq_status(const struct pm_proc *proc)
 {
-	int32_t ret;
-	int32_t result = 0;
+	uint32_t ret;
+	uint32_t result = (uint32_t)PM_RET_SUCCESS;
 
 	ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id,
 				    proc->ipi->remote_ipi_id);
-	if (((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) != 0U) {
-		result = 1;
-	} else {
-		result = 0;
+	if ((ret & IPI_MB_STATUS_RECV_PENDING) != 0U) {
+		result = IPI_MB_STATUS_RECV_PENDING;
 	}
 
 	return result;
 }
 
 #if IPI_CRC_CHECK
-uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t bufsize)
+uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize)
 {
 	uint32_t crcinit = CRC_INIT_VALUE;
 	uint32_t order   = CRC_ORDER;
@@ -316,20 +320,22 @@
 	uint32_t i, j, c, bit, datain, crcmask, crchighbit;
 	uint32_t crc = crcinit;
 
-	crcmask = ((uint32_t)((1U << (order - 1U)) - 1U) << 1U) | 1U;
-	crchighbit = (uint32_t)(1U << (order - 1U));
+	crcmask = ((((uint32_t)1U << (order - 1U)) - 1U) << 1U) | 1U;
+	crchighbit = ((uint32_t)1U << (order - 1U));
 
-	for (i = 0U; i < bufsize; i++) {
+	for (i = 0U; i < buffersize; i++) {
 		datain = mmio_read_8((unsigned long)payload + i);
 		c = datain;
 		j = 0x80U;
 		while (j != 0U) {
 			bit = crc & crchighbit;
 			crc <<= 1U;
-			if (0U != (c & j))
+			if (0U != (c & j)) {
 				bit ^= crchighbit;
-			if (bit != 0U)
+			}
+			if (bit != 0U) {
 				crc ^= polynom;
+			}
 			j >>= 1U;
 		}
 		crc &= crcmask;

diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index f586ac3..b8ff926 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c

@@ -29,7 +29,6 @@
 
 #define MODE				0x80000000U
 
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT    24U
 #define INVALID_SGI    0xFFU
 #define PM_INIT_SUSPEND_CB	(30U)
 #define PM_NOTIFY_CB		(32U)
@@ -72,7 +71,7 @@
 
 static void notify_os(void)
 {
-	plat_ic_raise_ns_sgi(sgi, read_mpidr_el1());
+	plat_ic_raise_ns_sgi((int)sgi, read_mpidr_el1());
 }
 
 static uint64_t cpu_pwrdwn_req_handler(uint32_t id, uint32_t flags,
@@ -89,7 +88,7 @@
 	/* Deactivate CPU power down SGI */
 	plat_ic_end_of_interrupt(CPU_PWR_DOWN_REQ_INTR);
 
-	return psci_cpu_off();
+	return (uint64_t)psci_cpu_off();
 }
 
 /**
@@ -101,19 +100,19 @@
  */
 static void raise_pwr_down_interrupt(u_register_t mpidr)
 {
-	plat_ic_raise_el3_sgi(CPU_PWR_DOWN_REQ_INTR, mpidr);
+	plat_ic_raise_el3_sgi((int)CPU_PWR_DOWN_REQ_INTR, mpidr);
 }
 
 void request_cpu_pwrdwn(void)
 {
-	enum pm_ret_status ret;
+	int ret;
 
 	VERBOSE("CPU power down request received\n");
 
 	/* Send powerdown request to online secondary core(s) */
 	ret = psci_stop_other_cores(plat_my_core_pos(), PWRDWN_WAIT_TIMEOUT,
 				    raise_pwr_down_interrupt);
-	if (ret != (uint32_t)PSCI_E_SUCCESS) {
+	if (ret != PSCI_E_SUCCESS) {
 		ERROR("Failed to powerdown secondary core(s)\n");
 	}
 
@@ -132,7 +131,7 @@
 	(void)cookie;
 	uint32_t payload[4] = {0};
 	enum pm_ret_status ret;
-	int ipi_status, i;
+	uint32_t ipi_status, i;
 
 	VERBOSE("Received IPI FIQ from firmware\n");
 
@@ -140,19 +139,19 @@
 	(void)plat_ic_acknowledge_interrupt();
 
 	/* Check status register for each IPI except PMC */
-	for (i = (int32_t)IPI_ID_APU; i <= IPI_ID_5; i++) {
+	for (i = IPI_ID_APU; i <= IPI_ID_5; i++) {
 		ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
 
 		/* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
-		if ((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) {
-			plat_ic_raise_ns_sgi(MBOX_SGI_SHARED_IPI, read_mpidr_el1());
+		if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) != 0U) {
+			plat_ic_raise_ns_sgi((int)MBOX_SGI_SHARED_IPI, read_mpidr_el1());
 			break;
 		}
 	}
 
 	/* If PMC has not generated interrupt then end ISR */
 	ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
-	if (((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0U) {
+	if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0U) {
 		plat_ic_end_of_interrupt(id);
 		goto exit_label;
 	}
@@ -171,7 +170,8 @@
 		break;
 	case PM_NOTIFY_CB:
 		if (sgi != INVALID_SGI) {
-			if (payload[2] == EVENT_CPU_PWRDWN) {
+			if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			    (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 				if (pwrdwn_req_received) {
 					pwrdwn_req_received = false;
 					request_cpu_pwrdwn();
@@ -182,12 +182,15 @@
 				}
 			}
 			notify_os();
-		} else if (payload[2] == EVENT_CPU_PWRDWN) {
-			request_cpu_pwrdwn();
-			(void)psci_cpu_off();
+		} else {
+			if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			    (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
+				request_cpu_pwrdwn();
+				(void)psci_cpu_off();
+			}
 		}
 		break;
-	case PM_RET_ERROR_INVALID_CRC:
+	case (uint32_t)PM_RET_ERROR_INVALID_CRC:
 		pm_ipi_irq_clear(primary_proc);
 		WARN("Invalid CRC in the payload\n");
 		break;
@@ -301,7 +304,7 @@
  * until their use case in linux driver changes.
  *
  */
-static uintptr_t eemi_for_compatibility(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_for_compatibility(uint32_t api_id, const uint32_t *pm_arg,
 					void *handle, uint32_t security_flag)
 {
 	enum pm_ret_status ret;
@@ -346,7 +349,7 @@
  * Return: If EEMI API found then, uintptr_t type address, else 0.
  *
  */
-static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, const uint32_t *pm_arg,
 					   void *handle, uint32_t security_flag)
 {
 	enum pm_ret_status ret;
@@ -359,16 +362,16 @@
 		SMC_RET1(handle, (u_register_t)ret);
 
 	case (uint32_t)PM_FORCE_POWERDOWN:
-		ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag);
+		ret = pm_force_powerdown(pm_arg[0], (uint8_t)pm_arg[1], security_flag);
 		SMC_RET1(handle, (u_register_t)ret);
 
 	case (uint32_t)PM_REQ_SUSPEND:
-		ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
+		ret = pm_req_suspend(pm_arg[0], (uint8_t)pm_arg[1], pm_arg[2],
 				     pm_arg[3], security_flag);
 		SMC_RET1(handle, (u_register_t)ret);
 
 	case (uint32_t)PM_ABORT_SUSPEND:
-		ret = pm_abort_suspend(pm_arg[0], security_flag);
+		ret = pm_abort_suspend((enum pm_abort_reason)pm_arg[0], security_flag);
 		SMC_RET1(handle, (u_register_t)ret);
 
 	case (uint32_t)PM_SYSTEM_SHUTDOWN:
@@ -394,7 +397,7 @@
  * Return: If TF-A specific API found then, uintptr_t type address, else 0
  *
  */
-static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t TF_A_specific_handler(uint32_t api_id, const uint32_t *pm_arg,
 				       void *handle, uint32_t security_flag)
 {
 	switch (api_id) {
@@ -426,7 +429,7 @@
 		enum pm_ret_status ret;
 
 		ret = pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U);
-		if (ret != 0) {
+		if (ret != PM_RET_SUCCESS) {
 			result[0] = (uint32_t)ret;
 		}
 
@@ -461,15 +464,14 @@
  * Return: If EEMI API found then, uintptr_t type address, else 0
  *
  */
-static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_handler(uint32_t api_id, const uint32_t *pm_arg,
 			      void *handle, uint32_t security_flag)
 {
 	enum pm_ret_status ret;
 	uint32_t buf[RET_PAYLOAD_ARG_CNT] = {0};
 
 	ret = pm_handle_eemi_call(security_flag, api_id, pm_arg[0], pm_arg[1],
-				  pm_arg[2], pm_arg[3], pm_arg[4],
-				  (uint64_t *)buf);
+				  pm_arg[2], pm_arg[3], pm_arg[4], buf);
 	/*
 	 * Two IOCTLs, to get clock name and pinctrl name of pm_query_data API
 	 * receives 5 words of respoonse from firmware. Currently linux driver can
@@ -597,7 +599,8 @@
 		return ret;
 	}
 
-	ret = eemi_psci_debugfs_handler(api_id, pm_arg, handle, flags);
+	ret = eemi_psci_debugfs_handler(api_id, pm_arg, handle,
+					(uint32_t)flags);
 	if (ret !=  (uintptr_t)0) {
 		return ret;
 	}

diff --git a/plat/xilinx/common/tsp/tsp_plat_setup.c b/plat/xilinx/common/tsp/tsp_plat_setup.c
index 21c29c3..5df4b6e 100644
--- a/plat/xilinx/common/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/common/tsp/tsp_plat_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2023, Advanced Micro Devices. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -17,7 +17,8 @@
 /*******************************************************************************
  * Initialize the UART
  ******************************************************************************/
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+			      u_register_t arg2, u_register_t arg3)
 {
 	/*
 	 * Register a different console than already in use to display

diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index befe36c..70b0fa6 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c

@@ -18,8 +18,9 @@
 #include <plat/common/platform.h>
 #include <plat_arm.h>
 #include <plat_console.h>
-#include <plat_clkfunc.h>
 
+#include <custom_svc.h>
+#include <plat_clkfunc.h>
 #include <plat_fdt.h>
 #include <plat_private.h>
 #include <plat_startup.h>
@@ -143,6 +144,8 @@
 
 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
+
+	custom_early_setup();
 }
 
 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
@@ -220,6 +223,8 @@
 	if (rc != 0) {
 		panic();
 	}
+
+	custom_runtime_setup();
 }
 
 /*
@@ -248,6 +253,8 @@
 		{0}
 	};
 
+	custom_mmap_add();
+
 	setup_page_tables(bl_regions, plat_get_mmap());
 	enable_mmu(0);
 }

diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 8cf8de0..d8b334a 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h

@@ -17,7 +17,9 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
+#ifndef PLATFORM_STACK_SIZE
 #define PLATFORM_STACK_SIZE	U(0x440)
+#endif
 
 #define PLATFORM_CORE_COUNT		U(2)
 #define PLAT_MAX_PWR_LVL		U(1)
@@ -64,6 +66,12 @@
 #endif
 
 /*******************************************************************************
+ * HIGH and LOW DDR MAX definitions
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX		U(0x80000000)
+#define PLAT_DDR_HIGHMEM_MAX		U(0x100000000)
+
+/*******************************************************************************
  * TSP  specific defines.
  ******************************************************************************/
 #define TSP_SEC_MEM_BASE		BL32_BASE

diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index b976267..1c365b4 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,6 +22,9 @@
 #include "pm_ipi.h"
 #include "pm_svc_main.h"
 
+#define SEC_ENTRY_ADDRESS_MASK		0xFFFFFFFFUL
+#define RESUME_ADDR_SET			0x1UL
+
 static uintptr_t versal_sec_entry;
 
 static int32_t versal_pwr_domain_on(u_register_t mpidr)
@@ -42,8 +45,9 @@
 	}
 
 	/* Send request to PMC to wake up selected ACPU core */
-	(void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
-			    versal_sec_entry >> 32, 0, SECURE_FLAG);
+	(void)pm_req_wakeup(proc->node_id,
+			    (uint32_t)((versal_sec_entry & SEC_ENTRY_ADDRESS_MASK) |
+			    RESUME_ADDR_SET), versal_sec_entry >> 32, 0, SECURE_FLAG);
 
 	/* Clear power down request */
 	pm_client_wakeup(proc);
@@ -132,6 +136,13 @@
 
 static void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
+	/*
+	 * Typecasting to void to intentionally retain the variable and avoid
+	 * MISRA violation for unused parameters. This may be used in the
+	 * future if specific action is required based on CPU power state.
+	 */
+	(void)target_state;
+
 	/* Enable the gic cpu interface */
 	plat_versal_gic_pcpu_init();
 
@@ -194,6 +205,18 @@
 	}
 }
 
+static int32_t versal_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+	int32_t ret = PSCI_E_SUCCESS;
+
+	if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
+		((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
+		ret = PSCI_E_INVALID_ADDRESS;
+	}
+
+	return ret;
+}
+
 /**
  * versal_pwr_domain_off() - This function performs actions to turn off core.
  * @target_state: Targated state.
@@ -225,7 +248,8 @@
 	 * invoking CPU_on function, during which resume address will
 	 * be set.
 	 */
-	ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG);
+	ret = (uint32_t)pm_feature_check((uint32_t)PM_SELF_SUSPEND,
+					 &version_type[0], SECURE_FLAG);
 	if (ret == (uint32_t)PM_RET_SUCCESS) {
 		fw_api_version = version_type[0] & 0xFFFFU;
 		if (fw_api_version >= 3U) {
@@ -291,6 +315,7 @@
 	.pwr_domain_suspend_finish	= versal_pwr_domain_suspend_finish,
 	.system_off			= versal_system_off,
 	.system_reset			= versal_system_reset,
+	.validate_ns_entrypoint		= versal_validate_ns_entrypoint,
 	.validate_power_state		= versal_validate_power_state,
 	.get_sys_suspend_power_state	= versal_get_sys_suspend_power_state,
 };
@@ -298,7 +323,7 @@
 /*******************************************************************************
  * Export the platform specific power ops.
  ******************************************************************************/
-int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint,
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const struct plat_psci_ops **psci_ops)
 {
 	versal_sec_entry = sec_entrypoint;

diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 8be4be6..83d2d6f 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk

@@ -144,3 +144,9 @@
 CORTEX_A72_H_INC	:= 1
 $(eval $(call add_define, CORTEX_A72_H_INC))
 endif
+
+ifdef CUSTOM_PKG_PATH
+include $(CUSTOM_PKG_PATH)/custom_pkg.mk
+else
+BL31_SOURCES		+=	plat/xilinx/common/custom_sip_svc.c
+endif

diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index de2cac8..77e3fb0 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,7 +28,7 @@
 
 #define UNDEFINED_CPUID		(~0U)
 
-DEFINE_BAKERY_LOCK(pm_client_secure_lock);
+static DEFINE_BAKERY_LOCK(pm_client_secure_lock);
 
 static const struct pm_ipi apu_ipi = {
 	.local_ipi_id = IPI_LOCAL_ID,

diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index 3027946..5e7ce9e 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,6 +13,7 @@
 #include <common/runtime_svc.h>
 #include <tools_share/uuid.h>
 
+#include <custom_svc.h>
 #include "ipi_mailbox_svc.h"
 #include "pm_svc_main.h"
 
@@ -105,6 +106,11 @@
 	case VERSAL_SIP_SVC_VERSION:
 		SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
 
+	case SOC_SIP_SVC_CUSTOM:
+	case SOC_SIP_SVC64_CUSTOM:
+		return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+					  handle, flags);
+
 	default:
 		WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
 		SMC_RET1(handle, SMC_UNK);
@@ -116,6 +122,6 @@
 		sip_svc,
 		OEN_SIP_START,
 		OEN_SIP_END,
-		SMC_TYPE_FAST,
+		(uint8_t)SMC_TYPE_FAST,
 		sip_svc_setup,
 		sip_svc_smc_handler);

diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index 74b082d..ac2a3c0 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -73,5 +73,6 @@
  */
 void versal_ipi_config_table_init(void)
 {
-	ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table));
+	ipi_config_table_init(versal_ipi_table,
+			      (uint32_t)ARRAY_SIZE(versal_ipi_table));
 }

diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index d131a92..2308a75 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -203,14 +203,28 @@
 	return ret;
 }
 
+#if SDEI_SUPPORT
+static int rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
+				     void *handle, void *cookie)
+#else
 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
 					  void *handle, void *cookie)
+#endif
 {
 	uint32_t intr_id;
 	uint32_t i;
 	interrupt_type_handler_t handler = NULL;
 
+#if SDEI_SUPPORT
+	/* when SDEI_SUPPORT is enabled, ehf_el3_interrupt_handler
+	 * reads the interrupt id prior to calling the
+	 * rdo_el3_interrupt_handler and passes that id to the
+	 * handler.
+	 */
+	intr_id = id;
+#else
 	intr_id = plat_ic_get_pending_interrupt_id();
+#endif
 
 	for (i = 0; i < MAX_INTR_EL3; i++) {
 		if (intr_id == type_el3_interrupt_table[i].id) {
@@ -236,6 +250,7 @@
 
 void bl31_plat_runtime_setup(void)
 {
+#if !SDEI_SUPPORT
 	uint64_t flags = 0;
 	int32_t rc;
 
@@ -245,6 +260,9 @@
 	if (rc != 0) {
 		panic();
 	}
+#else
+	ehf_register_priority_handler(PLAT_IPI_PRI, rdo_el3_interrupt_handler);
+#endif
 }
 
 /*

diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index a7ff84e..461fda8 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,7 @@
 #define PLATFORM_DEF_H
 
 #include <arch.h>
+#include <drivers/arm/gic_common.h>
 #include <plat_common.h>
 #include "versal_net_def.h"
 
@@ -73,6 +74,12 @@
 #endif
 
 /*******************************************************************************
+ * HIGH and LOW DDR MAX definitions
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX		U(0x80000000)
+#define PLAT_DDR_HIGHMEM_MAX		U(0x100000000)
+
+/*******************************************************************************
  * TSP  specific defines.
  ******************************************************************************/
 #define TSP_SEC_MEM_BASE		BL32_BASE
@@ -84,7 +91,6 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define PLAT_DDR_LOWMEM_MAX		U(0x80000000)
 
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32U)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32U)
@@ -114,6 +120,24 @@
 #define PLAT_ARM_GICD_BASE	U(0xE2000000)
 #define PLAT_ARM_GICR_BASE	U(0xE2060000)
 
+/* interrupt priorities when SDEI is enabled:
+ * RAS in future is planned to have highest priority (lower value 0x10)
+ * followed by IPI and SDEI exceptions in a step of 0x10.
+ */
+
+#if SDEI_SUPPORT
+#define VERSAL_NET_SDEI_SGI_PRIVATE     U(8)
+#define PLAT_SDEI_CRITICAL_PRI		0x30
+#define PLAT_SDEI_NORMAL_PRI		0x40
+#define PLAT_PRI_BITS			U(3)
+#define PLAT_IPI_PRI			0x20
+
+#define PLAT_EHF_DESC	EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_IPI_PRI)
+
+#define VERSAL_NET_SDEI_SH_EVENT_0	U(200)
+#define VERSAL_NET_SDEI_PRV_EV		U(201)
+#endif
+
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
@@ -122,6 +146,19 @@
 #define PLAT_VERSAL_NET_IPI_IRQ	89
 #define PLAT_VERSAL_IPI_IRQ	PLAT_VERSAL_NET_IPI_IRQ
 
+#if SDEI_SUPPORT
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, PLAT_IPI_PRI, grp, \
+			GIC_INTR_CFG_LEVEL)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, PLAT_IPI_PRI, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, PLAT_IPI_PRI, grp, \
+			GIC_INTR_CFG_EDGE), \
+	INTR_PROP_DESC(VERSAL_NET_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI, grp, \
+			GIC_INTR_CFG_EDGE)
+#else
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 	INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_LEVEL)
@@ -131,6 +168,7 @@
 			GIC_INTR_CFG_EDGE), \
 	INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \
 			GIC_INTR_CFG_EDGE)
+#endif
 
 #define IRQ_MAX		200U
 

diff --git a/plat/xilinx/versal_net/plat_psci.c b/plat/xilinx/versal_net/plat_psci.c
index fcb32b9..399500d 100644
--- a/plat/xilinx/versal_net/plat_psci.c
+++ b/plat/xilinx/versal_net/plat_psci.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,8 +19,6 @@
 #include <plat_private.h>
 #include <pm_defs.h>
 
-#define PM_RET_ERROR_NOFEATURE U(19)
-
 static uintptr_t versal_net_sec_entry;
 
 static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
@@ -175,7 +173,7 @@
 		mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1);
 		return 0;
 	}
-	return PM_RET_ERROR_NOFEATURE;
+	return PM_RET_ERROR_IOCTL_NOT_SUPPORTED;
 }
 
 static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,

diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index a76832e..6ec8649 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -103,13 +103,27 @@
 	return;
 }
 
+static int32_t versal_net_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+	int32_t ret = PSCI_E_SUCCESS;
+
+	if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
+		((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
+		ret = PSCI_E_INVALID_ADDRESS;
+	}
+
+	return ret;
+}
+
 /**
- * versal_net_system_reset() - This function sends the reset request to firmware
- *                             for the system to reset. This function does not
- *                             return.
+ * versal_net_system_reset_scope() - Sends the reset request to firmware for
+ * the system to reset.
+ * @scope : scope of reset which could be SYSTEM/SUBSYSTEM/PS-ONLY
  *
+ * Return:
+ *     Does not return if system resets, none if there is a failure.
  */
-static void __dead2 versal_net_system_reset(void)
+static void __dead2 versal_net_system_reset_scope(uint32_t scope)
 {
 	uint32_t ret, timeout = 10000U;
 
@@ -121,7 +135,7 @@
 	 */
 	if (!pwrdwn_req_received) {
 		(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
-					 pm_get_shutdown_scope(), SECURE_FLAG);
+					 scope, SECURE_FLAG);
 
 		/*
 		 * Wait for system shutdown request completed and idle callback
@@ -143,6 +157,54 @@
 }
 
 /**
+ * versal_net_system_reset() - This function sends the reset request to firmware
+ * for the system to reset in response to SYSTEM_RESET call
+ *
+ * Return:
+ *     Does not return if system resets, none if there is a failure.
+ */
+static void __dead2 versal_net_system_reset(void)
+{
+	/*
+	 * Any platform-specific actions for handling a cold reset
+	 * should be performed here before invoking
+	 * versal_net_system_reset_scope.
+	 */
+	versal_net_system_reset_scope(XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM);
+}
+
+/**
+ * versal_net_system_reset2() - Handles warm / vendor-specific system reset
+ * in response to SYSTEM_RESET2 call.
+ * @is_vendor: Flag indicating if this is a vendor-specific reset
+ * @reset_type: Type of reset requested
+ * @cookie: Additional reset data
+ *
+ * This function initiates a controlled system reset by requesting it
+ * through the PM firmware.
+ *
+ * Return:
+ *	Does not return if system resets, PSCI_E_INTERN_FAIL
+ *	if there is a failure.
+ */
+static int versal_net_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+	if (is_vendor == 0 && reset_type == PSCI_RESET2_SYSTEM_WARM_RESET) {
+		/*
+		 * Any platform-specific actions for handling a warm reset
+		 * should be performed here before invoking
+		 * versal_net_system_reset_scope.
+		 */
+		versal_net_system_reset_scope(XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM);
+	} else {
+		/* Vendor specific reset */
+		versal_net_system_reset_scope(pm_get_shutdown_scope());
+	}
+
+	return PSCI_E_INTERN_FAIL;
+}
+
+/**
  * versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend
  *                                   core.
  * @target_state: Targeted state.
@@ -303,6 +365,8 @@
 	.pwr_domain_suspend_finish      = versal_net_pwr_domain_suspend_finish,
 	.system_off                     = versal_net_system_off,
 	.system_reset                   = versal_net_system_reset,
+	.system_reset2                  = versal_net_system_reset2,
+	.validate_ns_entrypoint		= versal_net_validate_ns_entrypoint,
 	.validate_power_state           = versal_net_validate_power_state,
 	.get_sys_suspend_power_state    = versal_net_get_sys_suspend_power_state,
 };

diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 25caab4..5e8f2b4 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk

@@ -141,7 +141,14 @@
 				${PLAT_PATH}/bl31_versal_net_setup.c		\
 				common/fdt_fixup.c				\
 				common/fdt_wrappers.c				\
-				plat/arm/common/arm_gicv3.c 			\
+				plat/common/plat_gicv3_base.c			\
 				${LIBFDT_SRCS}					\
 				${PLAT_PATH}/sip_svc_setup.c			\
 				${XLAT_TABLES_LIB_SRCS}
+
+SDEI_SUPPORT := 0
+EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES		+=	plat/common/aarch64/plat_ehf.c          \
+				plat/xilinx/versal_net/versal_net_sdei.c
+endif

diff --git a/plat/xilinx/versal_net/versal_net_sdei.c b/plat/xilinx/versal_net/versal_net_sdei.c
new file mode 100644
index 0000000..e42c066
--- /dev/null
+++ b/plat/xilinx/versal_net/versal_net_sdei.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <bl31/ehf.h>
+#include <common/debug.h>
+#include <plat/common/platform.h>
+#include <services/sdei.h>
+
+#include <platform_def.h>
+
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+	int ret;
+	uintptr_t base = BL31_BASE;
+	uintptr_t limit = BL31_LIMIT;
+
+	ret = ((entrypoint < base) || (entrypoint > limit)) ? 0 : -1;
+	return ret;
+}
+
+/* Private event mappings */
+static sdei_ev_map_t versal_net_sdei_private[] = {
+	SDEI_DEFINE_EVENT_0(VERSAL_NET_SDEI_SGI_PRIVATE),
+	SDEI_PRIVATE_EVENT(VERSAL_NET_SDEI_PRV_EV, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
+};
+
+/* Shared event mappings */
+static sdei_ev_map_t versal_net_sdei_shared[] = {
+	SDEI_SHARED_EVENT(VERSAL_NET_SDEI_SH_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
+};
+
+void plat_sdei_setup(void)
+{
+	INFO("SDEI platform setup\n");
+}
+
+/* Export ARM SDEI events */
+REGISTER_SDEI_MAP(versal_net_sdei_private, versal_net_sdei_shared);

diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 412238d..822919b 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c

@@ -406,7 +406,7 @@
 	uint32_t ret = 0U;
 
 	if (ver == ZYNQMP_CSU_VERSION_QEMU) {
-		ret = 65000000U;
+		ret = 62500000U;
 	} else {
 		ret = mmio_read_32((uint64_t)IOU_SCNTRS_BASEFREQ);
 	}

diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index b29e1c6..65616e5 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c

@@ -64,6 +64,26 @@
 					  DISABLE_ALL_EXCEPTIONS);
 }
 
+static inline uint64_t read_cntvct_el0(void)
+{
+	uint64_t val;
+
+	asm volatile("mrs %0, cntvct_el0" : "=r" (val));
+	return val;
+}
+
+static inline void reset_cntvct_el0_to_zero(void)
+{
+	asm volatile(
+		"mrs x0, cntpct_el0\n"   /* Read physical counter into x0 */
+		"neg x0, x0\n"           /* Negate it: x0 = -x0 */
+		"msr cntvoff_el2, x0\n"  /* Write offset to virtual counter */
+		:
+		:
+		: "x0", "memory"
+	);
+}
+
 /*
  * Perform any BL31 specific platform actions. Here is an opportunity to copy
  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
@@ -93,6 +113,10 @@
 	/* Initialize the platform config for future decision making */
 	zynqmp_config_setup();
 
+	INFO("Counter TICK 0x%lx\n", read_cntvct_el0());
+	reset_cntvct_el0_to_zero();
+	INFO("Counter TICK after reset 0x%lx\n", read_cntvct_el0());
+
 	/*
 	 * Do initial security configuration to allow DRAM/device access. On
 	 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but

diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 9a9c8d1..bf6ed58 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h

@@ -75,6 +75,12 @@
 #endif
 
 /*******************************************************************************
+ * HIGH and LOW DDR MAX definitions.
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX		U(0x80000000)
+#define PLAT_DDR_HIGHMEM_MAX		U(0x100000000)
+
+/*******************************************************************************
  * TSP  specific defines.
  ******************************************************************************/
 #define TSP_SEC_MEM_BASE		BL32_BASE
@@ -87,7 +93,6 @@
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
 #define XILINX_OF_BOARD_DTB_MAX_SIZE	U(0x200000)
-#define PLAT_DDR_LOWMEM_MAX		U(0x80000000)
 #define PLAT_OCM_BASE			U(0xFFFC0000)
 #define PLAT_OCM_LIMIT			U(0xFFFFFFFF)
 

diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 3fae407..d2faa37 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c

@@ -193,6 +193,18 @@
 	}
 }
 
+static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+	int32_t ret = PSCI_E_SUCCESS;
+
+	if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
+		((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
+		ret = PSCI_E_INVALID_ADDRESS;
+	}
+
+	return ret;
+}
+
 static int32_t zynqmp_validate_power_state(uint32_t power_state,
 				psci_power_state_t *req_state)
 {
@@ -235,6 +247,7 @@
 	.pwr_domain_suspend_finish	= zynqmp_pwr_domain_suspend_finish,
 	.system_off			= zynqmp_system_off,
 	.system_reset			= zynqmp_system_reset,
+	.validate_ns_entrypoint		= zynqmp_validate_ns_entrypoint,
 	.validate_power_state		= zynqmp_validate_power_state,
 	.get_sys_suspend_power_state	= zynqmp_get_sys_suspend_power_state,
 };

diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 5a86658..d2cb220 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk

@@ -101,7 +101,7 @@
 				drivers/cadence/uart/aarch64/cdns_console.S	\
 				plat/arm/common/arm_cci.c			\
 				plat/arm/common/arm_common.c			\
-				plat/arm/common/arm_gicv2.c			\
+				plat/common/plat_gicv2_base.c			\
 				plat/common/plat_gicv2.c			\
 				plat/xilinx/common/ipi.c			\
 				plat/xilinx/zynqmp/zynqmp_ipi.c			\
@@ -162,7 +162,7 @@
 ifdef CUSTOM_PKG_PATH
 include $(CUSTOM_PKG_PATH)/custom_pkg.mk
 else
-BL31_SOURCES		+=	plat/xilinx/zynqmp/custom_sip_svc.c
+BL31_SOURCES		+=	plat/xilinx/common/custom_sip_svc.c
 endif
 
 ifneq (${RESET_TO_BL31},1)

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index 5ffd9ef..849e38a 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -123,7 +123,7 @@
 		.name = "qspi0",
 		.regval = 0x02,
 		.group_base = PINCTRL_GRP_QSPI0_0,
-		.group_size = PINCTRL_GRP_QSPI0_0 - PINCTRL_GRP_QSPI0_0 + 1U,
+		.group_size = PINCTRL_GRP_QSPI0_1 - PINCTRL_GRP_QSPI0_0 + 1U,
 	},
 	[PINCTRL_FUNC_QSPI_FBCLK] = {
 		.name = "qspi_fbclk",
@@ -135,7 +135,7 @@
 		.name = "qspi_ss",
 		.regval = 0x02,
 		.group_base = PINCTRL_GRP_QSPI_SS,
-		.group_size = PINCTRL_GRP_QSPI_SS - PINCTRL_GRP_QSPI_SS + 1U,
+		.group_size = PINCTRL_GRP_QSPI_SS_1 - PINCTRL_GRP_QSPI_SS + 1U,
 	},
 	[PINCTRL_FUNC_SPI0] = {
 		.name = "spi0",
@@ -383,6 +383,7 @@
 	[PINCTRL_PIN_0] = {
 		.groups = &((uint16_t []) {
 			PINCTRL_GRP_QSPI0_0,
+			PINCTRL_GRP_QSPI0_1,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_TESTSCAN0_0,
@@ -401,6 +402,7 @@
 	[PINCTRL_PIN_1] = {
 		.groups = &((uint16_t []) {
 			PINCTRL_GRP_QSPI0_0,
+			PINCTRL_GRP_QSPI0_1,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_TESTSCAN0_0,
@@ -419,6 +421,7 @@
 	[PINCTRL_PIN_2] = {
 		.groups = &((uint16_t []) {
 			PINCTRL_GRP_QSPI0_0,
+			PINCTRL_GRP_QSPI0_1,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_TESTSCAN0_0,
@@ -437,6 +440,7 @@
 	[PINCTRL_PIN_3] = {
 		.groups = &((uint16_t []) {
 			PINCTRL_GRP_QSPI0_0,
+			PINCTRL_GRP_QSPI0_1,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_TESTSCAN0_0,
@@ -455,6 +459,7 @@
 	[PINCTRL_PIN_4] = {
 		.groups = &((uint16_t []) {
 			PINCTRL_GRP_QSPI0_0,
+			PINCTRL_GRP_QSPI0_1,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_TESTSCAN0_0,
@@ -473,6 +478,7 @@
 	[PINCTRL_PIN_5] = {
 		.groups = &((uint16_t []) {
 			PINCTRL_GRP_QSPI_SS,
+			PINCTRL_GRP_QSPI_SS_1,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_RESERVED,
 			PINCTRL_GRP_TESTSCAN0_0,

diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
index 277af4b..cb3b62e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -184,7 +185,9 @@
 	PINCTRL_GRP_MDIO2_0,
 	PINCTRL_GRP_MDIO3_0,
 	PINCTRL_GRP_QSPI0_0,
+	PINCTRL_GRP_QSPI0_1,
 	PINCTRL_GRP_QSPI_SS,
+	PINCTRL_GRP_QSPI_SS_1,
 	PINCTRL_GRP_QSPI_FBCLK,
 	PINCTRL_GRP_SPI0_0,
 	PINCTRL_GRP_SPI0_1,

diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index 1baefb3..6d94422 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c

@@ -105,8 +105,8 @@
 	case ZYNQMP_SIP_SVC_VERSION:
 		SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
 
-	case ZYNQMP_SIP_SVC_CUSTOM:
-	case ZYNQMP_SIP_SVC64_CUSTOM:
+	case SOC_SIP_SVC_CUSTOM:
+	case SOC_SIP_SVC64_CUSTOM:
 		return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
 					  handle, flags);
 

diff --git a/pyproject.toml b/pyproject.toml
index 88c4753..0c39f49 100644
--- a/pyproject.toml
+++ b/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "trusted-firmware-a"
-version = "2.12.0"
+version = "2.13.0"
 description = "Trusted Firmware-A (TF-A) Python dependencies."
 authors = ["Arm Ltd."]
 license = "BSD-3-Clause"

diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 46333af..329f59b 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c

@@ -7,9 +7,6 @@
 #include <common/debug.h>
 #include <common/runtime_svc.h>
 #include <lib/cpus/errata.h>
-#include <lib/cpus/wa_cve_2017_5715.h>
-#include <lib/cpus/wa_cve_2018_3639.h>
-#include <lib/cpus/wa_cve_2022_23960.h>
 #include <lib/smccc.h>
 #include <services/arm_arch_svc.h>
 #include <smccc_helpers.h>
@@ -20,7 +17,7 @@
 
 static int32_t smccc_version(void)
 {
-	return MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION);
+	return (int32_t)MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION);
 }
 
 static int32_t smccc_arch_features(u_register_t arg1)
@@ -35,8 +32,11 @@
 	/* Workaround checks are currently only implemented for aarch64 */
 #if WORKAROUND_CVE_2017_5715
 	case SMCCC_ARCH_WORKAROUND_1:
-		if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
+		if (check_erratum_applies(CVE(2017, 5715))
+			== ERRATA_NOT_APPLIES) {
 			return 1;
+		}
+
 		return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
 #endif
 
@@ -66,8 +66,10 @@
 		 * or permanently mitigated, report the latter as not
 		 * needing dynamic mitigation.
 		 */
-		if (wa_cve_2018_3639_get_disable_ptr() == NULL)
+		if (check_erratum_applies(ERRATUM(ARCH_WORKAROUND_2))
+			== ERRATA_NOT_APPLIES)
 			return 1;
+
 		/*
 		 * If we get here, this CPU requires dynamic mitigation
 		 * so report it as such.
@@ -87,10 +89,13 @@
 		 * CVE-2017-5715 since this SMC can be used instead of
 		 * SMCCC_ARCH_WORKAROUND_1.
 		 */
-		if ((check_smccc_arch_wa3_applies() == ERRATA_NOT_APPLIES) &&
-		    (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)) {
+		if ((check_erratum_applies(ERRATUM(ARCH_WORKAROUND_3))
+			== ERRATA_NOT_APPLIES) &&
+		    (check_erratum_applies(CVE(2017, 5715))
+			== ERRATA_NOT_APPLIES)) {
 			return 1;
 		}
+
 		return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
 #endif
 
@@ -101,7 +106,7 @@
 
 #if WORKAROUND_CVE_2024_7881
 	case SMCCC_ARCH_WORKAROUND_4:
-		if (check_wa_cve_2024_7881() != ERRATA_APPLIES) {
+		if (check_erratum_applies(CVE(2024, 7881)) != ERRATA_APPLIES) {
 			return SMC_ARCH_CALL_NOT_SUPPORTED;
 		}
 		return 0;
@@ -289,7 +294,7 @@
 		arm_arch_svc,
 		OEN_ARM_START,
 		OEN_ARM_END,
-		SMC_TYPE_FAST,
+		(uint8_t)SMC_TYPE_FAST,
 		NULL,
 		arm_arch_svc_smc_handler
 );

diff --git a/services/el3/ven_el3_svc.c b/services/el3/ven_el3_svc.c
index 32a3dc2..431bfbf 100644
--- a/services/el3/ven_el3_svc.c
+++ b/services/el3/ven_el3_svc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,9 @@
 #include <common/runtime_svc.h>
 #include <lib/debugfs.h>
 #include <lib/pmf/pmf.h>
+#if PLAT_ARM_ACS_SMC_HANDLER
+#include <plat/arm/common/plat_acs_smc_handler.h>
+#endif /* PLAT_ARM_ACS_SMC_HANDLER */
 #include <services/ven_el3_svc.h>
 #include <tools_share/uuid.h>
 
@@ -71,6 +74,15 @@
 
 #endif /* ENABLE_PMF */
 
+#if PLAT_ARM_ACS_SMC_HANDLER
+	/*
+	 * Dispatch ACS calls to ACS SMC handler and return its return value
+	 */
+	if (is_acs_fid(smc_fid)) {
+		return plat_arm_acs_smc_handler(smc_fid, x1, x2, x3, x4, handle);
+	}
+#endif /* PLAT_ARM_ACS_SMC_HANDLER */
+
 	switch (smc_fid) {
 	case VEN_EL3_SVC_UID:
 		/* Return UID to the caller */

diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index 8910ec6..5e232f9 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,9 @@
 #include <lib/coreboot.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/optee_utils.h>
+#if TRANSFER_LIST
 #include <lib/transfer_list.h>
+#endif
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #if OPTEE_ALLOW_SMC_LOAD
 #include <libfdt.h>
@@ -40,7 +42,7 @@
 #include "teesmc_opteed.h"
 
 #if OPTEE_ALLOW_SMC_LOAD
-static struct transfer_list_header *bl31_tl;
+static struct transfer_list_header __maybe_unused *bl31_tl;
 #endif
 
 /*******************************************************************************
@@ -163,9 +165,9 @@
 	uint64_t arg1;
 	uint64_t arg2;
 	uint64_t arg3;
-	struct transfer_list_header *tl = NULL;
-	struct transfer_list_entry *te = NULL;
-	void *dt = NULL;
+	struct transfer_list_header __maybe_unused *tl = NULL;
+	struct transfer_list_entry __maybe_unused *te = NULL;
+	void __maybe_unused *dt = NULL;
 
 	linear_id = plat_my_core_pos();
 
@@ -190,8 +192,10 @@
 	if (!optee_ep_info->pc)
 		return 1;
 
+#if TRANSFER_LIST
 	tl = (void *)optee_ep_info->args.arg3;
-	if (TRANSFER_LIST && transfer_list_check_header(tl)) {
+
+	if (transfer_list_check_header(tl)) {
 		te = transfer_list_find(tl, TL_TAG_FDT);
 		dt = transfer_list_entry_data(te);
 
@@ -199,7 +203,7 @@
 		if (opteed_rw == OPTEE_AARCH64) {
 			if (optee_ep_info->args.arg1 !=
 			    TRANSFER_LIST_HANDOFF_X1_VALUE(
-				REGISTER_CONVENTION_VERSION))
+				    REGISTER_CONVENTION_VERSION))
 				return 1;
 
 			arg0 = (uint64_t)dt;
@@ -207,7 +211,7 @@
 		} else {
 			if (optee_ep_info->args.arg1 !=
 			    TRANSFER_LIST_HANDOFF_R1_VALUE(
-				REGISTER_CONVENTION_VERSION))
+				    REGISTER_CONVENTION_VERSION))
 				return 1;
 
 			arg0 = 0;
@@ -216,7 +220,10 @@
 
 		arg1 = optee_ep_info->args.arg1;
 		arg3 = optee_ep_info->args.arg3;
-	} else {
+
+	} else
+#endif /* TRANSFER_LIST */
+	{
 		/* Default handoff arguments */
 		opteed_rw = optee_ep_info->args.arg0;
 		arg0 = optee_ep_info->args.arg1; /* opteed_pageable_part */
@@ -225,9 +232,9 @@
 		arg3 = 0;
 	}
 
-	opteed_init_optee_ep_state(optee_ep_info, opteed_rw, optee_ep_info->pc,
-				arg0, arg1, arg2, arg3,
-				&opteed_sp_context[linear_id]);
+	opteed_init_optee_ep_state(optee_ep_info, opteed_rw,
+				   optee_ep_info->pc, arg0, arg1, arg2,
+				   arg3, &opteed_sp_context[linear_id]);
 
 	/*
 	 * All OPTEED initialization done. Now register our init function with
@@ -430,9 +437,9 @@
 	return fdt_finish(fdt_buf);
 }
 
+#if TRANSFER_LIST
 static int32_t create_smc_tl(const void *fdt, uint32_t fdt_sz)
 {
-#if TRANSFER_LIST
 	bl31_tl = transfer_list_init((void *)(uintptr_t)FW_HANDOFF_BASE,
 				FW_HANDOFF_SIZE);
 	if (!bl31_tl) {
@@ -445,10 +452,8 @@
 		return -1;
 	}
 	return 0;
-#else
-	return -1;
-#endif
 }
+#endif
 
 /*******************************************************************************
  * This function is responsible for handling the SMC that loads the OP-TEE
@@ -546,8 +551,8 @@
 	dt_addr = (uint64_t)fdt_buf;
 	flush_dcache_range(dt_addr, OPTEED_FDT_SIZE);
 
-	if (TRANSFER_LIST &&
-	    !create_smc_tl((void *)dt_addr, OPTEED_FDT_SIZE)) {
+#if TRANSFER_LIST
+	if (!create_smc_tl((void *)dt_addr, OPTEED_FDT_SIZE)) {
 		struct transfer_list_entry *te = NULL;
 		void *dt = NULL;
 
@@ -565,7 +570,9 @@
 		}
 
 		arg3 = (uint64_t)bl31_tl;
-	} else {
+	} else
+#endif /* TRANSFER_LIST */
+	{
 		/* Default handoff arguments */
 		arg2 = dt_addr;
 	}

diff --git a/services/spd/tlkd/tlkd.mk b/services/spd/tlkd/tlkd.mk
index fc8840d..6d71632 100644
--- a/services/spd/tlkd/tlkd.mk
+++ b/services/spd/tlkd/tlkd.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2024-2025, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -8,9 +8,11 @@
 SPD_INCLUDES		:=	-Iinclude/bl32/payloads
 endif
 
-ifeq (${ENABLE_FEAT_D128}, 0)
+ifneq (${ENABLE_FEAT_D128}, 0)
+        $(error spd=tlkd will not work with ENABLE_FEAT_D128 enabled.)
+endif
+
 SPD_SOURCES		:=	services/spd/tlkd/tlkd_common.c		\
 				services/spd/tlkd/tlkd_helpers.S	\
 				services/spd/tlkd/tlkd_main.c		\
 				services/spd/tlkd/tlkd_pm.c
-endif
\ No newline at end of file

diff --git a/services/std_svc/drtm/drtm_dma_prot.h b/services/std_svc/drtm/drtm_dma_prot.h
index 79dc9cb..5ccff87 100644
--- a/services/std_svc/drtm/drtm_dma_prot.h
+++ b/services/std_svc/drtm/drtm_dma_prot.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier:    BSD-3-Clause
  *
@@ -20,7 +20,7 @@
 enum dma_prot_type {
 	PROTECT_NONE    = -1,
 	PROTECT_MEM_ALL = 0,
-	PROTECT_MEM_REGION = 2,
+	PROTECT_MEM_REGION = 1,
 };
 
 struct dma_prot {

diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c
index c302863..b7a03f3 100644
--- a/services/std_svc/drtm/drtm_main.c
+++ b/services/std_svc/drtm/drtm_main.c

@@ -293,8 +293,8 @@
 	/* Prepare DRTM event log for DLME. */
 	drtm_serialise_event_log(dlme_data_cursor, &serialised_bytes_actual);
 	assert(serialised_bytes_actual <= ARM_DRTM_MIN_EVENT_LOG_SIZE);
-	dlme_data_hdr->dlme_tpm_log_size = ARM_DRTM_MIN_EVENT_LOG_SIZE;
-	dlme_data_cursor +=  dlme_data_hdr->dlme_tpm_log_size;
+	dlme_data_hdr->dlme_tpm_log_size = serialised_bytes_actual;
+	dlme_data_cursor +=  serialised_bytes_actual;
 
 	/*
 	 * TODO: Prepare the TCB hashes for DLME, currently its size
@@ -329,10 +329,8 @@
 	 * Ensure that if DLME Authorities Schema (Bits [2:1]) is set, then
 	 * DLME image authentication (Bit[6]) must also be set
 	 */
-	if ((EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_MASK,
-			   DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_SHIFT) == DLME_AUTH_SCHEMA) &&
-	    (EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_MASK,
-			    DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_SHIFT) != DLME_IMG_AUTH)) {
+	if ((EXTRACT(DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA, val) == DLME_AUTH_SCHEMA) &&
+	    (EXTRACT(DRTM_LAUNCH_FEAT_DLME_IMG_AUTH, val) != DLME_IMG_AUTH)) {
 		return INVALID_PARAMETERS;
 	}
 
@@ -340,8 +338,7 @@
 	 * Check if Bits [5:3] (Memory protection type) matches with platform's
 	 * memory protection type
 	 */
-	if (EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_MASK,
-			  DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_SHIFT) !=
+	if (EXTRACT(DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE, val) !=
 	    __builtin_ctz(plat_dma_prot_feat->dma_protection_support)) {
 		return INVALID_PARAMETERS;
 	}
@@ -350,8 +347,7 @@
 	 * Check if Bits [0] (Type of hashing) matches with platform's
 	 * supported hash type.
 	 */
-	if (EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_HASHING_TYPE_MASK,
-			  DRTM_LAUNCH_FEAT_HASHING_TYPE_SHIFT) !=
+	if (EXTRACT(DRTM_LAUNCH_FEAT_HASHING_TYPE, val) !=
 	    plat_tpm_feat->tpm_based_hash_support) {
 		return INVALID_PARAMETERS;
 	}

diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index d4f2b57..4518d37 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c

@@ -56,7 +56,10 @@
 	}
 
 	/* Record the mesasurement in the EventLog buffer */
-	event_log_record(hash_data, event_type, &metadata);
+	rc = event_log_record(hash_data, event_type, &metadata);
+	if (rc != 0) {
+		return rc;
+	}
 
 	return 0;
 }
@@ -135,7 +138,8 @@
 	/* PCR-17: End of DCE measurements. */
 	rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
 					       strlen(drtm_event_arm_sep_data),
-					       DRTM_EVENT_ARM_SEPARATOR, NULL,
+					       DRTM_EVENT_ARM_SEPARATOR,
+					       drtm_event_arm_sep_data,
 					       PCR_17);
 	CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
 
@@ -185,7 +189,7 @@
 
 	/* PCR-18: Measure the DLME image entry point. */
 	dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a);
-	drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep,
+	drtm_event_log_measure_and_record((uintptr_t)&(a->dlme_img_ep_off),
 					  sizeof(dlme_img_ep),
 					  DRTM_EVENT_ARM_DLME_EP, NULL,
 					  PCR_18);
@@ -194,7 +198,8 @@
 	/* PCR-18: End of DCE measurements. */
 	rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
 					       strlen(drtm_event_arm_sep_data),
-					       DRTM_EVENT_ARM_SEPARATOR, NULL,
+					       DRTM_EVENT_ARM_SEPARATOR,
+					       drtm_event_arm_sep_data,
 					       PCR_18);
 	CHECK_RC(rc,
 		 drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));

diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index d688431..d685eef 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -48,5 +48,5 @@
 	struct   em_cpu cpu_errata_list[MAX_PLAT_CPU_ERRATA_ENTRIES];
 };
 
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag);
+int32_t verify_errata_implemented(uint32_t errata_id);
 #endif /* ERRATA_CPUSPEC_H */

diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index a945637..74a1586 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -166,50 +166,33 @@
 #endif
 
 /* Function to check if the errata exists for the specific CPU and rxpx */
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag)
+int32_t verify_errata_implemented(uint32_t errata_id)
 {
-	int32_t ret_val;
-	struct cpu_ops *cpu_ops;
-	struct erratum_entry *entry, *end;
+	struct erratum_entry *entry;
 	long rev_var;
 
-	ret_val = EM_UNKNOWN_ERRATUM;
 	rev_var = cpu_get_rev_var();
 
 #if ERRATA_NON_ARM_INTERCONNECT
-	ret_val = non_arm_interconnect_errata(errata_id, rev_var);
+	int32_t ret_val = non_arm_interconnect_errata(errata_id, rev_var);
 	if (ret_val != EM_UNKNOWN_ERRATUM) {
 		return ret_val;
 	}
 #endif
+	entry = find_erratum_entry(errata_id);
+	if (entry == NULL)
+		return EM_UNKNOWN_ERRATUM;
 
-	cpu_ops = get_cpu_ops_ptr();
-	assert(cpu_ops != NULL);
-
-	entry = cpu_ops->errata_list_start;
-	assert(entry != NULL);
-
-	end = cpu_ops->errata_list_end;
-	assert(end != NULL);
-
-	end--; /* point to the last erratum entry of the queried cpu */
-
-	while ((entry <= end) && (ret_val == EM_UNKNOWN_ERRATUM)) {
-		if (entry->id == errata_id) {
-			if (entry->check_func(rev_var)) {
-				if (entry->chosen & WA_ENABLED_MASK)
-					if (entry->chosen & SPLIT_WA_MASK)
-						return EM_AFFECTED;
-					else
-						return EM_HIGHER_EL_MITIGATION;
-				else
-					return EM_AFFECTED;
-			}
-			return EM_NOT_AFFECTED;
-		}
-		entry += 1;
+	if (entry->check_func(rev_var)) {
+		if (entry->chosen & WA_ENABLED_MASK)
+			if (entry->chosen & SPLIT_WA_MASK)
+				return EM_AFFECTED;
+			else
+				return EM_HIGHER_EL_MITIGATION;
+		else
+			return EM_AFFECTED;
 	}
-	return ret_val;
+	return EM_NOT_AFFECTED;
 }
 
 /* Predicate indicating that a function id is part of EM_ABI */
@@ -271,7 +254,7 @@
 		if (((uint32_t)x2 != 0) && (validate_spsr_mode())) {
 			SMC_RET1(handle, EM_INVALID_PARAMETERS);
 		}
-		ret_id = verify_errata_implemented((uint32_t)x1, (uint32_t)x2);
+		ret_id = verify_errata_implemented((uint32_t)x1);
 		SMC_RET1(handle, ret_id);
 		break; /* unreachable */
 	default:

diff --git a/services/std_svc/lfa/bl31_lfa.c b/services/std_svc/lfa/bl31_lfa.c
new file mode 100644
index 0000000..6f66826
--- /dev/null
+++ b/services/std_svc/lfa/bl31_lfa.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <services/bl31_lfa.h>
+#include <services/lfa_svc.h>
+
+static int32_t lfa_bl31_prime(struct lfa_component_status *activation)
+{
+	return LFA_WRONG_STATE;
+}
+
+static int32_t lfa_bl31_activate(struct lfa_component_status *activation,
+		uint64_t ep_address,
+		uint64_t context_id)
+{
+	return LFA_WRONG_STATE;
+}
+
+static struct lfa_component_ops bl31_activator = {
+	.prime = lfa_bl31_prime,
+	.activate = lfa_bl31_activate,
+	.may_reset_cpu = false,
+	.cpu_rendezvous_required = true,
+};
+
+struct lfa_component_ops *get_bl31_activator(void)
+{
+	return &bl31_activator;
+}

diff --git a/services/std_svc/lfa/lfa.mk b/services/std_svc/lfa/lfa.mk
new file mode 100644
index 0000000..056b537
--- /dev/null
+++ b/services/std_svc/lfa/lfa.mk

@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LFA_SOURCES	+=	$(addprefix services/std_svc/lfa/, \
+			  lfa_main.c \
+			  bl31_lfa.c \
+			  lfa_holding_pen.c)
+
+ifeq (${ENABLE_RME}, 1)
+LFA_SOURCES	+=	services/std_svc/rmmd/rmmd_rmm_lfa.c
+endif

diff --git a/services/std_svc/lfa/lfa_holding_pen.c b/services/std_svc/lfa/lfa_holding_pen.c
new file mode 100644
index 0000000..8ee260c
--- /dev/null
+++ b/services/std_svc/lfa/lfa_holding_pen.c

@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/psci/psci_lib.h>
+#include <lib/spinlock.h>
+#include <lib/utils_def.h>
+#include <plat/common/platform.h>
+#include <services/lfa_holding_pen.h>
+
+#include <platform_def.h>
+
+static spinlock_t holding_lock;
+static spinlock_t activation_lock;
+static uint32_t activation_count;
+static enum lfa_retc activation_status;
+
+/**
+ * lfa_holding_start - Called by each active CPU to coordinate live activation.
+ *
+ * Note that only CPUs that are active at the time of activation will
+ * participate in CPU rendezvous.
+ *
+ * This function is invoked by each CPU participating in the LFA Activate
+ * process. It increments the shared activation count under `activation_lock`
+ * to track how many CPUs have entered the activation phase.
+ *
+ * The first CPU to enter acquires the `holding_lock`, which ensures
+ * serialization during the wait and activation phases. This lock is
+ * released only after the last CPU completes the activation.
+ *
+ * The function returns `true` only for the last CPU to enter, allowing it
+ * to proceed with performing the live firmware activation. All other CPUs
+ * receive `false` and will wait in `lfa_holding_wait()` until activation
+ * is complete.
+ *
+ * @return `true` for the last CPU, `false` for all others.
+ */
+bool lfa_holding_start(void)
+{
+	bool status;
+	unsigned int no_of_cpus;
+
+	spin_lock(&activation_lock);
+
+	if (activation_count == 0U) {
+		/* First CPU locks holding lock */
+		spin_lock(&holding_lock);
+	}
+
+	activation_count += 1U;
+
+	no_of_cpus = psci_num_cpus_running_on_safe(plat_my_core_pos());
+	status = (activation_count == no_of_cpus);
+	if (!status) {
+		VERBOSE("Hold, %d CPU left\n",
+			 PLATFORM_CORE_COUNT - activation_count);
+	}
+
+	spin_unlock(&activation_lock);
+
+	return status;
+}
+
+/**
+ * lfa_holding_wait - CPUs wait until activation is completed by the last CPU.
+ *
+ * All CPUs are serialized using `holding_lock`, which is initially acquired
+ * by the first CPU in `lfa_holding_start()` and only released by the last
+ * CPU through `lfa_holding_release()`. This ensures that no two CPUs enter
+ * the critical section at the same time during the wait phase. Once the
+ * last CPU completes activation, each CPU decrements the activation count
+ * and returns the final activation status,  which was set by the last CPU
+ * to complete the activation process.
+ *
+ * @return Activation status set by the last CPU.
+ */
+enum lfa_retc lfa_holding_wait(void)
+{
+	spin_lock(&holding_lock);
+	activation_count -= 1U;
+	spin_unlock(&holding_lock);
+	return activation_status;
+}
+
+/**
+ * lfa_holding_release - Called by the last CPU to complete activation.
+ *
+ * This function is used by the last participating CPU after it completes
+ * live firmware activation. It updates the shared activation status and
+ * resets the activation count. Finally, it releases the `holding_lock` to
+ * allow other CPUs that were waiting in `lfa_holding_wait()` to proceed.
+ *
+ * @param status Activation status to be shared with other CPUs.
+ */
+void lfa_holding_release(enum lfa_retc status)
+{
+	activation_count = 0U;
+	activation_status = status;
+	spin_unlock(&holding_lock);
+}

diff --git a/services/std_svc/lfa/lfa_main.c b/services/std_svc/lfa/lfa_main.c
new file mode 100644
index 0000000..1cf65ae
--- /dev/null
+++ b/services/std_svc/lfa/lfa_main.c

@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <plat/common/platform.h>
+#include <services/bl31_lfa.h>
+#include <services/lfa_svc.h>
+#include <services/rmmd_rmm_lfa.h>
+#include <smccc_helpers.h>
+
+static uint32_t lfa_component_count;
+static plat_lfa_component_info_t *lfa_components;
+static struct lfa_component_status current_activation;
+static bool is_lfa_initialized;
+
+void lfa_reset_activation(void)
+{
+	current_activation.component_id = LFA_INVALID_COMPONENT;
+	current_activation.prime_status = PRIME_NONE;
+	current_activation.cpu_rendezvous_required = false;
+}
+
+static int convert_to_lfa_error(int ret)
+{
+	switch (ret) {
+	case 0:
+		return LFA_SUCCESS;
+	case -EAUTH:
+		return LFA_AUTH_ERROR;
+	case -ENOMEM:
+		return LFA_NO_MEMORY;
+	default:
+		return LFA_DEVICE_ERROR;
+	}
+}
+
+static bool lfa_initialize_components(void)
+{
+	lfa_component_count = plat_lfa_get_components(&lfa_components);
+
+	if (lfa_component_count == 0U || lfa_components == NULL) {
+		/* unlikely to reach here */
+		ERROR("Invalid LFA component setup: count = 0 or components are NULL");
+		return false;
+	}
+
+	return true;
+}
+
+static uint64_t get_fw_activation_flags(uint32_t fw_seq_id)
+{
+	const plat_lfa_component_info_t *comp =
+				&lfa_components[fw_seq_id];
+	uint64_t flags = 0ULL;
+
+	flags |= ((comp->activator == NULL ? 0ULL : 1ULL)
+		 << LFA_ACTIVATION_CAPABLE_SHIFT);
+	flags |= (uint64_t)(comp->activation_pending)
+		 << LFA_ACTIVATION_PENDING_SHIFT;
+
+	if (comp->activator != NULL) {
+		flags |= ((comp->activator->may_reset_cpu ? 1ULL : 0ULL)
+			 << LFA_MAY_RESET_CPU_SHIFT);
+		flags |= ((comp->activator->cpu_rendezvous_required ? 0ULL : 1ULL)
+			 << LFA_CPU_RENDEZVOUS_OPTIONAL_SHIFT);
+	}
+
+	return flags;
+}
+
+static int lfa_cancel(uint32_t component_id)
+{
+	int ret = LFA_SUCCESS;
+
+	if (lfa_component_count == 0U) {
+		return LFA_WRONG_STATE;
+	}
+
+	/* Check if component ID is in range. */
+	if ((component_id >= lfa_component_count) ||
+	    (component_id != current_activation.component_id)) {
+		return LFA_INVALID_PARAMETERS;
+	}
+
+	ret = plat_lfa_cancel(component_id);
+	if (ret != LFA_SUCCESS) {
+		return LFA_BUSY;
+	}
+
+	/* TODO: add proper termination prime and activate phases */
+	lfa_reset_activation();
+
+	return ret;
+}
+
+static int lfa_activate(uint32_t component_id, uint64_t flags,
+			uint64_t ep_address, uint64_t context_id)
+{
+	int ret = LFA_ACTIVATION_FAILED;
+	struct lfa_component_ops *activator;
+
+	if ((lfa_component_count == 0U) ||
+	    (!lfa_components[component_id].activation_pending) ||
+	    (current_activation.prime_status != PRIME_COMPLETE)) {
+		return LFA_COMPONENT_WRONG_STATE;
+	}
+
+	/* Check if fw_seq_id is in range. */
+	if ((component_id >= lfa_component_count) ||
+	    (current_activation.component_id != component_id)) {
+		return LFA_INVALID_PARAMETERS;
+	}
+
+	if (lfa_components[component_id].activator == NULL) {
+		return LFA_NOT_SUPPORTED;
+	}
+
+	activator = lfa_components[component_id].activator;
+	if (activator->activate != NULL) {
+		/*
+		 * Pass skip_cpu_rendezvous (flag[0]) only if flag[0]==1
+		 * & CPU_RENDEZVOUS is not required.
+		 */
+		if (flags & LFA_SKIP_CPU_RENDEZVOUS_BIT) {
+			if (!activator->cpu_rendezvous_required) {
+				INFO("Skipping rendezvous requested by caller.\n");
+				current_activation.cpu_rendezvous_required = false;
+			}
+			/*
+			 * Return error if caller tries to skip rendezvous when
+			 * it is required.
+			 */
+			else {
+				ERROR("CPU Rendezvous is required, can't skip.\n");
+				return LFA_INVALID_PARAMETERS;
+			}
+		}
+
+		ret = activator->activate(&current_activation, ep_address,
+					  context_id);
+	}
+
+	lfa_components[component_id].activation_pending = false;
+
+	return ret;
+}
+
+static int lfa_prime(uint32_t component_id, uint64_t *flags)
+{
+	int ret = LFA_SUCCESS;
+	struct lfa_component_ops *activator;
+
+	if (lfa_component_count == 0U ||
+	    !lfa_components[component_id].activation_pending) {
+		return LFA_WRONG_STATE;
+	}
+
+	/* Check if fw_seq_id is in range. */
+	if (component_id >= lfa_component_count) {
+		return LFA_INVALID_PARAMETERS;
+	}
+
+	if (lfa_components[component_id].activator == NULL) {
+		return LFA_NOT_SUPPORTED;
+	}
+
+	switch (current_activation.prime_status) {
+	case PRIME_NONE:
+		current_activation.component_id = component_id;
+		current_activation.prime_status = PRIME_STARTED;
+		break;
+
+	case PRIME_STARTED:
+		if (current_activation.component_id != component_id) {
+			/* Mismatched component trying to continue PRIME - error */
+			return LFA_WRONG_STATE;
+		}
+		break;
+
+	case PRIME_COMPLETE:
+	default:
+		break;
+	}
+
+	ret = plat_lfa_load_auth_image(component_id);
+	ret = convert_to_lfa_error(ret);
+
+	activator = lfa_components[component_id].activator;
+	if (activator->prime != NULL) {
+		ret = activator->prime(&current_activation);
+		if (ret != LFA_SUCCESS) {
+			/*
+			 * TODO: it should be LFA_PRIME_FAILED but specification
+			 * has not define this error yet
+			 */
+			return ret;
+		}
+	}
+
+	current_activation.prime_status = PRIME_COMPLETE;
+
+	/* TODO: split this into multiple PRIME calls */
+	*flags = 0ULL;
+
+	return ret;
+}
+
+int lfa_setup(void)
+{
+	is_lfa_initialized = lfa_initialize_components();
+	if (!is_lfa_initialized) {
+		return -1;
+	}
+
+	lfa_reset_activation();
+
+	return 0;
+}
+
+uint64_t lfa_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+			 u_register_t x3, u_register_t x4, void *cookie,
+			 void *handle, u_register_t flags)
+{
+	uint64_t retx1, retx2;
+	uint64_t lfa_flags;
+	uint8_t *uuid_p;
+	uint32_t fw_seq_id = (uint32_t)x1;
+	int ret;
+
+	/**
+	 * TODO: Acquire serialization lock.
+	 */
+
+	if (!is_lfa_initialized) {
+		return LFA_NOT_SUPPORTED;
+	}
+
+	switch (smc_fid) {
+	case LFA_VERSION:
+		SMC_RET1(handle, LFA_VERSION_VAL);
+		break;
+
+	case LFA_FEATURES:
+		SMC_RET1(handle, is_lfa_fid(x1) ? LFA_SUCCESS : LFA_NOT_SUPPORTED);
+		break;
+
+	case LFA_GET_INFO:
+		/**
+		 * The current specification limits this input parameter to be zero for
+		 * version 1.0 of LFA
+		 */
+		if (x1 == 0ULL) {
+			SMC_RET3(handle, LFA_SUCCESS, lfa_component_count, 0);
+		} else {
+			SMC_RET1(handle, LFA_INVALID_PARAMETERS);
+		}
+		break;
+
+	case LFA_GET_INVENTORY:
+		if (lfa_component_count == 0U) {
+			SMC_RET1(handle, LFA_WRONG_STATE);
+		}
+
+		/*
+		 * Check if fw_seq_id is in range. LFA_GET_INFO must be called first to scan
+		 * platform firmware and create a valid number of firmware components.
+		 */
+		if (fw_seq_id >= lfa_component_count) {
+			SMC_RET1(handle, LFA_INVALID_PARAMETERS);
+		}
+
+		/*
+		 * grab the UUID of asked fw_seq_id and set the return UUID
+		 * variables
+		 */
+		uuid_p = (uint8_t *)&lfa_components[fw_seq_id].uuid;
+		memcpy(&retx1, uuid_p, sizeof(uint64_t));
+		memcpy(&retx2, uuid_p + sizeof(uint64_t), sizeof(uint64_t));
+
+		/*
+		 * check the given fw_seq_id's update available
+		 * and accordingly set the active_pending flag
+		 */
+		lfa_components[fw_seq_id].activation_pending =
+				is_plat_lfa_activation_pending(fw_seq_id);
+
+		INFO("Component %lu %s live activation:\n", x1,
+		      lfa_components[fw_seq_id].activator ? "supports" :
+		      "does not support");
+
+		if (lfa_components[fw_seq_id].activator != NULL) {
+			INFO("Activation pending: %s\n",
+			      lfa_components[fw_seq_id].activation_pending ? "true" : "false");
+		}
+
+		INFO("x1 = 0x%016lx, x2 = 0x%016lx\n", retx1, retx2);
+
+		SMC_RET4(handle, LFA_SUCCESS, retx1, retx2, get_fw_activation_flags(fw_seq_id));
+
+		break;
+
+	case LFA_PRIME:
+		ret = lfa_prime(x1, &lfa_flags);
+		if (ret != LFA_SUCCESS) {
+			SMC_RET1(handle, ret);
+		} else {
+			SMC_RET2(handle, ret, lfa_flags);
+		}
+		break;
+
+	case LFA_ACTIVATE:
+		ret = lfa_activate(fw_seq_id, x2, x3, x4);
+		/* TODO: implement activate again */
+		SMC_RET2(handle, ret, 0ULL);
+
+		break;
+
+	case LFA_CANCEL:
+		ret = lfa_cancel(x1);
+		SMC_RET1(handle, ret);
+		break;
+
+	default:
+		WARN("Unimplemented LFA Service Call: 0x%x\n", smc_fid);
+		SMC_RET1(handle, SMC_UNK);
+		break; /* unreachable */
+
+	}
+
+	SMC_RET1(handle, SMC_UNK);
+
+	return 0;
+}

diff --git a/services/std_svc/rmmd/rmmd.mk b/services/std_svc/rmmd/rmmd.mk
index eae5031..67955ff 100644
--- a/services/std_svc/rmmd/rmmd.mk
+++ b/services/std_svc/rmmd/rmmd.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2025, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -16,7 +16,8 @@
 RMMD_SOURCES	+=	$(addprefix services/std_svc/rmmd/,	\
 			${ARCH}/rmmd_helpers.S			\
 			rmmd_main.c				\
-			rmmd_attest.c)
+			rmmd_attest.c				\
+			rmmd_keymgmt.c)
 
 # Let the top-level Makefile know that we intend to include RMM image
 NEED_RMM	:=	yes

diff --git a/services/std_svc/rmmd/rmmd_keymgmt.c b/services/std_svc/rmmd/rmmd_keymgmt.c
new file mode 100644
index 0000000..2414b35
--- /dev/null
+++ b/services/std_svc/rmmd/rmmd_keymgmt.c

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include "rmmd_private.h"
+#include <common/debug.h>
+#include <lib/spinlock.h>
+#include <plat/common/platform.h>
+#include <services/rmmd_svc.h>
+#include <smccc_helpers.h>
+
+#define DIR_BIT_SHIFT		0xB
+#define KEYSET_BIT_SHIFT	0xC
+#define STREAM_ID_MASK		0xFF
+#define SUBSTREAM_MASK		0x7
+#define SUBSTREAM_SHIFT		0x8
+#define MAX_STREAM_ID		32U
+#define MAX_SUBSTREAM		3U
+
+bool extract_ide_stream_info(uint64_t ide_stream_info)
+{
+	uint8_t keyset, dir;
+	uint8_t stream_id, substream;
+
+	/* Extract keyset, dir, substream and stream ID */
+	keyset = (ide_stream_info >> KEYSET_BIT_SHIFT) & 0x1;
+	dir = (ide_stream_info >> DIR_BIT_SHIFT) & 0x1;
+	stream_id = ide_stream_info & STREAM_ID_MASK;
+	substream = (ide_stream_info >> SUBSTREAM_SHIFT) & SUBSTREAM_MASK;
+
+	if ((stream_id >= MAX_STREAM_ID) || (substream >= MAX_SUBSTREAM)) {
+		ERROR("invalid input: stream_id = %x, substream = %x\n", stream_id, substream);
+		return false;
+	}
+
+	VERBOSE("keyset = %d, dir = %d, stream_id = %d and substream = %d\n", keyset, dir,
+		 stream_id, substream);
+
+	return true;
+}
+
+int rmmd_el3_ide_key_program(uint64_t ecam_address, uint64_t rp_id,
+			     uint64_t ide_stream_info, rp_ide_key_info_t *ide_key_info_ptr,
+			     uint64_t request_id, uint64_t cookie)
+{
+	int err;
+
+	/* TODO: Do validation of params */
+
+	VERBOSE("IDE_KEY_PROG: ecam address = 0x%lx and rp_id = 0x%lx\n", ecam_address, rp_id);
+
+	if (!extract_ide_stream_info(ide_stream_info)) {
+		err = E_RMM_INVAL;
+		goto exit_fn;
+	}
+
+	err = plat_rmmd_el3_ide_key_program(ecam_address, rp_id, ide_stream_info,
+					    ide_key_info_ptr, request_id, cookie);
+
+	assert(err == E_RMM_OK || err == E_RMM_AGAIN || err == E_RMM_INVAL ||
+		err == E_RMM_IN_PROGRESS || err == E_RMM_UNK || err == E_RMM_FAULT);
+
+exit_fn:
+	return err;
+}
+
+int rmmd_el3_ide_key_set_go(uint64_t ecam_address, uint64_t rp_id,
+			    uint64_t ide_stream_info, uint64_t request_id,
+			    uint64_t cookie)
+{
+	int err;
+
+	/* TODO: Do validation of params */
+
+	VERBOSE("IDE_KEY_SET_GO: ecam address = 0x%lx and rp_id = 0x%lx\n", ecam_address, rp_id);
+
+	if (!extract_ide_stream_info(ide_stream_info)) {
+		err = E_RMM_INVAL;
+		goto exit_fn;
+	}
+
+	err = plat_rmmd_el3_ide_key_set_go(ecam_address, rp_id, ide_stream_info,
+					   request_id, cookie);
+
+	assert(err == E_RMM_OK || err == E_RMM_AGAIN || err == E_RMM_INVAL ||
+		err == E_RMM_IN_PROGRESS || err == E_RMM_UNK || err == E_RMM_FAULT);
+
+exit_fn:
+	return err;
+}
+
+int rmmd_el3_ide_key_set_stop(uint64_t ecam_address, uint64_t rp_id,
+			      uint64_t ide_stream_info, uint64_t request_id,
+			      uint64_t cookie)
+{
+	int err;
+
+	/* TODO: Do validation of params */
+
+	VERBOSE("IDE_KEY_SET_STOP: ecam address = 0x%lx and rp_id = 0x%lx\n", ecam_address, rp_id);
+
+	if (!extract_ide_stream_info(ide_stream_info)) {
+		err = E_RMM_INVAL;
+		goto exit_fn;
+	}
+
+	err = plat_rmmd_el3_ide_key_set_stop(ecam_address, rp_id, ide_stream_info,
+					     request_id, cookie);
+
+	assert(err == E_RMM_OK || err == E_RMM_AGAIN || err == E_RMM_INVAL ||
+		err == E_RMM_IN_PROGRESS || err == E_RMM_UNK || err == E_RMM_FAULT);
+
+exit_fn:
+	return err;
+}
+
+int rmmd_el3_ide_km_pull_response(uint64_t ecam_address, uint64_t rp_id,
+				  uint64_t *req_resp, uint64_t *request_id,
+				  uint64_t *cookie)
+{
+	int err;
+
+	/* TODO: Do validation of params */
+
+	VERBOSE("IDE_KM_PULL: ecam address = 0x%lx, rp_id = 0x%lx\n", ecam_address, rp_id);
+
+	err = plat_rmmd_el3_ide_km_pull_response(ecam_address, rp_id, req_resp, request_id, cookie);
+
+	assert(err == E_RMM_OK || err == E_RMM_AGAIN || err == E_RMM_INVAL ||
+		err == E_RMM_IN_PROGRESS || err == E_RMM_UNK || err == E_RMM_FAULT);
+
+	return err;
+}

diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index e94b048..35582dc 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c

@@ -19,6 +19,7 @@
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/el3_runtime/cpu_data.h>
 #include <lib/el3_runtime/pubsub.h>
+#include <lib/extensions/mpam.h>
 #include <lib/extensions/pmuv3.h>
 #include <lib/extensions/sys_reg_trace.h>
 #include <lib/gpt_rme/gpt_rme.h>
@@ -169,6 +170,16 @@
 	if (is_feat_sme_supported()) {
 		sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
 	}
+
+	/*
+	 * If FEAT_MPAM is supported and enabled, then disable trapping access
+	 * to the MPAM registers for Realm world. Instead, RMM will configure
+	 * the access to be trapped by itself so it can inject undefined aborts
+	 * back to the Realm.
+	 */
+	if (is_feat_mpam_supported()) {
+		mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
+	}
 }
 
 /*******************************************************************************
@@ -479,6 +490,14 @@
 	int ret;
 
 	/*
+	 * Check whether FEAT_MEC is supported by the hardware. If not, return
+	 * unknown SMC.
+	 */
+	if (is_feat_mec_supported() == false) {
+		return E_RMM_UNK;
+	}
+
+	/*
 	 * Check whether the mecid parameter is at most MECIDR_EL2.MECIDWidthm1 + 1
 	 * in length.
 	 */
@@ -542,6 +561,37 @@
 	case RMM_EL3_TOKEN_SIGN:
 		return rmmd_el3_token_sign(handle, x1, x2, x3, x4);
 #endif
+
+#if RMMD_ENABLE_IDE_KEY_PROG
+	case RMM_IDE_KEY_PROG:
+	{
+		rp_ide_key_info_t ide_key_info;
+
+		ide_key_info.keyqw0 = x4;
+		ide_key_info.keyqw1 = SMC_GET_GP(handle, CTX_GPREG_X5);
+		ide_key_info.keyqw2 = SMC_GET_GP(handle, CTX_GPREG_X6);
+		ide_key_info.keyqw3 = SMC_GET_GP(handle, CTX_GPREG_X7);
+		ide_key_info.ifvqw0 = SMC_GET_GP(handle, CTX_GPREG_X8);
+		ide_key_info.ifvqw1 = SMC_GET_GP(handle, CTX_GPREG_X9);
+		uint64_t x10 = SMC_GET_GP(handle, CTX_GPREG_X10);
+		uint64_t x11 = SMC_GET_GP(handle, CTX_GPREG_X11);
+
+		ret = rmmd_el3_ide_key_program(x1, x2, x3, &ide_key_info, x10, x11);
+		SMC_RET1(handle, ret);
+	}
+	case RMM_IDE_KEY_SET_GO:
+		ret = rmmd_el3_ide_key_set_go(x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5));
+		SMC_RET1(handle, ret);
+	case RMM_IDE_KEY_SET_STOP:
+		ret = rmmd_el3_ide_key_set_stop(x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5));
+		SMC_RET1(handle, ret);
+	case RMM_IDE_KM_PULL_RESPONSE: {
+		uint64_t req_resp = 0, req_id = 0, cookie_var = 0;
+
+		ret = rmmd_el3_ide_km_pull_response(x1, x2, &req_resp, &req_id, &cookie_var);
+		SMC_RET4(handle, ret, req_resp, req_id, cookie_var);
+	}
+#endif /* RMMD_ENABLE_IDE_KEY_PROG */
 	case RMM_BOOT_COMPLETE:
 		VERBOSE("RMMD: running rmmd_rmm_sync_exit\n");
 		rmmd_rmm_sync_exit(x1);

diff --git a/services/std_svc/rmmd/rmmd_private.h b/services/std_svc/rmmd/rmmd_private.h
index 0ce104d..1fbcd31 100644
--- a/services/std_svc/rmmd/rmmd_private.h
+++ b/services/std_svc/rmmd/rmmd_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #define RMMD_PRIVATE_H
 
 #include <context.h>
+#include <services/rmmd_svc.h>
 
 /*******************************************************************************
  * Constants that allow assembler code to preserve callee-saved registers of the
@@ -54,6 +55,17 @@
 uint64_t rmmd_el3_token_sign(void *handle, uint64_t x1, uint64_t x2,
 				    uint64_t x3, uint64_t x4);
 
+/* Functions implementing IDE KM programming */
+int rmmd_el3_ide_key_program(uint64_t ecam_address, uint64_t rp_id,
+			     uint64_t ide_stream_info, rp_ide_key_info_t *ide_key_info_ptr,
+			     uint64_t request_id, uint64_t cookie);
+int rmmd_el3_ide_key_set_go(uint64_t ecam_address, uint64_t rp_id, uint64_t ide_stream_info,
+			    uint64_t request_id, uint64_t cookie);
+int rmmd_el3_ide_key_set_stop(uint64_t ecam_address, uint64_t rp_id, uint64_t ide_stream_info,
+			      uint64_t request_id, uint64_t cookie);
+int rmmd_el3_ide_km_pull_response(uint64_t ecam_address, uint64_t rp_id, uint64_t *req_resp,
+				  uint64_t *request_id, uint64_t *cookie_ptr);
+
 /* Assembly helpers */
 uint64_t rmmd_rmm_enter(uint64_t *c_rt_ctx);
 void __dead2 rmmd_rmm_exit(uint64_t c_rt_ctx, uint64_t ret);

diff --git a/services/std_svc/rmmd/rmmd_rmm_lfa.c b/services/std_svc/rmmd/rmmd_rmm_lfa.c
new file mode 100644
index 0000000..966266b
--- /dev/null
+++ b/services/std_svc/rmmd/rmmd_rmm_lfa.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <services/lfa_svc.h>
+#include <services/rmmd_rmm_lfa.h>
+
+static int32_t lfa_rmm_prime(struct lfa_component_status *activation)
+{
+	return LFA_WRONG_STATE;
+}
+
+static int32_t lfa_rmm_activate(struct lfa_component_status *activation,
+				uint64_t ep_address, uint64_t context_id)
+{
+	return LFA_WRONG_STATE;
+}
+
+static struct lfa_component_ops rmm_activator = {
+	.prime = lfa_rmm_prime,
+	.activate = lfa_rmm_activate,
+	.may_reset_cpu = false,
+	.cpu_rendezvous_required = true,
+};
+
+struct lfa_component_ops *get_rmm_activator(void)
+{
+	return &rmm_activator;
+}

diff --git a/services/std_svc/rmmd/trp/trp_entry.S b/services/std_svc/rmmd/trp/trp_entry.S
index 3e1d8c9..a2fd6a0 100644
--- a/services/std_svc/rmmd/trp/trp_entry.S
+++ b/services/std_svc/rmmd/trp/trp_entry.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,6 +21,8 @@
 	 * ---------------------------------------------
 	 */
 	.macro restore_args_call_smc
+	ldp	x10, x11, [x0, #TRP_ARG10]
+	ldp	x8, x9, [x0, #TRP_ARG8]
 	ldp	x6, x7, [x0, #TRP_ARG6]
 	ldp	x4, x5, [x0, #TRP_ARG4]
 	ldp	x2, x3, [x0, #TRP_ARG2]

diff --git a/services/std_svc/rmmd/trp/trp_helpers.c b/services/std_svc/rmmd/trp/trp_helpers.c
index 159f3a5..0607864 100644
--- a/services/std_svc/rmmd/trp/trp_helpers.c
+++ b/services/std_svc/rmmd/trp/trp_helpers.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,7 +25,11 @@
 			uint64_t arg4,
 			uint64_t arg5,
 			uint64_t arg6,
-			uint64_t arg7)
+			uint64_t arg7,
+			uint64_t arg8,
+			uint64_t arg9,
+			uint64_t arg10,
+			uint64_t arg11)
 {
 	uint32_t linear_id;
 	trp_args_t *pcpu_smc_args;
@@ -44,6 +48,10 @@
 	write_trp_arg(pcpu_smc_args, TRP_ARG5, arg5);
 	write_trp_arg(pcpu_smc_args, TRP_ARG6, arg6);
 	write_trp_arg(pcpu_smc_args, TRP_ARG7, arg7);
+	write_trp_arg(pcpu_smc_args, TRP_ARG8, arg8);
+	write_trp_arg(pcpu_smc_args, TRP_ARG9, arg9);
+	write_trp_arg(pcpu_smc_args, TRP_ARG10, arg10);
+	write_trp_arg(pcpu_smc_args, TRP_ARG11, arg11);
 
 	return pcpu_smc_args;
 }
@@ -53,6 +61,6 @@
  */
 __dead2 void trp_boot_abort(uint64_t err)
 {
-	(void)trp_smc(set_smc_args(RMM_BOOT_COMPLETE, err, 0, 0, 0, 0, 0, 0));
+	(void)trp_smc(set_smc_args(RMM_BOOT_COMPLETE, err, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0));
 	panic();
 }

diff --git a/services/std_svc/rmmd/trp/trp_main.c b/services/std_svc/rmmd/trp/trp_main.c
index b75483c..a82966e 100644
--- a/services/std_svc/rmmd/trp/trp_main.c
+++ b/services/std_svc/rmmd/trp/trp_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,6 +15,27 @@
 
 #include <platform_def.h>
 
+#define RMI_ERROR_REALM			2U
+#define RMI_ERROR_NOT_SUPPORTED		6U
+
+#define DIR_BIT_SHIFT			0x8
+#define KEYSET_SHIFT			0xC
+#define	STREAM_ID_MASK			0xFF
+#define STREAM_ID_SHIFT			0x0
+#define SUBSTREAM_MASK			0x7
+#define SUBSTREAM_SHIFT			0x8
+
+#define KEY_SET				0x0
+#define	DIR_VAL				0x0
+#define	SUBSTREAM_VAL			0x1
+#define	STREAM_ID			0x1
+
+#define ENCODE_STREAM_INFO(key, dir, substream, stream_id)			\
+		(((key & 0x1) << KEYSET_SHIFT) |				\
+		((dir & 0x1) << DIR_BIT_SHIFT) |				\
+		((substream && SUBSTREAM_MASK) << SUBSTREAM_SHIFT) |		\
+		((stream_id && STREAM_ID_MASK) << STREAM_ID_SHIFT))
+
 /* Parameters received from the previous image */
 static unsigned int trp_boot_abi_version;
 static uintptr_t trp_shared_region_start;
@@ -129,7 +150,7 @@
 {
 	VERBOSE("Delegating granule 0x%llx\n", x1);
 	smc_ret->x[0] = trp_smc(set_smc_args(RMM_GTSI_DELEGATE, x1,
-						0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
+				0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
 
 	if (smc_ret->x[0] != 0ULL) {
 		ERROR("Granule transition from NON-SECURE type to REALM type "
@@ -145,7 +166,7 @@
 {
 	VERBOSE("Undelegating granule 0x%llx\n", x1);
 	smc_ret->x[0] = trp_smc(set_smc_args(RMM_GTSI_UNDELEGATE, x1,
-						0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
+				0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
 
 	if (smc_ret->x[0] != 0ULL) {
 		ERROR("Granule transition from REALM type to NON-SECURE type "
@@ -154,6 +175,62 @@
 }
 
 /*******************************************************************************
+ * Test the IDE Key management interface
+ ******************************************************************************/
+static void trp_ide_keymgmt_interface_fn(unsigned long long x1, unsigned long long x2,
+					struct trp_smc_result *smc_ret)
+{
+	uint64_t ecam_address = 0U, rp_id = 0U, ide_stream_info;
+	uint64_t keyqw0, keyqw1, keyqw2, keyqw3;
+	uint64_t ifvqw0, ifvqw1;
+	int return_value;
+
+#if RMMD_ENABLE_IDE_KEY_PROG
+	trp_get_test_rootport(&ecam_address, &rp_id);
+#endif /* RMMD_ENABLE_IDE_KEY_PROG */
+	/*
+	 * Dummy values for testing:
+	 * Key set = 0x0
+	 * Dir = 0x0
+	 * Substream = 0x1
+	 * Stream ID = 0x1
+	 */
+	ide_stream_info  = ENCODE_STREAM_INFO(KEY_SET, DIR_VAL, SUBSTREAM_VAL, STREAM_ID);
+
+	/* Dummy key and IV values for testing */
+	keyqw0 = 0xA1B2C3D4E5F60708;
+	keyqw1 = 0x1122334455667788;
+	keyqw2 = 0xDEADBEEFCAFEBABE;
+	keyqw3 = 0x1234567890ABCDEF;
+	ifvqw0 = 0xABCDEF0123456789;
+	ifvqw1 = 0x9876543210FEDCBA;
+
+	return_value = trp_smc(set_smc_args(RMM_IDE_KEY_PROG, ecam_address, rp_id,
+				ide_stream_info, keyqw0, keyqw1, keyqw2, keyqw3, ifvqw0,
+				ifvqw1, 0UL, 0UL));
+
+	INFO("return value from RMM_IDE_KEY_PROG = %d\n", return_value);
+
+	return_value = trp_smc(set_smc_args(RMM_IDE_KEY_SET_GO, ecam_address, rp_id,
+				ide_stream_info, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
+
+	INFO("return value from RMM_IDE_KEY_SET_GO = %d\n", return_value);
+
+	return_value = trp_smc(set_smc_args(RMM_IDE_KEY_SET_STOP, ecam_address, rp_id,
+				ide_stream_info, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
+
+	INFO("return value from RMM_IDE_KEY_SET_STOP = %d\n", return_value);
+
+	return_value = trp_smc(set_smc_args(RMM_IDE_KM_PULL_RESPONSE, ecam_address, rp_id,
+				0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL));
+
+	INFO("return value from RMM_IDE_KEY_SET_STOP = %d\n", return_value);
+
+	smc_ret->x[0] = RMI_ERROR_NOT_SUPPORTED;
+
+}
+
+/*******************************************************************************
  * Main RMI SMC handler function
  ******************************************************************************/
 void trp_rmi_handler(unsigned long fid,
@@ -179,6 +256,9 @@
 	case RMI_RMM_GRANULE_UNDELEGATE:
 		trp_asc_mark_nonsecure(x1, smc_ret);
 		break;
+	case RMI_RMM_PDEV_CREATE:
+		trp_ide_keymgmt_interface_fn(x1, x2, smc_ret);
+		break;
 	default:
 		ERROR("Invalid SMC code to %s, FID %lx\n", __func__, fid);
 		smc_ret->x[0] = SMC_UNK;

diff --git a/services/std_svc/rmmd/trp/trp_private.h b/services/std_svc/rmmd/trp/trp_private.h
index d8c6960..16edc5e 100644
--- a/services/std_svc/rmmd/trp/trp_private.h
+++ b/services/std_svc/rmmd/trp/trp_private.h

@@ -28,6 +28,7 @@
 #define RMI_RMM_REQ_VERSION		SMC64_RMI_FID(U(0))
 #define RMI_RMM_GRANULE_DELEGATE	SMC64_RMI_FID(U(1))
 #define RMI_RMM_GRANULE_UNDELEGATE	SMC64_RMI_FID(U(2))
+#define RMI_RMM_PDEV_CREATE		SMC64_RMI_FID(U(0x26))
 
 /* Definitions for RMI VERSION */
 #define RMI_ABI_VERSION_MAJOR		U(0x0)

diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index e0c7971..9c7f74a 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,14 +19,14 @@
  * Both shared and private maps are stored in single-dimensional array. Private
  * event entries are kept for each PE forming a 2D array.
  */
-sdei_entry_t *get_event_entry(sdei_ev_map_t *map)
+sdei_entry_t *get_event_entry(const sdei_ev_map_t *map)
 {
 	const sdei_mapping_t *mapping;
 	sdei_entry_t *cpu_priv_base;
 	unsigned int base_idx;
 	long int idx;
 
-	if (is_event_private(map)) {
+	if ((map->map_flags & BIT_32(SDEI_MAPF_PRIVATE_SHIFT_)) != 0U) {
 		/*
 		 * For a private map, find the index of the mapping in the
 		 * array.
@@ -52,6 +52,49 @@
 }
 
 /*
+ * Retrieve the SDEI entry for the given mapping and target PE.
+ *
+ * on success : Returns a pointer to the SDEI entry
+ *
+ * On error, returns NULL
+ *
+ * Both shared and private maps are stored in single-dimensional array. Private
+ * event entries are kept for each PE forming a 2D array.
+ */
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm,
+uint64_t target_pe)
+{
+	sdei_entry_t *cpu_priv_base;
+	unsigned int base_idx = 0U;
+	long int idx;
+	int target_pos;
+
+	/*
+	 * For a private map, find the index of the mapping in the
+	 * array.
+	 */
+	idx = mapsub;
+
+	/* Base of private mappings for this CPU */
+	target_pos = plat_core_pos_by_mpidr(target_pe);
+
+	if ((target_pos < 0) || ((unsigned int)target_pos >= PLATFORM_CORE_COUNT)) {
+		return NULL;
+	}
+
+	base_idx = (unsigned int) target_pos;
+	base_idx *= nm;
+
+	cpu_priv_base = &sdei_private_event_table[base_idx];
+
+	/*
+	 * Return the address of the entry at the same index in the
+	 * per-CPU event entry.
+	 */
+	return &cpu_priv_base[idx];
+}
+
+/*
  * Find event mapping for a given interrupt number: On success, returns pointer
  * to the event mapping. On error, returns NULL.
  */

diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index c58adba..40c3c24 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,7 +29,8 @@
 #define MAX_EVENT_NESTING	2U
 
 /* Per-CPU SDEI state access macro */
-#define sdei_get_this_pe_state()	(&cpu_state[plat_my_core_pos()])
+#define sdei_get_this_pe_state()		(&cpu_state[plat_my_core_pos()])
+#define sdei_get_target_pe_state(_pe)	(&cpu_state[plat_core_pos_by_mpidr(_pe)])
 
 /* Structure to store information about an outstanding dispatch */
 typedef struct sdei_dispatch_context {
@@ -58,6 +59,16 @@
 /* SDEI states for all cores in the system */
 static sdei_cpu_state_t cpu_state[PLATFORM_CORE_COUNT];
 
+bool sdei_is_target_pe_masked(uint64_t target_pe)
+{
+	int errstat = plat_core_pos_by_mpidr(target_pe);
+	if (errstat >= 0) {
+		const sdei_cpu_state_t *state = &cpu_state[errstat];
+		return state->pe_masked;
+	}
+	return true;
+}
+
 int64_t sdei_pe_mask(void)
 {
 	int64_t ret = 0;

diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index 01cc131..52c01e8 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -910,25 +910,57 @@
 /* Send a signal to another SDEI client PE */
 static int sdei_signal(int ev_num, uint64_t target_pe)
 {
+	unsigned int i;
 	sdei_ev_map_t *map;
+	sdei_ev_map_t *map_priv;
+	sdei_entry_t *se;
 
 	/* Only event 0 can be signalled */
-	if (ev_num != SDEI_EVENT_0)
+	if (ev_num != SDEI_EVENT_0) {
 		return SDEI_EINVAL;
+	}
 
 	/* Find mapping for event 0 */
 	map = find_event_map(SDEI_EVENT_0);
-	if (map == NULL)
+	if (map == NULL) {
 		return SDEI_EINVAL;
+	}
 
 	/* The event must be signalable */
-	if (!is_event_signalable(map))
+	if (!is_event_signalable(map)) {
 		return SDEI_EINVAL;
+	}
 
 	/* Validate target */
-	if (!is_valid_mpidr(target_pe))
+	if (!is_valid_mpidr(target_pe)) {
 		return SDEI_EINVAL;
+	}
 
+	/* The event must be unmasked */
+	if (sdei_is_target_pe_masked(target_pe)) {
+		return SDEI_EINVAL;
+	}
+
+	/* The event must be registered and enabled */
+	if (is_event_private(map)) {
+		map_priv = SDEI_PRIVATE_MAPPING()->map;
+		for (i = 0; i < SDEI_PRIVATE_MAPPING()->num_maps; i++) {
+			if (map_priv->ev_num == SDEI_EVENT_0) {
+				se = get_event_entry_target_pe((long int) i,
+				(unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+				if (se == NULL) {
+					return SDEI_EINVAL;
+				}
+				if (!(GET_EV_STATE((se), REGISTERED))) {
+					return SDEI_EINVAL;
+				}
+				if (!(GET_EV_STATE((se), ENABLED))) {
+					return SDEI_EINVAL;
+				}
+			}
+			map_priv++;
+		}
+	}
 	/* Raise SGI. Platform will validate target_pe */
 	plat_ic_raise_el3_sgi((int) map->intr, (u_register_t) target_pe);
 

diff --git a/services/std_svc/sdei/sdei_private.h b/services/std_svc/sdei/sdei_private.h
index 44a7301..d48db46 100644
--- a/services/std_svc/sdei/sdei_private.h
+++ b/services/std_svc/sdei/sdei_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -232,13 +232,15 @@
 
 sdei_ev_map_t *find_event_map_by_intr(unsigned int intr_num, bool shared);
 sdei_ev_map_t *find_event_map(int ev_num);
-sdei_entry_t *get_event_entry(sdei_ev_map_t *map);
+sdei_entry_t *get_event_entry(const sdei_ev_map_t *map);
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe);
 
 int64_t sdei_event_context(void *handle, unsigned int param);
 int sdei_event_complete(bool resume, uint64_t pc);
 
-void sdei_pe_unmask(void);
+bool sdei_is_target_pe_masked(uint64_t target_pe);
 int64_t sdei_pe_mask(void);
+void sdei_pe_unmask(void);
 
 int sdei_intr_handler(uint32_t intr_raw, uint32_t flags, void *handle,
 		void *cookie);

diff --git a/services/std_svc/spm/el3_spmc/spmc_main.c b/services/std_svc/spm/el3_spmc/spmc_main.c
index bddfe96..c67a6fc 100644
--- a/services/std_svc/spm/el3_spmc/spmc_main.c
+++ b/services/std_svc/spm/el3_spmc/spmc_main.c

@@ -1359,6 +1359,16 @@
 		/* Execution stops here. */
 
 	/* Supported ABIs only from the secure world. */
+	case FFA_MEM_PERM_GET_SMC32:
+	case FFA_MEM_PERM_GET_SMC64:
+	case FFA_MEM_PERM_SET_SMC32:
+	case FFA_MEM_PERM_SET_SMC64:
+	/* these ABIs are only supported from S-EL0 SPs */
+	#if !(SPMC_AT_EL3_SEL0_SP)
+		return spmc_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+	#endif
+	/* fall through */
+
 	case FFA_SECONDARY_EP_REGISTER_SMC64:
 	case FFA_MSG_SEND_DIRECT_RESP_SMC32:
 	case FFA_MSG_SEND_DIRECT_RESP_SMC64:
@@ -1367,7 +1377,6 @@
 	case FFA_MSG_WAIT:
 	case FFA_CONSOLE_LOG_SMC32:
 	case FFA_CONSOLE_LOG_SMC64:
-
 		if (!secure_origin) {
 			return spmc_ffa_error_return(handle,
 				FFA_ERROR_NOT_SUPPORTED);

diff --git a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
index 5263c04..323f7f7 100644
--- a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
+++ b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c

@@ -679,6 +679,18 @@
 		return 0;
 }
 
+static bool compatible_version(uint32_t ffa_version, uint16_t major,
+			       uint16_t minor)
+{
+	bool bit31_set = ffa_version & FFA_VERSION_BIT31_MASK;
+	uint16_t majv = (ffa_version >> FFA_VERSION_MAJOR_SHIFT) &
+			FFA_VERSION_MAJOR_MASK;
+	uint16_t minv = (ffa_version >> FFA_VERSION_MINOR_SHIFT) &
+			FFA_VERSION_MINOR_MASK;
+
+	return !bit31_set && majv == major && minv >= minor;
+}
+
 static int
 spmc_validate_mtd_start(struct ffa_mtd *desc, uint32_t ffa_version,
 			size_t fragment_length, size_t total_length)
@@ -691,7 +703,7 @@
 	/* Determine the appropriate minimum descriptor size. */
 	if (ffa_version == MAKE_FFA_VERSION(1, 0)) {
 		min_desc_size = sizeof(struct ffa_mtd_v1_0);
-	} else if (ffa_version == MAKE_FFA_VERSION(1, 1)) {
+	} else if (compatible_version(ffa_version, 1, 1)) {
 		min_desc_size = sizeof(struct ffa_mtd);
 	} else {
 		return FFA_ERROR_INVALID_PARAMETER;
@@ -1212,7 +1224,7 @@
 
 	if (ffa_version == MAKE_FFA_VERSION(1, 0)) {
 		min_desc_size = sizeof(struct ffa_mtd_v1_0);
-	} else if (ffa_version == MAKE_FFA_VERSION(1, 1)) {
+	} else if (compatible_version(ffa_version, 1, 1)) {
 		min_desc_size = sizeof(struct ffa_mtd);
 	} else {
 		WARN("%s: bad FF-A version.\n", __func__);

diff --git a/services/std_svc/spm/spm_mm/spm_mm_main.c b/services/std_svc/spm/spm_mm/spm_mm_main.c
index 34e2c00..7fe826d 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_main.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,53 +34,19 @@
 /*******************************************************************************
  * Set state of a Secure Partition context.
  ******************************************************************************/
-void sp_state_set(sp_context_t *sp_ptr, sp_state_t state)
+static void sp_state_set(sp_context_t *sp_ptr, sp_state_t state)
 {
-	spin_lock(&(sp_ptr->state_lock));
 	sp_ptr->state = state;
 	spin_unlock(&(sp_ptr->state_lock));
 }
 
 /*******************************************************************************
- * Wait until the state of a Secure Partition is the specified one and change it
- * to the desired state.
+ * Change the state of a Secure Partition to the one specified.
  ******************************************************************************/
-void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
+static void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
 {
-	int success = 0;
-
-	while (success == 0) {
-		spin_lock(&(sp_ptr->state_lock));
-
-		if (sp_ptr->state == from) {
-			sp_ptr->state = to;
-
-			success = 1;
-		}
-
-		spin_unlock(&(sp_ptr->state_lock));
-	}
-}
-
-/*******************************************************************************
- * Check if the state of a Secure Partition is the specified one and, if so,
- * change it to the desired state. Returns 0 on success, -1 on error.
- ******************************************************************************/
-int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
-{
-	int ret = -1;
-
 	spin_lock(&(sp_ptr->state_lock));
-
-	if (sp_ptr->state == from) {
-		sp_ptr->state = to;
-
-		ret = 0;
-	}
-
-	spin_unlock(&(sp_ptr->state_lock));
-
-	return ret;
+	sp_ptr->state = to;
 }
 
 /*******************************************************************************

diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 94634f2..310610d 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c

@@ -888,11 +888,15 @@
 		}
 
 		/*
-		 * If there was an SPMD logical partition direct request on-going,
+		 * Perform a synchronous exit:
+		 * 1. If there was an SPMD logical partition direct request on-going,
 		 * return back to the SPMD logical partition so the error can be
 		 * consumed.
+		 * 2. SPMC sent FFA_ERROR in response to a power management
+		 * operation sent through direct request.
 		 */
-		if (is_spmd_logical_sp_dir_req_in_progress(ctx)) {
+		if (is_spmd_logical_sp_dir_req_in_progress(ctx) ||
+		    ctx->psci_operation_ongoing) {
 			assert(secure_origin);
 			spmd_spm_core_sync_exit(0ULL);
 		}

diff --git a/services/std_svc/spmd/spmd_pm.c b/services/std_svc/spmd/spmd_pm.c
index fd89c81..4ed3e2f 100644
--- a/services/std_svc/spmd/spmd_pm.c
+++ b/services/std_svc/spmd/spmd_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -117,6 +117,8 @@
 	spmd_spm_core_context_t *ctx = spmd_get_context();
 	unsigned int linear_id = plat_my_core_pos();
 	int64_t rc;
+	uint32_t ffa_resp_func_id, msg_flags;
+	int status;
 
 	assert(ctx != NULL);
 	assert(ctx->state != SPMC_STATE_OFF);
@@ -137,24 +139,60 @@
 	write_ctx_reg(gpregs, CTX_GPREG_X16, 0);
 	write_ctx_reg(gpregs, CTX_GPREG_X17, 0);
 
+	/* Mark current core as processing a PSCI operation. */
+	ctx->psci_operation_ongoing = true;
+
 	rc = spmd_spm_core_sync_entry(ctx);
+
 	if (rc != 0ULL) {
 		ERROR("%s failed (%" PRIu64 ") on CPU%u\n", __func__, rc, linear_id);
 	}
 
+	ctx->psci_operation_ongoing = false;
+
 	/* Expect a direct message response from the SPMC. */
-	u_register_t ffa_resp_func = read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+	ffa_resp_func_id = (uint32_t)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
 						  CTX_GPREG_X0);
-	if (ffa_resp_func != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
-		ERROR("%s invalid SPMC response (%lx).\n",
-			__func__, ffa_resp_func);
-		return -EINVAL;
+
+	/*
+	 * Retrieve flags indicating framework message and power management
+	 * response.
+	 */
+	msg_flags = (uint32_t)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+						  CTX_GPREG_X2);
+
+	/* Retrieve error code indicating status of power management operation. */
+	status = (int)read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+						  CTX_GPREG_X3);
+
+	if (ffa_resp_func_id == FFA_ERROR) {
+		/*
+		 * It is likely that SPMC does not support receiving PSCI
+		 * operation through framework message. SPMD takes an
+		 * implementation defined choice to not treat it as a fatal
+		 * error. Consequently, SPMD ignores the error and continues
+		 * with power management operation.
+		 */
+		VERBOSE("SPMC ignored PSCI CPU_OFF framework message\n");
+	} else if (ffa_resp_func_id != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
+		ERROR("%s invalid SPMC response (%x).\n",
+			__func__, ffa_resp_func_id);
+		panic();
+	} else if (((msg_flags & FFA_FWK_MSG_BIT) == 0U) ||
+			 ((msg_flags & FFA_FWK_MSG_MASK) != FFA_PM_MSG_PM_RESP)) {
+		ERROR("SPMC failed to send framework message response for power"
+			" management operation, message flags = (%x)\n",
+			 msg_flags);
+		panic();
+	} else if (status != PSCI_E_SUCCESS) {
+		ERROR("SPMC denied CPU_OFF power management request\n");
+		panic();
+	} else {
+		VERBOSE("CPU %u off!\n", linear_id);
 	}
 
 	ctx->state = SPMC_STATE_OFF;
 
-	VERBOSE("CPU %u off!\n", linear_id);
-
 	return 0;
 }
 

diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index 2cd18a2..0dfad02 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -52,6 +52,7 @@
 	cpu_context_t cpu_ctx;
 	spmc_state_t state;
 	bool secure_interrupt_ongoing;
+	bool psci_operation_ongoing;
 #if ENABLE_SPMD_LP
 	uint8_t spmd_lp_sync_req_ongoing;
 #endif

diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 5cfe5f9..11c6031 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,6 +15,7 @@
 #include <lib/runtime_instr.h>
 #include <services/drtm_svc.h>
 #include <services/errata_abi_svc.h>
+#include <services/lfa_svc.h>
 #include <services/pci_svc.h>
 #include <services/rmmd_svc.h>
 #include <services/sdei.h>
@@ -86,6 +87,15 @@
 	}
 #endif /* DRTM_SUPPORT */
 
+#if LFA_SUPPORT
+	/*
+	 * Setup/Initialize resources useful during LFA
+	 */
+	if (lfa_setup() != 0) {
+		ret = 1;
+	}
+#endif /* LFA_SUPPORT */
+
 	return ret;
 }
 
@@ -94,14 +104,19 @@
  * calls to PSCI SMC handler
  */
 static uintptr_t std_svc_smc_handler(uint32_t smc_fid,
-			     u_register_t x1,
-			     u_register_t x2,
-			     u_register_t x3,
-			     u_register_t x4,
+			     u_register_t x1_arg,
+			     u_register_t x2_arg,
+			     u_register_t x3_arg,
+			     u_register_t x4_arg,
 			     void *cookie,
 			     void *handle,
 			     u_register_t flags)
 {
+	u_register_t x1 = x1_arg;
+	u_register_t x2 = x2_arg;
+	u_register_t x3 = x3_arg;
+	u_register_t x4 = x4_arg;
+
 	if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
 		/* 32-bit SMC function, clear top parameter bits */
 
@@ -212,6 +227,13 @@
 	}
 #endif /* DRTM_SUPPORT */
 
+#if LFA_SUPPORT
+	if (is_lfa_fid(smc_fid)) {
+		return lfa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+	}
+#endif /* LFA_SUPPORT */
+
+
 	switch (smc_fid) {
 	case ARM_STD_SVC_CALL_COUNT:
 		/*

diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index 9975ea3..81e9fb8 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json

@@ -1,6 +1,6 @@
 {
   "name": "conventional-changelog-tf-a",
-  "version": "2.12.0",
+  "version": "2.13.0",
   "license": "BSD-3-Clause",
   "private": true,
   "main": "index.js",

diff --git a/tools/marvell/doimage/doimage.c b/tools/marvell/doimage/doimage.c
index 1f0985c..12e1327 100644
--- a/tools/marvell/doimage/doimage.c
+++ b/tools/marvell/doimage/doimage.c

@@ -421,7 +421,7 @@
 	char			*ptmp = (char *)&tv;
 	unsigned char		digest[32];
 	unsigned char		IV[AES_BLOCK_SZ];
-	int			i, k;
+	size_t			i, k;
 	mbedtls_aes_context	aes_ctx;
 	int			rval = -1;
 	uint8_t			*test_img = 0;
@@ -516,7 +516,8 @@
 	for (i = 0; i < blen; i++) {
 		if (buf[i] != test_img[i]) {
 			fprintf(stderr, "Failed to compare the image after");
-			fprintf(stderr, " decryption! Byte count is %d\n", i);
+			fprintf(stderr, " decryption! Byte count is %lu\n",
+				(unsigned long)i);
 			rval = -1;
 			goto encrypt_exit;
 		}
@@ -614,11 +615,11 @@
 int verify_and_copy_file_name_entry(const char *element_name,
 				    const char *element, char *copy_to)
 {
-	int element_length = strlen(element);
+	size_t element_length = strlen(element);
 
 	if (element_length >= MAX_FILENAME) {
-		fprintf(stderr, "The file name %s for %s is too long (%d). ",
-			element, element_name, element_length);
+		fprintf(stderr, "The file name %s for %s is too long (%lu). ",
+			element, element_name, (unsigned long)element_length);
 		fprintf(stderr, "Maximum allowed %d characters!\n",
 			MAX_FILENAME);
 		return -1;

diff --git a/tools/memory/poetry.lock b/tools/memory/poetry.lock
index 2747479..67641ee 100644
--- a/tools/memory/poetry.lock
+++ b/tools/memory/poetry.lock

@@ -40,6 +40,103 @@
 ]
 
 [[package]]
+name = "jinja2"
+version = "3.1.6"
+description = "A very fast and expressive template engine."
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "jinja2-3.1.6-py3-none-any.whl", hash = "sha256:85ece4451f492d0c13c5dd7c13a64681a86afae63a5f347908daf103ce6d2f67"},
+    {file = "jinja2-3.1.6.tar.gz", hash = "sha256:0137fb05990d35f1275a587e9aee6d56da821fc83491a0fb838183be43f66d6d"},
+]
+
+[package.dependencies]
+MarkupSafe = ">=2.0"
+
+[package.extras]
+i18n = ["Babel (>=2.7)"]
+
+[[package]]
+name = "markupsafe"
+version = "2.1.5"
+description = "Safely add untrusted strings to HTML/XML markup."
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "MarkupSafe-2.1.5-cp310-cp310-macosx_10_9_universal2.whl", hash = "sha256:a17a92de5231666cfbe003f0e4b9b3a7ae3afb1ec2845aadc2bacc93ff85febc"},
+    {file = "MarkupSafe-2.1.5-cp310-cp310-macosx_10_9_x86_64.whl", hash = "sha256:72b6be590cc35924b02c78ef34b467da4ba07e4e0f0454a2c5907f473fc50ce5"},
+    {file = "MarkupSafe-2.1.5-cp310-cp310-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:e61659ba32cf2cf1481e575d0462554625196a1f2fc06a1c777d3f48e8865d46"},
+    {file = "MarkupSafe-2.1.5-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:2174c595a0d73a3080ca3257b40096db99799265e1c27cc5a610743acd86d62f"},
+    {file = "MarkupSafe-2.1.5-cp310-cp310-manylinux_2_5_i686.manylinux1_i686.manylinux_2_17_i686.manylinux2014_i686.whl", hash = "sha256:ae2ad8ae6ebee9d2d94b17fb62763125f3f374c25618198f40cbb8b525411900"},
+    {file = "MarkupSafe-2.1.5-cp310-cp310-musllinux_1_1_aarch64.whl", hash = "sha256:075202fa5b72c86ad32dc7d0b56024ebdbcf2048c0ba09f1cde31bfdd57bcfff"},
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+    {file = "MarkupSafe-2.1.5-cp310-cp310-win32.whl", hash = "sha256:d9fad5155d72433c921b782e58892377c44bd6252b5af2f67f16b194987338a4"},
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+    {file = "MarkupSafe-2.1.5-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:b91c037585eba9095565a3556f611e3cbfaa42ca1e865f7b8015fe5c7336d5a5"},
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+    {file = "MarkupSafe-2.1.5-cp39-cp39-win_amd64.whl", hash = "sha256:fa173ec60341d6bb97a89f5ea19c85c5643c1e7dedebc22f5181eb73573142c5"},
+    {file = "MarkupSafe-2.1.5.tar.gz", hash = "sha256:d283d37a890ba4c1ae73ffadf8046435c76e7bc2247bbb63c00bd1a709c6544b"},
+]
+
+[[package]]
+name = "nodeenv"
+version = "1.9.1"
+description = "Node.js virtual environment builder"
+optional = false
+python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*,>=2.7"
+files = [
+    {file = "nodeenv-1.9.1-py2.py3-none-any.whl", hash = "sha256:ba11c9782d29c27c70ffbdda2d7415098754709be8a7056d79a737cd901155c9"},
+    {file = "nodeenv-1.9.1.tar.gz", hash = "sha256:6ec12890a2dab7946721edbfbcd91f3319c6ccc9aec47be7c7e6b7011ee6645f"},
+]
+
+[[package]]
 name = "prettytable"
 version = "3.11.0"
 description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format"
@@ -68,6 +165,53 @@
 ]
 
 [[package]]
+name = "pyright"
+version = "1.1.399"
+description = "Command line wrapper for pyright"
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "pyright-1.1.399-py3-none-any.whl", hash = "sha256:55f9a875ddf23c9698f24208c764465ffdfd38be6265f7faf9a176e1dc549f3b"},
+    {file = "pyright-1.1.399.tar.gz", hash = "sha256:439035d707a36c3d1b443aec980bc37053fbda88158eded24b8eedcf1c7b7a1b"},
+]
+
+[package.dependencies]
+nodeenv = ">=1.6.0"
+typing-extensions = ">=4.1"
+
+[package.extras]
+all = ["nodejs-wheel-binaries", "twine (>=3.4.1)"]
+dev = ["twine (>=3.4.1)"]
+nodejs = ["nodejs-wheel-binaries"]
+
+[[package]]
+name = "ruff"
+version = "0.11.2"
+description = "An extremely fast Python linter and code formatter, written in Rust."
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "ruff-0.11.2-py3-none-linux_armv6l.whl", hash = "sha256:c69e20ea49e973f3afec2c06376eb56045709f0212615c1adb0eda35e8a4e477"},
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+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_aarch64.whl", hash = "sha256:2a2b50ca35457ba785cd8c93ebbe529467594087b527a08d487cf0ee7b3087e9"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_armv7l.whl", hash = "sha256:7c69c74bf53ddcfbc22e6eb2f31211df7f65054bfc1f72288fc71e5f82db3eab"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_i686.whl", hash = "sha256:6e8fb75e14560f7cf53b15bbc55baf5ecbe373dd5f3aab96ff7aa7777edd7630"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_x86_64.whl", hash = "sha256:842a472d7b4d6f5924e9297aa38149e5dcb1e628773b70e6387ae2c97a63c58f"},
+    {file = "ruff-0.11.2-py3-none-win32.whl", hash = "sha256:aca01ccd0eb5eb7156b324cfaa088586f06a86d9e5314b0eb330cb48415097cc"},
+    {file = "ruff-0.11.2-py3-none-win_amd64.whl", hash = "sha256:3170150172a8f994136c0c66f494edf199a0bbea7a409f649e4bc8f4d7084080"},
+    {file = "ruff-0.11.2-py3-none-win_arm64.whl", hash = "sha256:52933095158ff328f4c77af3d74f0379e34fd52f175144cefc1b192e7ccd32b4"},
+    {file = "ruff-0.11.2.tar.gz", hash = "sha256:ec47591497d5a1050175bdf4e1a4e6272cddff7da88a2ad595e1e326041d8d94"},
+]
+
+[[package]]
 name = "six"
 version = "1.17.0"
 description = "Python 2 and 3 compatibility utilities"
@@ -79,6 +223,17 @@
 ]
 
 [[package]]
+name = "typing-extensions"
+version = "4.13.2"
+description = "Backported and Experimental Type Hints for Python 3.8+"
+optional = false
+python-versions = ">=3.8"
+files = [
+    {file = "typing_extensions-4.13.2-py3-none-any.whl", hash = "sha256:a439e7c04b49fec3e5d3e2beaa21755cadbbdc391694e28ccdd36ca4a1408f8c"},
+    {file = "typing_extensions-4.13.2.tar.gz", hash = "sha256:e6c81219bd689f51865d9e372991c540bda33a0379d5573cddb9a3a23f7caaef"},
+]
+
+[[package]]
 name = "wcwidth"
 version = "0.2.13"
 description = "Measures the displayed width of unicode strings in a terminal"
@@ -92,4 +247,4 @@
 [metadata]
 lock-version = "2.0"
 python-versions = "^3.8.0"
-content-hash = "d7c185b3dbfc9bba145f12146e18ce501caf081d7762f138bc5a7fde99f40543"
+content-hash = "72f05cdcfe5278c3fb4408ba76cc502c83a56615681d8307bf67fe759a9da442"

diff --git a/tools/memory/pyproject.toml b/tools/memory/pyproject.toml
index c2fdfcb..70d3de7 100644
--- a/tools/memory/pyproject.toml
+++ b/tools/memory/pyproject.toml

@@ -12,10 +12,18 @@
 prettytable = "^3.5.0"
 pyelftools = "^0.29.0"
 python = "^3.8.0"
+jinja2 = "^3.1.6"
 
 [tool.poetry.scripts]
 memory = "memory.memmap:main"
 
+[tool.poetry.group.dev]
+optional = true
+
+[tool.poetry.group.dev.dependencies]
+ruff = "^0.11.2"
+pyright = "^1.1.399"
+
 [build-system]
 requires = ["poetry-core"]
 build-backend = "poetry.core.masonry.api"

diff --git a/tools/memory/src/memory/buildparser.py b/tools/memory/src/memory/buildparser.py
deleted file mode 100755
index ea417e1..0000000
--- a/tools/memory/src/memory/buildparser.py
+++ /dev/null

@@ -1,88 +0,0 @@
-#
-# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-import re
-from pathlib import Path
-
-from memory.elfparser import TfaElfParser
-from memory.mapparser import TfaMapParser
-
-
-class TfaBuildParser:
-    """A class for performing analysis on the memory layout of a TF-A build."""
-
-    def __init__(self, path: Path, map_backend=False):
-        self._modules = dict()
-        self._path = path
-        self.map_backend = map_backend
-        self._parse_modules()
-
-    def __getitem__(self, module: str):
-        """Returns an TfaElfParser instance indexed by module."""
-        return self._modules[module]
-
-    def _parse_modules(self):
-        """Parse the build files using the selected backend."""
-        backend = TfaElfParser
-        files = list(self._path.glob("**/*.elf"))
-        io_perms = "rb"
-
-        if self.map_backend or len(files) == 0:
-            backend = TfaMapParser
-            files = self._path.glob("**/*.map")
-            io_perms = "r"
-
-        for file in files:
-            module_name = file.name.split("/")[-1].split(".")[0]
-            with open(file, io_perms) as f:
-                self._modules[module_name] = backend(f)
-
-        if not len(self._modules):
-            raise FileNotFoundError(
-                f"failed to find files to analyse in path {self._path}!"
-            )
-
-    @property
-    def symbols(self) -> list:
-        return [
-            (*sym, k) for k, v in self._modules.items() for sym in v.symbols
-        ]
-
-    @staticmethod
-    def filter_symbols(symbols: list, regex: str = None) -> list:
-        """Returns a map of symbols to modules."""
-        regex = r".*" if not regex else regex
-        return sorted(
-            filter(lambda s: re.match(regex, s[0]), symbols),
-            key=lambda s: (-s[1], s[0]),
-            reverse=True,
-        )
-
-    def get_mem_usage_dict(self) -> dict:
-        """Returns map of memory usage per memory type for each module."""
-        mem_map = {}
-        for k, v in self._modules.items():
-            mod_mem_map = v.get_memory_layout()
-            if len(mod_mem_map):
-                mem_map[k] = mod_mem_map
-        return mem_map
-
-    def get_mem_tree_as_dict(self) -> dict:
-        """Returns _tree of modules, segments and segments and their total
-        memory usage."""
-        return {
-            k: {
-                "name": k,
-                **v.get_mod_mem_usage_dict(),
-                **{"children": v.get_seg_map_as_dict()},
-            }
-            for k, v in self._modules.items()
-        }
-
-    @property
-    def module_names(self):
-        """Returns sorted list of module names."""
-        return sorted(self._modules.keys())

diff --git a/tools/memory/src/memory/elfparser.py b/tools/memory/src/memory/elfparser.py
index e6581c9..019d6da 100644
--- a/tools/memory/src/memory/elfparser.py
+++ b/tools/memory/src/memory/elfparser.py

@@ -6,9 +6,22 @@
 
 import re
 from dataclasses import asdict, dataclass
-from typing import BinaryIO
+from typing import (
+    Any,
+    BinaryIO,
+    Dict,
+    Iterable,
+    List,
+    Optional,
+    Tuple,
+    Union,
+)
 
 from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import Section, SymbolTableSection
+from elftools.elf.segments import Segment
+
+from memory.image import Image, Region
 
 
 @dataclass(frozen=True)
@@ -17,10 +30,10 @@
     start: int
     end: int
     size: int
-    children: list
+    children: List["TfaMemObject"]
 
 
-class TfaElfParser:
+class TfaElfParser(Image):
     """A class representing an ELF file built for TF-A.
 
     Provides a basic interface for reading the symbol table and other
@@ -28,53 +41,70 @@
     the contents an ELF file.
     """
 
-    def __init__(self, elf_file: BinaryIO):
-        self._segments = {}
-        self._memory_layout = {}
+    def __init__(self, elf_file: BinaryIO) -> None:
+        self._segments: Dict[int, TfaMemObject] = {}
+        self._memory_layout: Dict[str, Dict[str, int]] = {}
 
         elf = ELFFile(elf_file)
 
-        self._symbols = {
-            sym.name: sym.entry["st_value"]
-            for sym in elf.get_section_by_name(".symtab").iter_symbols()
+        symtab = elf.get_section_by_name(".symtab")
+        assert isinstance(symtab, SymbolTableSection)
+
+        self._symbols: Dict[str, int] = {
+            sym.name: sym.entry["st_value"] for sym in symtab.iter_symbols()
         }
 
         self.set_segment_section_map(elf.iter_segments(), elf.iter_sections())
         self._memory_layout = self.get_memory_layout_from_symbols()
-        self._start = elf["e_entry"]
+        self._start: int = elf["e_entry"]
+        self._size: int
+        self._free: int
         self._size, self._free = self._get_mem_usage()
-        self._end = self._start + self._size
+        self._end: int = self._start + self._size
+
+        self._footprint: Dict[str, Region] = {}
+
+        for mem, attrs in self._memory_layout.items():
+            self._footprint[mem] = Region(
+                attrs["start"],
+                attrs["end"],
+                attrs["length"],
+            )
 
     @property
-    def symbols(self):
-        return self._symbols.items()
+    def symbols(self) -> Dict[str, int]:
+        return self._symbols
 
     @staticmethod
-    def tfa_mem_obj_factory(elf_obj, name=None, children=None, segment=False):
+    def tfa_mem_obj_factory(
+        elf_obj: Union[Segment, Section],
+        name: Optional[str] = None,
+        children: Optional[List[TfaMemObject]] = None,
+    ) -> TfaMemObject:
         """Converts a pyelfparser Segment or Section to a TfaMemObject."""
         # Ensure each segment is provided a name since they aren't in the
         # program header.
-        assert not (
-            segment and name is None
-        ), "Attempting to make segment without a name"
-
-        if children is None:
-            children = list()
+        assert not (isinstance(elf_obj, Segment) and name is None), (
+            "Attempting to make segment without a name"
+        )
 
         # Segment and sections header keys have different prefixes.
-        vaddr = "p_vaddr" if segment else "sh_addr"
-        size = "p_memsz" if segment else "sh_size"
+        vaddr = "p_vaddr" if isinstance(elf_obj, Segment) else "sh_addr"
+        size = "p_memsz" if isinstance(elf_obj, Segment) else "sh_size"
+
+        name = name if isinstance(elf_obj, Segment) else elf_obj.name
+        assert name is not None
 
         # TODO figure out how to handle free space for sections and segments
         return TfaMemObject(
-            name if segment else elf_obj.name,
+            name,
             elf_obj[vaddr],
             elf_obj[vaddr] + elf_obj[size],
             elf_obj[size],
-            [] if not children else children,
+            children or [],
         )
 
-    def _get_mem_usage(self) -> (int, int):
+    def _get_mem_usage(self) -> Tuple[int, int]:
         """Get total size and free space for this component."""
         size = free = 0
 
@@ -89,36 +119,37 @@
 
         return size, free
 
-    def set_segment_section_map(self, segments, sections):
+    def set_segment_section_map(
+        self,
+        segments: Iterable[Segment],
+        sections: Iterable[Section],
+    ) -> None:
         """Set segment to section mappings."""
-        segments = list(
-            filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
-        )
+        segments = filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
+        segments_list = list(segments)
 
         for sec in sections:
-            for n, seg in enumerate(segments):
+            for n, seg in enumerate(segments_list):
                 if seg.section_in_segment(sec):
-                    if n not in self._segments.keys():
+                    if n not in self._segments:
                         self._segments[n] = self.tfa_mem_obj_factory(
-                            seg, name=f"{n:#02}", segment=True
+                            seg, name=f"{n:#02}"
                         )
 
-                    self._segments[n].children.append(
-                        self.tfa_mem_obj_factory(sec)
-                    )
+                    self._segments[n].children.append(self.tfa_mem_obj_factory(sec))
 
-    def get_memory_layout_from_symbols(self, expr=None) -> dict:
+    def get_memory_layout_from_symbols(self) -> Dict[str, Dict[str, int]]:
         """Retrieve information about the memory configuration from the symbol
         table.
         """
-        assert len(self._symbols), "Symbol table is empty!"
+        assert self._symbols, "Symbol table is empty!"
 
-        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)" if not expr else expr
+        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
         region_symbols = filter(lambda s: re.match(expr, s), self._symbols)
-        memory_layout = {}
+        memory_layout: Dict[str, Dict[str, int]] = {}
 
         for symbol in region_symbols:
-            region, _, attr = tuple(symbol.lower().strip("__").split("_"))
+            region, _, attr = symbol.lower().strip("__").split("_")
             if region not in memory_layout:
                 memory_layout[region] = {}
 
@@ -127,29 +158,30 @@
 
         return memory_layout
 
-    def get_seg_map_as_dict(self):
+    def get_seg_map_as_dict(self) -> List[Dict[str, Any]]:
         """Get a dictionary of segments and their section mappings."""
-        return [asdict(v) for k, v in self._segments.items()]
+        return [asdict(segment) for segment in self._segments.values()]
 
-    def get_memory_layout(self):
+    def get_memory_layout(self) -> Dict[str, Region]:
         """Get the total memory consumed by this module from the memory
         configuration.
-            {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
         """
-        mem_dict = {}
+        mem_dict: Dict[str, Region] = {}
 
         for mem, attrs in self._memory_layout.items():
-            limit = attrs["start"] + attrs["length"]
-            mem_dict[mem] = {
-                "start": attrs["start"],
-                "limit": limit,
-                "size": attrs["end"] - attrs["start"],
-                "free": limit - attrs["end"],
-                "total": attrs["length"],
-            }
+            mem_dict[mem] = Region(
+                attrs["start"],
+                attrs["end"],
+                attrs["length"],
+            )
+
         return mem_dict
 
-    def get_mod_mem_usage_dict(self):
+    @property
+    def footprint(self) -> Dict[str, Region]:
+        return self._footprint
+
+    def get_mod_mem_usage_dict(self) -> Dict[str, int]:
         """Get the total memory consumed by the module, this combines the
         information in the memory configuration.
         """

diff --git a/tools/memory/src/memory/image.py b/tools/memory/src/memory/image.py
new file mode 100644
index 0000000..cda1d8a
--- /dev/null
+++ b/tools/memory/src/memory/image.py

@@ -0,0 +1,77 @@
+#
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+from abc import ABC, abstractmethod
+from dataclasses import dataclass
+from typing import Dict, Optional
+
+
+@dataclass
+class Region:
+    """Represents a memory region."""
+
+    start: Optional[int] = None
+    """Memory address of the beginning of the region."""
+
+    end: Optional[int] = None
+    """Memory address of the end of the region."""
+
+    length: Optional[int] = None
+    """Current size of the region in bytes."""
+
+    @property
+    def limit(self) -> Optional[int]:
+        """Largest possible end memory address of the region."""
+
+        if self.start is None:
+            return None
+
+        if self.length is None:
+            return None
+
+        return self.start + self.length
+
+    @property
+    def size(self) -> Optional[int]:
+        """Maximum possible size of the region in bytes."""
+
+        if self.end is None:
+            return None
+
+        if self.start is None:
+            return None
+
+        return self.end - self.start
+
+    @property
+    def free(self) -> Optional[int]:
+        """Number of bytes that the region is permitted to further expand."""
+
+        if self.limit is None:
+            return None
+
+        if self.end is None:
+            return None
+
+        return self.limit - self.end
+
+
+class Image(ABC):
+    """An image under analysis."""
+
+    @property
+    @abstractmethod
+    def footprint(self) -> Dict[str, Region]:
+        """Get metrics about the memory regions that this image occupies."""
+
+        pass
+
+    @property
+    @abstractmethod
+    def symbols(self) -> Dict[str, int]:
+        """Get a dictionary of the image's symbols and their corresponding addresses."""
+
+        pass

diff --git a/tools/memory/src/memory/mapparser.py b/tools/memory/src/memory/mapparser.py
index 1c28e71..24ee264 100644
--- a/tools/memory/src/memory/mapparser.py
+++ b/tools/memory/src/memory/mapparser.py

@@ -4,11 +4,14 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+from collections import defaultdict
 from re import match, search
-from typing import TextIO
+from typing import Dict, TextIO
+
+from memory.image import Image, Region
 
 
-class TfaMapParser:
+class TfaMapParser(Image):
     """A class representing a map file built for TF-A.
 
     Provides a basic interface for reading the symbol table. The constructor
@@ -16,17 +19,31 @@
     are supported at this stage.
     """
 
-    def __init__(self, map_file: TextIO):
-        self._symbols = self.read_symbols(map_file)
+    def __init__(self, map_file: TextIO) -> None:
+        self._symbols: Dict[str, int] = self.read_symbols(map_file)
+        assert self._symbols, "Symbol table is empty!"
+
+        self._footprint: Dict[str, Region] = defaultdict(Region)
+
+        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
+        for symbol in filter(lambda s: match(expr, s), self._symbols):
+            region, _, attr = symbol.lower().strip("__").split("_")
+
+            if attr == "start":
+                self._footprint[region].start = self._symbols[symbol]
+            elif attr == "end":
+                self._footprint[region].end = self._symbols[symbol]
+            if attr == "length":
+                self._footprint[region].length = self._symbols[symbol]
 
     @property
-    def symbols(self):
-        return self._symbols.items()
+    def symbols(self) -> Dict[str, int]:
+        return self._symbols
 
     @staticmethod
-    def read_symbols(file: TextIO, pattern: str = None) -> dict:
-        pattern = r"\b(0x\w*)\s*(\w*)\s=" if not pattern else pattern
-        symbols = {}
+    def read_symbols(file: TextIO) -> Dict[str, int]:
+        pattern = r"\b(0x\w*)\s*(\w*)\s="
+        symbols: Dict[str, int] = {}
 
         for line in file.readlines():
             match = search(pattern, line)
@@ -37,39 +54,6 @@
 
         return symbols
 
-    def get_memory_layout(self) -> dict:
-        """Get the total memory consumed by this module from the memory
-        configuration.
-            {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
-        """
-        assert len(self._symbols), "Symbol table is empty!"
-        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
-        memory_layout = {}
-
-        region_symbols = filter(lambda s: match(expr, s), self._symbols)
-
-        for symbol in region_symbols:
-            region, _, attr = tuple(symbol.lower().strip("__").split("_"))
-            if region not in memory_layout:
-                memory_layout[region] = {}
-
-            memory_layout[region][attr] = self._symbols[symbol]
-
-            if "start" and "length" and "end" in memory_layout[region]:
-                memory_layout[region]["limit"] = (
-                    memory_layout[region]["start"]
-                    + memory_layout[region]["length"]
-                )
-                memory_layout[region]["free"] = (
-                    memory_layout[region]["limit"]
-                    - memory_layout[region]["end"]
-                )
-                memory_layout[region]["total"] = memory_layout[region][
-                    "length"
-                ]
-                memory_layout[region]["size"] = (
-                    memory_layout[region]["end"]
-                    - memory_layout[region]["start"]
-                )
-
-        return memory_layout
+    @property
+    def footprint(self) -> Dict[str, Region]:
+        return self._footprint

diff --git a/tools/memory/src/memory/memmap.py b/tools/memory/src/memory/memmap.py
index f46db8c..e02010b 100755
--- a/tools/memory/src/memory/memmap.py
+++ b/tools/memory/src/memory/memmap.py

@@ -1,19 +1,32 @@
-#!/usr/bin/env python3
-
 #
 # Copyright (c) 2023-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+import re
+import shutil
+from dataclasses import dataclass
 from pathlib import Path
+from typing import Any, Dict, List, Optional
 
 import click
-from memory.buildparser import TfaBuildParser
+
+from memory.elfparser import TfaElfParser
+from memory.image import Image
+from memory.mapparser import TfaMapParser
 from memory.printer import TfaPrettyPrinter
+from memory.summary import MapParser
 
 
-@click.command()
+@dataclass
+class Context:
+    build_path: Optional[Path] = None
+    printer: Optional[TfaPrettyPrinter] = None
+
+
+@click.group()
+@click.pass_obj
 @click.option(
     "-r",
     "--root",
@@ -36,75 +49,171 @@
     type=click.Choice(["debug", "release"], case_sensitive=False),
 )
 @click.option(
-    "-f",
-    "--footprint",
-    is_flag=True,
-    show_default=True,
-    help="Generate a high level view of memory usage by memory types.",
+    "-w",
+    "--width",
+    type=int,
+    default=shutil.get_terminal_size().columns,
+    help="Column width for printing.",
 )
 @click.option(
-    "-t",
-    "--tree",
-    is_flag=True,
-    help="Generate a hierarchical view of the modules, segments and sections.",
-)
-@click.option(
-    "--depth",
-    default=3,
-    help="Generate a virtual address map of important TF symbols.",
-)
-@click.option(
-    "-s",
-    "--symbols",
-    is_flag=True,
-    help="Generate a map of important TF symbols.",
-)
-@click.option("-w", "--width", type=int, envvar="COLUMNS")
-@click.option(
     "-d",
     is_flag=True,
     default=False,
     help="Display numbers in decimal base.",
 )
+def cli(
+    obj: Context,
+    root: Optional[Path],
+    platform: str,
+    build_type: str,
+    width: int,
+    d: bool,
+):
+    obj.build_path = root if root is not None else Path("build", platform, build_type)
+    click.echo(f"build-path: {obj.build_path.resolve()}")
+
+    obj.printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+
+
+@cli.command()
+@click.pass_obj
 @click.option(
     "--no-elf-images",
     is_flag=True,
     help="Analyse the build's map files instead of ELF images.",
 )
-def main(
-    root: Path,
-    platform: str,
-    build_type: str,
-    footprint: str,
-    tree: bool,
-    symbols: bool,
-    depth: int,
-    width: int,
-    d: bool,
-    no_elf_images: bool,
-):
-    build_path = root if root else Path("build/", platform, build_type)
-    click.echo(f"build-path: {build_path.resolve()}")
+def footprint(obj: Context, no_elf_images: bool):
+    """Generate a high level view of memory usage by memory types."""
 
-    parser = TfaBuildParser(build_path, map_backend=no_elf_images)
-    printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+    assert obj.build_path is not None
+    assert obj.printer is not None
 
-    if footprint or not (tree or symbols):
-        printer.print_footprint(parser.get_mem_usage_dict())
+    elf_image_paths: List[Path] = (
+        [] if no_elf_images else list(obj.build_path.glob("**/*.elf"))
+    )
 
-    if tree:
-        printer.print_mem_tree(
-            parser.get_mem_tree_as_dict(), parser.module_names, depth=depth
-        )
+    map_file_paths: List[Path] = (
+        [] if not no_elf_images else list(obj.build_path.glob("**/*.map"))
+    )
 
-    if symbols:
-        expr = (
-            r"(.*)(TEXT|BSS|RO|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF|RELA"
-            r"|R.M)(.*)(START|UNALIGNED|END)__$"
-        )
-        printer.print_symbol_table(
-            parser.filter_symbols(parser.symbols, expr), parser.module_names
-        )
+    images: Dict[str, Image] = dict()
+
+    for elf_image_path in elf_image_paths:
+        with open(elf_image_path, "rb") as elf_image_io:
+            images[elf_image_path.stem.upper()] = TfaElfParser(elf_image_io)
+
+    for map_file_path in map_file_paths:
+        with open(map_file_path, "r") as map_file_io:
+            images[map_file_path.stem.upper()] = TfaMapParser(map_file_io)
+
+    obj.printer.print_footprint({k: v.footprint for k, v in images.items()})
+
+
+@cli.command()
+@click.pass_obj
+@click.option(
+    "--depth",
+    default=3,
+    show_default=True,
+    help="Generate a virtual address map of important TF symbols.",
+)
+def tree(obj: Context, depth: int):
+    """Generate a hierarchical view of the modules, segments and sections."""
+
+    assert obj.build_path is not None
+    assert obj.printer is not None
+
+    paths: List[Path] = list(obj.build_path.glob("**/*.elf"))
+    images: Dict[str, TfaElfParser] = dict()
+
+    for path in paths:
+        with open(path, "rb") as io:
+            images[path.stem] = TfaElfParser(io)
+
+    mtree: Dict[str, Dict[str, Any]] = {
+        k: {
+            "name": k,
+            **v.get_mod_mem_usage_dict(),
+            **{"children": v.get_seg_map_as_dict()},
+        }
+        for k, v in images.items()
+    }
+
+    obj.printer.print_mem_tree(mtree, list(mtree.keys()), depth=depth)
+
+
+@cli.command()
+@click.pass_obj
+@click.option(
+    "--no-elf-images",
+    is_flag=True,
+    help="Analyse the build's map files instead of ELF images.",
+)
+def symbols(obj: Context, no_elf_images: bool):
+    """Generate a map of important TF symbols."""
+
+    assert obj.build_path is not None
+    assert obj.printer is not None
+
+    expr: str = (
+        r"(.*)(TEXT|BSS|RO|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF|RELA"
+        r"|R.M)(.*)(START|UNALIGNED|END)__$"
+    )
+
+    elf_image_paths: List[Path] = (
+        [] if no_elf_images else list(obj.build_path.glob("**/*.elf"))
+    )
+
+    map_file_paths: List[Path] = (
+        [] if not no_elf_images else list(obj.build_path.glob("**/*.map"))
+    )
+
+    images: Dict[str, Image] = dict()
+
+    for elf_image_path in elf_image_paths:
+        with open(elf_image_path, "rb") as elf_image_io:
+            images[elf_image_path.stem] = TfaElfParser(elf_image_io)
+
+    for map_file_path in map_file_paths:
+        with open(map_file_path, "r") as map_file_io:
+            images[map_file_path.stem] = TfaMapParser(map_file_io)
+
+    symbols = {k: v.symbols for k, v in images.items()}
+    symbols = {
+        image: {
+            symbol: symbol_value
+            for symbol, symbol_value in symbols.items()
+            if re.match(expr, symbol)
+        }
+        for image, symbols in symbols.items()
+    }
+
+    obj.printer.print_symbol_table(symbols, list(images.keys()))
+
+
+@cli.command()
+@click.option("-o", "--old", type=click.Path(exists=True))
+@click.option("-d", "--depth", type=int, default=2)
+@click.option("-e", "--exclude-fill")
+@click.option(
+    "-t",
+    "--type",
+    type=click.Choice(MapParser.export_formats, case_sensitive=False),
+    default="table",
+)
+@click.argument("file", type=click.Path(exists=True))
+def summary(file: Path, old: Optional[Path], depth: int, exclude_fill: bool, type: str):
+    """Summarize the sizes of translation units within the resulting binary"""
+    memap = MapParser()
+
+    if not memap.parse(file, old, exclude_fill):
+        exit(1)
+
+    memap.generate_output(type, depth)
+
+
+def main():
+    cli(obj=Context())
 
 
 if __name__ == "__main__":

diff --git a/tools/memory/src/memory/printer.py b/tools/memory/src/memory/printer.py
index f797139..6debf53 100755
--- a/tools/memory/src/memory/printer.py
+++ b/tools/memory/src/memory/printer.py

@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+from typing import Any, Dict, List, Optional, Tuple
+
 from anytree import RenderTree
 from anytree.importer import DictImporter
 from prettytable import PrettyTable
 
+from memory.image import Region
+
 
 class TfaPrettyPrinter:
     """A class for printing the memory layout of ELF files.
@@ -17,19 +21,29 @@
     structured and consumed.
     """
 
-    def __init__(self, columns: int = None, as_decimal: bool = False):
-        self.term_size = columns if columns and columns > 120 else 120
-        self._tree = None
-        self._footprint = None
-        self._symbol_map = None
-        self.as_decimal = as_decimal
+    def __init__(self, columns: int, as_decimal: bool = False) -> None:
+        self.term_size: int = columns
+        self._tree: Optional[List[str]] = None
+        self._symbol_map: Optional[List[str]] = None
+        self.as_decimal: bool = as_decimal
 
-    def format_args(self, *args, width=10, fmt=None):
-        if not fmt and type(args[0]) is int:
+    def format_args(
+        self,
+        *args: Any,
+        width: int = 10,
+        fmt: Optional[str] = None,
+    ) -> List[str]:
+        if not fmt and isinstance(args[0], int):
             fmt = f">{width}x" if not self.as_decimal else f">{width}"
-        return [f"{arg:{fmt}}" if fmt else arg for arg in args]
+        return [f"{arg:{fmt}}" if fmt else str(arg) for arg in args]
 
-    def format_row(self, leading, *args, width=10, fmt=None):
+    def format_row(
+        self,
+        leading: str,
+        *args: Any,
+        width: int = 10,
+        fmt: Optional[str] = None,
+    ) -> str:
         formatted_args = self.format_args(*args, width=width, fmt=fmt)
         return leading + " ".join(formatted_args)
 
@@ -39,9 +53,9 @@
         section_name: str,
         rel_pos: int,
         columns: int,
-        width: int = None,
+        width: int,
         is_edge: bool = False,
-    ):
+    ) -> str:
         empty_col = "{:{}{}}"
 
         # Some symbols are longer than the column width, truncate them until
@@ -50,28 +64,26 @@
         if len_over > 0:
             section_name = section_name[len_over:-len_over]
 
-        sec_row = f"+{section_name:-^{width-1}}+"
+        sec_row = f"+{section_name:-^{width - 1}}+"
         sep, fill = ("+", "-") if is_edge else ("|", "")
 
         sec_row_l = empty_col.format(sep, fill + "<", width) * rel_pos
-        sec_row_r = empty_col.format(sep, fill + ">", width) * (
-            columns - rel_pos - 1
-        )
+        sec_row_r = empty_col.format(sep, fill + ">", width) * (columns - rel_pos - 1)
 
         return leading + sec_row_l + sec_row + sec_row_r
 
     def print_footprint(
-        self, app_mem_usage: dict, sort_key: str = None, fields: list = None
+        self,
+        app_mem_usage: Dict[str, Dict[str, Region]],
     ):
-        assert len(app_mem_usage), "Empty memory layout dictionary!"
-        if not fields:
-            fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+        assert app_mem_usage, "Empty memory layout dictionary!"
 
-        sort_key = fields[0] if not sort_key else sort_key
+        fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+        sort_key = fields[0]
 
         # Iterate through all the memory types, create a table for each
         # type, rows represent a single module.
-        for mem in sorted(set(k for _, v in app_mem_usage.items() for k in v)):
+        for mem in sorted({k for v in app_mem_usage.values() for k in v}):
             table = PrettyTable(
                 sortby=sort_key,
                 title=f"Memory Usage (bytes) [{mem.upper()}]",
@@ -79,13 +91,19 @@
             )
 
             for mod, vals in app_mem_usage.items():
-                if mem in vals.keys():
+                if mem in vals:
                     val = vals[mem]
                     table.add_row(
                         [
-                            mod.upper(),
+                            mod,
                             *self.format_args(
-                                *[val[k.lower()] for k in fields[1:]]
+                                *[
+                                    val.start if val.start is not None else "?",
+                                    val.limit if val.limit is not None else "?",
+                                    val.size if val.size is not None else "?",
+                                    val.free if val.free is not None else "?",
+                                    val.length if val.length is not None else "?",
+                                ]
                             ),
                         ]
                     )
@@ -93,31 +111,34 @@
 
     def print_symbol_table(
         self,
-        symbols: list,
-        modules: list,
+        symbol_table: Dict[str, Dict[str, int]],
+        modules: List[str],
         start: int = 12,
-    ):
-        assert len(symbols), "Empty symbol list!"
+    ) -> None:
+        assert len(symbol_table), "Empty symbol list!"
         modules = sorted(modules)
-        col_width = int((self.term_size - start) / len(modules))
+        col_width = (self.term_size - start) // len(modules)
         address_fixed_width = 11
 
-        num_fmt = (
-            f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
-        )
+        num_fmt = f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
 
         _symbol_map = [
-            " " * start
-            + "".join(self.format_args(*modules, fmt=f"^{col_width}"))
+            " " * start + "".join(self.format_args(*modules, fmt=f"^{col_width}"))
         ]
         last_addr = None
 
-        for i, (name, addr, mod) in enumerate(symbols):
+        symbols_list: List[Tuple[str, int, str]] = [
+            (name, addr, mod)
+            for mod, syms in symbol_table.items()
+            for name, addr in syms.items()
+        ]
+
+        symbols_list.sort(key=lambda x: (-x[1], x[0]), reverse=True)
+
+        for i, (name, addr, mod) in enumerate(symbols_list):
             # Do not print out an address twice if two symbols overlap,
             # for example, at the end of one region and start of another.
-            leading = (
-                f"{addr:{num_fmt}}" + " " if addr != last_addr else " " * start
-            )
+            leading = f"{addr:{num_fmt}}" + " " if addr != last_addr else " " * start
 
             _symbol_map.append(
                 self.map_elf_symbol(
@@ -125,28 +146,30 @@
                     name,
                     modules.index(mod),
                     len(modules),
-                    width=col_width,
-                    is_edge=(not i or i == len(symbols) - 1),
+                    col_width,
+                    is_edge=(i == 0 or i == len(symbols_list) - 1),
                 )
             )
 
             last_addr = addr
 
-        self._symbol_map = ["Memory Layout:"]
-        self._symbol_map += list(reversed(_symbol_map))
+        self._symbol_map = ["Memory Layout:"] + list(reversed(_symbol_map))
         print("\n".join(self._symbol_map))
 
     def print_mem_tree(
-        self, mem_map_dict, modules, depth=1, min_pad=12, node_right_pad=12
-    ):
+        self,
+        mem_map_dict: Dict[str, Any],
+        modules: List[str],
+        depth: int = 1,
+        min_pad: int = 12,
+        node_right_pad: int = 12,
+    ) -> None:
         # Start column should have some padding between itself and its data
         # values.
         anchor = min_pad + node_right_pad * (depth - 1)
         headers = ["start", "end", "size"]
 
-        self._tree = [
-            (f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers))
-        ]
+        self._tree = [f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers)]
 
         for mod in sorted(modules):
             root = DictImporter().import_(mem_map_dict[mod])

diff --git a/tools/memory/src/memory/summary.py b/tools/memory/src/memory/summary.py
new file mode 100644
index 0000000..b116caa
--- /dev/null
+++ b/tools/memory/src/memory/summary.py

@@ -0,0 +1,557 @@
+#
+# Copyright (c) 2016-2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+import json
+import os
+import re
+from collections import defaultdict
+from copy import deepcopy
+from os.path import (
+    abspath,
+    basename,
+    commonprefix,
+    dirname,
+    join,
+    relpath,
+    splitext,
+)
+from pathlib import Path
+from sys import stdout
+from typing import IO, Any, Dict, List, Optional, Pattern, Tuple, Union
+
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
+from prettytable import HEADER, PrettyTable
+
+ModuleStats = Dict[str, int]
+Modules = Dict[str, ModuleStats]
+
+SECTIONS: Tuple[str, ...] = (".text", ".data", ".bss", ".heap", ".stack")
+MISC_FLASH_SECTIONS: Tuple[str, ...] = (".interrupts", ".flash_config")
+OTHER_SECTIONS: Tuple[str, ...] = (
+    ".interrupts_ram",
+    ".init",
+    ".ARM.extab",
+    ".ARM.exidx",
+    ".ARM.attributes",
+    ".eh_frame",
+    ".init_array",
+    ".fini_array",
+    ".jcr",
+    ".stab",
+    ".stabstr",
+    ".ARM.exidx",
+    ".ARM",
+)
+ALL_SECTIONS: Tuple[str, ...] = (
+    SECTIONS + OTHER_SECTIONS + MISC_FLASH_SECTIONS + ("unknown", "OUTPUT")
+)
+
+
+class Parser:
+    """Internal interface for parsing"""
+
+    _RE_OBJECT_FILE: Pattern[str] = re.compile(r"^(.+\/.+\.o(bj)?)$")
+    _RE_LIBRARY_OBJECT: Pattern[str] = re.compile(
+        r"((^.+" + r"" + r"lib.+\.a)\((.+\.o(bj)?)\))$"
+    )
+    _RE_STD_SECTION: Pattern[str] = re.compile(r"^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$")
+    _RE_FILL_SECTION: Pattern[str] = re.compile(
+        r"^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$"
+    )
+    _RE_TRANS_FILE: Pattern[str] = re.compile(r"^(.+\/|.+\.ltrans.o(bj)?)$")
+    _OBJECT_EXTENSIONS: Tuple[str, ...] = (".o", ".obj")
+
+    _modules: Modules
+    _fill: bool
+
+    def __init__(self, fill: bool = True):
+        self._modules: Modules = {}
+        self._fill = fill
+
+    def module_add(self, object_name: str, size: int, section: str):
+        """Adds a module or section to the list
+
+        Positional arguments:
+        object_name - name of the entry to add
+        size - the size of the module being added
+        section - the section the module contributes to
+        """
+        if (
+            not object_name
+            or not size
+            or not section
+            or (not self._fill and object_name == "[fill]")
+        ):
+            return
+
+        if object_name in self._modules:
+            self._modules[object_name].setdefault(section, 0)
+            self._modules[object_name][section] += size
+            return
+
+        obj_split = os.sep + basename(object_name)
+        for module_path, contents in self._modules.items():
+            if module_path.endswith(obj_split) or module_path == object_name:
+                contents.setdefault(section, 0)
+                contents[section] += size
+                return
+
+        new_module: ModuleStats = defaultdict(int)
+        new_module[section] = size
+        self._modules[object_name] = new_module
+
+    def module_replace(self, old_object: str, new_object: str):
+        """Replaces an object name with a new one"""
+        if old_object in self._modules:
+            self._modules[new_object] = self._modules.pop(old_object)
+
+    def check_new_section(self, line: str) -> Optional[str]:
+        """Check whether a new section in a map file has been detected
+
+        Positional arguments:
+        line - the line to check for a new section
+
+        return value - A section name, if a new section was found, None
+                       otherwise
+        """
+        line_s = line.strip()
+        for i in ALL_SECTIONS:
+            if line_s.startswith(i):
+                return i
+        if line.startswith("."):
+            return "unknown"
+        else:
+            return None
+
+    def parse_object_name(self, line: str) -> str:
+        """Parse a path to object file
+
+        Positional arguments:
+        line - the path to parse the object and module name from
+
+        return value - an object file name
+        """
+        if re.match(self._RE_TRANS_FILE, line):
+            return "[misc]"
+
+        test_re_file_name = re.match(self._RE_OBJECT_FILE, line)
+
+        if test_re_file_name:
+            object_name = test_re_file_name.group(1)
+
+            return object_name
+        else:
+            test_re_obj_name = re.match(self._RE_LIBRARY_OBJECT, line)
+
+            if test_re_obj_name:
+                return join(test_re_obj_name.group(2), test_re_obj_name.group(3))
+            else:
+                if not line.startswith("LONG") and not line.startswith("linker stubs"):
+                    print("Unknown object name found in GCC map file: %s" % line)
+                return "[misc]"
+
+    def parse_section(self, line: str) -> Tuple[str, int]:
+        """Parse data from a section of gcc map file
+
+        examples:
+                        0x00004308       0x7c ./BUILD/K64F/GCC_ARM/spi_api.o
+         .text          0x00000608      0x198 ./BUILD/K64F/HAL_CM4.o
+
+        Positional arguments:
+        line - the line to parse a section from
+        """
+        is_fill = re.match(self._RE_FILL_SECTION, line)
+        if is_fill:
+            o_name: str = "[fill]"
+            o_size: int = int(is_fill.group(2), 16)
+            return o_name, o_size
+
+        is_section = re.match(self._RE_STD_SECTION, line)
+        if is_section:
+            o_size: int = int(is_section.group(2), 16)
+            if o_size:
+                o_name: str = self.parse_object_name(is_section.group(3))
+                return o_name, o_size
+
+        return "", 0
+
+    def parse_mapfile(self, file_desc: IO[str]) -> Modules:
+        """Main logic to decode gcc map files
+
+        Positional arguments:
+        file_desc - a stream object to parse as a gcc map file
+        """
+        current_section: str = "unknown"
+
+        with file_desc as infile:
+            for line in infile:
+                if line.startswith("Linker script and memory map"):
+                    current_section = "unknown"
+                    break
+
+            for line in infile:
+                next_section = self.check_new_section(line)
+
+                if next_section == "OUTPUT":
+                    break
+                elif next_section:
+                    current_section = next_section
+
+                object_name, object_size = self.parse_section(line)
+                self.module_add(object_name, object_size, current_section)
+
+        def is_obj(name: str) -> bool:
+            return not name.startswith("[") or not name.endswith("]")
+
+        common_prefix: str = dirname(
+            commonprefix([o for o in self._modules.keys() if is_obj(o)])
+        )
+        new_modules: Modules = {}
+        for name, stats in self._modules.items():
+            if is_obj(name):
+                new_modules[relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        return new_modules
+
+
+class MapParser(object):
+    """An object that represents parsed results, parses the memory map files,
+    and writes out different file types of memory results
+    """
+
+    print_sections: Tuple[str, ...] = (".text", ".data", ".bss")
+    delta_sections: Tuple[str, ...] = (".text-delta", ".data-delta", ".bss-delta")
+
+    # sections to print info (generic for all toolchains)
+    sections: Tuple[str, ...] = SECTIONS
+    misc_flash_sections: Tuple[str, ...] = MISC_FLASH_SECTIONS
+    other_sections: Tuple[str, ...] = OTHER_SECTIONS
+
+    modules: Modules
+    old_modules: Modules
+    short_modules: Modules
+    mem_report: List[Dict[str, Union[str, ModuleStats]]]
+    mem_summary: Dict[str, int]
+    subtotal: Dict[str, int]
+    tc_name: Optional[str]
+
+    RAM_FORMAT_STR: str = "Total Static RAM memory (data + bss): {}({:+}) bytes\n"
+    ROM_FORMAT_STR: str = "Total Flash memory (text + data): {}({:+}) bytes\n"
+
+    def __init__(self):
+        # list of all modules and their sections
+        # full list - doesn't change with depth
+        self.modules: Modules = {}
+        self.old_modules = {}
+        # short version with specific depth
+        self.short_modules: Modules = {}
+
+        # Memory report (sections + summary)
+        self.mem_report: List[Dict[str, Union[str, ModuleStats]]] = []
+
+        # Memory summary
+        self.mem_summary: Dict[str, int] = {}
+
+        # Totals of ".text", ".data" and ".bss"
+        self.subtotal: Dict[str, int] = {}
+
+        # Name of the toolchain, for better headings
+        self.tc_name = None
+
+    def reduce_depth(self, depth: Optional[int]):
+        """
+        populates the short_modules attribute with a truncated module list
+
+        (1) depth = 1:
+        main.o
+        mbed-os
+
+        (2) depth = 2:
+        main.o
+        mbed-os/test.o
+        mbed-os/drivers
+
+        """
+        if depth == 0 or depth is None:
+            self.short_modules = deepcopy(self.modules)
+        else:
+            self.short_modules = dict()
+            for module_name, v in self.modules.items():
+                split_name = module_name.split(os.sep)
+                if split_name[0] == "":
+                    split_name = split_name[1:]
+                new_name = join(*split_name[:depth])
+                self.short_modules.setdefault(new_name, defaultdict(int))
+                for section_idx, value in v.items():
+                    self.short_modules[new_name][section_idx] += value
+                    delta_name = section_idx + "-delta"
+                    self.short_modules[new_name][delta_name] += value
+
+            for module_name, v in self.old_modules.items():
+                split_name = module_name.split(os.sep)
+                if split_name[0] == "":
+                    split_name = split_name[1:]
+                new_name = join(*split_name[:depth])
+                self.short_modules.setdefault(new_name, defaultdict(int))
+                for section_idx, value in v.items():
+                    delta_name = section_idx + "-delta"
+                    self.short_modules[new_name][delta_name] -= value
+
+    export_formats: List[str] = ["json", "html", "table"]
+
+    def generate_output(
+        self,
+        export_format: str,
+        depth: Optional[int],
+        file_output: Optional[str] = None,
+    ) -> Optional[bool]:
+        """Generates summary of memory map data
+
+        Positional arguments:
+        export_format - the format to dump
+
+        Keyword arguments:
+        file_desc - descriptor (either stdout or file)
+        depth - directory depth on report
+
+        Returns: generated string for the 'table' format, otherwise Nonef
+        """
+        if depth is None or depth > 0:
+            self.reduce_depth(depth)
+        self.compute_report()
+        try:
+            if file_output:
+                file_desc = open(file_output, "w")
+            else:
+                file_desc = stdout
+        except IOError as error:
+            print("I/O error({0}): {1}".format(error.errno, error.strerror))
+            return False
+
+        to_call = {
+            "json": self.generate_json,
+            "html": self.generate_html,
+            "table": self.generate_table,
+        }[export_format]
+        to_call(file_desc)
+
+        if file_desc is not stdout:
+            file_desc.close()
+
+    @staticmethod
+    def _move_up_tree(tree: Dict[str, Any], next_module: str) -> Dict[str, Any]:
+        tree.setdefault("children", [])
+        for child in tree["children"]:
+            if child["name"] == next_module:
+                return child
+
+        new_module = {"name": next_module, "value": 0, "delta": 0}
+        tree["children"].append(new_module)
+
+        return new_module
+
+    def generate_html(self, file_desc: IO[str]):
+        """Generate a json file from a memory map for D3
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+
+        tree_text = {"name": ".text", "value": 0, "delta": 0}
+        tree_bss = {"name": ".bss", "value": 0, "delta": 0}
+        tree_data = {"name": ".data", "value": 0, "delta": 0}
+
+        def accumulate(tree_root: Dict[str, Any], size_key: str, stats: ModuleStats):
+            parts = module_name.split(os.sep)
+
+            val = stats.get(size_key, 0)
+            tree_root["value"] += val
+            tree_root["delta"] += val
+
+            cur = tree_root
+            for part in parts:
+                cur = self._move_up_tree(cur, part)
+                cur["value"] += val
+                cur["delta"] += val
+
+        def subtract(tree_root: Dict[str, Any], size_key: str, stats: ModuleStats):
+            parts = module_name.split(os.sep)
+
+            cur = tree_root
+            cur["delta"] -= stats.get(size_key, 0)
+
+            for part in parts:
+                children = {c["name"]: c for c in cur.get("children", [])}
+                if part not in children:
+                    return
+
+                cur = children[part]
+                cur["delta"] -= stats.get(size_key, 0)
+
+        for module_name, dct in self.modules.items():
+            accumulate(tree_text, ".text", dct)
+            accumulate(tree_data, ".data", dct)
+            accumulate(tree_bss, ".bss", dct)
+
+        for module_name, dct in self.old_modules.items():
+            subtract(tree_text, ".text", dct)
+            subtract(tree_data, ".data", dct)
+            subtract(tree_bss, ".bss", dct)
+
+        jinja_loader = FileSystemLoader(dirname(abspath(__file__)))
+        jinja_environment = Environment(loader=jinja_loader, undefined=StrictUndefined)
+        template = jinja_environment.get_template("templates/summary-flamegraph.html")
+
+        name, _ = splitext(basename(file_desc.name))
+
+        if name.endswith("_map"):
+            name = name[:-4]
+        if self.tc_name:
+            name = f"{name} {self.tc_name}"
+
+        file_desc.write(
+            template.render(
+                {
+                    "name": name,
+                    "rom": json.dumps(
+                        {
+                            "name": "ROM",
+                            "value": tree_text["value"] + tree_data["value"],
+                            "delta": tree_text["delta"] + tree_data["delta"],
+                            "children": [tree_text, tree_data],
+                        }
+                    ),
+                    "ram": json.dumps(
+                        {
+                            "name": "RAM",
+                            "value": tree_bss["value"] + tree_data["value"],
+                            "delta": tree_bss["delta"] + tree_data["delta"],
+                            "children": [tree_bss, tree_data],
+                        }
+                    ),
+                }
+            )
+        )
+
+    def generate_json(self, file_desc: IO[str]):
+        """Generate a json file from a memory map
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+        file_desc.write(json.dumps(self.mem_report, indent=4))
+        file_desc.write("\n")
+
+    def generate_table(self, file_desc: IO[str]):
+        """Generate a table from a memory map
+
+        Returns: string of the generated table
+        """
+        # Create table
+        columns = ["Module"]
+        columns.extend(self.print_sections)
+
+        table = PrettyTable(columns, junction_char="|", hrules=HEADER)
+        table.align["Module"] = "l"
+
+        for col in self.print_sections:
+            table.align[col] = "r"
+
+        for i in sorted(self.short_modules):
+            row = [i]
+
+            for k in self.print_sections:
+                row.append(
+                    "{}({:+})".format(
+                        self.short_modules[i][k], self.short_modules[i][k + "-delta"]
+                    )
+                )
+
+            table.add_row(row)
+
+        subtotal_row = ["Subtotals"]
+        for k in self.print_sections:
+            subtotal_row.append(
+                "{}({:+})".format(self.subtotal[k], self.subtotal[k + "-delta"])
+            )
+
+        table.add_row(subtotal_row)
+
+        output = table.get_string()
+        output += "\n"
+
+        output += self.RAM_FORMAT_STR.format(
+            self.mem_summary["static_ram"], self.mem_summary["static_ram_delta"]
+        )
+        output += self.ROM_FORMAT_STR.format(
+            self.mem_summary["total_flash"], self.mem_summary["total_flash_delta"]
+        )
+        file_desc.write(output)
+
+    def compute_report(self):
+        """Generates summary of memory usage for main areas"""
+        self.subtotal = defaultdict(int)
+
+        for mod in self.modules.values():
+            for k in self.sections:
+                self.subtotal[k] += mod[k]
+                self.subtotal[k + "-delta"] += mod[k]
+
+        for mod in self.old_modules.values():
+            for k in self.sections:
+                self.subtotal[k + "-delta"] -= mod[k]
+
+        self.mem_summary = {
+            "static_ram": self.subtotal[".data"] + self.subtotal[".bss"],
+            "static_ram_delta": self.subtotal[".data-delta"]
+            + self.subtotal[".bss-delta"],
+            "total_flash": (self.subtotal[".text"] + self.subtotal[".data"]),
+            "total_flash_delta": self.subtotal[".text-delta"]
+            + self.subtotal[".data-delta"],
+        }
+
+        self.mem_report = []
+        if self.short_modules:
+            for name, sizes in sorted(self.short_modules.items()):
+                self.mem_report.append(
+                    {
+                        "module": name,
+                        "size": {
+                            k: sizes.get(k, 0)
+                            for k in (self.print_sections + self.delta_sections)
+                        },
+                    }
+                )
+
+        self.mem_report.append({"summary": self.mem_summary})
+
+    def parse(
+        self, mapfile: Path, oldfile: Optional[Path] = None, no_fill: bool = False
+    ) -> bool:
+        """Parse and decode map file depending on the toolchain
+
+        Positional arguments:
+        mapfile - the file name of the memory map file
+        toolchain - the toolchain used to create the file
+        """
+        try:
+            with open(mapfile, "r") as file_input:
+                self.modules = Parser(not no_fill).parse_mapfile(file_input)
+            try:
+                if oldfile is not None:
+                    with open(oldfile, "r") as old_input:
+                        self.old_modules = Parser(not no_fill).parse_mapfile(old_input)
+                else:
+                    self.old_modules = self.modules
+            except IOError:
+                self.old_modules = {}
+            return True
+
+        except IOError as error:
+            print("I/O error({0}): {1}".format(error.errno, error.strerror))
+            return False

diff --git a/tools/memory/src/memory/templates/summary-flamegraph.html b/tools/memory/src/memory/templates/summary-flamegraph.html
new file mode 100644
index 0000000..9ec8ecb
--- /dev/null
+++ b/tools/memory/src/memory/templates/summary-flamegraph.html

@@ -0,0 +1,110 @@
+<!DOCTYPE html>
+<html lang="en">
+
+<head>
+  <meta charset="utf-8">
+  <meta http-equiv="X-UA-Compatible" content="IE=edge">
+  <meta name="viewport" content="width=device-width, initial-scale=1">
+
+  <link rel="stylesheet" type="text/css" href="https://maxcdn.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css"
+    integrity="sha256-916EbMg70RQy9LHiGkXzG8hSg9EdNy97GazNG/aiY1w=" crossorigin="anonymous" />
+  <link rel="stylesheet" type="text/css"
+    href="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.css"
+    integrity="sha256-w762vSe6WGrkVZ7gEOpnn2Y+FSmAGlX77jYj7nhuCyY=" crossorigin="anonymous" />
+
+  <style>
+    /* Space out content a bit */
+    body {
+      padding-top: 20px;
+      padding-bottom: 20px;
+    }
+
+    /* Custom page header */
+    .header {
+      padding-bottom: 20px;
+      padding-right: 15px;
+      padding-left: 15px;
+      border-bottom: 1px solid #e5e5e5;
+    }
+
+    /* Make the masthead heading the same height as the navigation */
+    .header h3 {
+      margin-top: 0;
+      margin-bottom: 0;
+      line-height: 40px;
+    }
+  </style>
+
+  <title>{{name}} Memory Details</title>
+</head>
+
+<body>
+  <div class="container">
+    <div class="header clearfix">
+      <h3 class="text-muted">{{name}} Memory Details</h3>
+    </div>
+    <div id="chart-rom">
+    </div>
+    <hr />
+    <div id="chart-ram">
+    </div>
+    <hr />
+    <div id="details"></div>
+  </div>
+
+  <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/d3/4.10.0/d3.min.js"
+    integrity="sha256-r7j1FXNTvPzHR41+V71Jvej6fIq4v4Kzu5ee7J/RitM=" crossorigin="anonymous">
+    </script>
+  <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/d3-tip/0.7.1/d3-tip.min.js"
+    integrity="sha256-z0A2CQF8xxCKuOJsn4sJ5HBjxiHHRAfTX8hDF4RSN5s=" crossorigin="anonymous">
+    </script>
+  <script type="text/javascript"
+    src="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.js"
+    integrity="sha256-I1CkrWbmjv+GWjgbulJ4i0vbzdrDGfxqdye2qNlhG3Q=" crossorigin="anonymous">
+    </script>
+
+  <script type="text/javascript">
+    var tip = d3.tip()
+      .direction("s")
+      .offset([8, 0])
+      .attr('class', 'd3-flame-graph-tip')
+      .html(function (d) { return "module: " + d.data.name + ", bytes: " + d.data.value + ", delta: " + d.data.delta; });
+    var colorizer = function (d) {
+      if (d.data.delta > 0) {
+        ratio = (d.data.value - d.data.delta) / d.data.value;
+        green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+        blue = ("0" + (Number(ratio * 0xEE | 0).toString(16))).slice(-2).toUpperCase();
+        console.log(d.data.name, green, blue);
+        return "#EE" + green + blue
+      } else if (d.data.delta < 0) {
+        ratio = (d.data.value + d.data.delta) / d.data.value;
+        green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+        red = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+        console.log(d.data.name, red, green);
+        return "#" + red + green + "EE";
+      } else {
+        return "#FFFFEE";
+      }
+    }
+    var flameGraph_rom = d3.flameGraph()
+      .transitionDuration(250)
+      .transitionEase(d3.easeCubic)
+      .sort(true)
+      .color(colorizer)
+      .tooltip(tip);
+    var flameGraph_ram = d3.flameGraph()
+      .transitionDuration(250)
+      .transitionEase(d3.easeCubic)
+      .sort(true)
+      .color(colorizer)
+      .tooltip(tip);
+    var rom_elem = d3.select("#chart-rom");
+    flameGraph_rom.width(rom_elem.node().getBoundingClientRect().width);
+    rom_elem.datum({{ rom }}).call(flameGraph_rom);
+    var ram_elem = d3.select("#chart-ram");
+    flameGraph_ram.width(ram_elem.node().getBoundingClientRect().width);
+    ram_elem.datum({{ ram }}).call(flameGraph_ram);
+  </script>
+</body>
+
+</html>

diff --git a/tools/nxp/create_pbl/Makefile b/tools/nxp/create_pbl/Makefile
index cd2ccc1..9285b72 100644
--- a/tools/nxp/create_pbl/Makefile
+++ b/tools/nxp/create_pbl/Makefile

@@ -44,7 +44,7 @@
 	$(s)echo "Built $@ successfully"
 	$(s)echo
 
-+${OBJECTS_1} ${OBJECTS_2}: %.o: %.c Makefile
+${OBJECTS_1} ${OBJECTS_2}: %.o: %.c Makefile
 	$(s)echo "  CC      $<"
 	$(q)$(host-cc) -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@