| commit | 42920aa743901395431f8c0ad0b79d0d79ef4ade | [log] [tgz] |
|---|---|---|
| author | Arvind Ram Prakash <arvind.ramprakash@arm.com> | Thu Jul 10 09:59:00 2025 -0500 |
| committer | Arvind Ram Prakash <arvind.ramprakash@arm.com> | Wed Jul 16 09:39:38 2025 -0500 |
| tree | f8eba8127c76c393b7d8b8404a06fefa7f423c95 | |
| parent | 6a464ee7754d9b24a9a35668bc5019164267dac7 [diff] |
fix(cpus): workaround for Cortex-X3 erratum 3213672 Cortex-X3 erratum 3213672 is a Cat B erratum that applies to r0p0, r1p0, r1p1 and r1p2. It is still open. This erratum can be worked around by setting CPUACTLR_EL1[36] before enabling icache. SDEN Documentation: https://developer.arm.com/documentation/SDEN-2055130/latest/ Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: Ia1c03217f4e1816b4e8754a090cf5bc17546be40