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Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02001/*
Mark Dykese7810b52020-06-03 15:46:55 -05002 * Copyright (c) 2020, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8#include <xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tftf_entrypoint)
13
14MEMORY {
15 RAM (rwx): ORIGIN = DRAM_BASE, LENGTH = DRAM_SIZE
16}
17
18
19SECTIONS
20{
21 . = TFTF_BASE;
22 __TFTF_BASE__ = .;
23
Ambroise Vincentee3e7cd2019-07-03 16:44:49 +010024 .text . : {
25 __TEXT_START__ = .;
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020026 *entrypoint.o(.text*)
27 *(.text*)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020028 *(.vectors)
Ambroise Vincentee3e7cd2019-07-03 16:44:49 +010029 . = NEXT(PAGE_SIZE);
30 __TEXT_END__ = .;
31 } >RAM
32
33 .rodata . : {
34 __RODATA_START__ = .;
35 *(.rodata*)
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020036 /*
37 * Memory page(s) mapped to this section will be marked as
38 * read-only, executable. No RW data from the next section must
39 * creep in. Ensure the rest of the current memory page is unused.
40 */
41 . = NEXT(PAGE_SIZE);
Ambroise Vincentee3e7cd2019-07-03 16:44:49 +010042 __RODATA_END__ = .;
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020043 } >RAM
44
45 .data : {
46 __DATA_START__ = .;
47 *(.data*)
48 __DATA_END__ = .;
49 } >RAM
50
51 stacks (NOLOAD) : {
52 __STACKS_START__ = .;
53 *(tftf_normal_stacks)
54 __STACKS_END__ = .;
55 } >RAM
56
57 /*
58 * The .bss section gets initialised to 0 at runtime.
59 * Its base address must be 16-byte aligned.
60 */
61 .bss : ALIGN(16) {
62 __BSS_START__ = .;
63 *(SORT_BY_ALIGNMENT(.bss*))
64 *(COMMON)
65 __BSS_END__ = .;
66 } >RAM
67
68 /*
69 * The xlat_table section is for full, aligned page tables (4K).
70 * Removing them from .bss avoids forcing 4K alignment on
71 * the .bss section and eliminates the unecessary zero init
72 */
73 xlat_table (NOLOAD) : {
74 *(xlat_table)
75 } >RAM
76
77 /*
Mark Dykese7810b52020-06-03 15:46:55 -050078 * The SMC fuzzing module requires alignment due to malloc
79 * constraints. Also size must be at least around 64K
80 */
81 smcfuzz (NOLOAD) : {
82 *(smcfuzz)
83 } >RAM
84
85 /*
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +020086 * The base address of the coherent memory section must be page-aligned (4K)
87 * to guarantee that the coherent data are stored on their own pages and
88 * are not mixed with normal data. This is required to set up the correct
89 * memory attributes for the coherent data page tables.
90 */
91 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
92 __COHERENT_RAM_START__ = .;
93 *(tftf_coherent_stacks)
94 *(tftf_coherent_mem)
95 __COHERENT_RAM_END_UNALIGNED__ = .;
96 /*
97 * Memory page(s) mapped to this section will be marked
98 * as device memory. No other unexpected data must creep in.
99 * Ensure the rest of the current memory page is unused.
100 */
101 . = NEXT(PAGE_SIZE);
102 __COHERENT_RAM_END__ = .;
103 } >RAM
104
105 __COHERENT_RAM_UNALIGNED_SIZE__ =
106 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
107
108
109 __TFTF_END__ = .;
110
111 __BSS_SIZE__ = SIZEOF(.bss);
112
113}