Introduce test for SVE support
When SVE extension is enabled, test that it correctly performs simple
operations.
Generating SVE instructions requires O3 compilation optimization. Since
the build structure does not allow compilation flag modification for
specific files, the function testing SVE support has been pre-compiled
and added as an assembly file.
Change-Id: Id9ba7d9e1de9bcbae3065cad2dd3e1dbe87ef03a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index c4ec4ff..fea256b 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -364,12 +364,12 @@
#define CPTR_EL3_RESET_VAL U(0x0)
/* CPTR_EL2 definitions */
-#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
-#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
-#define CPTR_EL2_TAM_BIT (U(1) << 30)
-#define CPTR_EL2_TTA_BIT (U(1) << 20)
-#define CPTR_EL2_TFP_BIT (U(1) << 10)
-#define CPTR_EL2_TZ_BIT (U(1) << 8)
+#define CPTR_EL2_RES1 ((ULL(3) << 12) | (ULL(1) << 9) | (ULL(0xff)))
+#define CPTR_EL2_TCPAC_BIT (ULL(1) << 31)
+#define CPTR_EL2_TAM_BIT (ULL(1) << 30)
+#define CPTR_EL2_TTA_BIT (ULL(1) << 20)
+#define CPTR_EL2_TFP_BIT (ULL(1) << 10)
+#define CPTR_EL2_TZ_BIT (ULL(1) << 8)
#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
/* CPSR/SPSR definitions */
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 6af1d03..c5cdc3e 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -17,6 +17,12 @@
return true;
}
+static inline bool is_armv8_2_sve_present(void)
+{
+ return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) &
+ ID_AA64PFR0_SVE_MASK) == 1U;
+}
+
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &